1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * An RTC driver for Allwinner A31/A23 4 * 5 * Copyright (c) 2014, Chen-Yu Tsai <[email protected]> 6 * 7 * based on rtc-sunxi.c 8 * 9 * An RTC driver for Allwinner A10/A20 10 * 11 * Copyright (c) 2013, Carlo Caione <[email protected]> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/fs.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/rtc.h> 29 #include <linux/slab.h> 30 #include <linux/types.h> 31 32 /* Control register */ 33 #define SUN6I_LOSC_CTRL 0x0000 34 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) 35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) 36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) 37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) 38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) 39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) 40 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) 41 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) 42 43 #define SUN6I_LOSC_CLK_PRESCAL 0x0008 44 45 /* RTC */ 46 #define SUN6I_RTC_YMD 0x0010 47 #define SUN6I_RTC_HMS 0x0014 48 49 /* Alarm 0 (counter) */ 50 #define SUN6I_ALRM_COUNTER 0x0020 51 #define SUN6I_ALRM_CUR_VAL 0x0024 52 #define SUN6I_ALRM_EN 0x0028 53 #define SUN6I_ALRM_EN_CNT_EN BIT(0) 54 #define SUN6I_ALRM_IRQ_EN 0x002c 55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) 56 #define SUN6I_ALRM_IRQ_STA 0x0030 57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) 58 59 /* Alarm 1 (wall clock) */ 60 #define SUN6I_ALRM1_EN 0x0044 61 #define SUN6I_ALRM1_IRQ_EN 0x0048 62 #define SUN6I_ALRM1_IRQ_STA 0x004c 63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) 64 65 /* Alarm config */ 66 #define SUN6I_ALARM_CONFIG 0x0050 67 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) 68 69 #define SUN6I_LOSC_OUT_GATING 0x0060 70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 71 72 /* 73 * Get date values 74 */ 75 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) 76 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) 77 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) 78 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) 79 80 /* 81 * Get time values 82 */ 83 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) 84 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) 85 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) 86 87 /* 88 * Set date values 89 */ 90 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) 91 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) 92 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) 93 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) 94 95 /* 96 * Set time values 97 */ 98 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) 99 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) 100 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) 101 102 /* 103 * The year parameter passed to the driver is usually an offset relative to 104 * the year 1900. This macro is used to convert this offset to another one 105 * relative to the minimum year allowed by the hardware. 106 * 107 * The year range is 1970 - 2033. This range is selected to match Allwinner's 108 * driver, even though it is somewhat limited. 109 */ 110 #define SUN6I_YEAR_MIN 1970 111 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) 112 113 #define SECS_PER_DAY (24 * 3600ULL) 114 115 /* 116 * There are other differences between models, including: 117 * 118 * - number of GPIO pins that can be configured to hold a certain level 119 * - crypto-key related registers (H5, H6) 120 * - boot process related (super standby, secondary processor entry address) 121 * registers (R40, H6) 122 * - SYS power domain controls (R40) 123 * - DCXO controls (H6) 124 * - RC oscillator calibration (H6) 125 * 126 * These functions are not covered by this driver. 127 */ 128 struct sun6i_rtc_clk_data { 129 unsigned long rc_osc_rate; 130 unsigned int fixed_prescaler : 16; 131 unsigned int has_prescaler : 1; 132 unsigned int has_out_clk : 1; 133 unsigned int export_iosc : 1; 134 unsigned int has_losc_en : 1; 135 unsigned int has_auto_swt : 1; 136 }; 137 138 #define RTC_LINEAR_DAY BIT(0) 139 140 struct sun6i_rtc_dev { 141 struct rtc_device *rtc; 142 const struct sun6i_rtc_clk_data *data; 143 void __iomem *base; 144 int irq; 145 time64_t alarm; 146 unsigned long flags; 147 148 struct clk_hw hw; 149 struct clk_hw *int_osc; 150 struct clk *losc; 151 struct clk *ext_losc; 152 153 spinlock_t lock; 154 }; 155 156 static struct sun6i_rtc_dev *sun6i_rtc; 157 158 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, 159 unsigned long parent_rate) 160 { 161 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 162 u32 val = 0; 163 164 val = readl(rtc->base + SUN6I_LOSC_CTRL); 165 if (val & SUN6I_LOSC_CTRL_EXT_OSC) 166 return parent_rate; 167 168 if (rtc->data->fixed_prescaler) 169 parent_rate /= rtc->data->fixed_prescaler; 170 171 if (rtc->data->has_prescaler) { 172 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); 173 val &= GENMASK(4, 0); 174 } 175 176 return parent_rate / (val + 1); 177 } 178 179 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) 180 { 181 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 182 183 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; 184 } 185 186 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) 187 { 188 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 189 unsigned long flags; 190 u32 val; 191 192 if (index > 1) 193 return -EINVAL; 194 195 spin_lock_irqsave(&rtc->lock, flags); 196 val = readl(rtc->base + SUN6I_LOSC_CTRL); 197 val &= ~SUN6I_LOSC_CTRL_EXT_OSC; 198 val |= SUN6I_LOSC_CTRL_KEY; 199 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; 200 if (rtc->data->has_losc_en) { 201 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; 202 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; 203 } 204 writel(val, rtc->base + SUN6I_LOSC_CTRL); 205 spin_unlock_irqrestore(&rtc->lock, flags); 206 207 return 0; 208 } 209 210 static const struct clk_ops sun6i_rtc_osc_ops = { 211 .recalc_rate = sun6i_rtc_osc_recalc_rate, 212 213 .get_parent = sun6i_rtc_osc_get_parent, 214 .set_parent = sun6i_rtc_osc_set_parent, 215 }; 216 217 static void __init sun6i_rtc_clk_init(struct device_node *node, 218 const struct sun6i_rtc_clk_data *data) 219 { 220 struct clk_hw_onecell_data *clk_data; 221 struct sun6i_rtc_dev *rtc; 222 struct clk_init_data init = { 223 .ops = &sun6i_rtc_osc_ops, 224 .name = "losc", 225 }; 226 const char *iosc_name = "rtc-int-osc"; 227 const char *clkout_name = "osc32k-out"; 228 const char *parents[2]; 229 u32 reg; 230 231 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); 232 if (!rtc) 233 return; 234 235 rtc->data = data; 236 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); 237 if (!clk_data) { 238 kfree(rtc); 239 return; 240 } 241 242 spin_lock_init(&rtc->lock); 243 244 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); 245 if (IS_ERR(rtc->base)) { 246 pr_crit("Can't map RTC registers"); 247 goto err; 248 } 249 250 reg = SUN6I_LOSC_CTRL_KEY; 251 if (rtc->data->has_auto_swt) { 252 /* Bypass auto-switch to int osc, on ext losc failure */ 253 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; 254 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 255 } 256 257 /* Switch to the external, more precise, oscillator, if present */ 258 if (of_get_property(node, "clocks", NULL)) { 259 reg |= SUN6I_LOSC_CTRL_EXT_OSC; 260 if (rtc->data->has_losc_en) 261 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; 262 } 263 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 264 265 /* Yes, I know, this is ugly. */ 266 sun6i_rtc = rtc; 267 268 /* Only read IOSC name from device tree if it is exported */ 269 if (rtc->data->export_iosc) 270 of_property_read_string_index(node, "clock-output-names", 2, 271 &iosc_name); 272 273 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, 274 iosc_name, 275 NULL, 0, 276 rtc->data->rc_osc_rate, 277 300000000); 278 if (IS_ERR(rtc->int_osc)) { 279 pr_crit("Couldn't register the internal oscillator\n"); 280 goto err; 281 } 282 283 parents[0] = clk_hw_get_name(rtc->int_osc); 284 /* If there is no external oscillator, this will be NULL and ... */ 285 parents[1] = of_clk_get_parent_name(node, 0); 286 287 rtc->hw.init = &init; 288 289 init.parent_names = parents; 290 /* ... number of clock parents will be 1. */ 291 init.num_parents = of_clk_get_parent_count(node) + 1; 292 of_property_read_string_index(node, "clock-output-names", 0, 293 &init.name); 294 295 rtc->losc = clk_register(NULL, &rtc->hw); 296 if (IS_ERR(rtc->losc)) { 297 pr_crit("Couldn't register the LOSC clock\n"); 298 goto err_register; 299 } 300 301 of_property_read_string_index(node, "clock-output-names", 1, 302 &clkout_name); 303 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, 304 0, rtc->base + SUN6I_LOSC_OUT_GATING, 305 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 306 &rtc->lock); 307 if (IS_ERR(rtc->ext_losc)) { 308 pr_crit("Couldn't register the LOSC external gate\n"); 309 goto err_register; 310 } 311 312 clk_data->num = 2; 313 clk_data->hws[0] = &rtc->hw; 314 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); 315 if (rtc->data->export_iosc) { 316 clk_data->hws[2] = rtc->int_osc; 317 clk_data->num = 3; 318 } 319 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 320 return; 321 322 err_register: 323 clk_hw_unregister_fixed_rate(rtc->int_osc); 324 err: 325 kfree(clk_data); 326 } 327 328 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { 329 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 330 .has_prescaler = 1, 331 }; 332 333 static void __init sun6i_a31_rtc_clk_init(struct device_node *node) 334 { 335 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); 336 } 337 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", 338 sun6i_a31_rtc_clk_init); 339 340 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { 341 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 342 .has_prescaler = 1, 343 .has_out_clk = 1, 344 }; 345 346 static void __init sun8i_a23_rtc_clk_init(struct device_node *node) 347 { 348 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); 349 } 350 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", 351 sun8i_a23_rtc_clk_init); 352 353 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { 354 .rc_osc_rate = 16000000, 355 .fixed_prescaler = 32, 356 .has_prescaler = 1, 357 .has_out_clk = 1, 358 .export_iosc = 1, 359 }; 360 361 static void __init sun8i_h3_rtc_clk_init(struct device_node *node) 362 { 363 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); 364 } 365 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", 366 sun8i_h3_rtc_clk_init); 367 /* As far as we are concerned, clocks for H5 are the same as H3 */ 368 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", 369 sun8i_h3_rtc_clk_init); 370 371 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { 372 .rc_osc_rate = 16000000, 373 .fixed_prescaler = 32, 374 .has_prescaler = 1, 375 .has_out_clk = 1, 376 .export_iosc = 1, 377 .has_losc_en = 1, 378 .has_auto_swt = 1, 379 }; 380 381 static void __init sun50i_h6_rtc_clk_init(struct device_node *node) 382 { 383 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); 384 } 385 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", 386 sun50i_h6_rtc_clk_init); 387 388 /* 389 * The R40 user manual is self-conflicting on whether the prescaler is 390 * fixed or configurable. The clock diagram shows it as fixed, but there 391 * is also a configurable divider in the RTC block. 392 */ 393 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { 394 .rc_osc_rate = 16000000, 395 .fixed_prescaler = 512, 396 }; 397 static void __init sun8i_r40_rtc_clk_init(struct device_node *node) 398 { 399 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); 400 } 401 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", 402 sun8i_r40_rtc_clk_init); 403 404 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { 405 .rc_osc_rate = 32000, 406 .has_out_clk = 1, 407 }; 408 409 static void __init sun8i_v3_rtc_clk_init(struct device_node *node) 410 { 411 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); 412 } 413 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", 414 sun8i_v3_rtc_clk_init); 415 416 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) 417 { 418 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; 419 irqreturn_t ret = IRQ_NONE; 420 u32 val; 421 422 spin_lock(&chip->lock); 423 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 424 425 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { 426 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; 427 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 428 429 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 430 431 ret = IRQ_HANDLED; 432 } 433 spin_unlock(&chip->lock); 434 435 return ret; 436 } 437 438 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) 439 { 440 u32 alrm_val = 0; 441 u32 alrm_irq_val = 0; 442 u32 alrm_wake_val = 0; 443 unsigned long flags; 444 445 if (to) { 446 alrm_val = SUN6I_ALRM_EN_CNT_EN; 447 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; 448 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; 449 } else { 450 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 451 chip->base + SUN6I_ALRM_IRQ_STA); 452 } 453 454 spin_lock_irqsave(&chip->lock, flags); 455 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 456 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 457 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 458 spin_unlock_irqrestore(&chip->lock, flags); 459 } 460 461 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 462 { 463 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 464 u32 date, time; 465 466 /* 467 * read again in case it changes 468 */ 469 do { 470 date = readl(chip->base + SUN6I_RTC_YMD); 471 time = readl(chip->base + SUN6I_RTC_HMS); 472 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || 473 (time != readl(chip->base + SUN6I_RTC_HMS))); 474 475 if (chip->flags & RTC_LINEAR_DAY) { 476 /* 477 * Newer chips store a linear day number, the manual 478 * does not mandate any epoch base. The BSP driver uses 479 * the UNIX epoch, let's just copy that, as it's the 480 * easiest anyway. 481 */ 482 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); 483 } else { 484 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); 485 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; 486 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 487 488 /* 489 * switch from (data_year->min)-relative offset to 490 * a (1900)-relative one 491 */ 492 rtc_tm->tm_year += SUN6I_YEAR_OFF; 493 } 494 495 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); 496 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); 497 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 498 499 return 0; 500 } 501 502 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 503 { 504 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 505 unsigned long flags; 506 u32 alrm_st; 507 u32 alrm_en; 508 509 spin_lock_irqsave(&chip->lock, flags); 510 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); 511 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); 512 spin_unlock_irqrestore(&chip->lock, flags); 513 514 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); 515 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); 516 rtc_time64_to_tm(chip->alarm, &wkalrm->time); 517 518 return 0; 519 } 520 521 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 522 { 523 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 524 struct rtc_time *alrm_tm = &wkalrm->time; 525 struct rtc_time tm_now; 526 time64_t time_now, time_set; 527 int ret; 528 529 ret = sun6i_rtc_gettime(dev, &tm_now); 530 if (ret < 0) { 531 dev_err(dev, "Error in getting time\n"); 532 return -EINVAL; 533 } 534 535 time_set = rtc_tm_to_time64(alrm_tm); 536 time_now = rtc_tm_to_time64(&tm_now); 537 if (time_set <= time_now) { 538 dev_err(dev, "Date to set in the past\n"); 539 return -EINVAL; 540 } 541 542 if ((time_set - time_now) > U32_MAX) { 543 dev_err(dev, "Date too far in the future\n"); 544 return -EINVAL; 545 } 546 547 sun6i_rtc_setaie(0, chip); 548 writel(0, chip->base + SUN6I_ALRM_COUNTER); 549 usleep_range(100, 300); 550 551 writel(time_set - time_now, chip->base + SUN6I_ALRM_COUNTER); 552 chip->alarm = time_set; 553 554 sun6i_rtc_setaie(wkalrm->enabled, chip); 555 556 return 0; 557 } 558 559 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, 560 unsigned int mask, unsigned int ms_timeout) 561 { 562 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 563 u32 reg; 564 565 do { 566 reg = readl(chip->base + offset); 567 reg &= mask; 568 569 if (!reg) 570 return 0; 571 572 } while (time_before(jiffies, timeout)); 573 574 return -ETIMEDOUT; 575 } 576 577 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) 578 { 579 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 580 u32 date = 0; 581 u32 time = 0; 582 583 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | 584 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | 585 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); 586 587 if (chip->flags & RTC_LINEAR_DAY) { 588 /* The division will cut off the H:M:S part of rtc_tm. */ 589 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); 590 } else { 591 rtc_tm->tm_year -= SUN6I_YEAR_OFF; 592 rtc_tm->tm_mon += 1; 593 594 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | 595 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | 596 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); 597 598 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) 599 date |= SUN6I_LEAP_SET_VALUE(1); 600 } 601 602 /* Check whether registers are writable */ 603 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 604 SUN6I_LOSC_CTRL_ACC_MASK, 50)) { 605 dev_err(dev, "rtc is still busy.\n"); 606 return -EBUSY; 607 } 608 609 writel(time, chip->base + SUN6I_RTC_HMS); 610 611 /* 612 * After writing the RTC HH-MM-SS register, the 613 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not 614 * be cleared until the real writing operation is finished 615 */ 616 617 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 618 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { 619 dev_err(dev, "Failed to set rtc time.\n"); 620 return -ETIMEDOUT; 621 } 622 623 writel(date, chip->base + SUN6I_RTC_YMD); 624 625 /* 626 * After writing the RTC YY-MM-DD register, the 627 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not 628 * be cleared until the real writing operation is finished 629 */ 630 631 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 632 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { 633 dev_err(dev, "Failed to set rtc time.\n"); 634 return -ETIMEDOUT; 635 } 636 637 return 0; 638 } 639 640 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 641 { 642 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 643 644 if (!enabled) 645 sun6i_rtc_setaie(enabled, chip); 646 647 return 0; 648 } 649 650 static const struct rtc_class_ops sun6i_rtc_ops = { 651 .read_time = sun6i_rtc_gettime, 652 .set_time = sun6i_rtc_settime, 653 .read_alarm = sun6i_rtc_getalarm, 654 .set_alarm = sun6i_rtc_setalarm, 655 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable 656 }; 657 658 #ifdef CONFIG_PM_SLEEP 659 /* Enable IRQ wake on suspend, to wake up from RTC. */ 660 static int sun6i_rtc_suspend(struct device *dev) 661 { 662 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 663 664 if (device_may_wakeup(dev)) 665 enable_irq_wake(chip->irq); 666 667 return 0; 668 } 669 670 /* Disable IRQ wake on resume. */ 671 static int sun6i_rtc_resume(struct device *dev) 672 { 673 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 674 675 if (device_may_wakeup(dev)) 676 disable_irq_wake(chip->irq); 677 678 return 0; 679 } 680 #endif 681 682 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, 683 sun6i_rtc_suspend, sun6i_rtc_resume); 684 685 static void sun6i_rtc_bus_clk_cleanup(void *data) 686 { 687 struct clk *bus_clk = data; 688 689 clk_disable_unprepare(bus_clk); 690 } 691 692 static int sun6i_rtc_probe(struct platform_device *pdev) 693 { 694 struct sun6i_rtc_dev *chip = sun6i_rtc; 695 struct device *dev = &pdev->dev; 696 struct clk *bus_clk; 697 int ret; 698 699 bus_clk = devm_clk_get_optional(dev, "bus"); 700 if (IS_ERR(bus_clk)) 701 return PTR_ERR(bus_clk); 702 703 if (bus_clk) { 704 ret = clk_prepare_enable(bus_clk); 705 if (ret) 706 return ret; 707 708 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup, 709 bus_clk); 710 if (ret) 711 return ret; 712 } 713 714 if (!chip) { 715 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 716 if (!chip) 717 return -ENOMEM; 718 719 spin_lock_init(&chip->lock); 720 721 chip->base = devm_platform_ioremap_resource(pdev, 0); 722 if (IS_ERR(chip->base)) 723 return PTR_ERR(chip->base); 724 } 725 726 platform_set_drvdata(pdev, chip); 727 728 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); 729 730 chip->irq = platform_get_irq(pdev, 0); 731 if (chip->irq < 0) 732 return chip->irq; 733 734 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, 735 0, dev_name(&pdev->dev), chip); 736 if (ret) { 737 dev_err(&pdev->dev, "Could not request IRQ\n"); 738 return ret; 739 } 740 741 /* clear the alarm counter value */ 742 writel(0, chip->base + SUN6I_ALRM_COUNTER); 743 744 /* disable counter alarm */ 745 writel(0, chip->base + SUN6I_ALRM_EN); 746 747 /* disable counter alarm interrupt */ 748 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); 749 750 /* disable week alarm */ 751 writel(0, chip->base + SUN6I_ALRM1_EN); 752 753 /* disable week alarm interrupt */ 754 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); 755 756 /* clear counter alarm pending interrupts */ 757 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 758 chip->base + SUN6I_ALRM_IRQ_STA); 759 760 /* clear week alarm pending interrupts */ 761 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, 762 chip->base + SUN6I_ALRM1_IRQ_STA); 763 764 /* disable alarm wakeup */ 765 writel(0, chip->base + SUN6I_ALARM_CONFIG); 766 767 clk_prepare_enable(chip->losc); 768 769 device_init_wakeup(&pdev->dev, 1); 770 771 chip->rtc = devm_rtc_allocate_device(&pdev->dev); 772 if (IS_ERR(chip->rtc)) 773 return PTR_ERR(chip->rtc); 774 775 chip->rtc->ops = &sun6i_rtc_ops; 776 if (chip->flags & RTC_LINEAR_DAY) 777 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; 778 else 779 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ 780 781 ret = devm_rtc_register_device(chip->rtc); 782 if (ret) 783 return ret; 784 785 dev_info(&pdev->dev, "RTC enabled\n"); 786 787 return 0; 788 } 789 790 /* 791 * As far as RTC functionality goes, all models are the same. The 792 * datasheets claim that different models have different number of 793 * registers available for non-volatile storage, but experiments show 794 * that all SoCs have 16 registers available for this purpose. 795 */ 796 static const struct of_device_id sun6i_rtc_dt_ids[] = { 797 { .compatible = "allwinner,sun6i-a31-rtc" }, 798 { .compatible = "allwinner,sun8i-a23-rtc" }, 799 { .compatible = "allwinner,sun8i-h3-rtc" }, 800 { .compatible = "allwinner,sun8i-r40-rtc" }, 801 { .compatible = "allwinner,sun8i-v3-rtc" }, 802 { .compatible = "allwinner,sun50i-h5-rtc" }, 803 { .compatible = "allwinner,sun50i-h6-rtc" }, 804 { /* sentinel */ }, 805 }; 806 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); 807 808 static struct platform_driver sun6i_rtc_driver = { 809 .probe = sun6i_rtc_probe, 810 .driver = { 811 .name = "sun6i-rtc", 812 .of_match_table = sun6i_rtc_dt_ids, 813 .pm = &sun6i_rtc_pm_ops, 814 }, 815 }; 816 builtin_platform_driver(sun6i_rtc_driver); 817