1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/regmap.h> 26 #include <linux/watchdog.h> 27 28 /* Control register 1 */ 29 #define PCF2127_REG_CTRL1 0x00 30 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 31 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 32 /* Control register 2 */ 33 #define PCF2127_REG_CTRL2 0x01 34 #define PCF2127_BIT_CTRL2_AIE BIT(1) 35 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 36 #define PCF2127_BIT_CTRL2_AF BIT(4) 37 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 38 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 39 /* Control register 3 */ 40 #define PCF2127_REG_CTRL3 0x02 41 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 42 #define PCF2127_BIT_CTRL3_BIE BIT(1) 43 #define PCF2127_BIT_CTRL3_BLF BIT(2) 44 #define PCF2127_BIT_CTRL3_BF BIT(3) 45 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 46 /* Time and date registers */ 47 #define PCF2127_REG_TIME_BASE 0x03 48 #define PCF2127_BIT_SC_OSF BIT(7) 49 /* Alarm registers */ 50 #define PCF2127_REG_ALARM_BASE 0x0A 51 #define PCF2127_BIT_ALARM_AE BIT(7) 52 /* CLKOUT control register */ 53 #define PCF2127_REG_CLKOUT 0x0f 54 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 55 /* Watchdog registers */ 56 #define PCF2127_REG_WD_CTL 0x10 57 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 58 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 59 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 60 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 61 #define PCF2127_REG_WD_VAL 0x11 62 /* Tamper timestamp registers */ 63 #define PCF2127_REG_TS_CTRL 0x12 64 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 65 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 66 /* 67 * RAM registers 68 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 69 * battery backed and can survive a power outage. 70 * PCF2129 doesn't have this feature. 71 */ 72 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 73 #define PCF2127_REG_RAM_WRT_CMD 0x1C 74 #define PCF2127_REG_RAM_RD_CMD 0x1D 75 76 /* Watchdog timer value constants */ 77 #define PCF2127_WD_VAL_STOP 0 78 #define PCF2127_WD_VAL_MIN 2 79 #define PCF2127_WD_VAL_MAX 255 80 #define PCF2127_WD_VAL_DEFAULT 60 81 82 /* Mask for currently enabled interrupts */ 83 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 84 #define PCF2127_CTRL2_IRQ_MASK ( \ 85 PCF2127_BIT_CTRL2_AF | \ 86 PCF2127_BIT_CTRL2_WDTF | \ 87 PCF2127_BIT_CTRL2_TSF2) 88 89 enum pcf21xx_type { 90 PCF2127, 91 PCF2129, 92 PCF21XX_LAST_ID 93 }; 94 95 struct pcf21xx_config { 96 int type; /* IC variant */ 97 int max_register; 98 unsigned int has_nvmem:1; 99 unsigned int has_bit_wd_ctl_cd0:1; 100 u8 reg_time_base; /* Time/date base register. */ 101 u8 regs_alarm_base; /* Alarm function base registers. */ 102 u8 reg_wd_ctl; /* Watchdog control register. */ 103 u8 reg_wd_val; /* Watchdog value register. */ 104 u8 reg_clkout; /* Clkout register. */ 105 }; 106 107 struct pcf2127 { 108 struct rtc_device *rtc; 109 struct watchdog_device wdd; 110 struct regmap *regmap; 111 const struct pcf21xx_config *cfg; 112 time64_t ts; 113 bool ts_valid; 114 bool irq_enabled; 115 }; 116 117 /* 118 * In the routines that deal directly with the pcf2127 hardware, we use 119 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 120 */ 121 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 122 { 123 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 124 unsigned char buf[7]; 125 int ret; 126 127 /* 128 * Avoid reading CTRL2 register as it causes WD_VAL register 129 * value to reset to 0 which means watchdog is stopped. 130 */ 131 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 132 buf, sizeof(buf)); 133 if (ret) { 134 dev_err(dev, "%s: read error\n", __func__); 135 return ret; 136 } 137 138 /* Clock integrity is not guaranteed when OSF flag is set. */ 139 if (buf[0] & PCF2127_BIT_SC_OSF) { 140 /* 141 * no need clear the flag here, 142 * it will be cleared once the new date is saved 143 */ 144 dev_warn(dev, 145 "oscillator stop detected, date/time is not reliable\n"); 146 return -EINVAL; 147 } 148 149 dev_dbg(dev, 150 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 151 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 152 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 153 154 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 155 tm->tm_min = bcd2bin(buf[1] & 0x7F); 156 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 157 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 158 tm->tm_wday = buf[4] & 0x07; 159 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 160 tm->tm_year = bcd2bin(buf[6]); 161 tm->tm_year += 100; 162 163 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 164 "mday=%d, mon=%d, year=%d, wday=%d\n", 165 __func__, 166 tm->tm_sec, tm->tm_min, tm->tm_hour, 167 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 168 169 return 0; 170 } 171 172 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 173 { 174 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 175 unsigned char buf[7]; 176 int i = 0, err; 177 178 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 179 "mday=%d, mon=%d, year=%d, wday=%d\n", 180 __func__, 181 tm->tm_sec, tm->tm_min, tm->tm_hour, 182 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 183 184 /* hours, minutes and seconds */ 185 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 186 buf[i++] = bin2bcd(tm->tm_min); 187 buf[i++] = bin2bcd(tm->tm_hour); 188 buf[i++] = bin2bcd(tm->tm_mday); 189 buf[i++] = tm->tm_wday & 0x07; 190 191 /* month, 1 - 12 */ 192 buf[i++] = bin2bcd(tm->tm_mon + 1); 193 194 /* year */ 195 buf[i++] = bin2bcd(tm->tm_year - 100); 196 197 /* write register's data */ 198 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 199 if (err) { 200 dev_dbg(dev, "%s: err=%d", __func__, err); 201 return err; 202 } 203 204 return 0; 205 } 206 207 static int pcf2127_rtc_ioctl(struct device *dev, 208 unsigned int cmd, unsigned long arg) 209 { 210 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 211 int val, touser = 0; 212 int ret; 213 214 switch (cmd) { 215 case RTC_VL_READ: 216 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 217 if (ret) 218 return ret; 219 220 if (val & PCF2127_BIT_CTRL3_BLF) 221 touser |= RTC_VL_BACKUP_LOW; 222 223 if (val & PCF2127_BIT_CTRL3_BF) 224 touser |= RTC_VL_BACKUP_SWITCH; 225 226 return put_user(touser, (unsigned int __user *)arg); 227 228 case RTC_VL_CLR: 229 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 230 PCF2127_BIT_CTRL3_BF, 0); 231 232 default: 233 return -ENOIOCTLCMD; 234 } 235 } 236 237 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 238 void *val, size_t bytes) 239 { 240 struct pcf2127 *pcf2127 = priv; 241 int ret; 242 unsigned char offsetbuf[] = { offset >> 8, offset }; 243 244 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 245 offsetbuf, 2); 246 if (ret) 247 return ret; 248 249 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 250 val, bytes); 251 } 252 253 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 254 void *val, size_t bytes) 255 { 256 struct pcf2127 *pcf2127 = priv; 257 int ret; 258 unsigned char offsetbuf[] = { offset >> 8, offset }; 259 260 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 261 offsetbuf, 2); 262 if (ret) 263 return ret; 264 265 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 266 val, bytes); 267 } 268 269 /* watchdog driver */ 270 271 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 272 { 273 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 274 275 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout); 276 } 277 278 /* 279 * Restart watchdog timer if feature is active. 280 * 281 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 282 * since register also contain control/status flags for other features. 283 * Always call this function after reading CTRL2 register. 284 */ 285 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 286 { 287 int ret = 0; 288 289 if (watchdog_active(wdd)) { 290 ret = pcf2127_wdt_ping(wdd); 291 if (ret) 292 dev_err(wdd->parent, 293 "%s: watchdog restart failed, ret=%d\n", 294 __func__, ret); 295 } 296 297 return ret; 298 } 299 300 static int pcf2127_wdt_start(struct watchdog_device *wdd) 301 { 302 return pcf2127_wdt_ping(wdd); 303 } 304 305 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 306 { 307 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 308 309 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 310 PCF2127_WD_VAL_STOP); 311 } 312 313 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 314 unsigned int new_timeout) 315 { 316 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 317 new_timeout, wdd->timeout); 318 319 wdd->timeout = new_timeout; 320 321 return pcf2127_wdt_active_ping(wdd); 322 } 323 324 static const struct watchdog_info pcf2127_wdt_info = { 325 .identity = "NXP PCF2127/PCF2129 Watchdog", 326 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 327 }; 328 329 static const struct watchdog_ops pcf2127_watchdog_ops = { 330 .owner = THIS_MODULE, 331 .start = pcf2127_wdt_start, 332 .stop = pcf2127_wdt_stop, 333 .ping = pcf2127_wdt_ping, 334 .set_timeout = pcf2127_wdt_set_timeout, 335 }; 336 337 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 338 { 339 u32 wdd_timeout; 340 int ret; 341 342 if (!IS_ENABLED(CONFIG_WATCHDOG) || 343 !device_property_read_bool(dev, "reset-source")) 344 return 0; 345 346 pcf2127->wdd.parent = dev; 347 pcf2127->wdd.info = &pcf2127_wdt_info; 348 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 349 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 350 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 351 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 352 pcf2127->wdd.min_hw_heartbeat_ms = 500; 353 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 354 355 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 356 357 /* Test if watchdog timer is started by bootloader */ 358 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 359 if (ret) 360 return ret; 361 362 if (wdd_timeout) 363 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 364 365 return devm_watchdog_register_device(dev, &pcf2127->wdd); 366 } 367 368 /* Alarm */ 369 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 370 { 371 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 372 u8 buf[5]; 373 unsigned int ctrl2; 374 int ret; 375 376 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 377 if (ret) 378 return ret; 379 380 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 381 if (ret) 382 return ret; 383 384 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 385 buf, sizeof(buf)); 386 if (ret) 387 return ret; 388 389 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 390 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 391 392 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 393 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 394 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 395 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 396 397 return 0; 398 } 399 400 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 401 { 402 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 403 int ret; 404 405 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 406 PCF2127_BIT_CTRL2_AIE, 407 enable ? PCF2127_BIT_CTRL2_AIE : 0); 408 if (ret) 409 return ret; 410 411 return pcf2127_wdt_active_ping(&pcf2127->wdd); 412 } 413 414 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 415 { 416 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 417 uint8_t buf[5]; 418 int ret; 419 420 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 421 PCF2127_BIT_CTRL2_AF, 0); 422 if (ret) 423 return ret; 424 425 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 426 if (ret) 427 return ret; 428 429 buf[0] = bin2bcd(alrm->time.tm_sec); 430 buf[1] = bin2bcd(alrm->time.tm_min); 431 buf[2] = bin2bcd(alrm->time.tm_hour); 432 buf[3] = bin2bcd(alrm->time.tm_mday); 433 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 434 435 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 436 buf, sizeof(buf)); 437 if (ret) 438 return ret; 439 440 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 441 } 442 443 /* 444 * This function reads ctrl2 register, caller is responsible for calling 445 * pcf2127_wdt_active_ping() 446 */ 447 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) 448 { 449 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 450 struct rtc_time tm; 451 int ret; 452 unsigned char data[7]; 453 454 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_TS_CTRL, data, 455 sizeof(data)); 456 if (ret) { 457 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 458 return ret; 459 } 460 461 dev_dbg(dev, 462 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 463 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 464 465 tm.tm_sec = bcd2bin(data[1] & 0x7F); 466 tm.tm_min = bcd2bin(data[2] & 0x7F); 467 tm.tm_hour = bcd2bin(data[3] & 0x3F); 468 tm.tm_mday = bcd2bin(data[4] & 0x3F); 469 /* TS_MO register (month) value range: 1-12 */ 470 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 471 tm.tm_year = bcd2bin(data[6]); 472 if (tm.tm_year < 70) 473 tm.tm_year += 100; /* assume we are in 1970...2069 */ 474 475 ret = rtc_valid_tm(&tm); 476 if (ret) { 477 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 478 return ret; 479 } 480 481 *ts = rtc_tm_to_time64(&tm); 482 return 0; 483 }; 484 485 static void pcf2127_rtc_ts_snapshot(struct device *dev) 486 { 487 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 488 int ret; 489 490 /* Let userspace read the first timestamp */ 491 if (pcf2127->ts_valid) 492 return; 493 494 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts); 495 if (!ret) 496 pcf2127->ts_valid = true; 497 } 498 499 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 500 { 501 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 502 unsigned int ctrl1, ctrl2; 503 int ret = 0; 504 505 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 506 if (ret) 507 return IRQ_NONE; 508 509 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 510 if (ret) 511 return IRQ_NONE; 512 513 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 514 return IRQ_NONE; 515 516 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 517 pcf2127_rtc_ts_snapshot(dev); 518 519 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 520 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 521 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 522 523 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 524 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 525 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 526 527 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 528 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 529 530 pcf2127_wdt_active_ping(&pcf2127->wdd); 531 532 return IRQ_HANDLED; 533 } 534 535 static const struct rtc_class_ops pcf2127_rtc_ops = { 536 .ioctl = pcf2127_rtc_ioctl, 537 .read_time = pcf2127_rtc_read_time, 538 .set_time = pcf2127_rtc_set_time, 539 .read_alarm = pcf2127_rtc_read_alarm, 540 .set_alarm = pcf2127_rtc_set_alarm, 541 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 542 }; 543 544 /* sysfs interface */ 545 546 static ssize_t timestamp0_store(struct device *dev, 547 struct device_attribute *attr, 548 const char *buf, size_t count) 549 { 550 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 551 int ret; 552 553 if (pcf2127->irq_enabled) { 554 pcf2127->ts_valid = false; 555 } else { 556 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 557 PCF2127_BIT_CTRL1_TSF1, 0); 558 if (ret) { 559 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 560 return ret; 561 } 562 563 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 564 PCF2127_BIT_CTRL2_TSF2, 0); 565 if (ret) { 566 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 567 return ret; 568 } 569 570 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 571 if (ret) 572 return ret; 573 } 574 575 return count; 576 }; 577 578 static ssize_t timestamp0_show(struct device *dev, 579 struct device_attribute *attr, char *buf) 580 { 581 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 582 unsigned int ctrl1, ctrl2; 583 int ret; 584 time64_t ts; 585 586 if (pcf2127->irq_enabled) { 587 if (!pcf2127->ts_valid) 588 return 0; 589 ts = pcf2127->ts; 590 } else { 591 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 592 if (ret) 593 return 0; 594 595 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 596 if (ret) 597 return 0; 598 599 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && 600 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) 601 return 0; 602 603 ret = pcf2127_rtc_ts_read(dev->parent, &ts); 604 if (ret) 605 return 0; 606 607 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 608 if (ret) 609 return ret; 610 } 611 return sprintf(buf, "%llu\n", (unsigned long long)ts); 612 }; 613 614 static DEVICE_ATTR_RW(timestamp0); 615 616 static struct attribute *pcf2127_attrs[] = { 617 &dev_attr_timestamp0.attr, 618 NULL 619 }; 620 621 static const struct attribute_group pcf2127_attr_group = { 622 .attrs = pcf2127_attrs, 623 }; 624 625 static struct pcf21xx_config pcf21xx_cfg[] = { 626 [PCF2127] = { 627 .type = PCF2127, 628 .max_register = 0x1d, 629 .has_nvmem = 1, 630 .has_bit_wd_ctl_cd0 = 1, 631 .reg_time_base = PCF2127_REG_TIME_BASE, 632 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 633 .reg_wd_ctl = PCF2127_REG_WD_CTL, 634 .reg_wd_val = PCF2127_REG_WD_VAL, 635 .reg_clkout = PCF2127_REG_CLKOUT, 636 }, 637 [PCF2129] = { 638 .type = PCF2129, 639 .max_register = 0x19, 640 .has_nvmem = 0, 641 .has_bit_wd_ctl_cd0 = 0, 642 .reg_time_base = PCF2127_REG_TIME_BASE, 643 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 644 .reg_wd_ctl = PCF2127_REG_WD_CTL, 645 .reg_wd_val = PCF2127_REG_WD_VAL, 646 .reg_clkout = PCF2127_REG_CLKOUT, 647 }, 648 }; 649 650 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 651 int alarm_irq, const char *name, const struct pcf21xx_config *config) 652 { 653 struct pcf2127 *pcf2127; 654 int ret = 0; 655 unsigned int val; 656 657 dev_dbg(dev, "%s\n", __func__); 658 659 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 660 if (!pcf2127) 661 return -ENOMEM; 662 663 pcf2127->regmap = regmap; 664 pcf2127->cfg = config; 665 666 dev_set_drvdata(dev, pcf2127); 667 668 pcf2127->rtc = devm_rtc_allocate_device(dev); 669 if (IS_ERR(pcf2127->rtc)) 670 return PTR_ERR(pcf2127->rtc); 671 672 pcf2127->rtc->ops = &pcf2127_rtc_ops; 673 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 674 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 675 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 676 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 677 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 678 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 679 680 if (alarm_irq > 0) { 681 unsigned long flags; 682 683 /* 684 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 685 * obtained from device tree. 686 */ 687 if (dev_fwnode(dev)) 688 flags = 0; 689 else 690 flags = IRQF_TRIGGER_LOW; 691 692 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 693 pcf2127_rtc_irq, 694 flags | IRQF_ONESHOT, 695 dev_name(dev), dev); 696 if (ret) { 697 dev_err(dev, "failed to request alarm irq\n"); 698 return ret; 699 } 700 pcf2127->irq_enabled = true; 701 } 702 703 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 704 device_init_wakeup(dev, true); 705 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 706 } 707 708 if (pcf2127->cfg->has_nvmem) { 709 struct nvmem_config nvmem_cfg = { 710 .priv = pcf2127, 711 .reg_read = pcf2127_nvmem_read, 712 .reg_write = pcf2127_nvmem_write, 713 .size = 512, 714 }; 715 716 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 717 } 718 719 /* 720 * The "Power-On Reset Override" facility prevents the RTC to do a reset 721 * after power on. For normal operation the PORO must be disabled. 722 */ 723 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 724 PCF2127_BIT_CTRL1_POR_OVRD); 725 726 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); 727 if (ret < 0) 728 return ret; 729 730 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 731 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, 732 PCF2127_BIT_CLKOUT_OTPR); 733 if (ret < 0) 734 return ret; 735 736 msleep(100); 737 } 738 739 /* 740 * Watchdog timer enabled and reset pin /RST activated when timed out. 741 * Select 1Hz clock source for watchdog timer. 742 * Note: Countdown timer disabled and not available. 743 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 744 * of register watchdg_tim_ctl. The bit[6] is labeled 745 * as T. Bits labeled as T must always be written with 746 * logic 0. 747 */ 748 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 749 PCF2127_BIT_WD_CTL_CD1 | 750 PCF2127_BIT_WD_CTL_CD0 | 751 PCF2127_BIT_WD_CTL_TF1 | 752 PCF2127_BIT_WD_CTL_TF0, 753 PCF2127_BIT_WD_CTL_CD1 | 754 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 755 PCF2127_BIT_WD_CTL_TF1); 756 if (ret) { 757 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 758 return ret; 759 } 760 761 pcf2127_watchdog_init(dev, pcf2127); 762 763 /* 764 * Disable battery low/switch-over timestamp and interrupts. 765 * Clear battery interrupt flags which can block new trigger events. 766 * Note: This is the default chip behaviour but added to ensure 767 * correct tamper timestamp and interrupt function. 768 */ 769 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 770 PCF2127_BIT_CTRL3_BTSE | 771 PCF2127_BIT_CTRL3_BIE | 772 PCF2127_BIT_CTRL3_BLIE, 0); 773 if (ret) { 774 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 775 __func__); 776 return ret; 777 } 778 779 /* 780 * Enable timestamp function and store timestamp of first trigger 781 * event until TSF1 and TSF2 interrupt flags are cleared. 782 */ 783 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 784 PCF2127_BIT_TS_CTRL_TSOFF | 785 PCF2127_BIT_TS_CTRL_TSM, 786 PCF2127_BIT_TS_CTRL_TSM); 787 if (ret) { 788 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 789 __func__); 790 return ret; 791 } 792 793 /* 794 * Enable interrupt generation when TSF1 or TSF2 timestamp flags 795 * are set. Interrupt signal is an open-drain output and can be 796 * left floating if unused. 797 */ 798 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 799 PCF2127_BIT_CTRL2_TSIE, 800 PCF2127_BIT_CTRL2_TSIE); 801 if (ret) { 802 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 803 __func__); 804 return ret; 805 } 806 807 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 808 if (ret) { 809 dev_err(dev, "%s: tamper sysfs registering failed\n", 810 __func__); 811 return ret; 812 } 813 814 return devm_rtc_register_device(pcf2127->rtc); 815 } 816 817 #ifdef CONFIG_OF 818 static const struct of_device_id pcf2127_of_match[] = { 819 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 820 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 821 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 822 {} 823 }; 824 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 825 #endif 826 827 #if IS_ENABLED(CONFIG_I2C) 828 829 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 830 { 831 struct device *dev = context; 832 struct i2c_client *client = to_i2c_client(dev); 833 int ret; 834 835 ret = i2c_master_send(client, data, count); 836 if (ret != count) 837 return ret < 0 ? ret : -EIO; 838 839 return 0; 840 } 841 842 static int pcf2127_i2c_gather_write(void *context, 843 const void *reg, size_t reg_size, 844 const void *val, size_t val_size) 845 { 846 struct device *dev = context; 847 struct i2c_client *client = to_i2c_client(dev); 848 int ret; 849 void *buf; 850 851 if (WARN_ON(reg_size != 1)) 852 return -EINVAL; 853 854 buf = kmalloc(val_size + 1, GFP_KERNEL); 855 if (!buf) 856 return -ENOMEM; 857 858 memcpy(buf, reg, 1); 859 memcpy(buf + 1, val, val_size); 860 861 ret = i2c_master_send(client, buf, val_size + 1); 862 863 kfree(buf); 864 865 if (ret != val_size + 1) 866 return ret < 0 ? ret : -EIO; 867 868 return 0; 869 } 870 871 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 872 void *val, size_t val_size) 873 { 874 struct device *dev = context; 875 struct i2c_client *client = to_i2c_client(dev); 876 int ret; 877 878 if (WARN_ON(reg_size != 1)) 879 return -EINVAL; 880 881 ret = i2c_master_send(client, reg, 1); 882 if (ret != 1) 883 return ret < 0 ? ret : -EIO; 884 885 ret = i2c_master_recv(client, val, val_size); 886 if (ret != val_size) 887 return ret < 0 ? ret : -EIO; 888 889 return 0; 890 } 891 892 /* 893 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 894 * is that the STOP condition is required between set register address and 895 * read register data when reading from registers. 896 */ 897 static const struct regmap_bus pcf2127_i2c_regmap = { 898 .write = pcf2127_i2c_write, 899 .gather_write = pcf2127_i2c_gather_write, 900 .read = pcf2127_i2c_read, 901 }; 902 903 static struct i2c_driver pcf2127_i2c_driver; 904 905 static const struct i2c_device_id pcf2127_i2c_id[] = { 906 { "pcf2127", PCF2127 }, 907 { "pcf2129", PCF2129 }, 908 { "pca2129", PCF2129 }, 909 { } 910 }; 911 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 912 913 static int pcf2127_i2c_probe(struct i2c_client *client) 914 { 915 struct regmap *regmap; 916 static struct regmap_config config = { 917 .reg_bits = 8, 918 .val_bits = 8, 919 }; 920 const struct pcf21xx_config *variant; 921 922 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 923 return -ENODEV; 924 925 if (client->dev.of_node) { 926 variant = of_device_get_match_data(&client->dev); 927 if (!variant) 928 return -ENODEV; 929 } else { 930 enum pcf21xx_type type = 931 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 932 933 if (type >= PCF21XX_LAST_ID) 934 return -ENODEV; 935 variant = &pcf21xx_cfg[type]; 936 } 937 938 config.max_register = variant->max_register, 939 940 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 941 &client->dev, &config); 942 if (IS_ERR(regmap)) { 943 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 944 __func__, PTR_ERR(regmap)); 945 return PTR_ERR(regmap); 946 } 947 948 return pcf2127_probe(&client->dev, regmap, client->irq, 949 pcf2127_i2c_driver.driver.name, variant); 950 } 951 952 static struct i2c_driver pcf2127_i2c_driver = { 953 .driver = { 954 .name = "rtc-pcf2127-i2c", 955 .of_match_table = of_match_ptr(pcf2127_of_match), 956 }, 957 .probe = pcf2127_i2c_probe, 958 .id_table = pcf2127_i2c_id, 959 }; 960 961 static int pcf2127_i2c_register_driver(void) 962 { 963 return i2c_add_driver(&pcf2127_i2c_driver); 964 } 965 966 static void pcf2127_i2c_unregister_driver(void) 967 { 968 i2c_del_driver(&pcf2127_i2c_driver); 969 } 970 971 #else 972 973 static int pcf2127_i2c_register_driver(void) 974 { 975 return 0; 976 } 977 978 static void pcf2127_i2c_unregister_driver(void) 979 { 980 } 981 982 #endif 983 984 #if IS_ENABLED(CONFIG_SPI_MASTER) 985 986 static struct spi_driver pcf2127_spi_driver; 987 static const struct spi_device_id pcf2127_spi_id[]; 988 989 static int pcf2127_spi_probe(struct spi_device *spi) 990 { 991 static struct regmap_config config = { 992 .reg_bits = 8, 993 .val_bits = 8, 994 .read_flag_mask = 0xa0, 995 .write_flag_mask = 0x20, 996 }; 997 struct regmap *regmap; 998 const struct pcf21xx_config *variant; 999 1000 if (spi->dev.of_node) { 1001 variant = of_device_get_match_data(&spi->dev); 1002 if (!variant) 1003 return -ENODEV; 1004 } else { 1005 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1006 1007 if (type >= PCF21XX_LAST_ID) 1008 return -ENODEV; 1009 variant = &pcf21xx_cfg[type]; 1010 } 1011 1012 config.max_register = variant->max_register, 1013 1014 regmap = devm_regmap_init_spi(spi, &config); 1015 if (IS_ERR(regmap)) { 1016 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1017 __func__, PTR_ERR(regmap)); 1018 return PTR_ERR(regmap); 1019 } 1020 1021 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1022 pcf2127_spi_driver.driver.name, 1023 variant); 1024 } 1025 1026 static const struct spi_device_id pcf2127_spi_id[] = { 1027 { "pcf2127", PCF2127 }, 1028 { "pcf2129", PCF2129 }, 1029 { "pca2129", PCF2129 }, 1030 { } 1031 }; 1032 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1033 1034 static struct spi_driver pcf2127_spi_driver = { 1035 .driver = { 1036 .name = "rtc-pcf2127-spi", 1037 .of_match_table = of_match_ptr(pcf2127_of_match), 1038 }, 1039 .probe = pcf2127_spi_probe, 1040 .id_table = pcf2127_spi_id, 1041 }; 1042 1043 static int pcf2127_spi_register_driver(void) 1044 { 1045 return spi_register_driver(&pcf2127_spi_driver); 1046 } 1047 1048 static void pcf2127_spi_unregister_driver(void) 1049 { 1050 spi_unregister_driver(&pcf2127_spi_driver); 1051 } 1052 1053 #else 1054 1055 static int pcf2127_spi_register_driver(void) 1056 { 1057 return 0; 1058 } 1059 1060 static void pcf2127_spi_unregister_driver(void) 1061 { 1062 } 1063 1064 #endif 1065 1066 static int __init pcf2127_init(void) 1067 { 1068 int ret; 1069 1070 ret = pcf2127_i2c_register_driver(); 1071 if (ret) { 1072 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1073 return ret; 1074 } 1075 1076 ret = pcf2127_spi_register_driver(); 1077 if (ret) { 1078 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1079 pcf2127_i2c_unregister_driver(); 1080 } 1081 1082 return ret; 1083 } 1084 module_init(pcf2127_init) 1085 1086 static void __exit pcf2127_exit(void) 1087 { 1088 pcf2127_spi_unregister_driver(); 1089 pcf2127_i2c_unregister_driver(); 1090 } 1091 module_exit(pcf2127_exit) 1092 1093 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1094 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 1095 MODULE_LICENSE("GPL v2"); 1096