1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * PCF2131 support 12 * Author: Hugo Villeneuve <[email protected]> 13 * 14 * based on the other drivers in this same directory. 15 * 16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/spi/spi.h> 22 #include <linux/bcd.h> 23 #include <linux/rtc.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_device.h> 29 #include <linux/regmap.h> 30 #include <linux/watchdog.h> 31 32 /* Control register 1 */ 33 #define PCF2127_REG_CTRL1 0x00 34 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 35 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 36 /* Control register 2 */ 37 #define PCF2127_REG_CTRL2 0x01 38 #define PCF2127_BIT_CTRL2_AIE BIT(1) 39 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 40 #define PCF2127_BIT_CTRL2_AF BIT(4) 41 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 42 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 43 /* Control register 3 */ 44 #define PCF2127_REG_CTRL3 0x02 45 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 46 #define PCF2127_BIT_CTRL3_BIE BIT(1) 47 #define PCF2127_BIT_CTRL3_BLF BIT(2) 48 #define PCF2127_BIT_CTRL3_BF BIT(3) 49 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 50 /* Time and date registers */ 51 #define PCF2127_REG_TIME_BASE 0x03 52 #define PCF2127_BIT_SC_OSF BIT(7) 53 /* Alarm registers */ 54 #define PCF2127_REG_ALARM_BASE 0x0A 55 #define PCF2127_BIT_ALARM_AE BIT(7) 56 /* CLKOUT control register */ 57 #define PCF2127_REG_CLKOUT 0x0f 58 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 59 /* Watchdog registers */ 60 #define PCF2127_REG_WD_CTL 0x10 61 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 62 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 63 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 64 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 65 #define PCF2127_REG_WD_VAL 0x11 66 /* Tamper timestamp1 registers */ 67 #define PCF2127_REG_TS1_BASE 0x12 68 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 69 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 70 /* 71 * RAM registers 72 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 73 * battery backed and can survive a power outage. 74 * PCF2129/31 doesn't have this feature. 75 */ 76 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 77 #define PCF2127_REG_RAM_WRT_CMD 0x1C 78 #define PCF2127_REG_RAM_RD_CMD 0x1D 79 80 /* Watchdog timer value constants */ 81 #define PCF2127_WD_VAL_STOP 0 82 #define PCF2127_WD_VAL_MIN 2 83 #define PCF2127_WD_VAL_MAX 255 84 #define PCF2127_WD_VAL_DEFAULT 60 85 86 /* Mask for currently enabled interrupts */ 87 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 88 #define PCF2127_CTRL2_IRQ_MASK ( \ 89 PCF2127_BIT_CTRL2_AF | \ 90 PCF2127_BIT_CTRL2_WDTF | \ 91 PCF2127_BIT_CTRL2_TSF2) 92 93 #define PCF2127_MAX_TS_SUPPORTED 4 94 95 /* Control register 4 */ 96 #define PCF2131_REG_CTRL4 0x03 97 #define PCF2131_BIT_CTRL4_TSF4 BIT(4) 98 #define PCF2131_BIT_CTRL4_TSF3 BIT(5) 99 #define PCF2131_BIT_CTRL4_TSF2 BIT(6) 100 #define PCF2131_BIT_CTRL4_TSF1 BIT(7) 101 /* Control register 5 */ 102 #define PCF2131_REG_CTRL5 0x04 103 #define PCF2131_BIT_CTRL5_TSIE4 BIT(4) 104 #define PCF2131_BIT_CTRL5_TSIE3 BIT(5) 105 #define PCF2131_BIT_CTRL5_TSIE2 BIT(6) 106 #define PCF2131_BIT_CTRL5_TSIE1 BIT(7) 107 /* Software reset register */ 108 #define PCF2131_REG_SR_RESET 0x05 109 #define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5)) 110 #define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7)) 111 /* Time and date registers */ 112 #define PCF2131_REG_TIME_BASE 0x07 113 /* Alarm registers */ 114 #define PCF2131_REG_ALARM_BASE 0x0E 115 /* CLKOUT control register */ 116 #define PCF2131_REG_CLKOUT 0x13 117 /* Watchdog registers */ 118 #define PCF2131_REG_WD_CTL 0x35 119 #define PCF2131_REG_WD_VAL 0x36 120 /* Tamper timestamp1 registers */ 121 #define PCF2131_REG_TS1_BASE 0x14 122 /* Tamper timestamp2 registers */ 123 #define PCF2131_REG_TS2_BASE 0x1B 124 /* Tamper timestamp3 registers */ 125 #define PCF2131_REG_TS3_BASE 0x22 126 /* Tamper timestamp4 registers */ 127 #define PCF2131_REG_TS4_BASE 0x29 128 /* Interrupt mask registers */ 129 #define PCF2131_REG_INT_A_MASK1 0x31 130 #define PCF2131_REG_INT_A_MASK2 0x32 131 #define PCF2131_REG_INT_B_MASK1 0x33 132 #define PCF2131_REG_INT_B_MASK2 0x34 133 #define PCF2131_BIT_INT_BLIE BIT(0) 134 #define PCF2131_BIT_INT_BIE BIT(1) 135 #define PCF2131_BIT_INT_AIE BIT(2) 136 #define PCF2131_BIT_INT_WD_CD BIT(3) 137 #define PCF2131_BIT_INT_SI BIT(4) 138 #define PCF2131_BIT_INT_MI BIT(5) 139 #define PCF2131_CTRL2_IRQ_MASK ( \ 140 PCF2127_BIT_CTRL2_AF | \ 141 PCF2127_BIT_CTRL2_WDTF) 142 #define PCF2131_CTRL4_IRQ_MASK ( \ 143 PCF2131_BIT_CTRL4_TSF4 | \ 144 PCF2131_BIT_CTRL4_TSF3 | \ 145 PCF2131_BIT_CTRL4_TSF2 | \ 146 PCF2131_BIT_CTRL4_TSF1) 147 148 enum pcf21xx_type { 149 PCF2127, 150 PCF2129, 151 PCF2131, 152 PCF21XX_LAST_ID 153 }; 154 155 struct pcf21xx_ts_config { 156 u8 reg_base; /* Base register to read timestamp values. */ 157 158 /* 159 * If the TS input pin is driven to GND, an interrupt can be generated 160 * (supported by all variants). 161 */ 162 u8 gnd_detect_reg; /* Interrupt control register address. */ 163 u8 gnd_detect_bit; /* Interrupt bit. */ 164 165 /* 166 * If the TS input pin is driven to an intermediate level between GND 167 * and supply, an interrupt can be generated (optional feature depending 168 * on variant). 169 */ 170 u8 inter_detect_reg; /* Interrupt control register address. */ 171 u8 inter_detect_bit; /* Interrupt bit. */ 172 173 u8 ie_reg; /* Interrupt enable control register. */ 174 u8 ie_bit; /* Interrupt enable bit. */ 175 }; 176 177 struct pcf21xx_config { 178 int type; /* IC variant */ 179 int max_register; 180 unsigned int has_nvmem:1; 181 unsigned int has_bit_wd_ctl_cd0:1; 182 unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */ 183 u8 reg_time_base; /* Time/date base register. */ 184 u8 regs_alarm_base; /* Alarm function base registers. */ 185 u8 reg_wd_ctl; /* Watchdog control register. */ 186 u8 reg_wd_val; /* Watchdog value register. */ 187 u8 reg_clkout; /* Clkout register. */ 188 unsigned int ts_count; 189 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED]; 190 struct attribute_group attribute_group; 191 }; 192 193 struct pcf2127 { 194 struct rtc_device *rtc; 195 struct watchdog_device wdd; 196 struct regmap *regmap; 197 const struct pcf21xx_config *cfg; 198 bool irq_enabled; 199 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */ 200 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */ 201 }; 202 203 /* 204 * In the routines that deal directly with the pcf2127 hardware, we use 205 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 206 */ 207 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 208 { 209 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 210 unsigned char buf[7]; 211 int ret; 212 213 /* 214 * Avoid reading CTRL2 register as it causes WD_VAL register 215 * value to reset to 0 which means watchdog is stopped. 216 */ 217 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 218 buf, sizeof(buf)); 219 if (ret) { 220 dev_err(dev, "%s: read error\n", __func__); 221 return ret; 222 } 223 224 /* Clock integrity is not guaranteed when OSF flag is set. */ 225 if (buf[0] & PCF2127_BIT_SC_OSF) { 226 /* 227 * no need clear the flag here, 228 * it will be cleared once the new date is saved 229 */ 230 dev_warn(dev, 231 "oscillator stop detected, date/time is not reliable\n"); 232 return -EINVAL; 233 } 234 235 dev_dbg(dev, 236 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 237 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 238 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 239 240 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 241 tm->tm_min = bcd2bin(buf[1] & 0x7F); 242 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 243 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 244 tm->tm_wday = buf[4] & 0x07; 245 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 246 tm->tm_year = bcd2bin(buf[6]); 247 tm->tm_year += 100; 248 249 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 250 "mday=%d, mon=%d, year=%d, wday=%d\n", 251 __func__, 252 tm->tm_sec, tm->tm_min, tm->tm_hour, 253 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 254 255 return 0; 256 } 257 258 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 259 { 260 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 261 unsigned char buf[7]; 262 int i = 0, err; 263 264 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 265 "mday=%d, mon=%d, year=%d, wday=%d\n", 266 __func__, 267 tm->tm_sec, tm->tm_min, tm->tm_hour, 268 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 269 270 /* hours, minutes and seconds */ 271 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 272 buf[i++] = bin2bcd(tm->tm_min); 273 buf[i++] = bin2bcd(tm->tm_hour); 274 buf[i++] = bin2bcd(tm->tm_mday); 275 buf[i++] = tm->tm_wday & 0x07; 276 277 /* month, 1 - 12 */ 278 buf[i++] = bin2bcd(tm->tm_mon + 1); 279 280 /* year */ 281 buf[i++] = bin2bcd(tm->tm_year - 100); 282 283 /* write register's data */ 284 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 285 if (err) { 286 dev_dbg(dev, "%s: err=%d", __func__, err); 287 return err; 288 } 289 290 return 0; 291 } 292 293 static int pcf2127_rtc_ioctl(struct device *dev, 294 unsigned int cmd, unsigned long arg) 295 { 296 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 297 int val, touser = 0; 298 int ret; 299 300 switch (cmd) { 301 case RTC_VL_READ: 302 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 303 if (ret) 304 return ret; 305 306 if (val & PCF2127_BIT_CTRL3_BLF) 307 touser |= RTC_VL_BACKUP_LOW; 308 309 if (val & PCF2127_BIT_CTRL3_BF) 310 touser |= RTC_VL_BACKUP_SWITCH; 311 312 return put_user(touser, (unsigned int __user *)arg); 313 314 case RTC_VL_CLR: 315 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 316 PCF2127_BIT_CTRL3_BF, 0); 317 318 default: 319 return -ENOIOCTLCMD; 320 } 321 } 322 323 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 324 void *val, size_t bytes) 325 { 326 struct pcf2127 *pcf2127 = priv; 327 int ret; 328 unsigned char offsetbuf[] = { offset >> 8, offset }; 329 330 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 331 offsetbuf, 2); 332 if (ret) 333 return ret; 334 335 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 336 val, bytes); 337 } 338 339 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 340 void *val, size_t bytes) 341 { 342 struct pcf2127 *pcf2127 = priv; 343 int ret; 344 unsigned char offsetbuf[] = { offset >> 8, offset }; 345 346 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 347 offsetbuf, 2); 348 if (ret) 349 return ret; 350 351 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 352 val, bytes); 353 } 354 355 /* watchdog driver */ 356 357 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 358 { 359 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 360 361 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout); 362 } 363 364 /* 365 * Restart watchdog timer if feature is active. 366 * 367 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 368 * since register also contain control/status flags for other features. 369 * Always call this function after reading CTRL2 register. 370 */ 371 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 372 { 373 int ret = 0; 374 375 if (watchdog_active(wdd)) { 376 ret = pcf2127_wdt_ping(wdd); 377 if (ret) 378 dev_err(wdd->parent, 379 "%s: watchdog restart failed, ret=%d\n", 380 __func__, ret); 381 } 382 383 return ret; 384 } 385 386 static int pcf2127_wdt_start(struct watchdog_device *wdd) 387 { 388 return pcf2127_wdt_ping(wdd); 389 } 390 391 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 392 { 393 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 394 395 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 396 PCF2127_WD_VAL_STOP); 397 } 398 399 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 400 unsigned int new_timeout) 401 { 402 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 403 new_timeout, wdd->timeout); 404 405 wdd->timeout = new_timeout; 406 407 return pcf2127_wdt_active_ping(wdd); 408 } 409 410 static const struct watchdog_info pcf2127_wdt_info = { 411 .identity = "NXP PCF2127/PCF2129 Watchdog", 412 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 413 }; 414 415 static const struct watchdog_ops pcf2127_watchdog_ops = { 416 .owner = THIS_MODULE, 417 .start = pcf2127_wdt_start, 418 .stop = pcf2127_wdt_stop, 419 .ping = pcf2127_wdt_ping, 420 .set_timeout = pcf2127_wdt_set_timeout, 421 }; 422 423 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 424 { 425 u32 wdd_timeout; 426 int ret; 427 428 if (!IS_ENABLED(CONFIG_WATCHDOG) || 429 !device_property_read_bool(dev, "reset-source")) 430 return 0; 431 432 pcf2127->wdd.parent = dev; 433 pcf2127->wdd.info = &pcf2127_wdt_info; 434 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 435 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 436 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 437 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 438 pcf2127->wdd.min_hw_heartbeat_ms = 500; 439 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 440 441 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 442 443 /* Test if watchdog timer is started by bootloader */ 444 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 445 if (ret) 446 return ret; 447 448 if (wdd_timeout) 449 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 450 451 return devm_watchdog_register_device(dev, &pcf2127->wdd); 452 } 453 454 /* Alarm */ 455 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 456 { 457 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 458 u8 buf[5]; 459 unsigned int ctrl2; 460 int ret; 461 462 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 463 if (ret) 464 return ret; 465 466 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 467 if (ret) 468 return ret; 469 470 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 471 buf, sizeof(buf)); 472 if (ret) 473 return ret; 474 475 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 476 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 477 478 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 479 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 480 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 481 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 482 483 return 0; 484 } 485 486 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 487 { 488 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 489 int ret; 490 491 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 492 PCF2127_BIT_CTRL2_AIE, 493 enable ? PCF2127_BIT_CTRL2_AIE : 0); 494 if (ret) 495 return ret; 496 497 return pcf2127_wdt_active_ping(&pcf2127->wdd); 498 } 499 500 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 501 { 502 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 503 uint8_t buf[5]; 504 int ret; 505 506 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 507 PCF2127_BIT_CTRL2_AF, 0); 508 if (ret) 509 return ret; 510 511 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 512 if (ret) 513 return ret; 514 515 buf[0] = bin2bcd(alrm->time.tm_sec); 516 buf[1] = bin2bcd(alrm->time.tm_min); 517 buf[2] = bin2bcd(alrm->time.tm_hour); 518 buf[3] = bin2bcd(alrm->time.tm_mday); 519 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 520 521 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 522 buf, sizeof(buf)); 523 if (ret) 524 return ret; 525 526 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 527 } 528 529 /* 530 * This function reads one timestamp function data, caller is responsible for 531 * calling pcf2127_wdt_active_ping() 532 */ 533 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts, 534 int ts_id) 535 { 536 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 537 struct rtc_time tm; 538 int ret; 539 unsigned char data[7]; 540 541 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base, 542 data, sizeof(data)); 543 if (ret) { 544 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 545 return ret; 546 } 547 548 dev_dbg(dev, 549 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 550 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 551 552 tm.tm_sec = bcd2bin(data[1] & 0x7F); 553 tm.tm_min = bcd2bin(data[2] & 0x7F); 554 tm.tm_hour = bcd2bin(data[3] & 0x3F); 555 tm.tm_mday = bcd2bin(data[4] & 0x3F); 556 /* TS_MO register (month) value range: 1-12 */ 557 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 558 tm.tm_year = bcd2bin(data[6]); 559 if (tm.tm_year < 70) 560 tm.tm_year += 100; /* assume we are in 1970...2069 */ 561 562 ret = rtc_valid_tm(&tm); 563 if (ret) { 564 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 565 return ret; 566 } 567 568 *ts = rtc_tm_to_time64(&tm); 569 return 0; 570 }; 571 572 static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id) 573 { 574 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 575 int ret; 576 577 if (ts_id >= pcf2127->cfg->ts_count) 578 return; 579 580 /* Let userspace read the first timestamp */ 581 if (pcf2127->ts_valid[ts_id]) 582 return; 583 584 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id); 585 if (!ret) 586 pcf2127->ts_valid[ts_id] = true; 587 } 588 589 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 590 { 591 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 592 unsigned int ctrl2; 593 int ret = 0; 594 595 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 596 if (ret) 597 return IRQ_NONE; 598 599 if (pcf2127->cfg->ts_count == 1) { 600 /* PCF2127/29 */ 601 unsigned int ctrl1; 602 603 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 604 if (ret) 605 return IRQ_NONE; 606 607 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 608 return IRQ_NONE; 609 610 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 611 pcf2127_rtc_ts_snapshot(dev, 0); 612 613 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 614 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 615 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 616 617 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 618 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 619 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 620 } else { 621 /* PCF2131. */ 622 unsigned int ctrl4; 623 624 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4); 625 if (ret) 626 return IRQ_NONE; 627 628 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK)) 629 return IRQ_NONE; 630 631 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) { 632 int i; 633 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */ 634 635 for (i = 0; i < pcf2127->cfg->ts_count; i++) { 636 if (ctrl4 & tsf_bit) 637 pcf2127_rtc_ts_snapshot(dev, i); 638 639 tsf_bit = tsf_bit >> 1; 640 } 641 642 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4, 643 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK); 644 } 645 646 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK) 647 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 648 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK); 649 } 650 651 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 652 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 653 654 pcf2127_wdt_active_ping(&pcf2127->wdd); 655 656 return IRQ_HANDLED; 657 } 658 659 static const struct rtc_class_ops pcf2127_rtc_ops = { 660 .ioctl = pcf2127_rtc_ioctl, 661 .read_time = pcf2127_rtc_read_time, 662 .set_time = pcf2127_rtc_set_time, 663 .read_alarm = pcf2127_rtc_read_alarm, 664 .set_alarm = pcf2127_rtc_set_alarm, 665 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 666 }; 667 668 /* sysfs interface */ 669 670 static ssize_t timestamp_store(struct device *dev, 671 struct device_attribute *attr, 672 const char *buf, size_t count, int ts_id) 673 { 674 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 675 int ret; 676 677 if (ts_id >= pcf2127->cfg->ts_count) 678 return 0; 679 680 if (pcf2127->irq_enabled) { 681 pcf2127->ts_valid[ts_id] = false; 682 } else { 683 /* Always clear GND interrupt bit. */ 684 ret = regmap_update_bits(pcf2127->regmap, 685 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 686 pcf2127->cfg->ts[ts_id].gnd_detect_bit, 687 0); 688 689 if (ret) { 690 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret); 691 return ret; 692 } 693 694 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 695 /* Clear intermediate level interrupt bit if supported. */ 696 ret = regmap_update_bits(pcf2127->regmap, 697 pcf2127->cfg->ts[ts_id].inter_detect_reg, 698 pcf2127->cfg->ts[ts_id].inter_detect_bit, 699 0); 700 if (ret) { 701 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n", 702 __func__, ret); 703 return ret; 704 } 705 } 706 707 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 708 if (ret) 709 return ret; 710 } 711 712 return count; 713 } 714 715 static ssize_t timestamp0_store(struct device *dev, 716 struct device_attribute *attr, 717 const char *buf, size_t count) 718 { 719 return timestamp_store(dev, attr, buf, count, 0); 720 }; 721 722 static ssize_t timestamp1_store(struct device *dev, 723 struct device_attribute *attr, 724 const char *buf, size_t count) 725 { 726 return timestamp_store(dev, attr, buf, count, 1); 727 }; 728 729 static ssize_t timestamp2_store(struct device *dev, 730 struct device_attribute *attr, 731 const char *buf, size_t count) 732 { 733 return timestamp_store(dev, attr, buf, count, 2); 734 }; 735 736 static ssize_t timestamp3_store(struct device *dev, 737 struct device_attribute *attr, 738 const char *buf, size_t count) 739 { 740 return timestamp_store(dev, attr, buf, count, 3); 741 }; 742 743 static ssize_t timestamp_show(struct device *dev, 744 struct device_attribute *attr, char *buf, 745 int ts_id) 746 { 747 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 748 int ret; 749 time64_t ts; 750 751 if (ts_id >= pcf2127->cfg->ts_count) 752 return 0; 753 754 if (pcf2127->irq_enabled) { 755 if (!pcf2127->ts_valid[ts_id]) 756 return 0; 757 ts = pcf2127->ts[ts_id]; 758 } else { 759 u8 valid_low = 0; 760 u8 valid_inter = 0; 761 unsigned int ctrl; 762 763 /* Check if TS input pin is driven to GND, supported by all 764 * variants. 765 */ 766 ret = regmap_read(pcf2127->regmap, 767 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 768 &ctrl); 769 if (ret) 770 return 0; 771 772 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit; 773 774 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 775 /* Check if TS input pin is driven to intermediate level 776 * between GND and supply, if supported by variant. 777 */ 778 ret = regmap_read(pcf2127->regmap, 779 pcf2127->cfg->ts[ts_id].inter_detect_reg, 780 &ctrl); 781 if (ret) 782 return 0; 783 784 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit; 785 } 786 787 if (!valid_low && !valid_inter) 788 return 0; 789 790 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id); 791 if (ret) 792 return 0; 793 794 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 795 if (ret) 796 return ret; 797 } 798 return sprintf(buf, "%llu\n", (unsigned long long)ts); 799 } 800 801 static ssize_t timestamp0_show(struct device *dev, 802 struct device_attribute *attr, char *buf) 803 { 804 return timestamp_show(dev, attr, buf, 0); 805 }; 806 807 static ssize_t timestamp1_show(struct device *dev, 808 struct device_attribute *attr, char *buf) 809 { 810 return timestamp_show(dev, attr, buf, 1); 811 }; 812 813 static ssize_t timestamp2_show(struct device *dev, 814 struct device_attribute *attr, char *buf) 815 { 816 return timestamp_show(dev, attr, buf, 2); 817 }; 818 819 static ssize_t timestamp3_show(struct device *dev, 820 struct device_attribute *attr, char *buf) 821 { 822 return timestamp_show(dev, attr, buf, 3); 823 }; 824 825 static DEVICE_ATTR_RW(timestamp0); 826 static DEVICE_ATTR_RW(timestamp1); 827 static DEVICE_ATTR_RW(timestamp2); 828 static DEVICE_ATTR_RW(timestamp3); 829 830 static struct attribute *pcf2127_attrs[] = { 831 &dev_attr_timestamp0.attr, 832 NULL 833 }; 834 835 static struct attribute *pcf2131_attrs[] = { 836 &dev_attr_timestamp0.attr, 837 &dev_attr_timestamp1.attr, 838 &dev_attr_timestamp2.attr, 839 &dev_attr_timestamp3.attr, 840 NULL 841 }; 842 843 static struct pcf21xx_config pcf21xx_cfg[] = { 844 [PCF2127] = { 845 .type = PCF2127, 846 .max_register = 0x1d, 847 .has_nvmem = 1, 848 .has_bit_wd_ctl_cd0 = 1, 849 .has_int_a_b = 0, 850 .reg_time_base = PCF2127_REG_TIME_BASE, 851 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 852 .reg_wd_ctl = PCF2127_REG_WD_CTL, 853 .reg_wd_val = PCF2127_REG_WD_VAL, 854 .reg_clkout = PCF2127_REG_CLKOUT, 855 .ts_count = 1, 856 .ts[0] = { 857 .reg_base = PCF2127_REG_TS1_BASE, 858 .gnd_detect_reg = PCF2127_REG_CTRL1, 859 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 860 .inter_detect_reg = PCF2127_REG_CTRL2, 861 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 862 .ie_reg = PCF2127_REG_CTRL2, 863 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 864 }, 865 .attribute_group = { 866 .attrs = pcf2127_attrs, 867 }, 868 }, 869 [PCF2129] = { 870 .type = PCF2129, 871 .max_register = 0x19, 872 .has_nvmem = 0, 873 .has_bit_wd_ctl_cd0 = 0, 874 .has_int_a_b = 0, 875 .reg_time_base = PCF2127_REG_TIME_BASE, 876 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 877 .reg_wd_ctl = PCF2127_REG_WD_CTL, 878 .reg_wd_val = PCF2127_REG_WD_VAL, 879 .reg_clkout = PCF2127_REG_CLKOUT, 880 .ts_count = 1, 881 .ts[0] = { 882 .reg_base = PCF2127_REG_TS1_BASE, 883 .gnd_detect_reg = PCF2127_REG_CTRL1, 884 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 885 .inter_detect_reg = PCF2127_REG_CTRL2, 886 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 887 .ie_reg = PCF2127_REG_CTRL2, 888 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 889 }, 890 .attribute_group = { 891 .attrs = pcf2127_attrs, 892 }, 893 }, 894 [PCF2131] = { 895 .type = PCF2131, 896 .max_register = 0x36, 897 .has_nvmem = 0, 898 .has_bit_wd_ctl_cd0 = 0, 899 .has_int_a_b = 1, 900 .reg_time_base = PCF2131_REG_TIME_BASE, 901 .regs_alarm_base = PCF2131_REG_ALARM_BASE, 902 .reg_wd_ctl = PCF2131_REG_WD_CTL, 903 .reg_wd_val = PCF2131_REG_WD_VAL, 904 .reg_clkout = PCF2131_REG_CLKOUT, 905 .ts_count = 4, 906 .ts[0] = { 907 .reg_base = PCF2131_REG_TS1_BASE, 908 .gnd_detect_reg = PCF2131_REG_CTRL4, 909 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1, 910 .inter_detect_bit = 0, 911 .ie_reg = PCF2131_REG_CTRL5, 912 .ie_bit = PCF2131_BIT_CTRL5_TSIE1, 913 }, 914 .ts[1] = { 915 .reg_base = PCF2131_REG_TS2_BASE, 916 .gnd_detect_reg = PCF2131_REG_CTRL4, 917 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2, 918 .inter_detect_bit = 0, 919 .ie_reg = PCF2131_REG_CTRL5, 920 .ie_bit = PCF2131_BIT_CTRL5_TSIE2, 921 }, 922 .ts[2] = { 923 .reg_base = PCF2131_REG_TS3_BASE, 924 .gnd_detect_reg = PCF2131_REG_CTRL4, 925 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3, 926 .inter_detect_bit = 0, 927 .ie_reg = PCF2131_REG_CTRL5, 928 .ie_bit = PCF2131_BIT_CTRL5_TSIE3, 929 }, 930 .ts[3] = { 931 .reg_base = PCF2131_REG_TS4_BASE, 932 .gnd_detect_reg = PCF2131_REG_CTRL4, 933 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4, 934 .inter_detect_bit = 0, 935 .ie_reg = PCF2131_REG_CTRL5, 936 .ie_bit = PCF2131_BIT_CTRL5_TSIE4, 937 }, 938 .attribute_group = { 939 .attrs = pcf2131_attrs, 940 }, 941 }, 942 }; 943 944 /* 945 * Enable timestamp function and corresponding interrupt(s). 946 */ 947 static int pcf2127_enable_ts(struct device *dev, int ts_id) 948 { 949 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 950 int ret; 951 952 if (ts_id >= pcf2127->cfg->ts_count) { 953 dev_err(dev, "%s: invalid tamper detection ID (%d)\n", 954 __func__, ts_id); 955 return -EINVAL; 956 } 957 958 /* Enable timestamp function. */ 959 ret = regmap_update_bits(pcf2127->regmap, 960 pcf2127->cfg->ts[ts_id].reg_base, 961 PCF2127_BIT_TS_CTRL_TSOFF | 962 PCF2127_BIT_TS_CTRL_TSM, 963 PCF2127_BIT_TS_CTRL_TSM); 964 if (ret) { 965 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n", 966 __func__, ts_id); 967 return ret; 968 } 969 970 /* TS input pin driven to GND detection is supported by all variants. 971 * Make sure that interrupt bit is defined. 972 */ 973 if (pcf2127->cfg->ts[ts_id].gnd_detect_bit == 0) { 974 dev_err(dev, "%s: tamper detection to GND configuration invalid\n", 975 __func__); 976 return ret; 977 } 978 979 /* 980 * Enable interrupt generation when TSF timestamp flag is set. 981 * Interrupt signals are open-drain outputs and can be left floating if 982 * unused. 983 */ 984 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg, 985 pcf2127->cfg->ts[ts_id].ie_bit, 986 pcf2127->cfg->ts[ts_id].ie_bit); 987 if (ret) { 988 dev_err(dev, "%s: tamper detection TSIE%d config failed\n", 989 __func__, ts_id); 990 return ret; 991 } 992 993 return ret; 994 } 995 996 /* Route all interrupt sources to INT A pin. */ 997 static int pcf2127_configure_interrupt_pins(struct device *dev) 998 { 999 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 1000 int ret; 1001 1002 /* Mask bits need to be cleared to enable corresponding 1003 * interrupt source. 1004 */ 1005 ret = regmap_write(pcf2127->regmap, 1006 PCF2131_REG_INT_A_MASK1, 0); 1007 if (ret) 1008 return ret; 1009 1010 ret = regmap_write(pcf2127->regmap, 1011 PCF2131_REG_INT_A_MASK2, 0); 1012 if (ret) 1013 return ret; 1014 1015 return ret; 1016 } 1017 1018 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 1019 int alarm_irq, const char *name, const struct pcf21xx_config *config) 1020 { 1021 struct pcf2127 *pcf2127; 1022 int ret = 0; 1023 unsigned int val; 1024 1025 dev_dbg(dev, "%s\n", __func__); 1026 1027 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 1028 if (!pcf2127) 1029 return -ENOMEM; 1030 1031 pcf2127->regmap = regmap; 1032 pcf2127->cfg = config; 1033 1034 dev_set_drvdata(dev, pcf2127); 1035 1036 pcf2127->rtc = devm_rtc_allocate_device(dev); 1037 if (IS_ERR(pcf2127->rtc)) 1038 return PTR_ERR(pcf2127->rtc); 1039 1040 pcf2127->rtc->ops = &pcf2127_rtc_ops; 1041 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 1042 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 1043 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 1044 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 1045 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 1046 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1047 1048 if (alarm_irq > 0) { 1049 unsigned long flags; 1050 1051 /* 1052 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 1053 * obtained from device tree. 1054 */ 1055 if (dev_fwnode(dev)) 1056 flags = 0; 1057 else 1058 flags = IRQF_TRIGGER_LOW; 1059 1060 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 1061 pcf2127_rtc_irq, 1062 flags | IRQF_ONESHOT, 1063 dev_name(dev), dev); 1064 if (ret) { 1065 dev_err(dev, "failed to request alarm irq\n"); 1066 return ret; 1067 } 1068 pcf2127->irq_enabled = true; 1069 } 1070 1071 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 1072 device_init_wakeup(dev, true); 1073 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1074 } 1075 1076 if (pcf2127->cfg->has_int_a_b) { 1077 /* Configure int A/B pins, independently of alarm_irq. */ 1078 ret = pcf2127_configure_interrupt_pins(dev); 1079 if (ret) { 1080 dev_err(dev, "failed to configure interrupt pins\n"); 1081 return ret; 1082 } 1083 } 1084 1085 if (pcf2127->cfg->has_nvmem) { 1086 struct nvmem_config nvmem_cfg = { 1087 .priv = pcf2127, 1088 .reg_read = pcf2127_nvmem_read, 1089 .reg_write = pcf2127_nvmem_write, 1090 .size = 512, 1091 }; 1092 1093 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 1094 } 1095 1096 /* 1097 * The "Power-On Reset Override" facility prevents the RTC to do a reset 1098 * after power on. For normal operation the PORO must be disabled. 1099 */ 1100 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 1101 PCF2127_BIT_CTRL1_POR_OVRD); 1102 1103 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); 1104 if (ret < 0) 1105 return ret; 1106 1107 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 1108 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, 1109 PCF2127_BIT_CLKOUT_OTPR); 1110 if (ret < 0) 1111 return ret; 1112 1113 msleep(100); 1114 } 1115 1116 /* 1117 * Watchdog timer enabled and reset pin /RST activated when timed out. 1118 * Select 1Hz clock source for watchdog timer. 1119 * Note: Countdown timer disabled and not available. 1120 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD 1121 * of register watchdg_tim_ctl. The bit[6] is labeled 1122 * as T. Bits labeled as T must always be written with 1123 * logic 0. 1124 */ 1125 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 1126 PCF2127_BIT_WD_CTL_CD1 | 1127 PCF2127_BIT_WD_CTL_CD0 | 1128 PCF2127_BIT_WD_CTL_TF1 | 1129 PCF2127_BIT_WD_CTL_TF0, 1130 PCF2127_BIT_WD_CTL_CD1 | 1131 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 1132 PCF2127_BIT_WD_CTL_TF1); 1133 if (ret) { 1134 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 1135 return ret; 1136 } 1137 1138 pcf2127_watchdog_init(dev, pcf2127); 1139 1140 /* 1141 * Disable battery low/switch-over timestamp and interrupts. 1142 * Clear battery interrupt flags which can block new trigger events. 1143 * Note: This is the default chip behaviour but added to ensure 1144 * correct tamper timestamp and interrupt function. 1145 */ 1146 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 1147 PCF2127_BIT_CTRL3_BTSE | 1148 PCF2127_BIT_CTRL3_BIE | 1149 PCF2127_BIT_CTRL3_BLIE, 0); 1150 if (ret) { 1151 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 1152 __func__); 1153 return ret; 1154 } 1155 1156 /* 1157 * Enable timestamp functions 1 to 4. 1158 */ 1159 for (int i = 0; i < pcf2127->cfg->ts_count; i++) { 1160 ret = pcf2127_enable_ts(dev, i); 1161 if (ret) 1162 return ret; 1163 } 1164 1165 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group); 1166 if (ret) { 1167 dev_err(dev, "%s: tamper sysfs registering failed\n", 1168 __func__); 1169 return ret; 1170 } 1171 1172 return devm_rtc_register_device(pcf2127->rtc); 1173 } 1174 1175 #ifdef CONFIG_OF 1176 static const struct of_device_id pcf2127_of_match[] = { 1177 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 1178 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 1179 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 1180 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] }, 1181 {} 1182 }; 1183 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 1184 #endif 1185 1186 #if IS_ENABLED(CONFIG_I2C) 1187 1188 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 1189 { 1190 struct device *dev = context; 1191 struct i2c_client *client = to_i2c_client(dev); 1192 int ret; 1193 1194 ret = i2c_master_send(client, data, count); 1195 if (ret != count) 1196 return ret < 0 ? ret : -EIO; 1197 1198 return 0; 1199 } 1200 1201 static int pcf2127_i2c_gather_write(void *context, 1202 const void *reg, size_t reg_size, 1203 const void *val, size_t val_size) 1204 { 1205 struct device *dev = context; 1206 struct i2c_client *client = to_i2c_client(dev); 1207 int ret; 1208 void *buf; 1209 1210 if (WARN_ON(reg_size != 1)) 1211 return -EINVAL; 1212 1213 buf = kmalloc(val_size + 1, GFP_KERNEL); 1214 if (!buf) 1215 return -ENOMEM; 1216 1217 memcpy(buf, reg, 1); 1218 memcpy(buf + 1, val, val_size); 1219 1220 ret = i2c_master_send(client, buf, val_size + 1); 1221 1222 kfree(buf); 1223 1224 if (ret != val_size + 1) 1225 return ret < 0 ? ret : -EIO; 1226 1227 return 0; 1228 } 1229 1230 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 1231 void *val, size_t val_size) 1232 { 1233 struct device *dev = context; 1234 struct i2c_client *client = to_i2c_client(dev); 1235 int ret; 1236 1237 if (WARN_ON(reg_size != 1)) 1238 return -EINVAL; 1239 1240 ret = i2c_master_send(client, reg, 1); 1241 if (ret != 1) 1242 return ret < 0 ? ret : -EIO; 1243 1244 ret = i2c_master_recv(client, val, val_size); 1245 if (ret != val_size) 1246 return ret < 0 ? ret : -EIO; 1247 1248 return 0; 1249 } 1250 1251 /* 1252 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 1253 * is that the STOP condition is required between set register address and 1254 * read register data when reading from registers. 1255 */ 1256 static const struct regmap_bus pcf2127_i2c_regmap = { 1257 .write = pcf2127_i2c_write, 1258 .gather_write = pcf2127_i2c_gather_write, 1259 .read = pcf2127_i2c_read, 1260 }; 1261 1262 static struct i2c_driver pcf2127_i2c_driver; 1263 1264 static const struct i2c_device_id pcf2127_i2c_id[] = { 1265 { "pcf2127", PCF2127 }, 1266 { "pcf2129", PCF2129 }, 1267 { "pca2129", PCF2129 }, 1268 { "pcf2131", PCF2131 }, 1269 { } 1270 }; 1271 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 1272 1273 static int pcf2127_i2c_probe(struct i2c_client *client) 1274 { 1275 struct regmap *regmap; 1276 static struct regmap_config config = { 1277 .reg_bits = 8, 1278 .val_bits = 8, 1279 }; 1280 const struct pcf21xx_config *variant; 1281 1282 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 1283 return -ENODEV; 1284 1285 if (client->dev.of_node) { 1286 variant = of_device_get_match_data(&client->dev); 1287 if (!variant) 1288 return -ENODEV; 1289 } else { 1290 enum pcf21xx_type type = 1291 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 1292 1293 if (type >= PCF21XX_LAST_ID) 1294 return -ENODEV; 1295 variant = &pcf21xx_cfg[type]; 1296 } 1297 1298 config.max_register = variant->max_register, 1299 1300 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 1301 &client->dev, &config); 1302 if (IS_ERR(regmap)) { 1303 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 1304 __func__, PTR_ERR(regmap)); 1305 return PTR_ERR(regmap); 1306 } 1307 1308 return pcf2127_probe(&client->dev, regmap, client->irq, 1309 pcf2127_i2c_driver.driver.name, variant); 1310 } 1311 1312 static struct i2c_driver pcf2127_i2c_driver = { 1313 .driver = { 1314 .name = "rtc-pcf2127-i2c", 1315 .of_match_table = of_match_ptr(pcf2127_of_match), 1316 }, 1317 .probe = pcf2127_i2c_probe, 1318 .id_table = pcf2127_i2c_id, 1319 }; 1320 1321 static int pcf2127_i2c_register_driver(void) 1322 { 1323 return i2c_add_driver(&pcf2127_i2c_driver); 1324 } 1325 1326 static void pcf2127_i2c_unregister_driver(void) 1327 { 1328 i2c_del_driver(&pcf2127_i2c_driver); 1329 } 1330 1331 #else 1332 1333 static int pcf2127_i2c_register_driver(void) 1334 { 1335 return 0; 1336 } 1337 1338 static void pcf2127_i2c_unregister_driver(void) 1339 { 1340 } 1341 1342 #endif 1343 1344 #if IS_ENABLED(CONFIG_SPI_MASTER) 1345 1346 static struct spi_driver pcf2127_spi_driver; 1347 static const struct spi_device_id pcf2127_spi_id[]; 1348 1349 static int pcf2127_spi_probe(struct spi_device *spi) 1350 { 1351 static struct regmap_config config = { 1352 .reg_bits = 8, 1353 .val_bits = 8, 1354 .read_flag_mask = 0xa0, 1355 .write_flag_mask = 0x20, 1356 }; 1357 struct regmap *regmap; 1358 const struct pcf21xx_config *variant; 1359 1360 if (spi->dev.of_node) { 1361 variant = of_device_get_match_data(&spi->dev); 1362 if (!variant) 1363 return -ENODEV; 1364 } else { 1365 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1366 1367 if (type >= PCF21XX_LAST_ID) 1368 return -ENODEV; 1369 variant = &pcf21xx_cfg[type]; 1370 } 1371 1372 config.max_register = variant->max_register, 1373 1374 regmap = devm_regmap_init_spi(spi, &config); 1375 if (IS_ERR(regmap)) { 1376 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1377 __func__, PTR_ERR(regmap)); 1378 return PTR_ERR(regmap); 1379 } 1380 1381 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1382 pcf2127_spi_driver.driver.name, 1383 variant); 1384 } 1385 1386 static const struct spi_device_id pcf2127_spi_id[] = { 1387 { "pcf2127", PCF2127 }, 1388 { "pcf2129", PCF2129 }, 1389 { "pca2129", PCF2129 }, 1390 { "pcf2131", PCF2131 }, 1391 { } 1392 }; 1393 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1394 1395 static struct spi_driver pcf2127_spi_driver = { 1396 .driver = { 1397 .name = "rtc-pcf2127-spi", 1398 .of_match_table = of_match_ptr(pcf2127_of_match), 1399 }, 1400 .probe = pcf2127_spi_probe, 1401 .id_table = pcf2127_spi_id, 1402 }; 1403 1404 static int pcf2127_spi_register_driver(void) 1405 { 1406 return spi_register_driver(&pcf2127_spi_driver); 1407 } 1408 1409 static void pcf2127_spi_unregister_driver(void) 1410 { 1411 spi_unregister_driver(&pcf2127_spi_driver); 1412 } 1413 1414 #else 1415 1416 static int pcf2127_spi_register_driver(void) 1417 { 1418 return 0; 1419 } 1420 1421 static void pcf2127_spi_unregister_driver(void) 1422 { 1423 } 1424 1425 #endif 1426 1427 static int __init pcf2127_init(void) 1428 { 1429 int ret; 1430 1431 ret = pcf2127_i2c_register_driver(); 1432 if (ret) { 1433 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1434 return ret; 1435 } 1436 1437 ret = pcf2127_spi_register_driver(); 1438 if (ret) { 1439 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1440 pcf2127_i2c_unregister_driver(); 1441 } 1442 1443 return ret; 1444 } 1445 module_init(pcf2127_init) 1446 1447 static void __exit pcf2127_exit(void) 1448 { 1449 pcf2127_spi_unregister_driver(); 1450 pcf2127_i2c_unregister_driver(); 1451 } 1452 module_exit(pcf2127_exit) 1453 1454 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1455 MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver"); 1456 MODULE_LICENSE("GPL v2"); 1457