1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * PCF2131 support 12 * Author: Hugo Villeneuve <[email protected]> 13 * 14 * based on the other drivers in this same directory. 15 * 16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/spi/spi.h> 22 #include <linux/bcd.h> 23 #include <linux/rtc.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_device.h> 29 #include <linux/regmap.h> 30 #include <linux/watchdog.h> 31 32 /* Control register 1 */ 33 #define PCF2127_REG_CTRL1 0x00 34 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 35 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 36 /* Control register 2 */ 37 #define PCF2127_REG_CTRL2 0x01 38 #define PCF2127_BIT_CTRL2_AIE BIT(1) 39 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 40 #define PCF2127_BIT_CTRL2_AF BIT(4) 41 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 42 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 43 /* Control register 3 */ 44 #define PCF2127_REG_CTRL3 0x02 45 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 46 #define PCF2127_BIT_CTRL3_BIE BIT(1) 47 #define PCF2127_BIT_CTRL3_BLF BIT(2) 48 #define PCF2127_BIT_CTRL3_BF BIT(3) 49 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 50 /* Time and date registers */ 51 #define PCF2127_REG_TIME_BASE 0x03 52 #define PCF2127_BIT_SC_OSF BIT(7) 53 /* Alarm registers */ 54 #define PCF2127_REG_ALARM_BASE 0x0A 55 #define PCF2127_BIT_ALARM_AE BIT(7) 56 /* CLKOUT control register */ 57 #define PCF2127_REG_CLKOUT 0x0f 58 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 59 /* Watchdog registers */ 60 #define PCF2127_REG_WD_CTL 0x10 61 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 62 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 63 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 64 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 65 #define PCF2127_REG_WD_VAL 0x11 66 /* Tamper timestamp1 registers */ 67 #define PCF2127_REG_TS1_BASE 0x12 68 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 69 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 70 /* 71 * RAM registers 72 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 73 * battery backed and can survive a power outage. 74 * PCF2129/31 doesn't have this feature. 75 */ 76 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 77 #define PCF2127_REG_RAM_WRT_CMD 0x1C 78 #define PCF2127_REG_RAM_RD_CMD 0x1D 79 80 /* Watchdog timer value constants */ 81 #define PCF2127_WD_VAL_STOP 0 82 #define PCF2127_WD_VAL_MIN 2 83 #define PCF2127_WD_VAL_MAX 255 84 #define PCF2127_WD_VAL_DEFAULT 60 85 86 /* Mask for currently enabled interrupts */ 87 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 88 #define PCF2127_CTRL2_IRQ_MASK ( \ 89 PCF2127_BIT_CTRL2_AF | \ 90 PCF2127_BIT_CTRL2_WDTF | \ 91 PCF2127_BIT_CTRL2_TSF2) 92 93 #define PCF2127_MAX_TS_SUPPORTED 4 94 95 /* Control register 4 */ 96 #define PCF2131_REG_CTRL4 0x03 97 #define PCF2131_BIT_CTRL4_TSF4 BIT(4) 98 #define PCF2131_BIT_CTRL4_TSF3 BIT(5) 99 #define PCF2131_BIT_CTRL4_TSF2 BIT(6) 100 #define PCF2131_BIT_CTRL4_TSF1 BIT(7) 101 /* Control register 5 */ 102 #define PCF2131_REG_CTRL5 0x04 103 #define PCF2131_BIT_CTRL5_TSIE4 BIT(4) 104 #define PCF2131_BIT_CTRL5_TSIE3 BIT(5) 105 #define PCF2131_BIT_CTRL5_TSIE2 BIT(6) 106 #define PCF2131_BIT_CTRL5_TSIE1 BIT(7) 107 /* Software reset register */ 108 #define PCF2131_REG_SR_RESET 0x05 109 #define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5)) 110 #define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7)) 111 /* Time and date registers */ 112 #define PCF2131_REG_TIME_BASE 0x07 113 /* Alarm registers */ 114 #define PCF2131_REG_ALARM_BASE 0x0E 115 /* CLKOUT control register */ 116 #define PCF2131_REG_CLKOUT 0x13 117 /* Watchdog registers */ 118 #define PCF2131_REG_WD_CTL 0x35 119 #define PCF2131_REG_WD_VAL 0x36 120 /* Tamper timestamp1 registers */ 121 #define PCF2131_REG_TS1_BASE 0x14 122 /* Tamper timestamp2 registers */ 123 #define PCF2131_REG_TS2_BASE 0x1B 124 /* Tamper timestamp3 registers */ 125 #define PCF2131_REG_TS3_BASE 0x22 126 /* Tamper timestamp4 registers */ 127 #define PCF2131_REG_TS4_BASE 0x29 128 /* Interrupt mask registers */ 129 #define PCF2131_REG_INT_A_MASK1 0x31 130 #define PCF2131_REG_INT_A_MASK2 0x32 131 #define PCF2131_REG_INT_B_MASK1 0x33 132 #define PCF2131_REG_INT_B_MASK2 0x34 133 #define PCF2131_BIT_INT_BLIE BIT(0) 134 #define PCF2131_BIT_INT_BIE BIT(1) 135 #define PCF2131_BIT_INT_AIE BIT(2) 136 #define PCF2131_BIT_INT_WD_CD BIT(3) 137 #define PCF2131_BIT_INT_SI BIT(4) 138 #define PCF2131_BIT_INT_MI BIT(5) 139 #define PCF2131_CTRL2_IRQ_MASK ( \ 140 PCF2127_BIT_CTRL2_AF | \ 141 PCF2127_BIT_CTRL2_WDTF) 142 #define PCF2131_CTRL4_IRQ_MASK ( \ 143 PCF2131_BIT_CTRL4_TSF4 | \ 144 PCF2131_BIT_CTRL4_TSF3 | \ 145 PCF2131_BIT_CTRL4_TSF2 | \ 146 PCF2131_BIT_CTRL4_TSF1) 147 148 enum pcf21xx_type { 149 PCF2127, 150 PCF2129, 151 PCF2131, 152 PCF21XX_LAST_ID 153 }; 154 155 struct pcf21xx_ts_config { 156 u8 reg_base; /* Base register to read timestamp values. */ 157 158 /* 159 * If the TS input pin is driven to GND, an interrupt can be generated 160 * (supported by all variants). 161 */ 162 u8 gnd_detect_reg; /* Interrupt control register address. */ 163 u8 gnd_detect_bit; /* Interrupt bit. */ 164 165 /* 166 * If the TS input pin is driven to an intermediate level between GND 167 * and supply, an interrupt can be generated (optional feature depending 168 * on variant). 169 */ 170 u8 inter_detect_reg; /* Interrupt control register address. */ 171 u8 inter_detect_bit; /* Interrupt bit. */ 172 173 u8 ie_reg; /* Interrupt enable control register. */ 174 u8 ie_bit; /* Interrupt enable bit. */ 175 }; 176 177 struct pcf21xx_config { 178 int type; /* IC variant */ 179 int max_register; 180 unsigned int has_nvmem:1; 181 unsigned int has_bit_wd_ctl_cd0:1; 182 u8 reg_time_base; /* Time/date base register. */ 183 u8 regs_alarm_base; /* Alarm function base registers. */ 184 u8 reg_wd_ctl; /* Watchdog control register. */ 185 u8 reg_wd_val; /* Watchdog value register. */ 186 u8 reg_clkout; /* Clkout register. */ 187 unsigned int ts_count; 188 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED]; 189 struct attribute_group attribute_group; 190 }; 191 192 struct pcf2127 { 193 struct rtc_device *rtc; 194 struct watchdog_device wdd; 195 struct regmap *regmap; 196 const struct pcf21xx_config *cfg; 197 bool irq_enabled; 198 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */ 199 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */ 200 }; 201 202 /* 203 * In the routines that deal directly with the pcf2127 hardware, we use 204 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 205 */ 206 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 207 { 208 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 209 unsigned char buf[7]; 210 int ret; 211 212 /* 213 * Avoid reading CTRL2 register as it causes WD_VAL register 214 * value to reset to 0 which means watchdog is stopped. 215 */ 216 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 217 buf, sizeof(buf)); 218 if (ret) { 219 dev_err(dev, "%s: read error\n", __func__); 220 return ret; 221 } 222 223 /* Clock integrity is not guaranteed when OSF flag is set. */ 224 if (buf[0] & PCF2127_BIT_SC_OSF) { 225 /* 226 * no need clear the flag here, 227 * it will be cleared once the new date is saved 228 */ 229 dev_warn(dev, 230 "oscillator stop detected, date/time is not reliable\n"); 231 return -EINVAL; 232 } 233 234 dev_dbg(dev, 235 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 236 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 237 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 238 239 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 240 tm->tm_min = bcd2bin(buf[1] & 0x7F); 241 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 242 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 243 tm->tm_wday = buf[4] & 0x07; 244 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 245 tm->tm_year = bcd2bin(buf[6]); 246 tm->tm_year += 100; 247 248 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 249 "mday=%d, mon=%d, year=%d, wday=%d\n", 250 __func__, 251 tm->tm_sec, tm->tm_min, tm->tm_hour, 252 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 253 254 return 0; 255 } 256 257 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 258 { 259 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 260 unsigned char buf[7]; 261 int i = 0, err; 262 263 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 264 "mday=%d, mon=%d, year=%d, wday=%d\n", 265 __func__, 266 tm->tm_sec, tm->tm_min, tm->tm_hour, 267 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 268 269 /* hours, minutes and seconds */ 270 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 271 buf[i++] = bin2bcd(tm->tm_min); 272 buf[i++] = bin2bcd(tm->tm_hour); 273 buf[i++] = bin2bcd(tm->tm_mday); 274 buf[i++] = tm->tm_wday & 0x07; 275 276 /* month, 1 - 12 */ 277 buf[i++] = bin2bcd(tm->tm_mon + 1); 278 279 /* year */ 280 buf[i++] = bin2bcd(tm->tm_year - 100); 281 282 /* write register's data */ 283 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 284 if (err) { 285 dev_dbg(dev, "%s: err=%d", __func__, err); 286 return err; 287 } 288 289 return 0; 290 } 291 292 static int pcf2127_rtc_ioctl(struct device *dev, 293 unsigned int cmd, unsigned long arg) 294 { 295 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 296 int val, touser = 0; 297 int ret; 298 299 switch (cmd) { 300 case RTC_VL_READ: 301 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 302 if (ret) 303 return ret; 304 305 if (val & PCF2127_BIT_CTRL3_BLF) 306 touser |= RTC_VL_BACKUP_LOW; 307 308 if (val & PCF2127_BIT_CTRL3_BF) 309 touser |= RTC_VL_BACKUP_SWITCH; 310 311 return put_user(touser, (unsigned int __user *)arg); 312 313 case RTC_VL_CLR: 314 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 315 PCF2127_BIT_CTRL3_BF, 0); 316 317 default: 318 return -ENOIOCTLCMD; 319 } 320 } 321 322 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 323 void *val, size_t bytes) 324 { 325 struct pcf2127 *pcf2127 = priv; 326 int ret; 327 unsigned char offsetbuf[] = { offset >> 8, offset }; 328 329 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 330 offsetbuf, 2); 331 if (ret) 332 return ret; 333 334 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 335 val, bytes); 336 } 337 338 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 339 void *val, size_t bytes) 340 { 341 struct pcf2127 *pcf2127 = priv; 342 int ret; 343 unsigned char offsetbuf[] = { offset >> 8, offset }; 344 345 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 346 offsetbuf, 2); 347 if (ret) 348 return ret; 349 350 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 351 val, bytes); 352 } 353 354 /* watchdog driver */ 355 356 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 357 { 358 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 359 360 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout); 361 } 362 363 /* 364 * Restart watchdog timer if feature is active. 365 * 366 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 367 * since register also contain control/status flags for other features. 368 * Always call this function after reading CTRL2 register. 369 */ 370 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 371 { 372 int ret = 0; 373 374 if (watchdog_active(wdd)) { 375 ret = pcf2127_wdt_ping(wdd); 376 if (ret) 377 dev_err(wdd->parent, 378 "%s: watchdog restart failed, ret=%d\n", 379 __func__, ret); 380 } 381 382 return ret; 383 } 384 385 static int pcf2127_wdt_start(struct watchdog_device *wdd) 386 { 387 return pcf2127_wdt_ping(wdd); 388 } 389 390 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 391 { 392 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 393 394 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 395 PCF2127_WD_VAL_STOP); 396 } 397 398 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 399 unsigned int new_timeout) 400 { 401 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 402 new_timeout, wdd->timeout); 403 404 wdd->timeout = new_timeout; 405 406 return pcf2127_wdt_active_ping(wdd); 407 } 408 409 static const struct watchdog_info pcf2127_wdt_info = { 410 .identity = "NXP PCF2127/PCF2129 Watchdog", 411 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 412 }; 413 414 static const struct watchdog_ops pcf2127_watchdog_ops = { 415 .owner = THIS_MODULE, 416 .start = pcf2127_wdt_start, 417 .stop = pcf2127_wdt_stop, 418 .ping = pcf2127_wdt_ping, 419 .set_timeout = pcf2127_wdt_set_timeout, 420 }; 421 422 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 423 { 424 u32 wdd_timeout; 425 int ret; 426 427 if (!IS_ENABLED(CONFIG_WATCHDOG) || 428 !device_property_read_bool(dev, "reset-source")) 429 return 0; 430 431 pcf2127->wdd.parent = dev; 432 pcf2127->wdd.info = &pcf2127_wdt_info; 433 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 434 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 435 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 436 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 437 pcf2127->wdd.min_hw_heartbeat_ms = 500; 438 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 439 440 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 441 442 /* Test if watchdog timer is started by bootloader */ 443 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 444 if (ret) 445 return ret; 446 447 if (wdd_timeout) 448 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 449 450 return devm_watchdog_register_device(dev, &pcf2127->wdd); 451 } 452 453 /* Alarm */ 454 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 455 { 456 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 457 u8 buf[5]; 458 unsigned int ctrl2; 459 int ret; 460 461 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 462 if (ret) 463 return ret; 464 465 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 466 if (ret) 467 return ret; 468 469 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 470 buf, sizeof(buf)); 471 if (ret) 472 return ret; 473 474 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 475 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 476 477 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 478 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 479 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 480 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 481 482 return 0; 483 } 484 485 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 486 { 487 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 488 int ret; 489 490 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 491 PCF2127_BIT_CTRL2_AIE, 492 enable ? PCF2127_BIT_CTRL2_AIE : 0); 493 if (ret) 494 return ret; 495 496 return pcf2127_wdt_active_ping(&pcf2127->wdd); 497 } 498 499 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 500 { 501 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 502 uint8_t buf[5]; 503 int ret; 504 505 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 506 PCF2127_BIT_CTRL2_AF, 0); 507 if (ret) 508 return ret; 509 510 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 511 if (ret) 512 return ret; 513 514 buf[0] = bin2bcd(alrm->time.tm_sec); 515 buf[1] = bin2bcd(alrm->time.tm_min); 516 buf[2] = bin2bcd(alrm->time.tm_hour); 517 buf[3] = bin2bcd(alrm->time.tm_mday); 518 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 519 520 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 521 buf, sizeof(buf)); 522 if (ret) 523 return ret; 524 525 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 526 } 527 528 /* 529 * This function reads one timestamp function data, caller is responsible for 530 * calling pcf2127_wdt_active_ping() 531 */ 532 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts, 533 int ts_id) 534 { 535 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 536 struct rtc_time tm; 537 int ret; 538 unsigned char data[7]; 539 540 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base, 541 data, sizeof(data)); 542 if (ret) { 543 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 544 return ret; 545 } 546 547 dev_dbg(dev, 548 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 549 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 550 551 tm.tm_sec = bcd2bin(data[1] & 0x7F); 552 tm.tm_min = bcd2bin(data[2] & 0x7F); 553 tm.tm_hour = bcd2bin(data[3] & 0x3F); 554 tm.tm_mday = bcd2bin(data[4] & 0x3F); 555 /* TS_MO register (month) value range: 1-12 */ 556 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 557 tm.tm_year = bcd2bin(data[6]); 558 if (tm.tm_year < 70) 559 tm.tm_year += 100; /* assume we are in 1970...2069 */ 560 561 ret = rtc_valid_tm(&tm); 562 if (ret) { 563 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 564 return ret; 565 } 566 567 *ts = rtc_tm_to_time64(&tm); 568 return 0; 569 }; 570 571 static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id) 572 { 573 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 574 int ret; 575 576 if (ts_id >= pcf2127->cfg->ts_count) 577 return; 578 579 /* Let userspace read the first timestamp */ 580 if (pcf2127->ts_valid[ts_id]) 581 return; 582 583 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id); 584 if (!ret) 585 pcf2127->ts_valid[ts_id] = true; 586 } 587 588 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 589 { 590 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 591 unsigned int ctrl2; 592 int ret = 0; 593 594 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 595 if (ret) 596 return IRQ_NONE; 597 598 if (pcf2127->cfg->ts_count == 1) { 599 /* PCF2127/29 */ 600 unsigned int ctrl1; 601 602 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 603 if (ret) 604 return IRQ_NONE; 605 606 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 607 return IRQ_NONE; 608 609 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 610 pcf2127_rtc_ts_snapshot(dev, 0); 611 612 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 613 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 614 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 615 616 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 617 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 618 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 619 } else { 620 /* PCF2131. */ 621 unsigned int ctrl4; 622 623 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4); 624 if (ret) 625 return IRQ_NONE; 626 627 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK)) 628 return IRQ_NONE; 629 630 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) { 631 int i; 632 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */ 633 634 for (i = 0; i < pcf2127->cfg->ts_count; i++) { 635 if (ctrl4 & tsf_bit) 636 pcf2127_rtc_ts_snapshot(dev, i); 637 638 tsf_bit = tsf_bit >> 1; 639 } 640 641 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4, 642 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK); 643 } 644 645 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK) 646 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 647 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK); 648 } 649 650 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 651 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 652 653 pcf2127_wdt_active_ping(&pcf2127->wdd); 654 655 return IRQ_HANDLED; 656 } 657 658 static const struct rtc_class_ops pcf2127_rtc_ops = { 659 .ioctl = pcf2127_rtc_ioctl, 660 .read_time = pcf2127_rtc_read_time, 661 .set_time = pcf2127_rtc_set_time, 662 .read_alarm = pcf2127_rtc_read_alarm, 663 .set_alarm = pcf2127_rtc_set_alarm, 664 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 665 }; 666 667 /* sysfs interface */ 668 669 static ssize_t timestamp_store(struct device *dev, 670 struct device_attribute *attr, 671 const char *buf, size_t count, int ts_id) 672 { 673 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 674 int ret; 675 676 if (ts_id >= pcf2127->cfg->ts_count) 677 return 0; 678 679 if (pcf2127->irq_enabled) { 680 pcf2127->ts_valid[ts_id] = false; 681 } else { 682 /* Always clear GND interrupt bit. */ 683 ret = regmap_update_bits(pcf2127->regmap, 684 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 685 pcf2127->cfg->ts[ts_id].gnd_detect_bit, 686 0); 687 688 if (ret) { 689 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret); 690 return ret; 691 } 692 693 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 694 /* Clear intermediate level interrupt bit if supported. */ 695 ret = regmap_update_bits(pcf2127->regmap, 696 pcf2127->cfg->ts[ts_id].inter_detect_reg, 697 pcf2127->cfg->ts[ts_id].inter_detect_bit, 698 0); 699 if (ret) { 700 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n", 701 __func__, ret); 702 return ret; 703 } 704 } 705 706 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 707 if (ret) 708 return ret; 709 } 710 711 return count; 712 } 713 714 static ssize_t timestamp0_store(struct device *dev, 715 struct device_attribute *attr, 716 const char *buf, size_t count) 717 { 718 return timestamp_store(dev, attr, buf, count, 0); 719 }; 720 721 static ssize_t timestamp1_store(struct device *dev, 722 struct device_attribute *attr, 723 const char *buf, size_t count) 724 { 725 return timestamp_store(dev, attr, buf, count, 1); 726 }; 727 728 static ssize_t timestamp2_store(struct device *dev, 729 struct device_attribute *attr, 730 const char *buf, size_t count) 731 { 732 return timestamp_store(dev, attr, buf, count, 2); 733 }; 734 735 static ssize_t timestamp3_store(struct device *dev, 736 struct device_attribute *attr, 737 const char *buf, size_t count) 738 { 739 return timestamp_store(dev, attr, buf, count, 3); 740 }; 741 742 static ssize_t timestamp_show(struct device *dev, 743 struct device_attribute *attr, char *buf, 744 int ts_id) 745 { 746 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 747 int ret; 748 time64_t ts; 749 750 if (ts_id >= pcf2127->cfg->ts_count) 751 return 0; 752 753 if (pcf2127->irq_enabled) { 754 if (!pcf2127->ts_valid[ts_id]) 755 return 0; 756 ts = pcf2127->ts[ts_id]; 757 } else { 758 u8 valid_low = 0; 759 u8 valid_inter = 0; 760 unsigned int ctrl; 761 762 /* Check if TS input pin is driven to GND, supported by all 763 * variants. 764 */ 765 ret = regmap_read(pcf2127->regmap, 766 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 767 &ctrl); 768 if (ret) 769 return 0; 770 771 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit; 772 773 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 774 /* Check if TS input pin is driven to intermediate level 775 * between GND and supply, if supported by variant. 776 */ 777 ret = regmap_read(pcf2127->regmap, 778 pcf2127->cfg->ts[ts_id].inter_detect_reg, 779 &ctrl); 780 if (ret) 781 return 0; 782 783 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit; 784 } 785 786 if (!valid_low && !valid_inter) 787 return 0; 788 789 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id); 790 if (ret) 791 return 0; 792 793 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 794 if (ret) 795 return ret; 796 } 797 return sprintf(buf, "%llu\n", (unsigned long long)ts); 798 } 799 800 static ssize_t timestamp0_show(struct device *dev, 801 struct device_attribute *attr, char *buf) 802 { 803 return timestamp_show(dev, attr, buf, 0); 804 }; 805 806 static ssize_t timestamp1_show(struct device *dev, 807 struct device_attribute *attr, char *buf) 808 { 809 return timestamp_show(dev, attr, buf, 1); 810 }; 811 812 static ssize_t timestamp2_show(struct device *dev, 813 struct device_attribute *attr, char *buf) 814 { 815 return timestamp_show(dev, attr, buf, 2); 816 }; 817 818 static ssize_t timestamp3_show(struct device *dev, 819 struct device_attribute *attr, char *buf) 820 { 821 return timestamp_show(dev, attr, buf, 3); 822 }; 823 824 static DEVICE_ATTR_RW(timestamp0); 825 static DEVICE_ATTR_RW(timestamp1); 826 static DEVICE_ATTR_RW(timestamp2); 827 static DEVICE_ATTR_RW(timestamp3); 828 829 static struct attribute *pcf2127_attrs[] = { 830 &dev_attr_timestamp0.attr, 831 NULL 832 }; 833 834 static struct attribute *pcf2131_attrs[] = { 835 &dev_attr_timestamp0.attr, 836 &dev_attr_timestamp1.attr, 837 &dev_attr_timestamp2.attr, 838 &dev_attr_timestamp3.attr, 839 NULL 840 }; 841 842 static struct pcf21xx_config pcf21xx_cfg[] = { 843 [PCF2127] = { 844 .type = PCF2127, 845 .max_register = 0x1d, 846 .has_nvmem = 1, 847 .has_bit_wd_ctl_cd0 = 1, 848 .reg_time_base = PCF2127_REG_TIME_BASE, 849 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 850 .reg_wd_ctl = PCF2127_REG_WD_CTL, 851 .reg_wd_val = PCF2127_REG_WD_VAL, 852 .reg_clkout = PCF2127_REG_CLKOUT, 853 .ts_count = 1, 854 .ts[0] = { 855 .reg_base = PCF2127_REG_TS1_BASE, 856 .gnd_detect_reg = PCF2127_REG_CTRL1, 857 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 858 .inter_detect_reg = PCF2127_REG_CTRL2, 859 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 860 .ie_reg = PCF2127_REG_CTRL2, 861 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 862 }, 863 .attribute_group = { 864 .attrs = pcf2127_attrs, 865 }, 866 }, 867 [PCF2129] = { 868 .type = PCF2129, 869 .max_register = 0x19, 870 .has_nvmem = 0, 871 .has_bit_wd_ctl_cd0 = 0, 872 .reg_time_base = PCF2127_REG_TIME_BASE, 873 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 874 .reg_wd_ctl = PCF2127_REG_WD_CTL, 875 .reg_wd_val = PCF2127_REG_WD_VAL, 876 .reg_clkout = PCF2127_REG_CLKOUT, 877 .ts_count = 1, 878 .ts[0] = { 879 .reg_base = PCF2127_REG_TS1_BASE, 880 .gnd_detect_reg = PCF2127_REG_CTRL1, 881 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 882 .inter_detect_reg = PCF2127_REG_CTRL2, 883 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 884 .ie_reg = PCF2127_REG_CTRL2, 885 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 886 }, 887 .attribute_group = { 888 .attrs = pcf2127_attrs, 889 }, 890 }, 891 [PCF2131] = { 892 .type = PCF2131, 893 .max_register = 0x36, 894 .has_nvmem = 0, 895 .has_bit_wd_ctl_cd0 = 0, 896 .reg_time_base = PCF2131_REG_TIME_BASE, 897 .regs_alarm_base = PCF2131_REG_ALARM_BASE, 898 .reg_wd_ctl = PCF2131_REG_WD_CTL, 899 .reg_wd_val = PCF2131_REG_WD_VAL, 900 .reg_clkout = PCF2131_REG_CLKOUT, 901 .ts_count = 4, 902 .ts[0] = { 903 .reg_base = PCF2131_REG_TS1_BASE, 904 .gnd_detect_reg = PCF2131_REG_CTRL4, 905 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1, 906 .inter_detect_bit = 0, 907 .ie_reg = PCF2131_REG_CTRL5, 908 .ie_bit = PCF2131_BIT_CTRL5_TSIE1, 909 }, 910 .ts[1] = { 911 .reg_base = PCF2131_REG_TS2_BASE, 912 .gnd_detect_reg = PCF2131_REG_CTRL4, 913 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2, 914 .inter_detect_bit = 0, 915 .ie_reg = PCF2131_REG_CTRL5, 916 .ie_bit = PCF2131_BIT_CTRL5_TSIE2, 917 }, 918 .ts[2] = { 919 .reg_base = PCF2131_REG_TS3_BASE, 920 .gnd_detect_reg = PCF2131_REG_CTRL4, 921 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3, 922 .inter_detect_bit = 0, 923 .ie_reg = PCF2131_REG_CTRL5, 924 .ie_bit = PCF2131_BIT_CTRL5_TSIE3, 925 }, 926 .ts[3] = { 927 .reg_base = PCF2131_REG_TS4_BASE, 928 .gnd_detect_reg = PCF2131_REG_CTRL4, 929 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4, 930 .inter_detect_bit = 0, 931 .ie_reg = PCF2131_REG_CTRL5, 932 .ie_bit = PCF2131_BIT_CTRL5_TSIE4, 933 }, 934 .attribute_group = { 935 .attrs = pcf2131_attrs, 936 }, 937 }, 938 }; 939 940 /* 941 * Enable timestamp function and corresponding interrupt(s). 942 */ 943 static int pcf2127_enable_ts(struct device *dev, int ts_id) 944 { 945 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 946 int ret; 947 948 if (ts_id >= pcf2127->cfg->ts_count) { 949 dev_err(dev, "%s: invalid tamper detection ID (%d)\n", 950 __func__, ts_id); 951 return -EINVAL; 952 } 953 954 /* Enable timestamp function. */ 955 ret = regmap_update_bits(pcf2127->regmap, 956 pcf2127->cfg->ts[ts_id].reg_base, 957 PCF2127_BIT_TS_CTRL_TSOFF | 958 PCF2127_BIT_TS_CTRL_TSM, 959 PCF2127_BIT_TS_CTRL_TSM); 960 if (ret) { 961 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n", 962 __func__, ts_id); 963 return ret; 964 } 965 966 /* TS input pin driven to GND detection is supported by all variants. 967 * Make sure that interrupt bit is defined. 968 */ 969 if (pcf2127->cfg->ts[ts_id].gnd_detect_bit == 0) { 970 dev_err(dev, "%s: tamper detection to GND configuration invalid\n", 971 __func__); 972 return ret; 973 } 974 975 /* 976 * Enable interrupt generation when TSF timestamp flag is set. 977 * Interrupt signals are open-drain outputs and can be left floating if 978 * unused. 979 */ 980 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg, 981 pcf2127->cfg->ts[ts_id].ie_bit, 982 pcf2127->cfg->ts[ts_id].ie_bit); 983 if (ret) { 984 dev_err(dev, "%s: tamper detection TSIE%d config failed\n", 985 __func__, ts_id); 986 return ret; 987 } 988 989 return ret; 990 } 991 992 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 993 int alarm_irq, const char *name, const struct pcf21xx_config *config) 994 { 995 struct pcf2127 *pcf2127; 996 int ret = 0; 997 unsigned int val; 998 999 dev_dbg(dev, "%s\n", __func__); 1000 1001 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 1002 if (!pcf2127) 1003 return -ENOMEM; 1004 1005 pcf2127->regmap = regmap; 1006 pcf2127->cfg = config; 1007 1008 dev_set_drvdata(dev, pcf2127); 1009 1010 pcf2127->rtc = devm_rtc_allocate_device(dev); 1011 if (IS_ERR(pcf2127->rtc)) 1012 return PTR_ERR(pcf2127->rtc); 1013 1014 pcf2127->rtc->ops = &pcf2127_rtc_ops; 1015 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 1016 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 1017 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 1018 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 1019 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 1020 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1021 1022 if (alarm_irq > 0) { 1023 unsigned long flags; 1024 1025 /* 1026 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 1027 * obtained from device tree. 1028 */ 1029 if (dev_fwnode(dev)) 1030 flags = 0; 1031 else 1032 flags = IRQF_TRIGGER_LOW; 1033 1034 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 1035 pcf2127_rtc_irq, 1036 flags | IRQF_ONESHOT, 1037 dev_name(dev), dev); 1038 if (ret) { 1039 dev_err(dev, "failed to request alarm irq\n"); 1040 return ret; 1041 } 1042 pcf2127->irq_enabled = true; 1043 } 1044 1045 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 1046 device_init_wakeup(dev, true); 1047 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1048 } 1049 1050 if (pcf2127->cfg->has_nvmem) { 1051 struct nvmem_config nvmem_cfg = { 1052 .priv = pcf2127, 1053 .reg_read = pcf2127_nvmem_read, 1054 .reg_write = pcf2127_nvmem_write, 1055 .size = 512, 1056 }; 1057 1058 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 1059 } 1060 1061 /* 1062 * The "Power-On Reset Override" facility prevents the RTC to do a reset 1063 * after power on. For normal operation the PORO must be disabled. 1064 */ 1065 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 1066 PCF2127_BIT_CTRL1_POR_OVRD); 1067 1068 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); 1069 if (ret < 0) 1070 return ret; 1071 1072 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 1073 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, 1074 PCF2127_BIT_CLKOUT_OTPR); 1075 if (ret < 0) 1076 return ret; 1077 1078 msleep(100); 1079 } 1080 1081 /* 1082 * Watchdog timer enabled and reset pin /RST activated when timed out. 1083 * Select 1Hz clock source for watchdog timer. 1084 * Note: Countdown timer disabled and not available. 1085 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD 1086 * of register watchdg_tim_ctl. The bit[6] is labeled 1087 * as T. Bits labeled as T must always be written with 1088 * logic 0. 1089 */ 1090 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 1091 PCF2127_BIT_WD_CTL_CD1 | 1092 PCF2127_BIT_WD_CTL_CD0 | 1093 PCF2127_BIT_WD_CTL_TF1 | 1094 PCF2127_BIT_WD_CTL_TF0, 1095 PCF2127_BIT_WD_CTL_CD1 | 1096 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 1097 PCF2127_BIT_WD_CTL_TF1); 1098 if (ret) { 1099 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 1100 return ret; 1101 } 1102 1103 pcf2127_watchdog_init(dev, pcf2127); 1104 1105 /* 1106 * Disable battery low/switch-over timestamp and interrupts. 1107 * Clear battery interrupt flags which can block new trigger events. 1108 * Note: This is the default chip behaviour but added to ensure 1109 * correct tamper timestamp and interrupt function. 1110 */ 1111 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 1112 PCF2127_BIT_CTRL3_BTSE | 1113 PCF2127_BIT_CTRL3_BIE | 1114 PCF2127_BIT_CTRL3_BLIE, 0); 1115 if (ret) { 1116 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 1117 __func__); 1118 return ret; 1119 } 1120 1121 /* 1122 * Enable timestamp functions 1 to 4. 1123 */ 1124 for (int i = 0; i < pcf2127->cfg->ts_count; i++) { 1125 ret = pcf2127_enable_ts(dev, i); 1126 if (ret) 1127 return ret; 1128 } 1129 1130 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group); 1131 if (ret) { 1132 dev_err(dev, "%s: tamper sysfs registering failed\n", 1133 __func__); 1134 return ret; 1135 } 1136 1137 return devm_rtc_register_device(pcf2127->rtc); 1138 } 1139 1140 #ifdef CONFIG_OF 1141 static const struct of_device_id pcf2127_of_match[] = { 1142 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 1143 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 1144 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 1145 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] }, 1146 {} 1147 }; 1148 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 1149 #endif 1150 1151 #if IS_ENABLED(CONFIG_I2C) 1152 1153 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 1154 { 1155 struct device *dev = context; 1156 struct i2c_client *client = to_i2c_client(dev); 1157 int ret; 1158 1159 ret = i2c_master_send(client, data, count); 1160 if (ret != count) 1161 return ret < 0 ? ret : -EIO; 1162 1163 return 0; 1164 } 1165 1166 static int pcf2127_i2c_gather_write(void *context, 1167 const void *reg, size_t reg_size, 1168 const void *val, size_t val_size) 1169 { 1170 struct device *dev = context; 1171 struct i2c_client *client = to_i2c_client(dev); 1172 int ret; 1173 void *buf; 1174 1175 if (WARN_ON(reg_size != 1)) 1176 return -EINVAL; 1177 1178 buf = kmalloc(val_size + 1, GFP_KERNEL); 1179 if (!buf) 1180 return -ENOMEM; 1181 1182 memcpy(buf, reg, 1); 1183 memcpy(buf + 1, val, val_size); 1184 1185 ret = i2c_master_send(client, buf, val_size + 1); 1186 1187 kfree(buf); 1188 1189 if (ret != val_size + 1) 1190 return ret < 0 ? ret : -EIO; 1191 1192 return 0; 1193 } 1194 1195 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 1196 void *val, size_t val_size) 1197 { 1198 struct device *dev = context; 1199 struct i2c_client *client = to_i2c_client(dev); 1200 int ret; 1201 1202 if (WARN_ON(reg_size != 1)) 1203 return -EINVAL; 1204 1205 ret = i2c_master_send(client, reg, 1); 1206 if (ret != 1) 1207 return ret < 0 ? ret : -EIO; 1208 1209 ret = i2c_master_recv(client, val, val_size); 1210 if (ret != val_size) 1211 return ret < 0 ? ret : -EIO; 1212 1213 return 0; 1214 } 1215 1216 /* 1217 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 1218 * is that the STOP condition is required between set register address and 1219 * read register data when reading from registers. 1220 */ 1221 static const struct regmap_bus pcf2127_i2c_regmap = { 1222 .write = pcf2127_i2c_write, 1223 .gather_write = pcf2127_i2c_gather_write, 1224 .read = pcf2127_i2c_read, 1225 }; 1226 1227 static struct i2c_driver pcf2127_i2c_driver; 1228 1229 static const struct i2c_device_id pcf2127_i2c_id[] = { 1230 { "pcf2127", PCF2127 }, 1231 { "pcf2129", PCF2129 }, 1232 { "pca2129", PCF2129 }, 1233 { "pcf2131", PCF2131 }, 1234 { } 1235 }; 1236 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 1237 1238 static int pcf2127_i2c_probe(struct i2c_client *client) 1239 { 1240 struct regmap *regmap; 1241 static struct regmap_config config = { 1242 .reg_bits = 8, 1243 .val_bits = 8, 1244 }; 1245 const struct pcf21xx_config *variant; 1246 1247 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 1248 return -ENODEV; 1249 1250 if (client->dev.of_node) { 1251 variant = of_device_get_match_data(&client->dev); 1252 if (!variant) 1253 return -ENODEV; 1254 } else { 1255 enum pcf21xx_type type = 1256 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 1257 1258 if (type >= PCF21XX_LAST_ID) 1259 return -ENODEV; 1260 variant = &pcf21xx_cfg[type]; 1261 } 1262 1263 config.max_register = variant->max_register, 1264 1265 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 1266 &client->dev, &config); 1267 if (IS_ERR(regmap)) { 1268 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 1269 __func__, PTR_ERR(regmap)); 1270 return PTR_ERR(regmap); 1271 } 1272 1273 return pcf2127_probe(&client->dev, regmap, client->irq, 1274 pcf2127_i2c_driver.driver.name, variant); 1275 } 1276 1277 static struct i2c_driver pcf2127_i2c_driver = { 1278 .driver = { 1279 .name = "rtc-pcf2127-i2c", 1280 .of_match_table = of_match_ptr(pcf2127_of_match), 1281 }, 1282 .probe = pcf2127_i2c_probe, 1283 .id_table = pcf2127_i2c_id, 1284 }; 1285 1286 static int pcf2127_i2c_register_driver(void) 1287 { 1288 return i2c_add_driver(&pcf2127_i2c_driver); 1289 } 1290 1291 static void pcf2127_i2c_unregister_driver(void) 1292 { 1293 i2c_del_driver(&pcf2127_i2c_driver); 1294 } 1295 1296 #else 1297 1298 static int pcf2127_i2c_register_driver(void) 1299 { 1300 return 0; 1301 } 1302 1303 static void pcf2127_i2c_unregister_driver(void) 1304 { 1305 } 1306 1307 #endif 1308 1309 #if IS_ENABLED(CONFIG_SPI_MASTER) 1310 1311 static struct spi_driver pcf2127_spi_driver; 1312 static const struct spi_device_id pcf2127_spi_id[]; 1313 1314 static int pcf2127_spi_probe(struct spi_device *spi) 1315 { 1316 static struct regmap_config config = { 1317 .reg_bits = 8, 1318 .val_bits = 8, 1319 .read_flag_mask = 0xa0, 1320 .write_flag_mask = 0x20, 1321 }; 1322 struct regmap *regmap; 1323 const struct pcf21xx_config *variant; 1324 1325 if (spi->dev.of_node) { 1326 variant = of_device_get_match_data(&spi->dev); 1327 if (!variant) 1328 return -ENODEV; 1329 } else { 1330 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1331 1332 if (type >= PCF21XX_LAST_ID) 1333 return -ENODEV; 1334 variant = &pcf21xx_cfg[type]; 1335 } 1336 1337 config.max_register = variant->max_register, 1338 1339 regmap = devm_regmap_init_spi(spi, &config); 1340 if (IS_ERR(regmap)) { 1341 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1342 __func__, PTR_ERR(regmap)); 1343 return PTR_ERR(regmap); 1344 } 1345 1346 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1347 pcf2127_spi_driver.driver.name, 1348 variant); 1349 } 1350 1351 static const struct spi_device_id pcf2127_spi_id[] = { 1352 { "pcf2127", PCF2127 }, 1353 { "pcf2129", PCF2129 }, 1354 { "pca2129", PCF2129 }, 1355 { "pcf2131", PCF2131 }, 1356 { } 1357 }; 1358 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1359 1360 static struct spi_driver pcf2127_spi_driver = { 1361 .driver = { 1362 .name = "rtc-pcf2127-spi", 1363 .of_match_table = of_match_ptr(pcf2127_of_match), 1364 }, 1365 .probe = pcf2127_spi_probe, 1366 .id_table = pcf2127_spi_id, 1367 }; 1368 1369 static int pcf2127_spi_register_driver(void) 1370 { 1371 return spi_register_driver(&pcf2127_spi_driver); 1372 } 1373 1374 static void pcf2127_spi_unregister_driver(void) 1375 { 1376 spi_unregister_driver(&pcf2127_spi_driver); 1377 } 1378 1379 #else 1380 1381 static int pcf2127_spi_register_driver(void) 1382 { 1383 return 0; 1384 } 1385 1386 static void pcf2127_spi_unregister_driver(void) 1387 { 1388 } 1389 1390 #endif 1391 1392 static int __init pcf2127_init(void) 1393 { 1394 int ret; 1395 1396 ret = pcf2127_i2c_register_driver(); 1397 if (ret) { 1398 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1399 return ret; 1400 } 1401 1402 ret = pcf2127_spi_register_driver(); 1403 if (ret) { 1404 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1405 pcf2127_i2c_unregister_driver(); 1406 } 1407 1408 return ret; 1409 } 1410 module_init(pcf2127_init) 1411 1412 static void __exit pcf2127_exit(void) 1413 { 1414 pcf2127_spi_unregister_driver(); 1415 pcf2127_i2c_unregister_driver(); 1416 } 1417 module_exit(pcf2127_exit) 1418 1419 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1420 MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver"); 1421 MODULE_LICENSE("GPL v2"); 1422