1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/regmap.h> 25 #include <linux/watchdog.h> 26 27 /* Control register 1 */ 28 #define PCF2127_REG_CTRL1 0x00 29 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 30 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 31 /* Control register 2 */ 32 #define PCF2127_REG_CTRL2 0x01 33 #define PCF2127_BIT_CTRL2_AIE BIT(1) 34 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 35 #define PCF2127_BIT_CTRL2_AF BIT(4) 36 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 37 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 38 /* Control register 3 */ 39 #define PCF2127_REG_CTRL3 0x02 40 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 41 #define PCF2127_BIT_CTRL3_BIE BIT(1) 42 #define PCF2127_BIT_CTRL3_BLF BIT(2) 43 #define PCF2127_BIT_CTRL3_BF BIT(3) 44 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 45 /* Time and date registers */ 46 #define PCF2127_REG_SC 0x03 47 #define PCF2127_BIT_SC_OSF BIT(7) 48 /* Alarm registers */ 49 #define PCF2127_REG_ALARM_SC 0x0A 50 #define PCF2127_REG_ALARM_MN 0x0B 51 #define PCF2127_REG_ALARM_HR 0x0C 52 #define PCF2127_REG_ALARM_DM 0x0D 53 #define PCF2127_REG_ALARM_DW 0x0E 54 #define PCF2127_BIT_ALARM_AE BIT(7) 55 /* CLKOUT control register */ 56 #define PCF2127_REG_CLKOUT 0x0f 57 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 58 /* Watchdog registers */ 59 #define PCF2127_REG_WD_CTL 0x10 60 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 61 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 62 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 63 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 64 #define PCF2127_REG_WD_VAL 0x11 65 /* Tamper timestamp registers */ 66 #define PCF2127_REG_TS_CTRL 0x12 67 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 68 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 69 /* 70 * RAM registers 71 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 72 * battery backed and can survive a power outage. 73 * PCF2129 doesn't have this feature. 74 */ 75 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 76 #define PCF2127_REG_RAM_WRT_CMD 0x1C 77 #define PCF2127_REG_RAM_RD_CMD 0x1D 78 79 /* Watchdog timer value constants */ 80 #define PCF2127_WD_VAL_STOP 0 81 #define PCF2127_WD_VAL_MIN 2 82 #define PCF2127_WD_VAL_MAX 255 83 #define PCF2127_WD_VAL_DEFAULT 60 84 85 /* Mask for currently enabled interrupts */ 86 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 87 #define PCF2127_CTRL2_IRQ_MASK ( \ 88 PCF2127_BIT_CTRL2_AF | \ 89 PCF2127_BIT_CTRL2_WDTF | \ 90 PCF2127_BIT_CTRL2_TSF2) 91 92 struct pcf2127 { 93 struct rtc_device *rtc; 94 struct watchdog_device wdd; 95 struct regmap *regmap; 96 time64_t ts; 97 bool ts_valid; 98 bool irq_enabled; 99 }; 100 101 /* 102 * In the routines that deal directly with the pcf2127 hardware, we use 103 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 104 */ 105 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 106 { 107 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 108 unsigned char buf[7]; 109 int ret; 110 111 /* 112 * Avoid reading CTRL2 register as it causes WD_VAL register 113 * value to reset to 0 which means watchdog is stopped. 114 */ 115 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_SC, buf, 116 sizeof(buf)); 117 if (ret) { 118 dev_err(dev, "%s: read error\n", __func__); 119 return ret; 120 } 121 122 /* Clock integrity is not guaranteed when OSF flag is set. */ 123 if (buf[0] & PCF2127_BIT_SC_OSF) { 124 /* 125 * no need clear the flag here, 126 * it will be cleared once the new date is saved 127 */ 128 dev_warn(dev, 129 "oscillator stop detected, date/time is not reliable\n"); 130 return -EINVAL; 131 } 132 133 dev_dbg(dev, 134 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 135 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 136 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 137 138 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 139 tm->tm_min = bcd2bin(buf[1] & 0x7F); 140 tm->tm_hour = bcd2bin(buf[2] & 0x3F); /* rtc hr 0-23 */ 141 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 142 tm->tm_wday = buf[4] & 0x07; 143 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; /* rtc mn 1-12 */ 144 tm->tm_year = bcd2bin(buf[6]); 145 tm->tm_year += 100; 146 147 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 148 "mday=%d, mon=%d, year=%d, wday=%d\n", 149 __func__, 150 tm->tm_sec, tm->tm_min, tm->tm_hour, 151 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 152 153 return 0; 154 } 155 156 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 157 { 158 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 159 unsigned char buf[7]; 160 int i = 0, err; 161 162 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 163 "mday=%d, mon=%d, year=%d, wday=%d\n", 164 __func__, 165 tm->tm_sec, tm->tm_min, tm->tm_hour, 166 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 167 168 /* hours, minutes and seconds */ 169 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 170 buf[i++] = bin2bcd(tm->tm_min); 171 buf[i++] = bin2bcd(tm->tm_hour); 172 buf[i++] = bin2bcd(tm->tm_mday); 173 buf[i++] = tm->tm_wday & 0x07; 174 175 /* month, 1 - 12 */ 176 buf[i++] = bin2bcd(tm->tm_mon + 1); 177 178 /* year */ 179 buf[i++] = bin2bcd(tm->tm_year - 100); 180 181 /* write register's data */ 182 err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i); 183 if (err) { 184 dev_err(dev, 185 "%s: err=%d", __func__, err); 186 return err; 187 } 188 189 return 0; 190 } 191 192 static int pcf2127_rtc_ioctl(struct device *dev, 193 unsigned int cmd, unsigned long arg) 194 { 195 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 196 int val, touser = 0; 197 int ret; 198 199 switch (cmd) { 200 case RTC_VL_READ: 201 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 202 if (ret) 203 return ret; 204 205 if (val & PCF2127_BIT_CTRL3_BLF) 206 touser |= RTC_VL_BACKUP_LOW; 207 208 if (val & PCF2127_BIT_CTRL3_BF) 209 touser |= RTC_VL_BACKUP_SWITCH; 210 211 return put_user(touser, (unsigned int __user *)arg); 212 213 case RTC_VL_CLR: 214 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 215 PCF2127_BIT_CTRL3_BF, 0); 216 217 default: 218 return -ENOIOCTLCMD; 219 } 220 } 221 222 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 223 void *val, size_t bytes) 224 { 225 struct pcf2127 *pcf2127 = priv; 226 int ret; 227 unsigned char offsetbuf[] = { offset >> 8, offset }; 228 229 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 230 offsetbuf, 2); 231 if (ret) 232 return ret; 233 234 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 235 val, bytes); 236 } 237 238 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 239 void *val, size_t bytes) 240 { 241 struct pcf2127 *pcf2127 = priv; 242 int ret; 243 unsigned char offsetbuf[] = { offset >> 8, offset }; 244 245 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 246 offsetbuf, 2); 247 if (ret) 248 return ret; 249 250 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 251 val, bytes); 252 } 253 254 /* watchdog driver */ 255 256 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 257 { 258 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 259 260 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout); 261 } 262 263 /* 264 * Restart watchdog timer if feature is active. 265 * 266 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 267 * since register also contain control/status flags for other features. 268 * Always call this function after reading CTRL2 register. 269 */ 270 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 271 { 272 int ret = 0; 273 274 if (watchdog_active(wdd)) { 275 ret = pcf2127_wdt_ping(wdd); 276 if (ret) 277 dev_err(wdd->parent, 278 "%s: watchdog restart failed, ret=%d\n", 279 __func__, ret); 280 } 281 282 return ret; 283 } 284 285 static int pcf2127_wdt_start(struct watchdog_device *wdd) 286 { 287 return pcf2127_wdt_ping(wdd); 288 } 289 290 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 291 { 292 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 293 294 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, 295 PCF2127_WD_VAL_STOP); 296 } 297 298 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 299 unsigned int new_timeout) 300 { 301 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 302 new_timeout, wdd->timeout); 303 304 wdd->timeout = new_timeout; 305 306 return pcf2127_wdt_active_ping(wdd); 307 } 308 309 static const struct watchdog_info pcf2127_wdt_info = { 310 .identity = "NXP PCF2127/PCF2129 Watchdog", 311 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 312 }; 313 314 static const struct watchdog_ops pcf2127_watchdog_ops = { 315 .owner = THIS_MODULE, 316 .start = pcf2127_wdt_start, 317 .stop = pcf2127_wdt_stop, 318 .ping = pcf2127_wdt_ping, 319 .set_timeout = pcf2127_wdt_set_timeout, 320 }; 321 322 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 323 { 324 u32 wdd_timeout; 325 int ret; 326 327 if (!IS_ENABLED(CONFIG_WATCHDOG) || 328 !device_property_read_bool(dev, "reset-source")) 329 return 0; 330 331 pcf2127->wdd.parent = dev; 332 pcf2127->wdd.info = &pcf2127_wdt_info; 333 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 334 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 335 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 336 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 337 pcf2127->wdd.min_hw_heartbeat_ms = 500; 338 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 339 340 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 341 342 /* Test if watchdog timer is started by bootloader */ 343 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout); 344 if (ret) 345 return ret; 346 347 if (wdd_timeout) 348 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 349 350 return devm_watchdog_register_device(dev, &pcf2127->wdd); 351 } 352 353 /* Alarm */ 354 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 355 { 356 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 357 u8 buf[5]; 358 unsigned int ctrl2; 359 int ret; 360 361 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 362 if (ret) 363 return ret; 364 365 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 366 if (ret) 367 return ret; 368 369 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 370 sizeof(buf)); 371 if (ret) 372 return ret; 373 374 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 375 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 376 377 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 378 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 379 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 380 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 381 382 return 0; 383 } 384 385 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 386 { 387 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 388 int ret; 389 390 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 391 PCF2127_BIT_CTRL2_AIE, 392 enable ? PCF2127_BIT_CTRL2_AIE : 0); 393 if (ret) 394 return ret; 395 396 return pcf2127_wdt_active_ping(&pcf2127->wdd); 397 } 398 399 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 400 { 401 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 402 uint8_t buf[5]; 403 int ret; 404 405 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 406 PCF2127_BIT_CTRL2_AF, 0); 407 if (ret) 408 return ret; 409 410 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 411 if (ret) 412 return ret; 413 414 buf[0] = bin2bcd(alrm->time.tm_sec); 415 buf[1] = bin2bcd(alrm->time.tm_min); 416 buf[2] = bin2bcd(alrm->time.tm_hour); 417 buf[3] = bin2bcd(alrm->time.tm_mday); 418 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 419 420 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 421 sizeof(buf)); 422 if (ret) 423 return ret; 424 425 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 426 } 427 428 /* 429 * This function reads ctrl2 register, caller is responsible for calling 430 * pcf2127_wdt_active_ping() 431 */ 432 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) 433 { 434 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 435 struct rtc_time tm; 436 int ret; 437 unsigned char data[7]; 438 439 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_TS_CTRL, data, 440 sizeof(data)); 441 if (ret) { 442 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 443 return ret; 444 } 445 446 dev_dbg(dev, 447 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 448 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 449 450 tm.tm_sec = bcd2bin(data[1] & 0x7F); 451 tm.tm_min = bcd2bin(data[2] & 0x7F); 452 tm.tm_hour = bcd2bin(data[3] & 0x3F); 453 tm.tm_mday = bcd2bin(data[4] & 0x3F); 454 /* TS_MO register (month) value range: 1-12 */ 455 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 456 tm.tm_year = bcd2bin(data[6]); 457 if (tm.tm_year < 70) 458 tm.tm_year += 100; /* assume we are in 1970...2069 */ 459 460 ret = rtc_valid_tm(&tm); 461 if (ret) { 462 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 463 return ret; 464 } 465 466 *ts = rtc_tm_to_time64(&tm); 467 return 0; 468 }; 469 470 static void pcf2127_rtc_ts_snapshot(struct device *dev) 471 { 472 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 473 int ret; 474 475 /* Let userspace read the first timestamp */ 476 if (pcf2127->ts_valid) 477 return; 478 479 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts); 480 if (!ret) 481 pcf2127->ts_valid = true; 482 } 483 484 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 485 { 486 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 487 unsigned int ctrl1, ctrl2; 488 int ret = 0; 489 490 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 491 if (ret) 492 return IRQ_NONE; 493 494 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 495 if (ret) 496 return IRQ_NONE; 497 498 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 499 return IRQ_NONE; 500 501 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 502 pcf2127_rtc_ts_snapshot(dev); 503 504 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 505 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 506 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 507 508 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 509 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 510 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 511 512 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 513 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 514 515 pcf2127_wdt_active_ping(&pcf2127->wdd); 516 517 return IRQ_HANDLED; 518 } 519 520 static const struct rtc_class_ops pcf2127_rtc_ops = { 521 .ioctl = pcf2127_rtc_ioctl, 522 .read_time = pcf2127_rtc_read_time, 523 .set_time = pcf2127_rtc_set_time, 524 .read_alarm = pcf2127_rtc_read_alarm, 525 .set_alarm = pcf2127_rtc_set_alarm, 526 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 527 }; 528 529 /* sysfs interface */ 530 531 static ssize_t timestamp0_store(struct device *dev, 532 struct device_attribute *attr, 533 const char *buf, size_t count) 534 { 535 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 536 int ret; 537 538 if (pcf2127->irq_enabled) { 539 pcf2127->ts_valid = false; 540 } else { 541 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 542 PCF2127_BIT_CTRL1_TSF1, 0); 543 if (ret) { 544 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 545 return ret; 546 } 547 548 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 549 PCF2127_BIT_CTRL2_TSF2, 0); 550 if (ret) { 551 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 552 return ret; 553 } 554 555 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 556 if (ret) 557 return ret; 558 } 559 560 return count; 561 }; 562 563 static ssize_t timestamp0_show(struct device *dev, 564 struct device_attribute *attr, char *buf) 565 { 566 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 567 unsigned int ctrl1, ctrl2; 568 int ret; 569 time64_t ts; 570 571 if (pcf2127->irq_enabled) { 572 if (!pcf2127->ts_valid) 573 return 0; 574 ts = pcf2127->ts; 575 } else { 576 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 577 if (ret) 578 return 0; 579 580 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 581 if (ret) 582 return 0; 583 584 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && 585 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) 586 return 0; 587 588 ret = pcf2127_rtc_ts_read(dev->parent, &ts); 589 if (ret) 590 return 0; 591 592 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 593 if (ret) 594 return ret; 595 } 596 return sprintf(buf, "%llu\n", (unsigned long long)ts); 597 }; 598 599 static DEVICE_ATTR_RW(timestamp0); 600 601 static struct attribute *pcf2127_attrs[] = { 602 &dev_attr_timestamp0.attr, 603 NULL 604 }; 605 606 static const struct attribute_group pcf2127_attr_group = { 607 .attrs = pcf2127_attrs, 608 }; 609 610 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 611 int alarm_irq, const char *name, bool is_pcf2127) 612 { 613 struct pcf2127 *pcf2127; 614 int ret = 0; 615 unsigned int val; 616 617 dev_dbg(dev, "%s\n", __func__); 618 619 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 620 if (!pcf2127) 621 return -ENOMEM; 622 623 pcf2127->regmap = regmap; 624 625 dev_set_drvdata(dev, pcf2127); 626 627 pcf2127->rtc = devm_rtc_allocate_device(dev); 628 if (IS_ERR(pcf2127->rtc)) 629 return PTR_ERR(pcf2127->rtc); 630 631 pcf2127->rtc->ops = &pcf2127_rtc_ops; 632 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 633 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 634 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 635 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 636 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 637 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 638 639 if (alarm_irq > 0) { 640 unsigned long flags; 641 642 /* 643 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 644 * obtained from device tree. 645 */ 646 if (dev_fwnode(dev)) 647 flags = 0; 648 else 649 flags = IRQF_TRIGGER_LOW; 650 651 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 652 pcf2127_rtc_irq, 653 flags | IRQF_ONESHOT, 654 dev_name(dev), dev); 655 if (ret) { 656 dev_err(dev, "failed to request alarm irq\n"); 657 return ret; 658 } 659 pcf2127->irq_enabled = true; 660 } 661 662 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 663 device_init_wakeup(dev, true); 664 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 665 } 666 667 if (is_pcf2127) { 668 struct nvmem_config nvmem_cfg = { 669 .priv = pcf2127, 670 .reg_read = pcf2127_nvmem_read, 671 .reg_write = pcf2127_nvmem_write, 672 .size = 512, 673 }; 674 675 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 676 } 677 678 /* 679 * The "Power-On Reset Override" facility prevents the RTC to do a reset 680 * after power on. For normal operation the PORO must be disabled. 681 */ 682 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 683 PCF2127_BIT_CTRL1_POR_OVRD); 684 685 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); 686 if (ret < 0) 687 return ret; 688 689 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 690 ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, 691 PCF2127_BIT_CLKOUT_OTPR); 692 if (ret < 0) 693 return ret; 694 695 msleep(100); 696 } 697 698 /* 699 * Watchdog timer enabled and reset pin /RST activated when timed out. 700 * Select 1Hz clock source for watchdog timer. 701 * Note: Countdown timer disabled and not available. 702 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 703 * of register watchdg_tim_ctl. The bit[6] is labeled 704 * as T. Bits labeled as T must always be written with 705 * logic 0. 706 */ 707 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, 708 PCF2127_BIT_WD_CTL_CD1 | 709 PCF2127_BIT_WD_CTL_CD0 | 710 PCF2127_BIT_WD_CTL_TF1 | 711 PCF2127_BIT_WD_CTL_TF0, 712 PCF2127_BIT_WD_CTL_CD1 | 713 (is_pcf2127 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 714 PCF2127_BIT_WD_CTL_TF1); 715 if (ret) { 716 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 717 return ret; 718 } 719 720 pcf2127_watchdog_init(dev, pcf2127); 721 722 /* 723 * Disable battery low/switch-over timestamp and interrupts. 724 * Clear battery interrupt flags which can block new trigger events. 725 * Note: This is the default chip behaviour but added to ensure 726 * correct tamper timestamp and interrupt function. 727 */ 728 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 729 PCF2127_BIT_CTRL3_BTSE | 730 PCF2127_BIT_CTRL3_BIE | 731 PCF2127_BIT_CTRL3_BLIE, 0); 732 if (ret) { 733 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 734 __func__); 735 return ret; 736 } 737 738 /* 739 * Enable timestamp function and store timestamp of first trigger 740 * event until TSF1 and TSF2 interrupt flags are cleared. 741 */ 742 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 743 PCF2127_BIT_TS_CTRL_TSOFF | 744 PCF2127_BIT_TS_CTRL_TSM, 745 PCF2127_BIT_TS_CTRL_TSM); 746 if (ret) { 747 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 748 __func__); 749 return ret; 750 } 751 752 /* 753 * Enable interrupt generation when TSF1 or TSF2 timestamp flags 754 * are set. Interrupt signal is an open-drain output and can be 755 * left floating if unused. 756 */ 757 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 758 PCF2127_BIT_CTRL2_TSIE, 759 PCF2127_BIT_CTRL2_TSIE); 760 if (ret) { 761 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 762 __func__); 763 return ret; 764 } 765 766 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 767 if (ret) { 768 dev_err(dev, "%s: tamper sysfs registering failed\n", 769 __func__); 770 return ret; 771 } 772 773 return devm_rtc_register_device(pcf2127->rtc); 774 } 775 776 #ifdef CONFIG_OF 777 static const struct of_device_id pcf2127_of_match[] = { 778 { .compatible = "nxp,pcf2127" }, 779 { .compatible = "nxp,pcf2129" }, 780 { .compatible = "nxp,pca2129" }, 781 {} 782 }; 783 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 784 #endif 785 786 #if IS_ENABLED(CONFIG_I2C) 787 788 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 789 { 790 struct device *dev = context; 791 struct i2c_client *client = to_i2c_client(dev); 792 int ret; 793 794 ret = i2c_master_send(client, data, count); 795 if (ret != count) 796 return ret < 0 ? ret : -EIO; 797 798 return 0; 799 } 800 801 static int pcf2127_i2c_gather_write(void *context, 802 const void *reg, size_t reg_size, 803 const void *val, size_t val_size) 804 { 805 struct device *dev = context; 806 struct i2c_client *client = to_i2c_client(dev); 807 int ret; 808 void *buf; 809 810 if (WARN_ON(reg_size != 1)) 811 return -EINVAL; 812 813 buf = kmalloc(val_size + 1, GFP_KERNEL); 814 if (!buf) 815 return -ENOMEM; 816 817 memcpy(buf, reg, 1); 818 memcpy(buf + 1, val, val_size); 819 820 ret = i2c_master_send(client, buf, val_size + 1); 821 822 kfree(buf); 823 824 if (ret != val_size + 1) 825 return ret < 0 ? ret : -EIO; 826 827 return 0; 828 } 829 830 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 831 void *val, size_t val_size) 832 { 833 struct device *dev = context; 834 struct i2c_client *client = to_i2c_client(dev); 835 int ret; 836 837 if (WARN_ON(reg_size != 1)) 838 return -EINVAL; 839 840 ret = i2c_master_send(client, reg, 1); 841 if (ret != 1) 842 return ret < 0 ? ret : -EIO; 843 844 ret = i2c_master_recv(client, val, val_size); 845 if (ret != val_size) 846 return ret < 0 ? ret : -EIO; 847 848 return 0; 849 } 850 851 /* 852 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 853 * is that the STOP condition is required between set register address and 854 * read register data when reading from registers. 855 */ 856 static const struct regmap_bus pcf2127_i2c_regmap = { 857 .write = pcf2127_i2c_write, 858 .gather_write = pcf2127_i2c_gather_write, 859 .read = pcf2127_i2c_read, 860 }; 861 862 static struct i2c_driver pcf2127_i2c_driver; 863 864 static const struct i2c_device_id pcf2127_i2c_id[] = { 865 { "pcf2127", 1 }, 866 { "pcf2129", 0 }, 867 { "pca2129", 0 }, 868 { } 869 }; 870 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 871 872 static int pcf2127_i2c_probe(struct i2c_client *client) 873 { 874 const struct i2c_device_id *id = i2c_match_id(pcf2127_i2c_id, client); 875 struct regmap *regmap; 876 static const struct regmap_config config = { 877 .reg_bits = 8, 878 .val_bits = 8, 879 .max_register = 0x1d, 880 }; 881 882 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 883 return -ENODEV; 884 885 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 886 &client->dev, &config); 887 if (IS_ERR(regmap)) { 888 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 889 __func__, PTR_ERR(regmap)); 890 return PTR_ERR(regmap); 891 } 892 893 return pcf2127_probe(&client->dev, regmap, client->irq, 894 pcf2127_i2c_driver.driver.name, id->driver_data); 895 } 896 897 static struct i2c_driver pcf2127_i2c_driver = { 898 .driver = { 899 .name = "rtc-pcf2127-i2c", 900 .of_match_table = of_match_ptr(pcf2127_of_match), 901 }, 902 .probe = pcf2127_i2c_probe, 903 .id_table = pcf2127_i2c_id, 904 }; 905 906 static int pcf2127_i2c_register_driver(void) 907 { 908 return i2c_add_driver(&pcf2127_i2c_driver); 909 } 910 911 static void pcf2127_i2c_unregister_driver(void) 912 { 913 i2c_del_driver(&pcf2127_i2c_driver); 914 } 915 916 #else 917 918 static int pcf2127_i2c_register_driver(void) 919 { 920 return 0; 921 } 922 923 static void pcf2127_i2c_unregister_driver(void) 924 { 925 } 926 927 #endif 928 929 #if IS_ENABLED(CONFIG_SPI_MASTER) 930 931 static struct spi_driver pcf2127_spi_driver; 932 933 static int pcf2127_spi_probe(struct spi_device *spi) 934 { 935 static const struct regmap_config config = { 936 .reg_bits = 8, 937 .val_bits = 8, 938 .read_flag_mask = 0xa0, 939 .write_flag_mask = 0x20, 940 .max_register = 0x1d, 941 }; 942 struct regmap *regmap; 943 944 regmap = devm_regmap_init_spi(spi, &config); 945 if (IS_ERR(regmap)) { 946 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 947 __func__, PTR_ERR(regmap)); 948 return PTR_ERR(regmap); 949 } 950 951 return pcf2127_probe(&spi->dev, regmap, spi->irq, 952 pcf2127_spi_driver.driver.name, 953 spi_get_device_id(spi)->driver_data); 954 } 955 956 static const struct spi_device_id pcf2127_spi_id[] = { 957 { "pcf2127", 1 }, 958 { "pcf2129", 0 }, 959 { "pca2129", 0 }, 960 { } 961 }; 962 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 963 964 static struct spi_driver pcf2127_spi_driver = { 965 .driver = { 966 .name = "rtc-pcf2127-spi", 967 .of_match_table = of_match_ptr(pcf2127_of_match), 968 }, 969 .probe = pcf2127_spi_probe, 970 .id_table = pcf2127_spi_id, 971 }; 972 973 static int pcf2127_spi_register_driver(void) 974 { 975 return spi_register_driver(&pcf2127_spi_driver); 976 } 977 978 static void pcf2127_spi_unregister_driver(void) 979 { 980 spi_unregister_driver(&pcf2127_spi_driver); 981 } 982 983 #else 984 985 static int pcf2127_spi_register_driver(void) 986 { 987 return 0; 988 } 989 990 static void pcf2127_spi_unregister_driver(void) 991 { 992 } 993 994 #endif 995 996 static int __init pcf2127_init(void) 997 { 998 int ret; 999 1000 ret = pcf2127_i2c_register_driver(); 1001 if (ret) { 1002 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1003 return ret; 1004 } 1005 1006 ret = pcf2127_spi_register_driver(); 1007 if (ret) { 1008 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1009 pcf2127_i2c_unregister_driver(); 1010 } 1011 1012 return ret; 1013 } 1014 module_init(pcf2127_init) 1015 1016 static void __exit pcf2127_exit(void) 1017 { 1018 pcf2127_spi_unregister_driver(); 1019 pcf2127_i2c_unregister_driver(); 1020 } 1021 module_exit(pcf2127_exit) 1022 1023 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1024 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 1025 MODULE_LICENSE("GPL v2"); 1026