1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/regmap.h> 26 #include <linux/watchdog.h> 27 28 /* Control register 1 */ 29 #define PCF2127_REG_CTRL1 0x00 30 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 31 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 32 /* Control register 2 */ 33 #define PCF2127_REG_CTRL2 0x01 34 #define PCF2127_BIT_CTRL2_AIE BIT(1) 35 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 36 #define PCF2127_BIT_CTRL2_AF BIT(4) 37 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 38 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 39 /* Control register 3 */ 40 #define PCF2127_REG_CTRL3 0x02 41 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 42 #define PCF2127_BIT_CTRL3_BIE BIT(1) 43 #define PCF2127_BIT_CTRL3_BLF BIT(2) 44 #define PCF2127_BIT_CTRL3_BF BIT(3) 45 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 46 /* Time and date registers */ 47 #define PCF2127_REG_TIME_BASE 0x03 48 #define PCF2127_BIT_SC_OSF BIT(7) 49 /* Alarm registers */ 50 #define PCF2127_REG_ALARM_BASE 0x0A 51 #define PCF2127_BIT_ALARM_AE BIT(7) 52 /* CLKOUT control register */ 53 #define PCF2127_REG_CLKOUT 0x0f 54 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 55 /* Watchdog registers */ 56 #define PCF2127_REG_WD_CTL 0x10 57 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 58 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 59 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 60 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 61 #define PCF2127_REG_WD_VAL 0x11 62 /* Tamper timestamp registers */ 63 #define PCF2127_REG_TS_CTRL 0x12 64 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 65 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 66 /* 67 * RAM registers 68 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 69 * battery backed and can survive a power outage. 70 * PCF2129 doesn't have this feature. 71 */ 72 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 73 #define PCF2127_REG_RAM_WRT_CMD 0x1C 74 #define PCF2127_REG_RAM_RD_CMD 0x1D 75 76 /* Watchdog timer value constants */ 77 #define PCF2127_WD_VAL_STOP 0 78 #define PCF2127_WD_VAL_MIN 2 79 #define PCF2127_WD_VAL_MAX 255 80 #define PCF2127_WD_VAL_DEFAULT 60 81 82 /* Mask for currently enabled interrupts */ 83 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 84 #define PCF2127_CTRL2_IRQ_MASK ( \ 85 PCF2127_BIT_CTRL2_AF | \ 86 PCF2127_BIT_CTRL2_WDTF | \ 87 PCF2127_BIT_CTRL2_TSF2) 88 89 enum pcf21xx_type { 90 PCF2127, 91 PCF2129, 92 PCF21XX_LAST_ID 93 }; 94 95 struct pcf21xx_config { 96 int type; /* IC variant */ 97 int max_register; 98 unsigned int has_nvmem:1; 99 unsigned int has_bit_wd_ctl_cd0:1; 100 u8 reg_time_base; /* Time/date base register. */ 101 u8 regs_alarm_base; /* Alarm function base registers. */ 102 u8 reg_wd_ctl; /* Watchdog control register. */ 103 u8 reg_wd_val; /* Watchdog value register. */ 104 }; 105 106 struct pcf2127 { 107 struct rtc_device *rtc; 108 struct watchdog_device wdd; 109 struct regmap *regmap; 110 const struct pcf21xx_config *cfg; 111 time64_t ts; 112 bool ts_valid; 113 bool irq_enabled; 114 }; 115 116 /* 117 * In the routines that deal directly with the pcf2127 hardware, we use 118 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 119 */ 120 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 121 { 122 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 123 unsigned char buf[7]; 124 int ret; 125 126 /* 127 * Avoid reading CTRL2 register as it causes WD_VAL register 128 * value to reset to 0 which means watchdog is stopped. 129 */ 130 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 131 buf, sizeof(buf)); 132 if (ret) { 133 dev_err(dev, "%s: read error\n", __func__); 134 return ret; 135 } 136 137 /* Clock integrity is not guaranteed when OSF flag is set. */ 138 if (buf[0] & PCF2127_BIT_SC_OSF) { 139 /* 140 * no need clear the flag here, 141 * it will be cleared once the new date is saved 142 */ 143 dev_warn(dev, 144 "oscillator stop detected, date/time is not reliable\n"); 145 return -EINVAL; 146 } 147 148 dev_dbg(dev, 149 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 150 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 151 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 152 153 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 154 tm->tm_min = bcd2bin(buf[1] & 0x7F); 155 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 156 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 157 tm->tm_wday = buf[4] & 0x07; 158 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 159 tm->tm_year = bcd2bin(buf[6]); 160 tm->tm_year += 100; 161 162 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 163 "mday=%d, mon=%d, year=%d, wday=%d\n", 164 __func__, 165 tm->tm_sec, tm->tm_min, tm->tm_hour, 166 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 167 168 return 0; 169 } 170 171 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 172 { 173 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 174 unsigned char buf[7]; 175 int i = 0, err; 176 177 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 178 "mday=%d, mon=%d, year=%d, wday=%d\n", 179 __func__, 180 tm->tm_sec, tm->tm_min, tm->tm_hour, 181 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 182 183 /* hours, minutes and seconds */ 184 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 185 buf[i++] = bin2bcd(tm->tm_min); 186 buf[i++] = bin2bcd(tm->tm_hour); 187 buf[i++] = bin2bcd(tm->tm_mday); 188 buf[i++] = tm->tm_wday & 0x07; 189 190 /* month, 1 - 12 */ 191 buf[i++] = bin2bcd(tm->tm_mon + 1); 192 193 /* year */ 194 buf[i++] = bin2bcd(tm->tm_year - 100); 195 196 /* write register's data */ 197 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 198 if (err) { 199 dev_dbg(dev, "%s: err=%d", __func__, err); 200 return err; 201 } 202 203 return 0; 204 } 205 206 static int pcf2127_rtc_ioctl(struct device *dev, 207 unsigned int cmd, unsigned long arg) 208 { 209 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 210 int val, touser = 0; 211 int ret; 212 213 switch (cmd) { 214 case RTC_VL_READ: 215 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 216 if (ret) 217 return ret; 218 219 if (val & PCF2127_BIT_CTRL3_BLF) 220 touser |= RTC_VL_BACKUP_LOW; 221 222 if (val & PCF2127_BIT_CTRL3_BF) 223 touser |= RTC_VL_BACKUP_SWITCH; 224 225 return put_user(touser, (unsigned int __user *)arg); 226 227 case RTC_VL_CLR: 228 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 229 PCF2127_BIT_CTRL3_BF, 0); 230 231 default: 232 return -ENOIOCTLCMD; 233 } 234 } 235 236 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 237 void *val, size_t bytes) 238 { 239 struct pcf2127 *pcf2127 = priv; 240 int ret; 241 unsigned char offsetbuf[] = { offset >> 8, offset }; 242 243 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 244 offsetbuf, 2); 245 if (ret) 246 return ret; 247 248 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 249 val, bytes); 250 } 251 252 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 253 void *val, size_t bytes) 254 { 255 struct pcf2127 *pcf2127 = priv; 256 int ret; 257 unsigned char offsetbuf[] = { offset >> 8, offset }; 258 259 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 260 offsetbuf, 2); 261 if (ret) 262 return ret; 263 264 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 265 val, bytes); 266 } 267 268 /* watchdog driver */ 269 270 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 271 { 272 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 273 274 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout); 275 } 276 277 /* 278 * Restart watchdog timer if feature is active. 279 * 280 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 281 * since register also contain control/status flags for other features. 282 * Always call this function after reading CTRL2 register. 283 */ 284 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 285 { 286 int ret = 0; 287 288 if (watchdog_active(wdd)) { 289 ret = pcf2127_wdt_ping(wdd); 290 if (ret) 291 dev_err(wdd->parent, 292 "%s: watchdog restart failed, ret=%d\n", 293 __func__, ret); 294 } 295 296 return ret; 297 } 298 299 static int pcf2127_wdt_start(struct watchdog_device *wdd) 300 { 301 return pcf2127_wdt_ping(wdd); 302 } 303 304 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 305 { 306 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 307 308 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 309 PCF2127_WD_VAL_STOP); 310 } 311 312 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 313 unsigned int new_timeout) 314 { 315 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 316 new_timeout, wdd->timeout); 317 318 wdd->timeout = new_timeout; 319 320 return pcf2127_wdt_active_ping(wdd); 321 } 322 323 static const struct watchdog_info pcf2127_wdt_info = { 324 .identity = "NXP PCF2127/PCF2129 Watchdog", 325 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 326 }; 327 328 static const struct watchdog_ops pcf2127_watchdog_ops = { 329 .owner = THIS_MODULE, 330 .start = pcf2127_wdt_start, 331 .stop = pcf2127_wdt_stop, 332 .ping = pcf2127_wdt_ping, 333 .set_timeout = pcf2127_wdt_set_timeout, 334 }; 335 336 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 337 { 338 u32 wdd_timeout; 339 int ret; 340 341 if (!IS_ENABLED(CONFIG_WATCHDOG) || 342 !device_property_read_bool(dev, "reset-source")) 343 return 0; 344 345 pcf2127->wdd.parent = dev; 346 pcf2127->wdd.info = &pcf2127_wdt_info; 347 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 348 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 349 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 350 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 351 pcf2127->wdd.min_hw_heartbeat_ms = 500; 352 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 353 354 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 355 356 /* Test if watchdog timer is started by bootloader */ 357 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 358 if (ret) 359 return ret; 360 361 if (wdd_timeout) 362 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 363 364 return devm_watchdog_register_device(dev, &pcf2127->wdd); 365 } 366 367 /* Alarm */ 368 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 369 { 370 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 371 u8 buf[5]; 372 unsigned int ctrl2; 373 int ret; 374 375 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 376 if (ret) 377 return ret; 378 379 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 380 if (ret) 381 return ret; 382 383 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 384 buf, sizeof(buf)); 385 if (ret) 386 return ret; 387 388 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 389 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 390 391 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 392 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 393 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 394 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 395 396 return 0; 397 } 398 399 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 400 { 401 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 402 int ret; 403 404 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 405 PCF2127_BIT_CTRL2_AIE, 406 enable ? PCF2127_BIT_CTRL2_AIE : 0); 407 if (ret) 408 return ret; 409 410 return pcf2127_wdt_active_ping(&pcf2127->wdd); 411 } 412 413 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 414 { 415 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 416 uint8_t buf[5]; 417 int ret; 418 419 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 420 PCF2127_BIT_CTRL2_AF, 0); 421 if (ret) 422 return ret; 423 424 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 425 if (ret) 426 return ret; 427 428 buf[0] = bin2bcd(alrm->time.tm_sec); 429 buf[1] = bin2bcd(alrm->time.tm_min); 430 buf[2] = bin2bcd(alrm->time.tm_hour); 431 buf[3] = bin2bcd(alrm->time.tm_mday); 432 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 433 434 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 435 buf, sizeof(buf)); 436 if (ret) 437 return ret; 438 439 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 440 } 441 442 /* 443 * This function reads ctrl2 register, caller is responsible for calling 444 * pcf2127_wdt_active_ping() 445 */ 446 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) 447 { 448 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 449 struct rtc_time tm; 450 int ret; 451 unsigned char data[7]; 452 453 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_TS_CTRL, data, 454 sizeof(data)); 455 if (ret) { 456 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 457 return ret; 458 } 459 460 dev_dbg(dev, 461 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 462 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 463 464 tm.tm_sec = bcd2bin(data[1] & 0x7F); 465 tm.tm_min = bcd2bin(data[2] & 0x7F); 466 tm.tm_hour = bcd2bin(data[3] & 0x3F); 467 tm.tm_mday = bcd2bin(data[4] & 0x3F); 468 /* TS_MO register (month) value range: 1-12 */ 469 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 470 tm.tm_year = bcd2bin(data[6]); 471 if (tm.tm_year < 70) 472 tm.tm_year += 100; /* assume we are in 1970...2069 */ 473 474 ret = rtc_valid_tm(&tm); 475 if (ret) { 476 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 477 return ret; 478 } 479 480 *ts = rtc_tm_to_time64(&tm); 481 return 0; 482 }; 483 484 static void pcf2127_rtc_ts_snapshot(struct device *dev) 485 { 486 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 487 int ret; 488 489 /* Let userspace read the first timestamp */ 490 if (pcf2127->ts_valid) 491 return; 492 493 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts); 494 if (!ret) 495 pcf2127->ts_valid = true; 496 } 497 498 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 499 { 500 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 501 unsigned int ctrl1, ctrl2; 502 int ret = 0; 503 504 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 505 if (ret) 506 return IRQ_NONE; 507 508 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 509 if (ret) 510 return IRQ_NONE; 511 512 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 513 return IRQ_NONE; 514 515 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 516 pcf2127_rtc_ts_snapshot(dev); 517 518 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 519 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 520 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 521 522 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 523 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 524 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 525 526 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 527 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 528 529 pcf2127_wdt_active_ping(&pcf2127->wdd); 530 531 return IRQ_HANDLED; 532 } 533 534 static const struct rtc_class_ops pcf2127_rtc_ops = { 535 .ioctl = pcf2127_rtc_ioctl, 536 .read_time = pcf2127_rtc_read_time, 537 .set_time = pcf2127_rtc_set_time, 538 .read_alarm = pcf2127_rtc_read_alarm, 539 .set_alarm = pcf2127_rtc_set_alarm, 540 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 541 }; 542 543 /* sysfs interface */ 544 545 static ssize_t timestamp0_store(struct device *dev, 546 struct device_attribute *attr, 547 const char *buf, size_t count) 548 { 549 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 550 int ret; 551 552 if (pcf2127->irq_enabled) { 553 pcf2127->ts_valid = false; 554 } else { 555 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 556 PCF2127_BIT_CTRL1_TSF1, 0); 557 if (ret) { 558 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 559 return ret; 560 } 561 562 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 563 PCF2127_BIT_CTRL2_TSF2, 0); 564 if (ret) { 565 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 566 return ret; 567 } 568 569 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 570 if (ret) 571 return ret; 572 } 573 574 return count; 575 }; 576 577 static ssize_t timestamp0_show(struct device *dev, 578 struct device_attribute *attr, char *buf) 579 { 580 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 581 unsigned int ctrl1, ctrl2; 582 int ret; 583 time64_t ts; 584 585 if (pcf2127->irq_enabled) { 586 if (!pcf2127->ts_valid) 587 return 0; 588 ts = pcf2127->ts; 589 } else { 590 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 591 if (ret) 592 return 0; 593 594 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 595 if (ret) 596 return 0; 597 598 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && 599 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) 600 return 0; 601 602 ret = pcf2127_rtc_ts_read(dev->parent, &ts); 603 if (ret) 604 return 0; 605 606 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 607 if (ret) 608 return ret; 609 } 610 return sprintf(buf, "%llu\n", (unsigned long long)ts); 611 }; 612 613 static DEVICE_ATTR_RW(timestamp0); 614 615 static struct attribute *pcf2127_attrs[] = { 616 &dev_attr_timestamp0.attr, 617 NULL 618 }; 619 620 static const struct attribute_group pcf2127_attr_group = { 621 .attrs = pcf2127_attrs, 622 }; 623 624 static struct pcf21xx_config pcf21xx_cfg[] = { 625 [PCF2127] = { 626 .type = PCF2127, 627 .max_register = 0x1d, 628 .has_nvmem = 1, 629 .has_bit_wd_ctl_cd0 = 1, 630 .reg_time_base = PCF2127_REG_TIME_BASE, 631 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 632 .reg_wd_ctl = PCF2127_REG_WD_CTL, 633 .reg_wd_val = PCF2127_REG_WD_VAL, 634 }, 635 [PCF2129] = { 636 .type = PCF2129, 637 .max_register = 0x19, 638 .has_nvmem = 0, 639 .has_bit_wd_ctl_cd0 = 0, 640 .reg_time_base = PCF2127_REG_TIME_BASE, 641 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 642 .reg_wd_ctl = PCF2127_REG_WD_CTL, 643 .reg_wd_val = PCF2127_REG_WD_VAL, 644 }, 645 }; 646 647 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 648 int alarm_irq, const char *name, const struct pcf21xx_config *config) 649 { 650 struct pcf2127 *pcf2127; 651 int ret = 0; 652 unsigned int val; 653 654 dev_dbg(dev, "%s\n", __func__); 655 656 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 657 if (!pcf2127) 658 return -ENOMEM; 659 660 pcf2127->regmap = regmap; 661 pcf2127->cfg = config; 662 663 dev_set_drvdata(dev, pcf2127); 664 665 pcf2127->rtc = devm_rtc_allocate_device(dev); 666 if (IS_ERR(pcf2127->rtc)) 667 return PTR_ERR(pcf2127->rtc); 668 669 pcf2127->rtc->ops = &pcf2127_rtc_ops; 670 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 671 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 672 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 673 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 674 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 675 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 676 677 if (alarm_irq > 0) { 678 unsigned long flags; 679 680 /* 681 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 682 * obtained from device tree. 683 */ 684 if (dev_fwnode(dev)) 685 flags = 0; 686 else 687 flags = IRQF_TRIGGER_LOW; 688 689 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 690 pcf2127_rtc_irq, 691 flags | IRQF_ONESHOT, 692 dev_name(dev), dev); 693 if (ret) { 694 dev_err(dev, "failed to request alarm irq\n"); 695 return ret; 696 } 697 pcf2127->irq_enabled = true; 698 } 699 700 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 701 device_init_wakeup(dev, true); 702 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 703 } 704 705 if (pcf2127->cfg->has_nvmem) { 706 struct nvmem_config nvmem_cfg = { 707 .priv = pcf2127, 708 .reg_read = pcf2127_nvmem_read, 709 .reg_write = pcf2127_nvmem_write, 710 .size = 512, 711 }; 712 713 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 714 } 715 716 /* 717 * The "Power-On Reset Override" facility prevents the RTC to do a reset 718 * after power on. For normal operation the PORO must be disabled. 719 */ 720 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 721 PCF2127_BIT_CTRL1_POR_OVRD); 722 723 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); 724 if (ret < 0) 725 return ret; 726 727 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 728 ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, 729 PCF2127_BIT_CLKOUT_OTPR); 730 if (ret < 0) 731 return ret; 732 733 msleep(100); 734 } 735 736 /* 737 * Watchdog timer enabled and reset pin /RST activated when timed out. 738 * Select 1Hz clock source for watchdog timer. 739 * Note: Countdown timer disabled and not available. 740 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 741 * of register watchdg_tim_ctl. The bit[6] is labeled 742 * as T. Bits labeled as T must always be written with 743 * logic 0. 744 */ 745 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 746 PCF2127_BIT_WD_CTL_CD1 | 747 PCF2127_BIT_WD_CTL_CD0 | 748 PCF2127_BIT_WD_CTL_TF1 | 749 PCF2127_BIT_WD_CTL_TF0, 750 PCF2127_BIT_WD_CTL_CD1 | 751 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 752 PCF2127_BIT_WD_CTL_TF1); 753 if (ret) { 754 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 755 return ret; 756 } 757 758 pcf2127_watchdog_init(dev, pcf2127); 759 760 /* 761 * Disable battery low/switch-over timestamp and interrupts. 762 * Clear battery interrupt flags which can block new trigger events. 763 * Note: This is the default chip behaviour but added to ensure 764 * correct tamper timestamp and interrupt function. 765 */ 766 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 767 PCF2127_BIT_CTRL3_BTSE | 768 PCF2127_BIT_CTRL3_BIE | 769 PCF2127_BIT_CTRL3_BLIE, 0); 770 if (ret) { 771 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 772 __func__); 773 return ret; 774 } 775 776 /* 777 * Enable timestamp function and store timestamp of first trigger 778 * event until TSF1 and TSF2 interrupt flags are cleared. 779 */ 780 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 781 PCF2127_BIT_TS_CTRL_TSOFF | 782 PCF2127_BIT_TS_CTRL_TSM, 783 PCF2127_BIT_TS_CTRL_TSM); 784 if (ret) { 785 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 786 __func__); 787 return ret; 788 } 789 790 /* 791 * Enable interrupt generation when TSF1 or TSF2 timestamp flags 792 * are set. Interrupt signal is an open-drain output and can be 793 * left floating if unused. 794 */ 795 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 796 PCF2127_BIT_CTRL2_TSIE, 797 PCF2127_BIT_CTRL2_TSIE); 798 if (ret) { 799 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 800 __func__); 801 return ret; 802 } 803 804 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 805 if (ret) { 806 dev_err(dev, "%s: tamper sysfs registering failed\n", 807 __func__); 808 return ret; 809 } 810 811 return devm_rtc_register_device(pcf2127->rtc); 812 } 813 814 #ifdef CONFIG_OF 815 static const struct of_device_id pcf2127_of_match[] = { 816 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 817 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 818 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 819 {} 820 }; 821 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 822 #endif 823 824 #if IS_ENABLED(CONFIG_I2C) 825 826 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 827 { 828 struct device *dev = context; 829 struct i2c_client *client = to_i2c_client(dev); 830 int ret; 831 832 ret = i2c_master_send(client, data, count); 833 if (ret != count) 834 return ret < 0 ? ret : -EIO; 835 836 return 0; 837 } 838 839 static int pcf2127_i2c_gather_write(void *context, 840 const void *reg, size_t reg_size, 841 const void *val, size_t val_size) 842 { 843 struct device *dev = context; 844 struct i2c_client *client = to_i2c_client(dev); 845 int ret; 846 void *buf; 847 848 if (WARN_ON(reg_size != 1)) 849 return -EINVAL; 850 851 buf = kmalloc(val_size + 1, GFP_KERNEL); 852 if (!buf) 853 return -ENOMEM; 854 855 memcpy(buf, reg, 1); 856 memcpy(buf + 1, val, val_size); 857 858 ret = i2c_master_send(client, buf, val_size + 1); 859 860 kfree(buf); 861 862 if (ret != val_size + 1) 863 return ret < 0 ? ret : -EIO; 864 865 return 0; 866 } 867 868 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 869 void *val, size_t val_size) 870 { 871 struct device *dev = context; 872 struct i2c_client *client = to_i2c_client(dev); 873 int ret; 874 875 if (WARN_ON(reg_size != 1)) 876 return -EINVAL; 877 878 ret = i2c_master_send(client, reg, 1); 879 if (ret != 1) 880 return ret < 0 ? ret : -EIO; 881 882 ret = i2c_master_recv(client, val, val_size); 883 if (ret != val_size) 884 return ret < 0 ? ret : -EIO; 885 886 return 0; 887 } 888 889 /* 890 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 891 * is that the STOP condition is required between set register address and 892 * read register data when reading from registers. 893 */ 894 static const struct regmap_bus pcf2127_i2c_regmap = { 895 .write = pcf2127_i2c_write, 896 .gather_write = pcf2127_i2c_gather_write, 897 .read = pcf2127_i2c_read, 898 }; 899 900 static struct i2c_driver pcf2127_i2c_driver; 901 902 static const struct i2c_device_id pcf2127_i2c_id[] = { 903 { "pcf2127", PCF2127 }, 904 { "pcf2129", PCF2129 }, 905 { "pca2129", PCF2129 }, 906 { } 907 }; 908 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 909 910 static int pcf2127_i2c_probe(struct i2c_client *client) 911 { 912 struct regmap *regmap; 913 static struct regmap_config config = { 914 .reg_bits = 8, 915 .val_bits = 8, 916 }; 917 const struct pcf21xx_config *variant; 918 919 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 920 return -ENODEV; 921 922 if (client->dev.of_node) { 923 variant = of_device_get_match_data(&client->dev); 924 if (!variant) 925 return -ENODEV; 926 } else { 927 enum pcf21xx_type type = 928 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 929 930 if (type >= PCF21XX_LAST_ID) 931 return -ENODEV; 932 variant = &pcf21xx_cfg[type]; 933 } 934 935 config.max_register = variant->max_register, 936 937 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 938 &client->dev, &config); 939 if (IS_ERR(regmap)) { 940 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 941 __func__, PTR_ERR(regmap)); 942 return PTR_ERR(regmap); 943 } 944 945 return pcf2127_probe(&client->dev, regmap, client->irq, 946 pcf2127_i2c_driver.driver.name, variant); 947 } 948 949 static struct i2c_driver pcf2127_i2c_driver = { 950 .driver = { 951 .name = "rtc-pcf2127-i2c", 952 .of_match_table = of_match_ptr(pcf2127_of_match), 953 }, 954 .probe = pcf2127_i2c_probe, 955 .id_table = pcf2127_i2c_id, 956 }; 957 958 static int pcf2127_i2c_register_driver(void) 959 { 960 return i2c_add_driver(&pcf2127_i2c_driver); 961 } 962 963 static void pcf2127_i2c_unregister_driver(void) 964 { 965 i2c_del_driver(&pcf2127_i2c_driver); 966 } 967 968 #else 969 970 static int pcf2127_i2c_register_driver(void) 971 { 972 return 0; 973 } 974 975 static void pcf2127_i2c_unregister_driver(void) 976 { 977 } 978 979 #endif 980 981 #if IS_ENABLED(CONFIG_SPI_MASTER) 982 983 static struct spi_driver pcf2127_spi_driver; 984 static const struct spi_device_id pcf2127_spi_id[]; 985 986 static int pcf2127_spi_probe(struct spi_device *spi) 987 { 988 static struct regmap_config config = { 989 .reg_bits = 8, 990 .val_bits = 8, 991 .read_flag_mask = 0xa0, 992 .write_flag_mask = 0x20, 993 }; 994 struct regmap *regmap; 995 const struct pcf21xx_config *variant; 996 997 if (spi->dev.of_node) { 998 variant = of_device_get_match_data(&spi->dev); 999 if (!variant) 1000 return -ENODEV; 1001 } else { 1002 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1003 1004 if (type >= PCF21XX_LAST_ID) 1005 return -ENODEV; 1006 variant = &pcf21xx_cfg[type]; 1007 } 1008 1009 config.max_register = variant->max_register, 1010 1011 regmap = devm_regmap_init_spi(spi, &config); 1012 if (IS_ERR(regmap)) { 1013 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1014 __func__, PTR_ERR(regmap)); 1015 return PTR_ERR(regmap); 1016 } 1017 1018 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1019 pcf2127_spi_driver.driver.name, 1020 variant); 1021 } 1022 1023 static const struct spi_device_id pcf2127_spi_id[] = { 1024 { "pcf2127", PCF2127 }, 1025 { "pcf2129", PCF2129 }, 1026 { "pca2129", PCF2129 }, 1027 { } 1028 }; 1029 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1030 1031 static struct spi_driver pcf2127_spi_driver = { 1032 .driver = { 1033 .name = "rtc-pcf2127-spi", 1034 .of_match_table = of_match_ptr(pcf2127_of_match), 1035 }, 1036 .probe = pcf2127_spi_probe, 1037 .id_table = pcf2127_spi_id, 1038 }; 1039 1040 static int pcf2127_spi_register_driver(void) 1041 { 1042 return spi_register_driver(&pcf2127_spi_driver); 1043 } 1044 1045 static void pcf2127_spi_unregister_driver(void) 1046 { 1047 spi_unregister_driver(&pcf2127_spi_driver); 1048 } 1049 1050 #else 1051 1052 static int pcf2127_spi_register_driver(void) 1053 { 1054 return 0; 1055 } 1056 1057 static void pcf2127_spi_unregister_driver(void) 1058 { 1059 } 1060 1061 #endif 1062 1063 static int __init pcf2127_init(void) 1064 { 1065 int ret; 1066 1067 ret = pcf2127_i2c_register_driver(); 1068 if (ret) { 1069 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1070 return ret; 1071 } 1072 1073 ret = pcf2127_spi_register_driver(); 1074 if (ret) { 1075 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1076 pcf2127_i2c_unregister_driver(); 1077 } 1078 1079 return ret; 1080 } 1081 module_init(pcf2127_init) 1082 1083 static void __exit pcf2127_exit(void) 1084 { 1085 pcf2127_spi_unregister_driver(); 1086 pcf2127_i2c_unregister_driver(); 1087 } 1088 module_exit(pcf2127_exit) 1089 1090 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1091 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 1092 MODULE_LICENSE("GPL v2"); 1093