1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/regmap.h> 26 #include <linux/watchdog.h> 27 28 /* Control register 1 */ 29 #define PCF2127_REG_CTRL1 0x00 30 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 31 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 32 /* Control register 2 */ 33 #define PCF2127_REG_CTRL2 0x01 34 #define PCF2127_BIT_CTRL2_AIE BIT(1) 35 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 36 #define PCF2127_BIT_CTRL2_AF BIT(4) 37 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 38 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 39 /* Control register 3 */ 40 #define PCF2127_REG_CTRL3 0x02 41 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 42 #define PCF2127_BIT_CTRL3_BIE BIT(1) 43 #define PCF2127_BIT_CTRL3_BLF BIT(2) 44 #define PCF2127_BIT_CTRL3_BF BIT(3) 45 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 46 /* Time and date registers */ 47 #define PCF2127_REG_TIME_BASE 0x03 48 #define PCF2127_BIT_SC_OSF BIT(7) 49 /* Alarm registers */ 50 #define PCF2127_REG_ALARM_BASE 0x0A 51 #define PCF2127_BIT_ALARM_AE BIT(7) 52 /* CLKOUT control register */ 53 #define PCF2127_REG_CLKOUT 0x0f 54 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 55 /* Watchdog registers */ 56 #define PCF2127_REG_WD_CTL 0x10 57 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 58 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 59 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 60 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 61 #define PCF2127_REG_WD_VAL 0x11 62 /* Tamper timestamp1 registers */ 63 #define PCF2127_REG_TS1_BASE 0x12 64 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 65 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 66 /* 67 * RAM registers 68 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 69 * battery backed and can survive a power outage. 70 * PCF2129 doesn't have this feature. 71 */ 72 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 73 #define PCF2127_REG_RAM_WRT_CMD 0x1C 74 #define PCF2127_REG_RAM_RD_CMD 0x1D 75 76 /* Watchdog timer value constants */ 77 #define PCF2127_WD_VAL_STOP 0 78 #define PCF2127_WD_VAL_MIN 2 79 #define PCF2127_WD_VAL_MAX 255 80 #define PCF2127_WD_VAL_DEFAULT 60 81 82 /* Mask for currently enabled interrupts */ 83 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 84 #define PCF2127_CTRL2_IRQ_MASK ( \ 85 PCF2127_BIT_CTRL2_AF | \ 86 PCF2127_BIT_CTRL2_WDTF | \ 87 PCF2127_BIT_CTRL2_TSF2) 88 89 #define PCF2127_MAX_TS_SUPPORTED 1 90 91 enum pcf21xx_type { 92 PCF2127, 93 PCF2129, 94 PCF21XX_LAST_ID 95 }; 96 97 struct pcf21xx_ts_config { 98 u8 reg_base; /* Base register to read timestamp values. */ 99 100 /* 101 * If the TS input pin is driven to GND, an interrupt can be generated 102 * (supported by all variants). 103 */ 104 u8 gnd_detect_reg; /* Interrupt control register address. */ 105 u8 gnd_detect_bit; /* Interrupt bit. */ 106 107 /* 108 * If the TS input pin is driven to an intermediate level between GND 109 * and supply, an interrupt can be generated (optional feature depending 110 * on variant). 111 */ 112 u8 inter_detect_reg; /* Interrupt control register address. */ 113 u8 inter_detect_bit; /* Interrupt bit. */ 114 115 u8 ie_reg; /* Interrupt enable control register. */ 116 u8 ie_bit; /* Interrupt enable bit. */ 117 }; 118 119 struct pcf21xx_config { 120 int type; /* IC variant */ 121 int max_register; 122 unsigned int has_nvmem:1; 123 unsigned int has_bit_wd_ctl_cd0:1; 124 u8 reg_time_base; /* Time/date base register. */ 125 u8 regs_alarm_base; /* Alarm function base registers. */ 126 u8 reg_wd_ctl; /* Watchdog control register. */ 127 u8 reg_wd_val; /* Watchdog value register. */ 128 u8 reg_clkout; /* Clkout register. */ 129 unsigned int ts_count; 130 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED]; 131 struct attribute_group attribute_group; 132 }; 133 134 struct pcf2127 { 135 struct rtc_device *rtc; 136 struct watchdog_device wdd; 137 struct regmap *regmap; 138 const struct pcf21xx_config *cfg; 139 bool irq_enabled; 140 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */ 141 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */ 142 }; 143 144 /* 145 * In the routines that deal directly with the pcf2127 hardware, we use 146 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 147 */ 148 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 149 { 150 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 151 unsigned char buf[7]; 152 int ret; 153 154 /* 155 * Avoid reading CTRL2 register as it causes WD_VAL register 156 * value to reset to 0 which means watchdog is stopped. 157 */ 158 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 159 buf, sizeof(buf)); 160 if (ret) { 161 dev_err(dev, "%s: read error\n", __func__); 162 return ret; 163 } 164 165 /* Clock integrity is not guaranteed when OSF flag is set. */ 166 if (buf[0] & PCF2127_BIT_SC_OSF) { 167 /* 168 * no need clear the flag here, 169 * it will be cleared once the new date is saved 170 */ 171 dev_warn(dev, 172 "oscillator stop detected, date/time is not reliable\n"); 173 return -EINVAL; 174 } 175 176 dev_dbg(dev, 177 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 178 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 179 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 180 181 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 182 tm->tm_min = bcd2bin(buf[1] & 0x7F); 183 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 184 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 185 tm->tm_wday = buf[4] & 0x07; 186 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 187 tm->tm_year = bcd2bin(buf[6]); 188 tm->tm_year += 100; 189 190 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 191 "mday=%d, mon=%d, year=%d, wday=%d\n", 192 __func__, 193 tm->tm_sec, tm->tm_min, tm->tm_hour, 194 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 195 196 return 0; 197 } 198 199 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 200 { 201 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 202 unsigned char buf[7]; 203 int i = 0, err; 204 205 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 206 "mday=%d, mon=%d, year=%d, wday=%d\n", 207 __func__, 208 tm->tm_sec, tm->tm_min, tm->tm_hour, 209 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 210 211 /* hours, minutes and seconds */ 212 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 213 buf[i++] = bin2bcd(tm->tm_min); 214 buf[i++] = bin2bcd(tm->tm_hour); 215 buf[i++] = bin2bcd(tm->tm_mday); 216 buf[i++] = tm->tm_wday & 0x07; 217 218 /* month, 1 - 12 */ 219 buf[i++] = bin2bcd(tm->tm_mon + 1); 220 221 /* year */ 222 buf[i++] = bin2bcd(tm->tm_year - 100); 223 224 /* write register's data */ 225 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 226 if (err) { 227 dev_dbg(dev, "%s: err=%d", __func__, err); 228 return err; 229 } 230 231 return 0; 232 } 233 234 static int pcf2127_rtc_ioctl(struct device *dev, 235 unsigned int cmd, unsigned long arg) 236 { 237 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 238 int val, touser = 0; 239 int ret; 240 241 switch (cmd) { 242 case RTC_VL_READ: 243 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 244 if (ret) 245 return ret; 246 247 if (val & PCF2127_BIT_CTRL3_BLF) 248 touser |= RTC_VL_BACKUP_LOW; 249 250 if (val & PCF2127_BIT_CTRL3_BF) 251 touser |= RTC_VL_BACKUP_SWITCH; 252 253 return put_user(touser, (unsigned int __user *)arg); 254 255 case RTC_VL_CLR: 256 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 257 PCF2127_BIT_CTRL3_BF, 0); 258 259 default: 260 return -ENOIOCTLCMD; 261 } 262 } 263 264 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 265 void *val, size_t bytes) 266 { 267 struct pcf2127 *pcf2127 = priv; 268 int ret; 269 unsigned char offsetbuf[] = { offset >> 8, offset }; 270 271 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 272 offsetbuf, 2); 273 if (ret) 274 return ret; 275 276 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 277 val, bytes); 278 } 279 280 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 281 void *val, size_t bytes) 282 { 283 struct pcf2127 *pcf2127 = priv; 284 int ret; 285 unsigned char offsetbuf[] = { offset >> 8, offset }; 286 287 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 288 offsetbuf, 2); 289 if (ret) 290 return ret; 291 292 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 293 val, bytes); 294 } 295 296 /* watchdog driver */ 297 298 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 299 { 300 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 301 302 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout); 303 } 304 305 /* 306 * Restart watchdog timer if feature is active. 307 * 308 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 309 * since register also contain control/status flags for other features. 310 * Always call this function after reading CTRL2 register. 311 */ 312 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 313 { 314 int ret = 0; 315 316 if (watchdog_active(wdd)) { 317 ret = pcf2127_wdt_ping(wdd); 318 if (ret) 319 dev_err(wdd->parent, 320 "%s: watchdog restart failed, ret=%d\n", 321 __func__, ret); 322 } 323 324 return ret; 325 } 326 327 static int pcf2127_wdt_start(struct watchdog_device *wdd) 328 { 329 return pcf2127_wdt_ping(wdd); 330 } 331 332 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 333 { 334 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 335 336 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 337 PCF2127_WD_VAL_STOP); 338 } 339 340 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 341 unsigned int new_timeout) 342 { 343 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 344 new_timeout, wdd->timeout); 345 346 wdd->timeout = new_timeout; 347 348 return pcf2127_wdt_active_ping(wdd); 349 } 350 351 static const struct watchdog_info pcf2127_wdt_info = { 352 .identity = "NXP PCF2127/PCF2129 Watchdog", 353 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 354 }; 355 356 static const struct watchdog_ops pcf2127_watchdog_ops = { 357 .owner = THIS_MODULE, 358 .start = pcf2127_wdt_start, 359 .stop = pcf2127_wdt_stop, 360 .ping = pcf2127_wdt_ping, 361 .set_timeout = pcf2127_wdt_set_timeout, 362 }; 363 364 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 365 { 366 u32 wdd_timeout; 367 int ret; 368 369 if (!IS_ENABLED(CONFIG_WATCHDOG) || 370 !device_property_read_bool(dev, "reset-source")) 371 return 0; 372 373 pcf2127->wdd.parent = dev; 374 pcf2127->wdd.info = &pcf2127_wdt_info; 375 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 376 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 377 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 378 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 379 pcf2127->wdd.min_hw_heartbeat_ms = 500; 380 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 381 382 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 383 384 /* Test if watchdog timer is started by bootloader */ 385 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 386 if (ret) 387 return ret; 388 389 if (wdd_timeout) 390 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 391 392 return devm_watchdog_register_device(dev, &pcf2127->wdd); 393 } 394 395 /* Alarm */ 396 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 397 { 398 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 399 u8 buf[5]; 400 unsigned int ctrl2; 401 int ret; 402 403 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 404 if (ret) 405 return ret; 406 407 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 408 if (ret) 409 return ret; 410 411 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 412 buf, sizeof(buf)); 413 if (ret) 414 return ret; 415 416 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 417 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 418 419 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 420 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 421 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 422 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 423 424 return 0; 425 } 426 427 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 428 { 429 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 430 int ret; 431 432 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 433 PCF2127_BIT_CTRL2_AIE, 434 enable ? PCF2127_BIT_CTRL2_AIE : 0); 435 if (ret) 436 return ret; 437 438 return pcf2127_wdt_active_ping(&pcf2127->wdd); 439 } 440 441 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 442 { 443 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 444 uint8_t buf[5]; 445 int ret; 446 447 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 448 PCF2127_BIT_CTRL2_AF, 0); 449 if (ret) 450 return ret; 451 452 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 453 if (ret) 454 return ret; 455 456 buf[0] = bin2bcd(alrm->time.tm_sec); 457 buf[1] = bin2bcd(alrm->time.tm_min); 458 buf[2] = bin2bcd(alrm->time.tm_hour); 459 buf[3] = bin2bcd(alrm->time.tm_mday); 460 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 461 462 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 463 buf, sizeof(buf)); 464 if (ret) 465 return ret; 466 467 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 468 } 469 470 /* 471 * This function reads one timestamp function data, caller is responsible for 472 * calling pcf2127_wdt_active_ping() 473 */ 474 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts, 475 int ts_id) 476 { 477 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 478 struct rtc_time tm; 479 int ret; 480 unsigned char data[7]; 481 482 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base, 483 data, sizeof(data)); 484 if (ret) { 485 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 486 return ret; 487 } 488 489 dev_dbg(dev, 490 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 491 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 492 493 tm.tm_sec = bcd2bin(data[1] & 0x7F); 494 tm.tm_min = bcd2bin(data[2] & 0x7F); 495 tm.tm_hour = bcd2bin(data[3] & 0x3F); 496 tm.tm_mday = bcd2bin(data[4] & 0x3F); 497 /* TS_MO register (month) value range: 1-12 */ 498 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 499 tm.tm_year = bcd2bin(data[6]); 500 if (tm.tm_year < 70) 501 tm.tm_year += 100; /* assume we are in 1970...2069 */ 502 503 ret = rtc_valid_tm(&tm); 504 if (ret) { 505 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 506 return ret; 507 } 508 509 *ts = rtc_tm_to_time64(&tm); 510 return 0; 511 }; 512 513 static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id) 514 { 515 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 516 int ret; 517 518 if (ts_id >= pcf2127->cfg->ts_count) 519 return; 520 521 /* Let userspace read the first timestamp */ 522 if (pcf2127->ts_valid[ts_id]) 523 return; 524 525 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id); 526 if (!ret) 527 pcf2127->ts_valid[ts_id] = true; 528 } 529 530 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 531 { 532 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 533 unsigned int ctrl1, ctrl2; 534 int ret = 0; 535 536 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 537 if (ret) 538 return IRQ_NONE; 539 540 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 541 if (ret) 542 return IRQ_NONE; 543 544 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 545 return IRQ_NONE; 546 547 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 548 pcf2127_rtc_ts_snapshot(dev, 0); 549 550 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 551 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 552 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 553 554 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 555 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 556 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 557 558 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 559 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 560 561 pcf2127_wdt_active_ping(&pcf2127->wdd); 562 563 return IRQ_HANDLED; 564 } 565 566 static const struct rtc_class_ops pcf2127_rtc_ops = { 567 .ioctl = pcf2127_rtc_ioctl, 568 .read_time = pcf2127_rtc_read_time, 569 .set_time = pcf2127_rtc_set_time, 570 .read_alarm = pcf2127_rtc_read_alarm, 571 .set_alarm = pcf2127_rtc_set_alarm, 572 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 573 }; 574 575 /* sysfs interface */ 576 577 static ssize_t timestamp_store(struct device *dev, 578 struct device_attribute *attr, 579 const char *buf, size_t count, int ts_id) 580 { 581 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 582 int ret; 583 584 if (ts_id >= pcf2127->cfg->ts_count) 585 return 0; 586 587 if (pcf2127->irq_enabled) { 588 pcf2127->ts_valid[ts_id] = false; 589 } else { 590 /* Always clear GND interrupt bit. */ 591 ret = regmap_update_bits(pcf2127->regmap, 592 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 593 pcf2127->cfg->ts[ts_id].gnd_detect_bit, 594 0); 595 596 if (ret) { 597 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret); 598 return ret; 599 } 600 601 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 602 /* Clear intermediate level interrupt bit if supported. */ 603 ret = regmap_update_bits(pcf2127->regmap, 604 pcf2127->cfg->ts[ts_id].inter_detect_reg, 605 pcf2127->cfg->ts[ts_id].inter_detect_bit, 606 0); 607 if (ret) { 608 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n", 609 __func__, ret); 610 return ret; 611 } 612 } 613 614 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 615 if (ret) 616 return ret; 617 } 618 619 return count; 620 } 621 622 static ssize_t timestamp0_store(struct device *dev, 623 struct device_attribute *attr, 624 const char *buf, size_t count) 625 { 626 return timestamp_store(dev, attr, buf, count, 0); 627 }; 628 629 static ssize_t timestamp_show(struct device *dev, 630 struct device_attribute *attr, char *buf, 631 int ts_id) 632 { 633 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 634 int ret; 635 time64_t ts; 636 637 if (ts_id >= pcf2127->cfg->ts_count) 638 return 0; 639 640 if (pcf2127->irq_enabled) { 641 if (!pcf2127->ts_valid[ts_id]) 642 return 0; 643 ts = pcf2127->ts[ts_id]; 644 } else { 645 u8 valid_low = 0; 646 u8 valid_inter = 0; 647 unsigned int ctrl; 648 649 /* Check if TS input pin is driven to GND, supported by all 650 * variants. 651 */ 652 ret = regmap_read(pcf2127->regmap, 653 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 654 &ctrl); 655 if (ret) 656 return 0; 657 658 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit; 659 660 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 661 /* Check if TS input pin is driven to intermediate level 662 * between GND and supply, if supported by variant. 663 */ 664 ret = regmap_read(pcf2127->regmap, 665 pcf2127->cfg->ts[ts_id].inter_detect_reg, 666 &ctrl); 667 if (ret) 668 return 0; 669 670 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit; 671 } 672 673 if (!valid_low && !valid_inter) 674 return 0; 675 676 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id); 677 if (ret) 678 return 0; 679 680 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 681 if (ret) 682 return ret; 683 } 684 return sprintf(buf, "%llu\n", (unsigned long long)ts); 685 } 686 687 static ssize_t timestamp0_show(struct device *dev, 688 struct device_attribute *attr, char *buf) 689 { 690 return timestamp_show(dev, attr, buf, 0); 691 }; 692 693 static DEVICE_ATTR_RW(timestamp0); 694 695 static struct attribute *pcf2127_attrs[] = { 696 &dev_attr_timestamp0.attr, 697 NULL 698 }; 699 700 static struct pcf21xx_config pcf21xx_cfg[] = { 701 [PCF2127] = { 702 .type = PCF2127, 703 .max_register = 0x1d, 704 .has_nvmem = 1, 705 .has_bit_wd_ctl_cd0 = 1, 706 .reg_time_base = PCF2127_REG_TIME_BASE, 707 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 708 .reg_wd_ctl = PCF2127_REG_WD_CTL, 709 .reg_wd_val = PCF2127_REG_WD_VAL, 710 .reg_clkout = PCF2127_REG_CLKOUT, 711 .ts_count = 1, 712 .ts[0] = { 713 .reg_base = PCF2127_REG_TS1_BASE, 714 .gnd_detect_reg = PCF2127_REG_CTRL1, 715 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 716 .inter_detect_reg = PCF2127_REG_CTRL2, 717 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 718 .ie_reg = PCF2127_REG_CTRL2, 719 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 720 }, 721 .attribute_group = { 722 .attrs = pcf2127_attrs, 723 }, 724 }, 725 [PCF2129] = { 726 .type = PCF2129, 727 .max_register = 0x19, 728 .has_nvmem = 0, 729 .has_bit_wd_ctl_cd0 = 0, 730 .reg_time_base = PCF2127_REG_TIME_BASE, 731 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 732 .reg_wd_ctl = PCF2127_REG_WD_CTL, 733 .reg_wd_val = PCF2127_REG_WD_VAL, 734 .reg_clkout = PCF2127_REG_CLKOUT, 735 .ts_count = 1, 736 .ts[0] = { 737 .reg_base = PCF2127_REG_TS1_BASE, 738 .gnd_detect_reg = PCF2127_REG_CTRL1, 739 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 740 .inter_detect_reg = PCF2127_REG_CTRL2, 741 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 742 .ie_reg = PCF2127_REG_CTRL2, 743 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 744 }, 745 .attribute_group = { 746 .attrs = pcf2127_attrs, 747 }, 748 }, 749 }; 750 751 /* 752 * Enable timestamp function and corresponding interrupt(s). 753 */ 754 static int pcf2127_enable_ts(struct device *dev, int ts_id) 755 { 756 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 757 int ret; 758 759 if (ts_id >= pcf2127->cfg->ts_count) { 760 dev_err(dev, "%s: invalid tamper detection ID (%d)\n", 761 __func__, ts_id); 762 return -EINVAL; 763 } 764 765 /* Enable timestamp function. */ 766 ret = regmap_update_bits(pcf2127->regmap, 767 pcf2127->cfg->ts[ts_id].reg_base, 768 PCF2127_BIT_TS_CTRL_TSOFF | 769 PCF2127_BIT_TS_CTRL_TSM, 770 PCF2127_BIT_TS_CTRL_TSM); 771 if (ret) { 772 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n", 773 __func__, ts_id); 774 return ret; 775 } 776 777 /* TS input pin driven to GND detection is supported by all variants. 778 * Make sure that interrupt bit is defined. 779 */ 780 if (pcf2127->cfg->ts[ts_id].gnd_detect_bit == 0) { 781 dev_err(dev, "%s: tamper detection to GND configuration invalid\n", 782 __func__); 783 return ret; 784 } 785 786 /* 787 * Enable interrupt generation when TSF timestamp flag is set. 788 * Interrupt signals are open-drain outputs and can be left floating if 789 * unused. 790 */ 791 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg, 792 pcf2127->cfg->ts[ts_id].ie_bit, 793 pcf2127->cfg->ts[ts_id].ie_bit); 794 if (ret) { 795 dev_err(dev, "%s: tamper detection TSIE%d config failed\n", 796 __func__, ts_id); 797 return ret; 798 } 799 800 return ret; 801 } 802 803 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 804 int alarm_irq, const char *name, const struct pcf21xx_config *config) 805 { 806 struct pcf2127 *pcf2127; 807 int ret = 0; 808 unsigned int val; 809 810 dev_dbg(dev, "%s\n", __func__); 811 812 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 813 if (!pcf2127) 814 return -ENOMEM; 815 816 pcf2127->regmap = regmap; 817 pcf2127->cfg = config; 818 819 dev_set_drvdata(dev, pcf2127); 820 821 pcf2127->rtc = devm_rtc_allocate_device(dev); 822 if (IS_ERR(pcf2127->rtc)) 823 return PTR_ERR(pcf2127->rtc); 824 825 pcf2127->rtc->ops = &pcf2127_rtc_ops; 826 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 827 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 828 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 829 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 830 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 831 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 832 833 if (alarm_irq > 0) { 834 unsigned long flags; 835 836 /* 837 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 838 * obtained from device tree. 839 */ 840 if (dev_fwnode(dev)) 841 flags = 0; 842 else 843 flags = IRQF_TRIGGER_LOW; 844 845 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 846 pcf2127_rtc_irq, 847 flags | IRQF_ONESHOT, 848 dev_name(dev), dev); 849 if (ret) { 850 dev_err(dev, "failed to request alarm irq\n"); 851 return ret; 852 } 853 pcf2127->irq_enabled = true; 854 } 855 856 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 857 device_init_wakeup(dev, true); 858 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 859 } 860 861 if (pcf2127->cfg->has_nvmem) { 862 struct nvmem_config nvmem_cfg = { 863 .priv = pcf2127, 864 .reg_read = pcf2127_nvmem_read, 865 .reg_write = pcf2127_nvmem_write, 866 .size = 512, 867 }; 868 869 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 870 } 871 872 /* 873 * The "Power-On Reset Override" facility prevents the RTC to do a reset 874 * after power on. For normal operation the PORO must be disabled. 875 */ 876 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 877 PCF2127_BIT_CTRL1_POR_OVRD); 878 879 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); 880 if (ret < 0) 881 return ret; 882 883 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 884 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, 885 PCF2127_BIT_CLKOUT_OTPR); 886 if (ret < 0) 887 return ret; 888 889 msleep(100); 890 } 891 892 /* 893 * Watchdog timer enabled and reset pin /RST activated when timed out. 894 * Select 1Hz clock source for watchdog timer. 895 * Note: Countdown timer disabled and not available. 896 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 897 * of register watchdg_tim_ctl. The bit[6] is labeled 898 * as T. Bits labeled as T must always be written with 899 * logic 0. 900 */ 901 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 902 PCF2127_BIT_WD_CTL_CD1 | 903 PCF2127_BIT_WD_CTL_CD0 | 904 PCF2127_BIT_WD_CTL_TF1 | 905 PCF2127_BIT_WD_CTL_TF0, 906 PCF2127_BIT_WD_CTL_CD1 | 907 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 908 PCF2127_BIT_WD_CTL_TF1); 909 if (ret) { 910 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 911 return ret; 912 } 913 914 pcf2127_watchdog_init(dev, pcf2127); 915 916 /* 917 * Disable battery low/switch-over timestamp and interrupts. 918 * Clear battery interrupt flags which can block new trigger events. 919 * Note: This is the default chip behaviour but added to ensure 920 * correct tamper timestamp and interrupt function. 921 */ 922 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 923 PCF2127_BIT_CTRL3_BTSE | 924 PCF2127_BIT_CTRL3_BIE | 925 PCF2127_BIT_CTRL3_BLIE, 0); 926 if (ret) { 927 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 928 __func__); 929 return ret; 930 } 931 932 /* 933 * Enable timestamp functions 1 to 4. 934 */ 935 for (int i = 0; i < pcf2127->cfg->ts_count; i++) { 936 ret = pcf2127_enable_ts(dev, i); 937 if (ret) 938 return ret; 939 } 940 941 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group); 942 if (ret) { 943 dev_err(dev, "%s: tamper sysfs registering failed\n", 944 __func__); 945 return ret; 946 } 947 948 return devm_rtc_register_device(pcf2127->rtc); 949 } 950 951 #ifdef CONFIG_OF 952 static const struct of_device_id pcf2127_of_match[] = { 953 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 954 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 955 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 956 {} 957 }; 958 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 959 #endif 960 961 #if IS_ENABLED(CONFIG_I2C) 962 963 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 964 { 965 struct device *dev = context; 966 struct i2c_client *client = to_i2c_client(dev); 967 int ret; 968 969 ret = i2c_master_send(client, data, count); 970 if (ret != count) 971 return ret < 0 ? ret : -EIO; 972 973 return 0; 974 } 975 976 static int pcf2127_i2c_gather_write(void *context, 977 const void *reg, size_t reg_size, 978 const void *val, size_t val_size) 979 { 980 struct device *dev = context; 981 struct i2c_client *client = to_i2c_client(dev); 982 int ret; 983 void *buf; 984 985 if (WARN_ON(reg_size != 1)) 986 return -EINVAL; 987 988 buf = kmalloc(val_size + 1, GFP_KERNEL); 989 if (!buf) 990 return -ENOMEM; 991 992 memcpy(buf, reg, 1); 993 memcpy(buf + 1, val, val_size); 994 995 ret = i2c_master_send(client, buf, val_size + 1); 996 997 kfree(buf); 998 999 if (ret != val_size + 1) 1000 return ret < 0 ? ret : -EIO; 1001 1002 return 0; 1003 } 1004 1005 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 1006 void *val, size_t val_size) 1007 { 1008 struct device *dev = context; 1009 struct i2c_client *client = to_i2c_client(dev); 1010 int ret; 1011 1012 if (WARN_ON(reg_size != 1)) 1013 return -EINVAL; 1014 1015 ret = i2c_master_send(client, reg, 1); 1016 if (ret != 1) 1017 return ret < 0 ? ret : -EIO; 1018 1019 ret = i2c_master_recv(client, val, val_size); 1020 if (ret != val_size) 1021 return ret < 0 ? ret : -EIO; 1022 1023 return 0; 1024 } 1025 1026 /* 1027 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 1028 * is that the STOP condition is required between set register address and 1029 * read register data when reading from registers. 1030 */ 1031 static const struct regmap_bus pcf2127_i2c_regmap = { 1032 .write = pcf2127_i2c_write, 1033 .gather_write = pcf2127_i2c_gather_write, 1034 .read = pcf2127_i2c_read, 1035 }; 1036 1037 static struct i2c_driver pcf2127_i2c_driver; 1038 1039 static const struct i2c_device_id pcf2127_i2c_id[] = { 1040 { "pcf2127", PCF2127 }, 1041 { "pcf2129", PCF2129 }, 1042 { "pca2129", PCF2129 }, 1043 { } 1044 }; 1045 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 1046 1047 static int pcf2127_i2c_probe(struct i2c_client *client) 1048 { 1049 struct regmap *regmap; 1050 static struct regmap_config config = { 1051 .reg_bits = 8, 1052 .val_bits = 8, 1053 }; 1054 const struct pcf21xx_config *variant; 1055 1056 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 1057 return -ENODEV; 1058 1059 if (client->dev.of_node) { 1060 variant = of_device_get_match_data(&client->dev); 1061 if (!variant) 1062 return -ENODEV; 1063 } else { 1064 enum pcf21xx_type type = 1065 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 1066 1067 if (type >= PCF21XX_LAST_ID) 1068 return -ENODEV; 1069 variant = &pcf21xx_cfg[type]; 1070 } 1071 1072 config.max_register = variant->max_register, 1073 1074 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 1075 &client->dev, &config); 1076 if (IS_ERR(regmap)) { 1077 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 1078 __func__, PTR_ERR(regmap)); 1079 return PTR_ERR(regmap); 1080 } 1081 1082 return pcf2127_probe(&client->dev, regmap, client->irq, 1083 pcf2127_i2c_driver.driver.name, variant); 1084 } 1085 1086 static struct i2c_driver pcf2127_i2c_driver = { 1087 .driver = { 1088 .name = "rtc-pcf2127-i2c", 1089 .of_match_table = of_match_ptr(pcf2127_of_match), 1090 }, 1091 .probe = pcf2127_i2c_probe, 1092 .id_table = pcf2127_i2c_id, 1093 }; 1094 1095 static int pcf2127_i2c_register_driver(void) 1096 { 1097 return i2c_add_driver(&pcf2127_i2c_driver); 1098 } 1099 1100 static void pcf2127_i2c_unregister_driver(void) 1101 { 1102 i2c_del_driver(&pcf2127_i2c_driver); 1103 } 1104 1105 #else 1106 1107 static int pcf2127_i2c_register_driver(void) 1108 { 1109 return 0; 1110 } 1111 1112 static void pcf2127_i2c_unregister_driver(void) 1113 { 1114 } 1115 1116 #endif 1117 1118 #if IS_ENABLED(CONFIG_SPI_MASTER) 1119 1120 static struct spi_driver pcf2127_spi_driver; 1121 static const struct spi_device_id pcf2127_spi_id[]; 1122 1123 static int pcf2127_spi_probe(struct spi_device *spi) 1124 { 1125 static struct regmap_config config = { 1126 .reg_bits = 8, 1127 .val_bits = 8, 1128 .read_flag_mask = 0xa0, 1129 .write_flag_mask = 0x20, 1130 }; 1131 struct regmap *regmap; 1132 const struct pcf21xx_config *variant; 1133 1134 if (spi->dev.of_node) { 1135 variant = of_device_get_match_data(&spi->dev); 1136 if (!variant) 1137 return -ENODEV; 1138 } else { 1139 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1140 1141 if (type >= PCF21XX_LAST_ID) 1142 return -ENODEV; 1143 variant = &pcf21xx_cfg[type]; 1144 } 1145 1146 config.max_register = variant->max_register, 1147 1148 regmap = devm_regmap_init_spi(spi, &config); 1149 if (IS_ERR(regmap)) { 1150 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1151 __func__, PTR_ERR(regmap)); 1152 return PTR_ERR(regmap); 1153 } 1154 1155 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1156 pcf2127_spi_driver.driver.name, 1157 variant); 1158 } 1159 1160 static const struct spi_device_id pcf2127_spi_id[] = { 1161 { "pcf2127", PCF2127 }, 1162 { "pcf2129", PCF2129 }, 1163 { "pca2129", PCF2129 }, 1164 { } 1165 }; 1166 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1167 1168 static struct spi_driver pcf2127_spi_driver = { 1169 .driver = { 1170 .name = "rtc-pcf2127-spi", 1171 .of_match_table = of_match_ptr(pcf2127_of_match), 1172 }, 1173 .probe = pcf2127_spi_probe, 1174 .id_table = pcf2127_spi_id, 1175 }; 1176 1177 static int pcf2127_spi_register_driver(void) 1178 { 1179 return spi_register_driver(&pcf2127_spi_driver); 1180 } 1181 1182 static void pcf2127_spi_unregister_driver(void) 1183 { 1184 spi_unregister_driver(&pcf2127_spi_driver); 1185 } 1186 1187 #else 1188 1189 static int pcf2127_spi_register_driver(void) 1190 { 1191 return 0; 1192 } 1193 1194 static void pcf2127_spi_unregister_driver(void) 1195 { 1196 } 1197 1198 #endif 1199 1200 static int __init pcf2127_init(void) 1201 { 1202 int ret; 1203 1204 ret = pcf2127_i2c_register_driver(); 1205 if (ret) { 1206 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1207 return ret; 1208 } 1209 1210 ret = pcf2127_spi_register_driver(); 1211 if (ret) { 1212 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1213 pcf2127_i2c_unregister_driver(); 1214 } 1215 1216 return ret; 1217 } 1218 module_init(pcf2127_init) 1219 1220 static void __exit pcf2127_exit(void) 1221 { 1222 pcf2127_spi_unregister_driver(); 1223 pcf2127_i2c_unregister_driver(); 1224 } 1225 module_exit(pcf2127_exit) 1226 1227 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1228 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 1229 MODULE_LICENSE("GPL v2"); 1230