1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * PCF2131 support 12 * Author: Hugo Villeneuve <[email protected]> 13 * 14 * based on the other drivers in this same directory. 15 * 16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/spi/spi.h> 22 #include <linux/bcd.h> 23 #include <linux/rtc.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_device.h> 29 #include <linux/regmap.h> 30 #include <linux/watchdog.h> 31 32 /* Control register 1 */ 33 #define PCF2127_REG_CTRL1 0x00 34 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 35 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 36 #define PCF2127_BIT_CTRL1_STOP BIT(5) 37 /* Control register 2 */ 38 #define PCF2127_REG_CTRL2 0x01 39 #define PCF2127_BIT_CTRL2_AIE BIT(1) 40 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 41 #define PCF2127_BIT_CTRL2_AF BIT(4) 42 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 43 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 44 /* Control register 3 */ 45 #define PCF2127_REG_CTRL3 0x02 46 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 47 #define PCF2127_BIT_CTRL3_BIE BIT(1) 48 #define PCF2127_BIT_CTRL3_BLF BIT(2) 49 #define PCF2127_BIT_CTRL3_BF BIT(3) 50 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 51 /* Time and date registers */ 52 #define PCF2127_REG_TIME_BASE 0x03 53 #define PCF2127_BIT_SC_OSF BIT(7) 54 /* Alarm registers */ 55 #define PCF2127_REG_ALARM_BASE 0x0A 56 #define PCF2127_BIT_ALARM_AE BIT(7) 57 /* CLKOUT control register */ 58 #define PCF2127_REG_CLKOUT 0x0f 59 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 60 /* Watchdog registers */ 61 #define PCF2127_REG_WD_CTL 0x10 62 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 63 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 64 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 65 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 66 #define PCF2127_REG_WD_VAL 0x11 67 /* Tamper timestamp1 registers */ 68 #define PCF2127_REG_TS1_BASE 0x12 69 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 70 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 71 /* 72 * RAM registers 73 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 74 * battery backed and can survive a power outage. 75 * PCF2129/31 doesn't have this feature. 76 */ 77 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 78 #define PCF2127_REG_RAM_WRT_CMD 0x1C 79 #define PCF2127_REG_RAM_RD_CMD 0x1D 80 81 /* Watchdog timer value constants */ 82 #define PCF2127_WD_VAL_STOP 0 83 #define PCF2127_WD_VAL_MIN 2 84 #define PCF2127_WD_VAL_MAX 255 85 #define PCF2127_WD_VAL_DEFAULT 60 86 87 /* Mask for currently enabled interrupts */ 88 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 89 #define PCF2127_CTRL2_IRQ_MASK ( \ 90 PCF2127_BIT_CTRL2_AF | \ 91 PCF2127_BIT_CTRL2_WDTF | \ 92 PCF2127_BIT_CTRL2_TSF2) 93 94 #define PCF2127_MAX_TS_SUPPORTED 4 95 96 /* Control register 4 */ 97 #define PCF2131_REG_CTRL4 0x03 98 #define PCF2131_BIT_CTRL4_TSF4 BIT(4) 99 #define PCF2131_BIT_CTRL4_TSF3 BIT(5) 100 #define PCF2131_BIT_CTRL4_TSF2 BIT(6) 101 #define PCF2131_BIT_CTRL4_TSF1 BIT(7) 102 /* Control register 5 */ 103 #define PCF2131_REG_CTRL5 0x04 104 #define PCF2131_BIT_CTRL5_TSIE4 BIT(4) 105 #define PCF2131_BIT_CTRL5_TSIE3 BIT(5) 106 #define PCF2131_BIT_CTRL5_TSIE2 BIT(6) 107 #define PCF2131_BIT_CTRL5_TSIE1 BIT(7) 108 /* Software reset register */ 109 #define PCF2131_REG_SR_RESET 0x05 110 #define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5)) 111 #define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7)) 112 /* Time and date registers */ 113 #define PCF2131_REG_TIME_BASE 0x07 114 /* Alarm registers */ 115 #define PCF2131_REG_ALARM_BASE 0x0E 116 /* CLKOUT control register */ 117 #define PCF2131_REG_CLKOUT 0x13 118 /* Watchdog registers */ 119 #define PCF2131_REG_WD_CTL 0x35 120 #define PCF2131_REG_WD_VAL 0x36 121 /* Tamper timestamp1 registers */ 122 #define PCF2131_REG_TS1_BASE 0x14 123 /* Tamper timestamp2 registers */ 124 #define PCF2131_REG_TS2_BASE 0x1B 125 /* Tamper timestamp3 registers */ 126 #define PCF2131_REG_TS3_BASE 0x22 127 /* Tamper timestamp4 registers */ 128 #define PCF2131_REG_TS4_BASE 0x29 129 /* Interrupt mask registers */ 130 #define PCF2131_REG_INT_A_MASK1 0x31 131 #define PCF2131_REG_INT_A_MASK2 0x32 132 #define PCF2131_REG_INT_B_MASK1 0x33 133 #define PCF2131_REG_INT_B_MASK2 0x34 134 #define PCF2131_BIT_INT_BLIE BIT(0) 135 #define PCF2131_BIT_INT_BIE BIT(1) 136 #define PCF2131_BIT_INT_AIE BIT(2) 137 #define PCF2131_BIT_INT_WD_CD BIT(3) 138 #define PCF2131_BIT_INT_SI BIT(4) 139 #define PCF2131_BIT_INT_MI BIT(5) 140 #define PCF2131_CTRL2_IRQ_MASK ( \ 141 PCF2127_BIT_CTRL2_AF | \ 142 PCF2127_BIT_CTRL2_WDTF) 143 #define PCF2131_CTRL4_IRQ_MASK ( \ 144 PCF2131_BIT_CTRL4_TSF4 | \ 145 PCF2131_BIT_CTRL4_TSF3 | \ 146 PCF2131_BIT_CTRL4_TSF2 | \ 147 PCF2131_BIT_CTRL4_TSF1) 148 149 enum pcf21xx_type { 150 PCF2127, 151 PCF2129, 152 PCF2131, 153 PCF21XX_LAST_ID 154 }; 155 156 struct pcf21xx_ts_config { 157 u8 reg_base; /* Base register to read timestamp values. */ 158 159 /* 160 * If the TS input pin is driven to GND, an interrupt can be generated 161 * (supported by all variants). 162 */ 163 u8 gnd_detect_reg; /* Interrupt control register address. */ 164 u8 gnd_detect_bit; /* Interrupt bit. */ 165 166 /* 167 * If the TS input pin is driven to an intermediate level between GND 168 * and supply, an interrupt can be generated (optional feature depending 169 * on variant). 170 */ 171 u8 inter_detect_reg; /* Interrupt control register address. */ 172 u8 inter_detect_bit; /* Interrupt bit. */ 173 174 u8 ie_reg; /* Interrupt enable control register. */ 175 u8 ie_bit; /* Interrupt enable bit. */ 176 }; 177 178 struct pcf21xx_config { 179 int type; /* IC variant */ 180 int max_register; 181 unsigned int has_nvmem:1; 182 unsigned int has_bit_wd_ctl_cd0:1; 183 unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */ 184 u8 reg_time_base; /* Time/date base register. */ 185 u8 regs_alarm_base; /* Alarm function base registers. */ 186 u8 reg_wd_ctl; /* Watchdog control register. */ 187 u8 reg_wd_val; /* Watchdog value register. */ 188 u8 reg_clkout; /* Clkout register. */ 189 unsigned int ts_count; 190 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED]; 191 struct attribute_group attribute_group; 192 }; 193 194 struct pcf2127 { 195 struct rtc_device *rtc; 196 struct watchdog_device wdd; 197 struct regmap *regmap; 198 const struct pcf21xx_config *cfg; 199 bool irq_enabled; 200 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */ 201 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */ 202 }; 203 204 /* 205 * In the routines that deal directly with the pcf2127 hardware, we use 206 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 207 */ 208 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 209 { 210 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 211 unsigned char buf[7]; 212 int ret; 213 214 /* 215 * Avoid reading CTRL2 register as it causes WD_VAL register 216 * value to reset to 0 which means watchdog is stopped. 217 */ 218 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 219 buf, sizeof(buf)); 220 if (ret) { 221 dev_err(dev, "%s: read error\n", __func__); 222 return ret; 223 } 224 225 /* Clock integrity is not guaranteed when OSF flag is set. */ 226 if (buf[0] & PCF2127_BIT_SC_OSF) { 227 /* 228 * no need clear the flag here, 229 * it will be cleared once the new date is saved 230 */ 231 dev_warn(dev, 232 "oscillator stop detected, date/time is not reliable\n"); 233 return -EINVAL; 234 } 235 236 dev_dbg(dev, 237 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 238 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 239 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 240 241 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 242 tm->tm_min = bcd2bin(buf[1] & 0x7F); 243 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 244 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 245 tm->tm_wday = buf[4] & 0x07; 246 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 247 tm->tm_year = bcd2bin(buf[6]); 248 tm->tm_year += 100; 249 250 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 251 "mday=%d, mon=%d, year=%d, wday=%d\n", 252 __func__, 253 tm->tm_sec, tm->tm_min, tm->tm_hour, 254 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 255 256 return 0; 257 } 258 259 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 260 { 261 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 262 unsigned char buf[7]; 263 int i = 0, err; 264 265 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 266 "mday=%d, mon=%d, year=%d, wday=%d\n", 267 __func__, 268 tm->tm_sec, tm->tm_min, tm->tm_hour, 269 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 270 271 /* hours, minutes and seconds */ 272 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 273 buf[i++] = bin2bcd(tm->tm_min); 274 buf[i++] = bin2bcd(tm->tm_hour); 275 buf[i++] = bin2bcd(tm->tm_mday); 276 buf[i++] = tm->tm_wday & 0x07; 277 278 /* month, 1 - 12 */ 279 buf[i++] = bin2bcd(tm->tm_mon + 1); 280 281 /* year */ 282 buf[i++] = bin2bcd(tm->tm_year - 100); 283 284 /* Write access to time registers: 285 * PCF2127/29: no special action required. 286 * PCF2131: requires setting the STOP and CPR bits. STOP bit needs to 287 * be cleared after time registers are updated. 288 */ 289 if (pcf2127->cfg->type == PCF2131) { 290 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 291 PCF2127_BIT_CTRL1_STOP, 292 PCF2127_BIT_CTRL1_STOP); 293 if (err) { 294 dev_dbg(dev, "setting STOP bit failed\n"); 295 return err; 296 } 297 298 err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET, 299 PCF2131_SR_RESET_CPR_CMD); 300 if (err) { 301 dev_dbg(dev, "sending CPR cmd failed\n"); 302 return err; 303 } 304 } 305 306 /* write time register's data */ 307 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 308 if (err) { 309 dev_dbg(dev, "%s: err=%d", __func__, err); 310 return err; 311 } 312 313 if (pcf2127->cfg->type == PCF2131) { 314 /* Clear STOP bit (PCF2131 only) after write is completed. */ 315 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 316 PCF2127_BIT_CTRL1_STOP, 0); 317 if (err) { 318 dev_dbg(dev, "clearing STOP bit failed\n"); 319 return err; 320 } 321 } 322 323 return 0; 324 } 325 326 static int pcf2127_rtc_ioctl(struct device *dev, 327 unsigned int cmd, unsigned long arg) 328 { 329 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 330 int val, touser = 0; 331 int ret; 332 333 switch (cmd) { 334 case RTC_VL_READ: 335 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 336 if (ret) 337 return ret; 338 339 if (val & PCF2127_BIT_CTRL3_BLF) 340 touser |= RTC_VL_BACKUP_LOW; 341 342 if (val & PCF2127_BIT_CTRL3_BF) 343 touser |= RTC_VL_BACKUP_SWITCH; 344 345 return put_user(touser, (unsigned int __user *)arg); 346 347 case RTC_VL_CLR: 348 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 349 PCF2127_BIT_CTRL3_BF, 0); 350 351 default: 352 return -ENOIOCTLCMD; 353 } 354 } 355 356 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 357 void *val, size_t bytes) 358 { 359 struct pcf2127 *pcf2127 = priv; 360 int ret; 361 unsigned char offsetbuf[] = { offset >> 8, offset }; 362 363 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 364 offsetbuf, 2); 365 if (ret) 366 return ret; 367 368 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 369 val, bytes); 370 } 371 372 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 373 void *val, size_t bytes) 374 { 375 struct pcf2127 *pcf2127 = priv; 376 int ret; 377 unsigned char offsetbuf[] = { offset >> 8, offset }; 378 379 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 380 offsetbuf, 2); 381 if (ret) 382 return ret; 383 384 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 385 val, bytes); 386 } 387 388 /* watchdog driver */ 389 390 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 391 { 392 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 393 394 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout); 395 } 396 397 /* 398 * Restart watchdog timer if feature is active. 399 * 400 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 401 * since register also contain control/status flags for other features. 402 * Always call this function after reading CTRL2 register. 403 */ 404 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 405 { 406 int ret = 0; 407 408 if (watchdog_active(wdd)) { 409 ret = pcf2127_wdt_ping(wdd); 410 if (ret) 411 dev_err(wdd->parent, 412 "%s: watchdog restart failed, ret=%d\n", 413 __func__, ret); 414 } 415 416 return ret; 417 } 418 419 static int pcf2127_wdt_start(struct watchdog_device *wdd) 420 { 421 return pcf2127_wdt_ping(wdd); 422 } 423 424 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 425 { 426 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 427 428 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 429 PCF2127_WD_VAL_STOP); 430 } 431 432 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 433 unsigned int new_timeout) 434 { 435 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 436 new_timeout, wdd->timeout); 437 438 wdd->timeout = new_timeout; 439 440 return pcf2127_wdt_active_ping(wdd); 441 } 442 443 static const struct watchdog_info pcf2127_wdt_info = { 444 .identity = "NXP PCF2127/PCF2129 Watchdog", 445 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 446 }; 447 448 static const struct watchdog_ops pcf2127_watchdog_ops = { 449 .owner = THIS_MODULE, 450 .start = pcf2127_wdt_start, 451 .stop = pcf2127_wdt_stop, 452 .ping = pcf2127_wdt_ping, 453 .set_timeout = pcf2127_wdt_set_timeout, 454 }; 455 456 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 457 { 458 u32 wdd_timeout; 459 int ret; 460 461 if (!IS_ENABLED(CONFIG_WATCHDOG) || 462 !device_property_read_bool(dev, "reset-source")) 463 return 0; 464 465 pcf2127->wdd.parent = dev; 466 pcf2127->wdd.info = &pcf2127_wdt_info; 467 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 468 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 469 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 470 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 471 pcf2127->wdd.min_hw_heartbeat_ms = 500; 472 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 473 474 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 475 476 /* Test if watchdog timer is started by bootloader */ 477 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 478 if (ret) 479 return ret; 480 481 if (wdd_timeout) 482 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 483 484 return devm_watchdog_register_device(dev, &pcf2127->wdd); 485 } 486 487 /* Alarm */ 488 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 489 { 490 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 491 u8 buf[5]; 492 unsigned int ctrl2; 493 int ret; 494 495 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 496 if (ret) 497 return ret; 498 499 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 500 if (ret) 501 return ret; 502 503 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 504 buf, sizeof(buf)); 505 if (ret) 506 return ret; 507 508 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 509 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 510 511 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 512 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 513 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 514 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 515 516 return 0; 517 } 518 519 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 520 { 521 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 522 int ret; 523 524 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 525 PCF2127_BIT_CTRL2_AIE, 526 enable ? PCF2127_BIT_CTRL2_AIE : 0); 527 if (ret) 528 return ret; 529 530 return pcf2127_wdt_active_ping(&pcf2127->wdd); 531 } 532 533 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 534 { 535 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 536 uint8_t buf[5]; 537 int ret; 538 539 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 540 PCF2127_BIT_CTRL2_AF, 0); 541 if (ret) 542 return ret; 543 544 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 545 if (ret) 546 return ret; 547 548 buf[0] = bin2bcd(alrm->time.tm_sec); 549 buf[1] = bin2bcd(alrm->time.tm_min); 550 buf[2] = bin2bcd(alrm->time.tm_hour); 551 buf[3] = bin2bcd(alrm->time.tm_mday); 552 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 553 554 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 555 buf, sizeof(buf)); 556 if (ret) 557 return ret; 558 559 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 560 } 561 562 /* 563 * This function reads one timestamp function data, caller is responsible for 564 * calling pcf2127_wdt_active_ping() 565 */ 566 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts, 567 int ts_id) 568 { 569 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 570 struct rtc_time tm; 571 int ret; 572 unsigned char data[7]; 573 574 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base, 575 data, sizeof(data)); 576 if (ret) { 577 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 578 return ret; 579 } 580 581 dev_dbg(dev, 582 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 583 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 584 585 tm.tm_sec = bcd2bin(data[1] & 0x7F); 586 tm.tm_min = bcd2bin(data[2] & 0x7F); 587 tm.tm_hour = bcd2bin(data[3] & 0x3F); 588 tm.tm_mday = bcd2bin(data[4] & 0x3F); 589 /* TS_MO register (month) value range: 1-12 */ 590 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 591 tm.tm_year = bcd2bin(data[6]); 592 if (tm.tm_year < 70) 593 tm.tm_year += 100; /* assume we are in 1970...2069 */ 594 595 ret = rtc_valid_tm(&tm); 596 if (ret) { 597 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 598 return ret; 599 } 600 601 *ts = rtc_tm_to_time64(&tm); 602 return 0; 603 }; 604 605 static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id) 606 { 607 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 608 int ret; 609 610 if (ts_id >= pcf2127->cfg->ts_count) 611 return; 612 613 /* Let userspace read the first timestamp */ 614 if (pcf2127->ts_valid[ts_id]) 615 return; 616 617 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id); 618 if (!ret) 619 pcf2127->ts_valid[ts_id] = true; 620 } 621 622 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 623 { 624 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 625 unsigned int ctrl2; 626 int ret = 0; 627 628 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 629 if (ret) 630 return IRQ_NONE; 631 632 if (pcf2127->cfg->ts_count == 1) { 633 /* PCF2127/29 */ 634 unsigned int ctrl1; 635 636 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 637 if (ret) 638 return IRQ_NONE; 639 640 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 641 return IRQ_NONE; 642 643 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 644 pcf2127_rtc_ts_snapshot(dev, 0); 645 646 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 647 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 648 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 649 650 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 651 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 652 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 653 } else { 654 /* PCF2131. */ 655 unsigned int ctrl4; 656 657 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4); 658 if (ret) 659 return IRQ_NONE; 660 661 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK)) 662 return IRQ_NONE; 663 664 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) { 665 int i; 666 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */ 667 668 for (i = 0; i < pcf2127->cfg->ts_count; i++) { 669 if (ctrl4 & tsf_bit) 670 pcf2127_rtc_ts_snapshot(dev, i); 671 672 tsf_bit = tsf_bit >> 1; 673 } 674 675 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4, 676 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK); 677 } 678 679 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK) 680 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 681 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK); 682 } 683 684 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 685 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 686 687 pcf2127_wdt_active_ping(&pcf2127->wdd); 688 689 return IRQ_HANDLED; 690 } 691 692 static const struct rtc_class_ops pcf2127_rtc_ops = { 693 .ioctl = pcf2127_rtc_ioctl, 694 .read_time = pcf2127_rtc_read_time, 695 .set_time = pcf2127_rtc_set_time, 696 .read_alarm = pcf2127_rtc_read_alarm, 697 .set_alarm = pcf2127_rtc_set_alarm, 698 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 699 }; 700 701 /* sysfs interface */ 702 703 static ssize_t timestamp_store(struct device *dev, 704 struct device_attribute *attr, 705 const char *buf, size_t count, int ts_id) 706 { 707 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 708 int ret; 709 710 if (ts_id >= pcf2127->cfg->ts_count) 711 return 0; 712 713 if (pcf2127->irq_enabled) { 714 pcf2127->ts_valid[ts_id] = false; 715 } else { 716 /* Always clear GND interrupt bit. */ 717 ret = regmap_update_bits(pcf2127->regmap, 718 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 719 pcf2127->cfg->ts[ts_id].gnd_detect_bit, 720 0); 721 722 if (ret) { 723 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret); 724 return ret; 725 } 726 727 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 728 /* Clear intermediate level interrupt bit if supported. */ 729 ret = regmap_update_bits(pcf2127->regmap, 730 pcf2127->cfg->ts[ts_id].inter_detect_reg, 731 pcf2127->cfg->ts[ts_id].inter_detect_bit, 732 0); 733 if (ret) { 734 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n", 735 __func__, ret); 736 return ret; 737 } 738 } 739 740 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 741 if (ret) 742 return ret; 743 } 744 745 return count; 746 } 747 748 static ssize_t timestamp0_store(struct device *dev, 749 struct device_attribute *attr, 750 const char *buf, size_t count) 751 { 752 return timestamp_store(dev, attr, buf, count, 0); 753 }; 754 755 static ssize_t timestamp1_store(struct device *dev, 756 struct device_attribute *attr, 757 const char *buf, size_t count) 758 { 759 return timestamp_store(dev, attr, buf, count, 1); 760 }; 761 762 static ssize_t timestamp2_store(struct device *dev, 763 struct device_attribute *attr, 764 const char *buf, size_t count) 765 { 766 return timestamp_store(dev, attr, buf, count, 2); 767 }; 768 769 static ssize_t timestamp3_store(struct device *dev, 770 struct device_attribute *attr, 771 const char *buf, size_t count) 772 { 773 return timestamp_store(dev, attr, buf, count, 3); 774 }; 775 776 static ssize_t timestamp_show(struct device *dev, 777 struct device_attribute *attr, char *buf, 778 int ts_id) 779 { 780 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 781 int ret; 782 time64_t ts; 783 784 if (ts_id >= pcf2127->cfg->ts_count) 785 return 0; 786 787 if (pcf2127->irq_enabled) { 788 if (!pcf2127->ts_valid[ts_id]) 789 return 0; 790 ts = pcf2127->ts[ts_id]; 791 } else { 792 u8 valid_low = 0; 793 u8 valid_inter = 0; 794 unsigned int ctrl; 795 796 /* Check if TS input pin is driven to GND, supported by all 797 * variants. 798 */ 799 ret = regmap_read(pcf2127->regmap, 800 pcf2127->cfg->ts[ts_id].gnd_detect_reg, 801 &ctrl); 802 if (ret) 803 return 0; 804 805 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit; 806 807 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 808 /* Check if TS input pin is driven to intermediate level 809 * between GND and supply, if supported by variant. 810 */ 811 ret = regmap_read(pcf2127->regmap, 812 pcf2127->cfg->ts[ts_id].inter_detect_reg, 813 &ctrl); 814 if (ret) 815 return 0; 816 817 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit; 818 } 819 820 if (!valid_low && !valid_inter) 821 return 0; 822 823 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id); 824 if (ret) 825 return 0; 826 827 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 828 if (ret) 829 return ret; 830 } 831 return sprintf(buf, "%llu\n", (unsigned long long)ts); 832 } 833 834 static ssize_t timestamp0_show(struct device *dev, 835 struct device_attribute *attr, char *buf) 836 { 837 return timestamp_show(dev, attr, buf, 0); 838 }; 839 840 static ssize_t timestamp1_show(struct device *dev, 841 struct device_attribute *attr, char *buf) 842 { 843 return timestamp_show(dev, attr, buf, 1); 844 }; 845 846 static ssize_t timestamp2_show(struct device *dev, 847 struct device_attribute *attr, char *buf) 848 { 849 return timestamp_show(dev, attr, buf, 2); 850 }; 851 852 static ssize_t timestamp3_show(struct device *dev, 853 struct device_attribute *attr, char *buf) 854 { 855 return timestamp_show(dev, attr, buf, 3); 856 }; 857 858 static DEVICE_ATTR_RW(timestamp0); 859 static DEVICE_ATTR_RW(timestamp1); 860 static DEVICE_ATTR_RW(timestamp2); 861 static DEVICE_ATTR_RW(timestamp3); 862 863 static struct attribute *pcf2127_attrs[] = { 864 &dev_attr_timestamp0.attr, 865 NULL 866 }; 867 868 static struct attribute *pcf2131_attrs[] = { 869 &dev_attr_timestamp0.attr, 870 &dev_attr_timestamp1.attr, 871 &dev_attr_timestamp2.attr, 872 &dev_attr_timestamp3.attr, 873 NULL 874 }; 875 876 static struct pcf21xx_config pcf21xx_cfg[] = { 877 [PCF2127] = { 878 .type = PCF2127, 879 .max_register = 0x1d, 880 .has_nvmem = 1, 881 .has_bit_wd_ctl_cd0 = 1, 882 .has_int_a_b = 0, 883 .reg_time_base = PCF2127_REG_TIME_BASE, 884 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 885 .reg_wd_ctl = PCF2127_REG_WD_CTL, 886 .reg_wd_val = PCF2127_REG_WD_VAL, 887 .reg_clkout = PCF2127_REG_CLKOUT, 888 .ts_count = 1, 889 .ts[0] = { 890 .reg_base = PCF2127_REG_TS1_BASE, 891 .gnd_detect_reg = PCF2127_REG_CTRL1, 892 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 893 .inter_detect_reg = PCF2127_REG_CTRL2, 894 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 895 .ie_reg = PCF2127_REG_CTRL2, 896 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 897 }, 898 .attribute_group = { 899 .attrs = pcf2127_attrs, 900 }, 901 }, 902 [PCF2129] = { 903 .type = PCF2129, 904 .max_register = 0x19, 905 .has_nvmem = 0, 906 .has_bit_wd_ctl_cd0 = 0, 907 .has_int_a_b = 0, 908 .reg_time_base = PCF2127_REG_TIME_BASE, 909 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 910 .reg_wd_ctl = PCF2127_REG_WD_CTL, 911 .reg_wd_val = PCF2127_REG_WD_VAL, 912 .reg_clkout = PCF2127_REG_CLKOUT, 913 .ts_count = 1, 914 .ts[0] = { 915 .reg_base = PCF2127_REG_TS1_BASE, 916 .gnd_detect_reg = PCF2127_REG_CTRL1, 917 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 918 .inter_detect_reg = PCF2127_REG_CTRL2, 919 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 920 .ie_reg = PCF2127_REG_CTRL2, 921 .ie_bit = PCF2127_BIT_CTRL2_TSIE, 922 }, 923 .attribute_group = { 924 .attrs = pcf2127_attrs, 925 }, 926 }, 927 [PCF2131] = { 928 .type = PCF2131, 929 .max_register = 0x36, 930 .has_nvmem = 0, 931 .has_bit_wd_ctl_cd0 = 0, 932 .has_int_a_b = 1, 933 .reg_time_base = PCF2131_REG_TIME_BASE, 934 .regs_alarm_base = PCF2131_REG_ALARM_BASE, 935 .reg_wd_ctl = PCF2131_REG_WD_CTL, 936 .reg_wd_val = PCF2131_REG_WD_VAL, 937 .reg_clkout = PCF2131_REG_CLKOUT, 938 .ts_count = 4, 939 .ts[0] = { 940 .reg_base = PCF2131_REG_TS1_BASE, 941 .gnd_detect_reg = PCF2131_REG_CTRL4, 942 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1, 943 .inter_detect_bit = 0, 944 .ie_reg = PCF2131_REG_CTRL5, 945 .ie_bit = PCF2131_BIT_CTRL5_TSIE1, 946 }, 947 .ts[1] = { 948 .reg_base = PCF2131_REG_TS2_BASE, 949 .gnd_detect_reg = PCF2131_REG_CTRL4, 950 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2, 951 .inter_detect_bit = 0, 952 .ie_reg = PCF2131_REG_CTRL5, 953 .ie_bit = PCF2131_BIT_CTRL5_TSIE2, 954 }, 955 .ts[2] = { 956 .reg_base = PCF2131_REG_TS3_BASE, 957 .gnd_detect_reg = PCF2131_REG_CTRL4, 958 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3, 959 .inter_detect_bit = 0, 960 .ie_reg = PCF2131_REG_CTRL5, 961 .ie_bit = PCF2131_BIT_CTRL5_TSIE3, 962 }, 963 .ts[3] = { 964 .reg_base = PCF2131_REG_TS4_BASE, 965 .gnd_detect_reg = PCF2131_REG_CTRL4, 966 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4, 967 .inter_detect_bit = 0, 968 .ie_reg = PCF2131_REG_CTRL5, 969 .ie_bit = PCF2131_BIT_CTRL5_TSIE4, 970 }, 971 .attribute_group = { 972 .attrs = pcf2131_attrs, 973 }, 974 }, 975 }; 976 977 /* 978 * Enable timestamp function and corresponding interrupt(s). 979 */ 980 static int pcf2127_enable_ts(struct device *dev, int ts_id) 981 { 982 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 983 int ret; 984 985 if (ts_id >= pcf2127->cfg->ts_count) { 986 dev_err(dev, "%s: invalid tamper detection ID (%d)\n", 987 __func__, ts_id); 988 return -EINVAL; 989 } 990 991 /* Enable timestamp function. */ 992 ret = regmap_update_bits(pcf2127->regmap, 993 pcf2127->cfg->ts[ts_id].reg_base, 994 PCF2127_BIT_TS_CTRL_TSOFF | 995 PCF2127_BIT_TS_CTRL_TSM, 996 PCF2127_BIT_TS_CTRL_TSM); 997 if (ret) { 998 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n", 999 __func__, ts_id); 1000 return ret; 1001 } 1002 1003 /* TS input pin driven to GND detection is supported by all variants. 1004 * Make sure that interrupt bit is defined. 1005 */ 1006 if (pcf2127->cfg->ts[ts_id].gnd_detect_bit == 0) { 1007 dev_err(dev, "%s: tamper detection to GND configuration invalid\n", 1008 __func__); 1009 return ret; 1010 } 1011 1012 /* 1013 * Enable interrupt generation when TSF timestamp flag is set. 1014 * Interrupt signals are open-drain outputs and can be left floating if 1015 * unused. 1016 */ 1017 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg, 1018 pcf2127->cfg->ts[ts_id].ie_bit, 1019 pcf2127->cfg->ts[ts_id].ie_bit); 1020 if (ret) { 1021 dev_err(dev, "%s: tamper detection TSIE%d config failed\n", 1022 __func__, ts_id); 1023 return ret; 1024 } 1025 1026 return ret; 1027 } 1028 1029 /* Route all interrupt sources to INT A pin. */ 1030 static int pcf2127_configure_interrupt_pins(struct device *dev) 1031 { 1032 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 1033 int ret; 1034 1035 /* Mask bits need to be cleared to enable corresponding 1036 * interrupt source. 1037 */ 1038 ret = regmap_write(pcf2127->regmap, 1039 PCF2131_REG_INT_A_MASK1, 0); 1040 if (ret) 1041 return ret; 1042 1043 ret = regmap_write(pcf2127->regmap, 1044 PCF2131_REG_INT_A_MASK2, 0); 1045 if (ret) 1046 return ret; 1047 1048 return ret; 1049 } 1050 1051 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 1052 int alarm_irq, const char *name, const struct pcf21xx_config *config) 1053 { 1054 struct pcf2127 *pcf2127; 1055 int ret = 0; 1056 unsigned int val; 1057 1058 dev_dbg(dev, "%s\n", __func__); 1059 1060 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 1061 if (!pcf2127) 1062 return -ENOMEM; 1063 1064 pcf2127->regmap = regmap; 1065 pcf2127->cfg = config; 1066 1067 dev_set_drvdata(dev, pcf2127); 1068 1069 pcf2127->rtc = devm_rtc_allocate_device(dev); 1070 if (IS_ERR(pcf2127->rtc)) 1071 return PTR_ERR(pcf2127->rtc); 1072 1073 pcf2127->rtc->ops = &pcf2127_rtc_ops; 1074 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 1075 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 1076 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 1077 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 1078 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 1079 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1080 1081 if (alarm_irq > 0) { 1082 unsigned long flags; 1083 1084 /* 1085 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 1086 * obtained from device tree. 1087 */ 1088 if (dev_fwnode(dev)) 1089 flags = 0; 1090 else 1091 flags = IRQF_TRIGGER_LOW; 1092 1093 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 1094 pcf2127_rtc_irq, 1095 flags | IRQF_ONESHOT, 1096 dev_name(dev), dev); 1097 if (ret) { 1098 dev_err(dev, "failed to request alarm irq\n"); 1099 return ret; 1100 } 1101 pcf2127->irq_enabled = true; 1102 } 1103 1104 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 1105 device_init_wakeup(dev, true); 1106 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 1107 } 1108 1109 if (pcf2127->cfg->has_int_a_b) { 1110 /* Configure int A/B pins, independently of alarm_irq. */ 1111 ret = pcf2127_configure_interrupt_pins(dev); 1112 if (ret) { 1113 dev_err(dev, "failed to configure interrupt pins\n"); 1114 return ret; 1115 } 1116 } 1117 1118 if (pcf2127->cfg->has_nvmem) { 1119 struct nvmem_config nvmem_cfg = { 1120 .priv = pcf2127, 1121 .reg_read = pcf2127_nvmem_read, 1122 .reg_write = pcf2127_nvmem_write, 1123 .size = 512, 1124 }; 1125 1126 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 1127 } 1128 1129 /* 1130 * The "Power-On Reset Override" facility prevents the RTC to do a reset 1131 * after power on. For normal operation the PORO must be disabled. 1132 */ 1133 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 1134 PCF2127_BIT_CTRL1_POR_OVRD); 1135 1136 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); 1137 if (ret < 0) 1138 return ret; 1139 1140 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 1141 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, 1142 PCF2127_BIT_CLKOUT_OTPR); 1143 if (ret < 0) 1144 return ret; 1145 1146 msleep(100); 1147 } 1148 1149 /* 1150 * Watchdog timer enabled and reset pin /RST activated when timed out. 1151 * Select 1Hz clock source for watchdog timer. 1152 * Note: Countdown timer disabled and not available. 1153 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD 1154 * of register watchdg_tim_ctl. The bit[6] is labeled 1155 * as T. Bits labeled as T must always be written with 1156 * logic 0. 1157 */ 1158 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 1159 PCF2127_BIT_WD_CTL_CD1 | 1160 PCF2127_BIT_WD_CTL_CD0 | 1161 PCF2127_BIT_WD_CTL_TF1 | 1162 PCF2127_BIT_WD_CTL_TF0, 1163 PCF2127_BIT_WD_CTL_CD1 | 1164 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 1165 PCF2127_BIT_WD_CTL_TF1); 1166 if (ret) { 1167 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 1168 return ret; 1169 } 1170 1171 pcf2127_watchdog_init(dev, pcf2127); 1172 1173 /* 1174 * Disable battery low/switch-over timestamp and interrupts. 1175 * Clear battery interrupt flags which can block new trigger events. 1176 * Note: This is the default chip behaviour but added to ensure 1177 * correct tamper timestamp and interrupt function. 1178 */ 1179 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 1180 PCF2127_BIT_CTRL3_BTSE | 1181 PCF2127_BIT_CTRL3_BIE | 1182 PCF2127_BIT_CTRL3_BLIE, 0); 1183 if (ret) { 1184 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 1185 __func__); 1186 return ret; 1187 } 1188 1189 /* 1190 * Enable timestamp functions 1 to 4. 1191 */ 1192 for (int i = 0; i < pcf2127->cfg->ts_count; i++) { 1193 ret = pcf2127_enable_ts(dev, i); 1194 if (ret) 1195 return ret; 1196 } 1197 1198 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group); 1199 if (ret) { 1200 dev_err(dev, "%s: tamper sysfs registering failed\n", 1201 __func__); 1202 return ret; 1203 } 1204 1205 return devm_rtc_register_device(pcf2127->rtc); 1206 } 1207 1208 #ifdef CONFIG_OF 1209 static const struct of_device_id pcf2127_of_match[] = { 1210 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 1211 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 1212 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 1213 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] }, 1214 {} 1215 }; 1216 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 1217 #endif 1218 1219 #if IS_ENABLED(CONFIG_I2C) 1220 1221 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 1222 { 1223 struct device *dev = context; 1224 struct i2c_client *client = to_i2c_client(dev); 1225 int ret; 1226 1227 ret = i2c_master_send(client, data, count); 1228 if (ret != count) 1229 return ret < 0 ? ret : -EIO; 1230 1231 return 0; 1232 } 1233 1234 static int pcf2127_i2c_gather_write(void *context, 1235 const void *reg, size_t reg_size, 1236 const void *val, size_t val_size) 1237 { 1238 struct device *dev = context; 1239 struct i2c_client *client = to_i2c_client(dev); 1240 int ret; 1241 void *buf; 1242 1243 if (WARN_ON(reg_size != 1)) 1244 return -EINVAL; 1245 1246 buf = kmalloc(val_size + 1, GFP_KERNEL); 1247 if (!buf) 1248 return -ENOMEM; 1249 1250 memcpy(buf, reg, 1); 1251 memcpy(buf + 1, val, val_size); 1252 1253 ret = i2c_master_send(client, buf, val_size + 1); 1254 1255 kfree(buf); 1256 1257 if (ret != val_size + 1) 1258 return ret < 0 ? ret : -EIO; 1259 1260 return 0; 1261 } 1262 1263 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 1264 void *val, size_t val_size) 1265 { 1266 struct device *dev = context; 1267 struct i2c_client *client = to_i2c_client(dev); 1268 int ret; 1269 1270 if (WARN_ON(reg_size != 1)) 1271 return -EINVAL; 1272 1273 ret = i2c_master_send(client, reg, 1); 1274 if (ret != 1) 1275 return ret < 0 ? ret : -EIO; 1276 1277 ret = i2c_master_recv(client, val, val_size); 1278 if (ret != val_size) 1279 return ret < 0 ? ret : -EIO; 1280 1281 return 0; 1282 } 1283 1284 /* 1285 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 1286 * is that the STOP condition is required between set register address and 1287 * read register data when reading from registers. 1288 */ 1289 static const struct regmap_bus pcf2127_i2c_regmap = { 1290 .write = pcf2127_i2c_write, 1291 .gather_write = pcf2127_i2c_gather_write, 1292 .read = pcf2127_i2c_read, 1293 }; 1294 1295 static struct i2c_driver pcf2127_i2c_driver; 1296 1297 static const struct i2c_device_id pcf2127_i2c_id[] = { 1298 { "pcf2127", PCF2127 }, 1299 { "pcf2129", PCF2129 }, 1300 { "pca2129", PCF2129 }, 1301 { "pcf2131", PCF2131 }, 1302 { } 1303 }; 1304 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 1305 1306 static int pcf2127_i2c_probe(struct i2c_client *client) 1307 { 1308 struct regmap *regmap; 1309 static struct regmap_config config = { 1310 .reg_bits = 8, 1311 .val_bits = 8, 1312 }; 1313 const struct pcf21xx_config *variant; 1314 1315 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 1316 return -ENODEV; 1317 1318 if (client->dev.of_node) { 1319 variant = of_device_get_match_data(&client->dev); 1320 if (!variant) 1321 return -ENODEV; 1322 } else { 1323 enum pcf21xx_type type = 1324 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 1325 1326 if (type >= PCF21XX_LAST_ID) 1327 return -ENODEV; 1328 variant = &pcf21xx_cfg[type]; 1329 } 1330 1331 config.max_register = variant->max_register, 1332 1333 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 1334 &client->dev, &config); 1335 if (IS_ERR(regmap)) { 1336 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 1337 __func__, PTR_ERR(regmap)); 1338 return PTR_ERR(regmap); 1339 } 1340 1341 return pcf2127_probe(&client->dev, regmap, client->irq, 1342 pcf2127_i2c_driver.driver.name, variant); 1343 } 1344 1345 static struct i2c_driver pcf2127_i2c_driver = { 1346 .driver = { 1347 .name = "rtc-pcf2127-i2c", 1348 .of_match_table = of_match_ptr(pcf2127_of_match), 1349 }, 1350 .probe = pcf2127_i2c_probe, 1351 .id_table = pcf2127_i2c_id, 1352 }; 1353 1354 static int pcf2127_i2c_register_driver(void) 1355 { 1356 return i2c_add_driver(&pcf2127_i2c_driver); 1357 } 1358 1359 static void pcf2127_i2c_unregister_driver(void) 1360 { 1361 i2c_del_driver(&pcf2127_i2c_driver); 1362 } 1363 1364 #else 1365 1366 static int pcf2127_i2c_register_driver(void) 1367 { 1368 return 0; 1369 } 1370 1371 static void pcf2127_i2c_unregister_driver(void) 1372 { 1373 } 1374 1375 #endif 1376 1377 #if IS_ENABLED(CONFIG_SPI_MASTER) 1378 1379 static struct spi_driver pcf2127_spi_driver; 1380 static const struct spi_device_id pcf2127_spi_id[]; 1381 1382 static int pcf2127_spi_probe(struct spi_device *spi) 1383 { 1384 static struct regmap_config config = { 1385 .reg_bits = 8, 1386 .val_bits = 8, 1387 .read_flag_mask = 0xa0, 1388 .write_flag_mask = 0x20, 1389 }; 1390 struct regmap *regmap; 1391 const struct pcf21xx_config *variant; 1392 1393 if (spi->dev.of_node) { 1394 variant = of_device_get_match_data(&spi->dev); 1395 if (!variant) 1396 return -ENODEV; 1397 } else { 1398 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1399 1400 if (type >= PCF21XX_LAST_ID) 1401 return -ENODEV; 1402 variant = &pcf21xx_cfg[type]; 1403 } 1404 1405 config.max_register = variant->max_register, 1406 1407 regmap = devm_regmap_init_spi(spi, &config); 1408 if (IS_ERR(regmap)) { 1409 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1410 __func__, PTR_ERR(regmap)); 1411 return PTR_ERR(regmap); 1412 } 1413 1414 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1415 pcf2127_spi_driver.driver.name, 1416 variant); 1417 } 1418 1419 static const struct spi_device_id pcf2127_spi_id[] = { 1420 { "pcf2127", PCF2127 }, 1421 { "pcf2129", PCF2129 }, 1422 { "pca2129", PCF2129 }, 1423 { "pcf2131", PCF2131 }, 1424 { } 1425 }; 1426 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1427 1428 static struct spi_driver pcf2127_spi_driver = { 1429 .driver = { 1430 .name = "rtc-pcf2127-spi", 1431 .of_match_table = of_match_ptr(pcf2127_of_match), 1432 }, 1433 .probe = pcf2127_spi_probe, 1434 .id_table = pcf2127_spi_id, 1435 }; 1436 1437 static int pcf2127_spi_register_driver(void) 1438 { 1439 return spi_register_driver(&pcf2127_spi_driver); 1440 } 1441 1442 static void pcf2127_spi_unregister_driver(void) 1443 { 1444 spi_unregister_driver(&pcf2127_spi_driver); 1445 } 1446 1447 #else 1448 1449 static int pcf2127_spi_register_driver(void) 1450 { 1451 return 0; 1452 } 1453 1454 static void pcf2127_spi_unregister_driver(void) 1455 { 1456 } 1457 1458 #endif 1459 1460 static int __init pcf2127_init(void) 1461 { 1462 int ret; 1463 1464 ret = pcf2127_i2c_register_driver(); 1465 if (ret) { 1466 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1467 return ret; 1468 } 1469 1470 ret = pcf2127_spi_register_driver(); 1471 if (ret) { 1472 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1473 pcf2127_i2c_unregister_driver(); 1474 } 1475 1476 return ret; 1477 } 1478 module_init(pcf2127_init) 1479 1480 static void __exit pcf2127_exit(void) 1481 { 1482 pcf2127_spi_unregister_driver(); 1483 pcf2127_i2c_unregister_driver(); 1484 } 1485 module_exit(pcf2127_exit) 1486 1487 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1488 MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver"); 1489 MODULE_LICENSE("GPL v2"); 1490