1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <[email protected]> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <[email protected]> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/regmap.h> 25 #include <linux/watchdog.h> 26 27 /* Control register 1 */ 28 #define PCF2127_REG_CTRL1 0x00 29 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 30 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 31 /* Control register 2 */ 32 #define PCF2127_REG_CTRL2 0x01 33 #define PCF2127_BIT_CTRL2_AIE BIT(1) 34 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 35 #define PCF2127_BIT_CTRL2_AF BIT(4) 36 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 37 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 38 /* Control register 3 */ 39 #define PCF2127_REG_CTRL3 0x02 40 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 41 #define PCF2127_BIT_CTRL3_BIE BIT(1) 42 #define PCF2127_BIT_CTRL3_BLF BIT(2) 43 #define PCF2127_BIT_CTRL3_BF BIT(3) 44 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 45 /* Time and date registers */ 46 #define PCF2127_REG_SC 0x03 47 #define PCF2127_BIT_SC_OSF BIT(7) 48 /* Alarm registers */ 49 #define PCF2127_REG_ALARM_SC 0x0A 50 #define PCF2127_REG_ALARM_MN 0x0B 51 #define PCF2127_REG_ALARM_HR 0x0C 52 #define PCF2127_REG_ALARM_DM 0x0D 53 #define PCF2127_REG_ALARM_DW 0x0E 54 #define PCF2127_BIT_ALARM_AE BIT(7) 55 /* CLKOUT control register */ 56 #define PCF2127_REG_CLKOUT 0x0f 57 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 58 /* Watchdog registers */ 59 #define PCF2127_REG_WD_CTL 0x10 60 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 61 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 62 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 63 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 64 #define PCF2127_REG_WD_VAL 0x11 65 /* Tamper timestamp registers */ 66 #define PCF2127_REG_TS_CTRL 0x12 67 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 68 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 69 /* 70 * RAM registers 71 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 72 * battery backed and can survive a power outage. 73 * PCF2129 doesn't have this feature. 74 */ 75 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 76 #define PCF2127_REG_RAM_WRT_CMD 0x1C 77 #define PCF2127_REG_RAM_RD_CMD 0x1D 78 79 /* Watchdog timer value constants */ 80 #define PCF2127_WD_VAL_STOP 0 81 #define PCF2127_WD_VAL_MIN 2 82 #define PCF2127_WD_VAL_MAX 255 83 #define PCF2127_WD_VAL_DEFAULT 60 84 85 /* Mask for currently enabled interrupts */ 86 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 87 #define PCF2127_CTRL2_IRQ_MASK ( \ 88 PCF2127_BIT_CTRL2_AF | \ 89 PCF2127_BIT_CTRL2_WDTF | \ 90 PCF2127_BIT_CTRL2_TSF2) 91 92 struct pcf2127 { 93 struct rtc_device *rtc; 94 struct watchdog_device wdd; 95 struct regmap *regmap; 96 time64_t ts; 97 bool ts_valid; 98 bool irq_enabled; 99 }; 100 101 /* 102 * In the routines that deal directly with the pcf2127 hardware, we use 103 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 104 */ 105 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 106 { 107 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 108 unsigned char buf[7]; 109 int ret; 110 111 /* 112 * Avoid reading CTRL2 register as it causes WD_VAL register 113 * value to reset to 0 which means watchdog is stopped. 114 */ 115 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_SC, buf, 116 sizeof(buf)); 117 if (ret) { 118 dev_err(dev, "%s: read error\n", __func__); 119 return ret; 120 } 121 122 /* Clock integrity is not guaranteed when OSF flag is set. */ 123 if (buf[0] & PCF2127_BIT_SC_OSF) { 124 /* 125 * no need clear the flag here, 126 * it will be cleared once the new date is saved 127 */ 128 dev_warn(dev, 129 "oscillator stop detected, date/time is not reliable\n"); 130 return -EINVAL; 131 } 132 133 dev_dbg(dev, 134 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 135 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 136 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 137 138 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 139 tm->tm_min = bcd2bin(buf[1] & 0x7F); 140 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 141 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 142 tm->tm_wday = buf[4] & 0x07; 143 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 144 tm->tm_year = bcd2bin(buf[6]); 145 tm->tm_year += 100; 146 147 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 148 "mday=%d, mon=%d, year=%d, wday=%d\n", 149 __func__, 150 tm->tm_sec, tm->tm_min, tm->tm_hour, 151 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 152 153 return 0; 154 } 155 156 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 157 { 158 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 159 unsigned char buf[7]; 160 int i = 0, err; 161 162 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 163 "mday=%d, mon=%d, year=%d, wday=%d\n", 164 __func__, 165 tm->tm_sec, tm->tm_min, tm->tm_hour, 166 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 167 168 /* hours, minutes and seconds */ 169 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 170 buf[i++] = bin2bcd(tm->tm_min); 171 buf[i++] = bin2bcd(tm->tm_hour); 172 buf[i++] = bin2bcd(tm->tm_mday); 173 buf[i++] = tm->tm_wday & 0x07; 174 175 /* month, 1 - 12 */ 176 buf[i++] = bin2bcd(tm->tm_mon + 1); 177 178 /* year */ 179 buf[i++] = bin2bcd(tm->tm_year - 100); 180 181 /* write register's data */ 182 err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i); 183 if (err) { 184 dev_dbg(dev, "%s: err=%d", __func__, err); 185 return err; 186 } 187 188 return 0; 189 } 190 191 static int pcf2127_rtc_ioctl(struct device *dev, 192 unsigned int cmd, unsigned long arg) 193 { 194 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 195 int val, touser = 0; 196 int ret; 197 198 switch (cmd) { 199 case RTC_VL_READ: 200 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 201 if (ret) 202 return ret; 203 204 if (val & PCF2127_BIT_CTRL3_BLF) 205 touser |= RTC_VL_BACKUP_LOW; 206 207 if (val & PCF2127_BIT_CTRL3_BF) 208 touser |= RTC_VL_BACKUP_SWITCH; 209 210 return put_user(touser, (unsigned int __user *)arg); 211 212 case RTC_VL_CLR: 213 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 214 PCF2127_BIT_CTRL3_BF, 0); 215 216 default: 217 return -ENOIOCTLCMD; 218 } 219 } 220 221 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 222 void *val, size_t bytes) 223 { 224 struct pcf2127 *pcf2127 = priv; 225 int ret; 226 unsigned char offsetbuf[] = { offset >> 8, offset }; 227 228 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 229 offsetbuf, 2); 230 if (ret) 231 return ret; 232 233 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 234 val, bytes); 235 } 236 237 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 238 void *val, size_t bytes) 239 { 240 struct pcf2127 *pcf2127 = priv; 241 int ret; 242 unsigned char offsetbuf[] = { offset >> 8, offset }; 243 244 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 245 offsetbuf, 2); 246 if (ret) 247 return ret; 248 249 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 250 val, bytes); 251 } 252 253 /* watchdog driver */ 254 255 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 256 { 257 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 258 259 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout); 260 } 261 262 /* 263 * Restart watchdog timer if feature is active. 264 * 265 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 266 * since register also contain control/status flags for other features. 267 * Always call this function after reading CTRL2 register. 268 */ 269 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 270 { 271 int ret = 0; 272 273 if (watchdog_active(wdd)) { 274 ret = pcf2127_wdt_ping(wdd); 275 if (ret) 276 dev_err(wdd->parent, 277 "%s: watchdog restart failed, ret=%d\n", 278 __func__, ret); 279 } 280 281 return ret; 282 } 283 284 static int pcf2127_wdt_start(struct watchdog_device *wdd) 285 { 286 return pcf2127_wdt_ping(wdd); 287 } 288 289 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 290 { 291 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 292 293 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, 294 PCF2127_WD_VAL_STOP); 295 } 296 297 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 298 unsigned int new_timeout) 299 { 300 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 301 new_timeout, wdd->timeout); 302 303 wdd->timeout = new_timeout; 304 305 return pcf2127_wdt_active_ping(wdd); 306 } 307 308 static const struct watchdog_info pcf2127_wdt_info = { 309 .identity = "NXP PCF2127/PCF2129 Watchdog", 310 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 311 }; 312 313 static const struct watchdog_ops pcf2127_watchdog_ops = { 314 .owner = THIS_MODULE, 315 .start = pcf2127_wdt_start, 316 .stop = pcf2127_wdt_stop, 317 .ping = pcf2127_wdt_ping, 318 .set_timeout = pcf2127_wdt_set_timeout, 319 }; 320 321 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 322 { 323 u32 wdd_timeout; 324 int ret; 325 326 if (!IS_ENABLED(CONFIG_WATCHDOG) || 327 !device_property_read_bool(dev, "reset-source")) 328 return 0; 329 330 pcf2127->wdd.parent = dev; 331 pcf2127->wdd.info = &pcf2127_wdt_info; 332 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 333 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 334 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 335 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 336 pcf2127->wdd.min_hw_heartbeat_ms = 500; 337 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 338 339 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 340 341 /* Test if watchdog timer is started by bootloader */ 342 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout); 343 if (ret) 344 return ret; 345 346 if (wdd_timeout) 347 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 348 349 return devm_watchdog_register_device(dev, &pcf2127->wdd); 350 } 351 352 /* Alarm */ 353 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 354 { 355 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 356 u8 buf[5]; 357 unsigned int ctrl2; 358 int ret; 359 360 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 361 if (ret) 362 return ret; 363 364 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 365 if (ret) 366 return ret; 367 368 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 369 sizeof(buf)); 370 if (ret) 371 return ret; 372 373 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 374 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 375 376 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 377 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 378 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 379 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 380 381 return 0; 382 } 383 384 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 385 { 386 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 387 int ret; 388 389 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 390 PCF2127_BIT_CTRL2_AIE, 391 enable ? PCF2127_BIT_CTRL2_AIE : 0); 392 if (ret) 393 return ret; 394 395 return pcf2127_wdt_active_ping(&pcf2127->wdd); 396 } 397 398 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 399 { 400 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 401 uint8_t buf[5]; 402 int ret; 403 404 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 405 PCF2127_BIT_CTRL2_AF, 0); 406 if (ret) 407 return ret; 408 409 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 410 if (ret) 411 return ret; 412 413 buf[0] = bin2bcd(alrm->time.tm_sec); 414 buf[1] = bin2bcd(alrm->time.tm_min); 415 buf[2] = bin2bcd(alrm->time.tm_hour); 416 buf[3] = bin2bcd(alrm->time.tm_mday); 417 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 418 419 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 420 sizeof(buf)); 421 if (ret) 422 return ret; 423 424 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 425 } 426 427 /* 428 * This function reads ctrl2 register, caller is responsible for calling 429 * pcf2127_wdt_active_ping() 430 */ 431 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) 432 { 433 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 434 struct rtc_time tm; 435 int ret; 436 unsigned char data[7]; 437 438 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_TS_CTRL, data, 439 sizeof(data)); 440 if (ret) { 441 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 442 return ret; 443 } 444 445 dev_dbg(dev, 446 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 447 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 448 449 tm.tm_sec = bcd2bin(data[1] & 0x7F); 450 tm.tm_min = bcd2bin(data[2] & 0x7F); 451 tm.tm_hour = bcd2bin(data[3] & 0x3F); 452 tm.tm_mday = bcd2bin(data[4] & 0x3F); 453 /* TS_MO register (month) value range: 1-12 */ 454 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 455 tm.tm_year = bcd2bin(data[6]); 456 if (tm.tm_year < 70) 457 tm.tm_year += 100; /* assume we are in 1970...2069 */ 458 459 ret = rtc_valid_tm(&tm); 460 if (ret) { 461 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 462 return ret; 463 } 464 465 *ts = rtc_tm_to_time64(&tm); 466 return 0; 467 }; 468 469 static void pcf2127_rtc_ts_snapshot(struct device *dev) 470 { 471 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 472 int ret; 473 474 /* Let userspace read the first timestamp */ 475 if (pcf2127->ts_valid) 476 return; 477 478 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts); 479 if (!ret) 480 pcf2127->ts_valid = true; 481 } 482 483 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 484 { 485 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 486 unsigned int ctrl1, ctrl2; 487 int ret = 0; 488 489 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 490 if (ret) 491 return IRQ_NONE; 492 493 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 494 if (ret) 495 return IRQ_NONE; 496 497 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 498 return IRQ_NONE; 499 500 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 501 pcf2127_rtc_ts_snapshot(dev); 502 503 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 504 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 505 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 506 507 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 508 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 509 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 510 511 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 512 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 513 514 pcf2127_wdt_active_ping(&pcf2127->wdd); 515 516 return IRQ_HANDLED; 517 } 518 519 static const struct rtc_class_ops pcf2127_rtc_ops = { 520 .ioctl = pcf2127_rtc_ioctl, 521 .read_time = pcf2127_rtc_read_time, 522 .set_time = pcf2127_rtc_set_time, 523 .read_alarm = pcf2127_rtc_read_alarm, 524 .set_alarm = pcf2127_rtc_set_alarm, 525 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 526 }; 527 528 /* sysfs interface */ 529 530 static ssize_t timestamp0_store(struct device *dev, 531 struct device_attribute *attr, 532 const char *buf, size_t count) 533 { 534 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 535 int ret; 536 537 if (pcf2127->irq_enabled) { 538 pcf2127->ts_valid = false; 539 } else { 540 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 541 PCF2127_BIT_CTRL1_TSF1, 0); 542 if (ret) { 543 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 544 return ret; 545 } 546 547 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 548 PCF2127_BIT_CTRL2_TSF2, 0); 549 if (ret) { 550 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 551 return ret; 552 } 553 554 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 555 if (ret) 556 return ret; 557 } 558 559 return count; 560 }; 561 562 static ssize_t timestamp0_show(struct device *dev, 563 struct device_attribute *attr, char *buf) 564 { 565 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 566 unsigned int ctrl1, ctrl2; 567 int ret; 568 time64_t ts; 569 570 if (pcf2127->irq_enabled) { 571 if (!pcf2127->ts_valid) 572 return 0; 573 ts = pcf2127->ts; 574 } else { 575 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 576 if (ret) 577 return 0; 578 579 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 580 if (ret) 581 return 0; 582 583 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && 584 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) 585 return 0; 586 587 ret = pcf2127_rtc_ts_read(dev->parent, &ts); 588 if (ret) 589 return 0; 590 591 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 592 if (ret) 593 return ret; 594 } 595 return sprintf(buf, "%llu\n", (unsigned long long)ts); 596 }; 597 598 static DEVICE_ATTR_RW(timestamp0); 599 600 static struct attribute *pcf2127_attrs[] = { 601 &dev_attr_timestamp0.attr, 602 NULL 603 }; 604 605 static const struct attribute_group pcf2127_attr_group = { 606 .attrs = pcf2127_attrs, 607 }; 608 609 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 610 int alarm_irq, const char *name, bool is_pcf2127) 611 { 612 struct pcf2127 *pcf2127; 613 int ret = 0; 614 unsigned int val; 615 616 dev_dbg(dev, "%s\n", __func__); 617 618 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 619 if (!pcf2127) 620 return -ENOMEM; 621 622 pcf2127->regmap = regmap; 623 624 dev_set_drvdata(dev, pcf2127); 625 626 pcf2127->rtc = devm_rtc_allocate_device(dev); 627 if (IS_ERR(pcf2127->rtc)) 628 return PTR_ERR(pcf2127->rtc); 629 630 pcf2127->rtc->ops = &pcf2127_rtc_ops; 631 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 632 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 633 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 634 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 635 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 636 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 637 638 if (alarm_irq > 0) { 639 unsigned long flags; 640 641 /* 642 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 643 * obtained from device tree. 644 */ 645 if (dev_fwnode(dev)) 646 flags = 0; 647 else 648 flags = IRQF_TRIGGER_LOW; 649 650 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 651 pcf2127_rtc_irq, 652 flags | IRQF_ONESHOT, 653 dev_name(dev), dev); 654 if (ret) { 655 dev_err(dev, "failed to request alarm irq\n"); 656 return ret; 657 } 658 pcf2127->irq_enabled = true; 659 } 660 661 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 662 device_init_wakeup(dev, true); 663 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 664 } 665 666 if (is_pcf2127) { 667 struct nvmem_config nvmem_cfg = { 668 .priv = pcf2127, 669 .reg_read = pcf2127_nvmem_read, 670 .reg_write = pcf2127_nvmem_write, 671 .size = 512, 672 }; 673 674 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 675 } 676 677 /* 678 * The "Power-On Reset Override" facility prevents the RTC to do a reset 679 * after power on. For normal operation the PORO must be disabled. 680 */ 681 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 682 PCF2127_BIT_CTRL1_POR_OVRD); 683 684 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); 685 if (ret < 0) 686 return ret; 687 688 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 689 ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, 690 PCF2127_BIT_CLKOUT_OTPR); 691 if (ret < 0) 692 return ret; 693 694 msleep(100); 695 } 696 697 /* 698 * Watchdog timer enabled and reset pin /RST activated when timed out. 699 * Select 1Hz clock source for watchdog timer. 700 * Note: Countdown timer disabled and not available. 701 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 702 * of register watchdg_tim_ctl. The bit[6] is labeled 703 * as T. Bits labeled as T must always be written with 704 * logic 0. 705 */ 706 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, 707 PCF2127_BIT_WD_CTL_CD1 | 708 PCF2127_BIT_WD_CTL_CD0 | 709 PCF2127_BIT_WD_CTL_TF1 | 710 PCF2127_BIT_WD_CTL_TF0, 711 PCF2127_BIT_WD_CTL_CD1 | 712 (is_pcf2127 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 713 PCF2127_BIT_WD_CTL_TF1); 714 if (ret) { 715 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 716 return ret; 717 } 718 719 pcf2127_watchdog_init(dev, pcf2127); 720 721 /* 722 * Disable battery low/switch-over timestamp and interrupts. 723 * Clear battery interrupt flags which can block new trigger events. 724 * Note: This is the default chip behaviour but added to ensure 725 * correct tamper timestamp and interrupt function. 726 */ 727 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 728 PCF2127_BIT_CTRL3_BTSE | 729 PCF2127_BIT_CTRL3_BIE | 730 PCF2127_BIT_CTRL3_BLIE, 0); 731 if (ret) { 732 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 733 __func__); 734 return ret; 735 } 736 737 /* 738 * Enable timestamp function and store timestamp of first trigger 739 * event until TSF1 and TSF2 interrupt flags are cleared. 740 */ 741 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 742 PCF2127_BIT_TS_CTRL_TSOFF | 743 PCF2127_BIT_TS_CTRL_TSM, 744 PCF2127_BIT_TS_CTRL_TSM); 745 if (ret) { 746 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 747 __func__); 748 return ret; 749 } 750 751 /* 752 * Enable interrupt generation when TSF1 or TSF2 timestamp flags 753 * are set. Interrupt signal is an open-drain output and can be 754 * left floating if unused. 755 */ 756 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 757 PCF2127_BIT_CTRL2_TSIE, 758 PCF2127_BIT_CTRL2_TSIE); 759 if (ret) { 760 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 761 __func__); 762 return ret; 763 } 764 765 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 766 if (ret) { 767 dev_err(dev, "%s: tamper sysfs registering failed\n", 768 __func__); 769 return ret; 770 } 771 772 return devm_rtc_register_device(pcf2127->rtc); 773 } 774 775 #ifdef CONFIG_OF 776 static const struct of_device_id pcf2127_of_match[] = { 777 { .compatible = "nxp,pcf2127" }, 778 { .compatible = "nxp,pcf2129" }, 779 { .compatible = "nxp,pca2129" }, 780 {} 781 }; 782 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 783 #endif 784 785 #if IS_ENABLED(CONFIG_I2C) 786 787 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 788 { 789 struct device *dev = context; 790 struct i2c_client *client = to_i2c_client(dev); 791 int ret; 792 793 ret = i2c_master_send(client, data, count); 794 if (ret != count) 795 return ret < 0 ? ret : -EIO; 796 797 return 0; 798 } 799 800 static int pcf2127_i2c_gather_write(void *context, 801 const void *reg, size_t reg_size, 802 const void *val, size_t val_size) 803 { 804 struct device *dev = context; 805 struct i2c_client *client = to_i2c_client(dev); 806 int ret; 807 void *buf; 808 809 if (WARN_ON(reg_size != 1)) 810 return -EINVAL; 811 812 buf = kmalloc(val_size + 1, GFP_KERNEL); 813 if (!buf) 814 return -ENOMEM; 815 816 memcpy(buf, reg, 1); 817 memcpy(buf + 1, val, val_size); 818 819 ret = i2c_master_send(client, buf, val_size + 1); 820 821 kfree(buf); 822 823 if (ret != val_size + 1) 824 return ret < 0 ? ret : -EIO; 825 826 return 0; 827 } 828 829 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 830 void *val, size_t val_size) 831 { 832 struct device *dev = context; 833 struct i2c_client *client = to_i2c_client(dev); 834 int ret; 835 836 if (WARN_ON(reg_size != 1)) 837 return -EINVAL; 838 839 ret = i2c_master_send(client, reg, 1); 840 if (ret != 1) 841 return ret < 0 ? ret : -EIO; 842 843 ret = i2c_master_recv(client, val, val_size); 844 if (ret != val_size) 845 return ret < 0 ? ret : -EIO; 846 847 return 0; 848 } 849 850 /* 851 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 852 * is that the STOP condition is required between set register address and 853 * read register data when reading from registers. 854 */ 855 static const struct regmap_bus pcf2127_i2c_regmap = { 856 .write = pcf2127_i2c_write, 857 .gather_write = pcf2127_i2c_gather_write, 858 .read = pcf2127_i2c_read, 859 }; 860 861 static struct i2c_driver pcf2127_i2c_driver; 862 863 static const struct i2c_device_id pcf2127_i2c_id[] = { 864 { "pcf2127", 1 }, 865 { "pcf2129", 0 }, 866 { "pca2129", 0 }, 867 { } 868 }; 869 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 870 871 static int pcf2127_i2c_probe(struct i2c_client *client) 872 { 873 const struct i2c_device_id *id = i2c_match_id(pcf2127_i2c_id, client); 874 struct regmap *regmap; 875 static const struct regmap_config config = { 876 .reg_bits = 8, 877 .val_bits = 8, 878 .max_register = 0x1d, 879 }; 880 881 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 882 return -ENODEV; 883 884 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 885 &client->dev, &config); 886 if (IS_ERR(regmap)) { 887 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 888 __func__, PTR_ERR(regmap)); 889 return PTR_ERR(regmap); 890 } 891 892 return pcf2127_probe(&client->dev, regmap, client->irq, 893 pcf2127_i2c_driver.driver.name, id->driver_data); 894 } 895 896 static struct i2c_driver pcf2127_i2c_driver = { 897 .driver = { 898 .name = "rtc-pcf2127-i2c", 899 .of_match_table = of_match_ptr(pcf2127_of_match), 900 }, 901 .probe = pcf2127_i2c_probe, 902 .id_table = pcf2127_i2c_id, 903 }; 904 905 static int pcf2127_i2c_register_driver(void) 906 { 907 return i2c_add_driver(&pcf2127_i2c_driver); 908 } 909 910 static void pcf2127_i2c_unregister_driver(void) 911 { 912 i2c_del_driver(&pcf2127_i2c_driver); 913 } 914 915 #else 916 917 static int pcf2127_i2c_register_driver(void) 918 { 919 return 0; 920 } 921 922 static void pcf2127_i2c_unregister_driver(void) 923 { 924 } 925 926 #endif 927 928 #if IS_ENABLED(CONFIG_SPI_MASTER) 929 930 static struct spi_driver pcf2127_spi_driver; 931 932 static int pcf2127_spi_probe(struct spi_device *spi) 933 { 934 static const struct regmap_config config = { 935 .reg_bits = 8, 936 .val_bits = 8, 937 .read_flag_mask = 0xa0, 938 .write_flag_mask = 0x20, 939 .max_register = 0x1d, 940 }; 941 struct regmap *regmap; 942 943 regmap = devm_regmap_init_spi(spi, &config); 944 if (IS_ERR(regmap)) { 945 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 946 __func__, PTR_ERR(regmap)); 947 return PTR_ERR(regmap); 948 } 949 950 return pcf2127_probe(&spi->dev, regmap, spi->irq, 951 pcf2127_spi_driver.driver.name, 952 spi_get_device_id(spi)->driver_data); 953 } 954 955 static const struct spi_device_id pcf2127_spi_id[] = { 956 { "pcf2127", 1 }, 957 { "pcf2129", 0 }, 958 { "pca2129", 0 }, 959 { } 960 }; 961 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 962 963 static struct spi_driver pcf2127_spi_driver = { 964 .driver = { 965 .name = "rtc-pcf2127-spi", 966 .of_match_table = of_match_ptr(pcf2127_of_match), 967 }, 968 .probe = pcf2127_spi_probe, 969 .id_table = pcf2127_spi_id, 970 }; 971 972 static int pcf2127_spi_register_driver(void) 973 { 974 return spi_register_driver(&pcf2127_spi_driver); 975 } 976 977 static void pcf2127_spi_unregister_driver(void) 978 { 979 spi_unregister_driver(&pcf2127_spi_driver); 980 } 981 982 #else 983 984 static int pcf2127_spi_register_driver(void) 985 { 986 return 0; 987 } 988 989 static void pcf2127_spi_unregister_driver(void) 990 { 991 } 992 993 #endif 994 995 static int __init pcf2127_init(void) 996 { 997 int ret; 998 999 ret = pcf2127_i2c_register_driver(); 1000 if (ret) { 1001 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1002 return ret; 1003 } 1004 1005 ret = pcf2127_spi_register_driver(); 1006 if (ret) { 1007 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1008 pcf2127_i2c_unregister_driver(); 1009 } 1010 1011 return ret; 1012 } 1013 module_init(pcf2127_init) 1014 1015 static void __exit pcf2127_exit(void) 1016 { 1017 pcf2127_spi_unregister_driver(); 1018 pcf2127_i2c_unregister_driver(); 1019 } 1020 module_exit(pcf2127_exit) 1021 1022 MODULE_AUTHOR("Renaud Cerrato <[email protected]>"); 1023 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 1024 MODULE_LICENSE("GPL v2"); 1025