1 /* 2 * An SPI driver for the Philips PCF2123 RTC 3 * Copyright 2009 Cyber Switching, Inc. 4 * 5 * Author: Chris Verges <[email protected]> 6 * Maintainers: http://www.cyberswitching.com 7 * 8 * based on the RS5C348 driver in this same directory. 9 * 10 * Thanks to Christian Pellegrin <[email protected]> for 11 * the sysfs contributions to this driver. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 * 17 * Please note that the CS is active high, so platform data 18 * should look something like: 19 * 20 * static struct spi_board_info ek_spi_devices[] = { 21 * ... 22 * { 23 * .modalias = "rtc-pcf2123", 24 * .chip_select = 1, 25 * .controller_data = (void *)AT91_PIN_PA10, 26 * .max_speed_hz = 1000 * 1000, 27 * .mode = SPI_CS_HIGH, 28 * .bus_num = 0, 29 * }, 30 * ... 31 *}; 32 * 33 */ 34 35 #include <linux/bcd.h> 36 #include <linux/delay.h> 37 #include <linux/device.h> 38 #include <linux/errno.h> 39 #include <linux/init.h> 40 #include <linux/kernel.h> 41 #include <linux/of.h> 42 #include <linux/string.h> 43 #include <linux/slab.h> 44 #include <linux/rtc.h> 45 #include <linux/spi/spi.h> 46 #include <linux/module.h> 47 #include <linux/regmap.h> 48 49 /* REGISTERS */ 50 #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ 51 #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ 52 #define PCF2123_REG_SC (0x02) /* datetime */ 53 #define PCF2123_REG_MN (0x03) 54 #define PCF2123_REG_HR (0x04) 55 #define PCF2123_REG_DM (0x05) 56 #define PCF2123_REG_DW (0x06) 57 #define PCF2123_REG_MO (0x07) 58 #define PCF2123_REG_YR (0x08) 59 #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ 60 #define PCF2123_REG_ALRM_HR (0x0a) 61 #define PCF2123_REG_ALRM_DM (0x0b) 62 #define PCF2123_REG_ALRM_DW (0x0c) 63 #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ 64 #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ 65 #define PCF2123_REG_CTDWN_TMR (0x0f) 66 67 /* PCF2123_REG_CTRL1 BITS */ 68 #define CTRL1_CLEAR (0) /* Clear */ 69 #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ 70 #define CTRL1_12_HOUR BIT(2) /* 12 hour time */ 71 #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ 72 #define CTRL1_STOP BIT(5) /* Stop the clock */ 73 #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ 74 75 /* PCF2123_REG_CTRL2 BITS */ 76 #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ 77 #define CTRL2_AIE BIT(1) /* Alarm irq enable */ 78 #define CTRL2_TF BIT(2) /* Countdown timer flag */ 79 #define CTRL2_AF BIT(3) /* Alarm flag */ 80 #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ 81 #define CTRL2_MSF BIT(5) /* Minute or second irq flag */ 82 #define CTRL2_SI BIT(6) /* Second irq enable */ 83 #define CTRL2_MI BIT(7) /* Minute irq enable */ 84 85 /* PCF2123_REG_SC BITS */ 86 #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ 87 88 /* PCF2123_REG_ALRM_XX BITS */ 89 #define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */ 90 91 /* PCF2123_REG_TMR_CLKOUT BITS */ 92 #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */ 93 #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */ 94 #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */ 95 #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */ 96 #define CD_TMR_TE BIT(3) /* Countdown timer enable */ 97 98 /* PCF2123_REG_OFFSET BITS */ 99 #define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */ 100 #define OFFSET_COARSE BIT(7) /* Coarse mode offset */ 101 #define OFFSET_STEP (2170) /* Offset step in parts per billion */ 102 #define OFFSET_MASK GENMASK(6, 0) /* Offset value */ 103 104 /* READ/WRITE ADDRESS BITS */ 105 #define PCF2123_WRITE BIT(4) 106 #define PCF2123_READ (BIT(4) | BIT(7)) 107 108 109 static struct spi_driver pcf2123_driver; 110 111 struct pcf2123_plat_data { 112 struct rtc_device *rtc; 113 struct regmap *map; 114 }; 115 116 static const struct regmap_config pcf2123_regmap_config = { 117 .reg_bits = 8, 118 .val_bits = 8, 119 .read_flag_mask = PCF2123_READ, 120 .write_flag_mask = PCF2123_WRITE, 121 .max_register = PCF2123_REG_CTDWN_TMR, 122 }; 123 124 static int pcf2123_read_offset(struct device *dev, long *offset) 125 { 126 struct pcf2123_plat_data *pdata = dev_get_platdata(dev); 127 int ret, val; 128 unsigned int reg; 129 130 ret = regmap_read(pdata->map, PCF2123_REG_OFFSET, ®); 131 if (ret) 132 return ret; 133 134 val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT); 135 136 if (reg & OFFSET_COARSE) 137 val *= 2; 138 139 *offset = ((long)val) * OFFSET_STEP; 140 141 return 0; 142 } 143 144 /* 145 * The offset register is a 7 bit signed value with a coarse bit in bit 7. 146 * The main difference between the two is normal offset adjusts the first 147 * second of n minutes every other hour, with 61, 62 and 63 being shoved 148 * into the 60th minute. 149 * The coarse adjustment does the same, but every hour. 150 * the two overlap, with every even normal offset value corresponding 151 * to a coarse offset. Based on this algorithm, it seems that despite the 152 * name, coarse offset is a better fit for overlapping values. 153 */ 154 static int pcf2123_set_offset(struct device *dev, long offset) 155 { 156 struct pcf2123_plat_data *pdata = dev_get_platdata(dev); 157 s8 reg; 158 159 if (offset > OFFSET_STEP * 127) 160 reg = 127; 161 else if (offset < OFFSET_STEP * -128) 162 reg = -128; 163 else 164 reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP); 165 166 /* choose fine offset only for odd values in the normal range */ 167 if (reg & 1 && reg <= 63 && reg >= -64) { 168 /* Normal offset. Clear the coarse bit */ 169 reg &= ~OFFSET_COARSE; 170 } else { 171 /* Coarse offset. Divide by 2 and set the coarse bit */ 172 reg >>= 1; 173 reg |= OFFSET_COARSE; 174 } 175 176 return regmap_write(pdata->map, PCF2123_REG_OFFSET, (unsigned int)reg); 177 } 178 179 static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm) 180 { 181 struct pcf2123_plat_data *pdata = dev_get_platdata(dev); 182 u8 rxbuf[7]; 183 int ret; 184 185 ret = regmap_bulk_read(pdata->map, PCF2123_REG_SC, rxbuf, 186 sizeof(rxbuf)); 187 if (ret) 188 return ret; 189 190 if (rxbuf[0] & OSC_HAS_STOPPED) { 191 dev_info(dev, "clock was stopped. Time is not valid\n"); 192 return -EINVAL; 193 } 194 195 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F); 196 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F); 197 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */ 198 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F); 199 tm->tm_wday = rxbuf[4] & 0x07; 200 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */ 201 tm->tm_year = bcd2bin(rxbuf[6]); 202 if (tm->tm_year < 70) 203 tm->tm_year += 100; /* assume we are in 1970...2069 */ 204 205 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 206 "mday=%d, mon=%d, year=%d, wday=%d\n", 207 __func__, 208 tm->tm_sec, tm->tm_min, tm->tm_hour, 209 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 210 211 return 0; 212 } 213 214 static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm) 215 { 216 struct pcf2123_plat_data *pdata = dev_get_platdata(dev); 217 u8 txbuf[7]; 218 int ret; 219 220 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 221 "mday=%d, mon=%d, year=%d, wday=%d\n", 222 __func__, 223 tm->tm_sec, tm->tm_min, tm->tm_hour, 224 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 225 226 /* Stop the counter first */ 227 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP); 228 if (ret) 229 return ret; 230 231 /* Set the new time */ 232 txbuf[0] = bin2bcd(tm->tm_sec & 0x7F); 233 txbuf[1] = bin2bcd(tm->tm_min & 0x7F); 234 txbuf[2] = bin2bcd(tm->tm_hour & 0x3F); 235 txbuf[3] = bin2bcd(tm->tm_mday & 0x3F); 236 txbuf[4] = tm->tm_wday & 0x07; 237 txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */ 238 txbuf[6] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100); 239 240 ret = regmap_bulk_write(pdata->map, PCF2123_REG_SC, txbuf, 241 sizeof(txbuf)); 242 if (ret) 243 return ret; 244 245 /* Start the counter */ 246 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR); 247 if (ret) 248 return ret; 249 250 return 0; 251 } 252 253 static int pcf2123_reset(struct device *dev) 254 { 255 struct pcf2123_plat_data *pdata = dev_get_platdata(dev); 256 int ret; 257 unsigned int val = 0; 258 259 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET); 260 if (ret) 261 return ret; 262 263 /* Stop the counter */ 264 dev_dbg(dev, "stopping RTC\n"); 265 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP); 266 if (ret) 267 return ret; 268 269 /* See if the counter was actually stopped */ 270 dev_dbg(dev, "checking for presence of RTC\n"); 271 ret = regmap_read(pdata->map, PCF2123_REG_CTRL1, &val); 272 if (ret) 273 return ret; 274 275 dev_dbg(dev, "received data from RTC (0x%08X)\n", val); 276 if (!(val & CTRL1_STOP)) 277 return -ENODEV; 278 279 /* Start the counter */ 280 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR); 281 if (ret) 282 return ret; 283 284 return 0; 285 } 286 287 static const struct rtc_class_ops pcf2123_rtc_ops = { 288 .read_time = pcf2123_rtc_read_time, 289 .set_time = pcf2123_rtc_set_time, 290 .read_offset = pcf2123_read_offset, 291 .set_offset = pcf2123_set_offset, 292 293 }; 294 295 static int pcf2123_probe(struct spi_device *spi) 296 { 297 struct rtc_device *rtc; 298 struct rtc_time tm; 299 struct pcf2123_plat_data *pdata; 300 int ret; 301 302 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data), 303 GFP_KERNEL); 304 if (!pdata) 305 return -ENOMEM; 306 spi->dev.platform_data = pdata; 307 308 pdata->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config); 309 310 if (IS_ERR(pdata->map)) { 311 dev_err(&spi->dev, "regmap init failed.\n"); 312 goto kfree_exit; 313 } 314 315 ret = pcf2123_rtc_read_time(&spi->dev, &tm); 316 if (ret < 0) { 317 ret = pcf2123_reset(&spi->dev); 318 if (ret < 0) { 319 dev_err(&spi->dev, "chip not found\n"); 320 goto kfree_exit; 321 } 322 } 323 324 dev_info(&spi->dev, "spiclk %u KHz.\n", 325 (spi->max_speed_hz + 500) / 1000); 326 327 /* Finalize the initialization */ 328 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name, 329 &pcf2123_rtc_ops, THIS_MODULE); 330 331 if (IS_ERR(rtc)) { 332 dev_err(&spi->dev, "failed to register.\n"); 333 ret = PTR_ERR(rtc); 334 goto kfree_exit; 335 } 336 337 pdata->rtc = rtc; 338 339 return 0; 340 341 kfree_exit: 342 spi->dev.platform_data = NULL; 343 return ret; 344 } 345 346 #ifdef CONFIG_OF 347 static const struct of_device_id pcf2123_dt_ids[] = { 348 { .compatible = "nxp,rtc-pcf2123", }, 349 { .compatible = "microcrystal,rv2123", }, 350 { /* sentinel */ } 351 }; 352 MODULE_DEVICE_TABLE(of, pcf2123_dt_ids); 353 #endif 354 355 static struct spi_driver pcf2123_driver = { 356 .driver = { 357 .name = "rtc-pcf2123", 358 .of_match_table = of_match_ptr(pcf2123_dt_ids), 359 }, 360 .probe = pcf2123_probe, 361 }; 362 363 module_spi_driver(pcf2123_driver); 364 365 MODULE_AUTHOR("Chris Verges <[email protected]>"); 366 MODULE_DESCRIPTION("NXP PCF2123 RTC driver"); 367 MODULE_LICENSE("GPL"); 368