1 /* 2 * An SPI driver for the Philips PCF2123 RTC 3 * Copyright 2009 Cyber Switching, Inc. 4 * 5 * Author: Chris Verges <[email protected]> 6 * Maintainers: http://www.cyberswitching.com 7 * 8 * based on the RS5C348 driver in this same directory. 9 * 10 * Thanks to Christian Pellegrin <[email protected]> for 11 * the sysfs contributions to this driver. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 * 17 * Please note that the CS is active high, so platform data 18 * should look something like: 19 * 20 * static struct spi_board_info ek_spi_devices[] = { 21 * ... 22 * { 23 * .modalias = "rtc-pcf2123", 24 * .chip_select = 1, 25 * .controller_data = (void *)AT91_PIN_PA10, 26 * .max_speed_hz = 1000 * 1000, 27 * .mode = SPI_CS_HIGH, 28 * .bus_num = 0, 29 * }, 30 * ... 31 *}; 32 * 33 */ 34 35 #include <linux/bcd.h> 36 #include <linux/delay.h> 37 #include <linux/device.h> 38 #include <linux/errno.h> 39 #include <linux/init.h> 40 #include <linux/kernel.h> 41 #include <linux/of.h> 42 #include <linux/string.h> 43 #include <linux/slab.h> 44 #include <linux/rtc.h> 45 #include <linux/spi/spi.h> 46 #include <linux/module.h> 47 48 /* REGISTERS */ 49 #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ 50 #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ 51 #define PCF2123_REG_SC (0x02) /* datetime */ 52 #define PCF2123_REG_MN (0x03) 53 #define PCF2123_REG_HR (0x04) 54 #define PCF2123_REG_DM (0x05) 55 #define PCF2123_REG_DW (0x06) 56 #define PCF2123_REG_MO (0x07) 57 #define PCF2123_REG_YR (0x08) 58 #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ 59 #define PCF2123_REG_ALRM_HR (0x0a) 60 #define PCF2123_REG_ALRM_DM (0x0b) 61 #define PCF2123_REG_ALRM_DW (0x0c) 62 #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ 63 #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ 64 #define PCF2123_REG_CTDWN_TMR (0x0f) 65 66 /* PCF2123_REG_CTRL1 BITS */ 67 #define CTRL1_CLEAR (0) /* Clear */ 68 #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ 69 #define CTRL1_12_HOUR BIT(2) /* 12 hour time */ 70 #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ 71 #define CTRL1_STOP BIT(5) /* Stop the clock */ 72 #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ 73 74 /* PCF2123_REG_CTRL2 BITS */ 75 #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ 76 #define CTRL2_AIE BIT(1) /* Alarm irq enable */ 77 #define CTRL2_TF BIT(2) /* Countdown timer flag */ 78 #define CTRL2_AF BIT(3) /* Alarm flag */ 79 #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ 80 #define CTRL2_MSF BIT(5) /* Minute or second irq flag */ 81 #define CTRL2_SI BIT(6) /* Second irq enable */ 82 #define CTRL2_MI BIT(7) /* Minute irq enable */ 83 84 /* PCF2123_REG_SC BITS */ 85 #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ 86 87 /* PCF2123_REG_ALRM_XX BITS */ 88 #define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */ 89 90 /* PCF2123_REG_TMR_CLKOUT BITS */ 91 #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */ 92 #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */ 93 #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */ 94 #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */ 95 #define CD_TMR_TE BIT(3) /* Countdown timer enable */ 96 97 /* PCF2123_REG_OFFSET BITS */ 98 #define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */ 99 #define OFFSET_COARSE BIT(7) /* Coarse mode offset */ 100 #define OFFSET_STEP (2170) /* Offset step in parts per billion */ 101 102 /* READ/WRITE ADDRESS BITS */ 103 #define PCF2123_WRITE BIT(4) 104 #define PCF2123_READ (BIT(4) | BIT(7)) 105 106 107 static struct spi_driver pcf2123_driver; 108 109 struct pcf2123_plat_data { 110 struct rtc_device *rtc; 111 }; 112 113 /* 114 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select 115 * is released properly after an SPI write. This function should be 116 * called after EVERY read/write call over SPI. 117 */ 118 static inline void pcf2123_delay_trec(void) 119 { 120 ndelay(30); 121 } 122 123 static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size) 124 { 125 struct spi_device *spi = to_spi_device(dev); 126 int ret; 127 128 reg |= PCF2123_READ; 129 ret = spi_write_then_read(spi, ®, 1, rxbuf, size); 130 pcf2123_delay_trec(); 131 132 return ret; 133 } 134 135 static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size) 136 { 137 struct spi_device *spi = to_spi_device(dev); 138 int ret; 139 140 txbuf[0] |= PCF2123_WRITE; 141 ret = spi_write(spi, txbuf, size); 142 pcf2123_delay_trec(); 143 144 return ret; 145 } 146 147 static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val) 148 { 149 u8 txbuf[2]; 150 151 txbuf[0] = reg; 152 txbuf[1] = val; 153 return pcf2123_write(dev, txbuf, sizeof(txbuf)); 154 } 155 156 static int pcf2123_read_offset(struct device *dev, long *offset) 157 { 158 int ret; 159 s8 reg; 160 161 ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1); 162 if (ret < 0) 163 return ret; 164 165 if (reg & OFFSET_COARSE) 166 reg <<= 1; /* multiply by 2 and sign extend */ 167 else 168 reg = sign_extend32(reg, OFFSET_SIGN_BIT); 169 170 *offset = ((long)reg) * OFFSET_STEP; 171 172 return 0; 173 } 174 175 /* 176 * The offset register is a 7 bit signed value with a coarse bit in bit 7. 177 * The main difference between the two is normal offset adjusts the first 178 * second of n minutes every other hour, with 61, 62 and 63 being shoved 179 * into the 60th minute. 180 * The coarse adjustment does the same, but every hour. 181 * the two overlap, with every even normal offset value corresponding 182 * to a coarse offset. Based on this algorithm, it seems that despite the 183 * name, coarse offset is a better fit for overlapping values. 184 */ 185 static int pcf2123_set_offset(struct device *dev, long offset) 186 { 187 s8 reg; 188 189 if (offset > OFFSET_STEP * 127) 190 reg = 127; 191 else if (offset < OFFSET_STEP * -128) 192 reg = -128; 193 else 194 reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP); 195 196 /* choose fine offset only for odd values in the normal range */ 197 if (reg & 1 && reg <= 63 && reg >= -64) { 198 /* Normal offset. Clear the coarse bit */ 199 reg &= ~OFFSET_COARSE; 200 } else { 201 /* Coarse offset. Divide by 2 and set the coarse bit */ 202 reg >>= 1; 203 reg |= OFFSET_COARSE; 204 } 205 206 return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg); 207 } 208 209 static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm) 210 { 211 u8 rxbuf[7]; 212 int ret; 213 214 ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf)); 215 if (ret < 0) 216 return ret; 217 218 if (rxbuf[0] & OSC_HAS_STOPPED) { 219 dev_info(dev, "clock was stopped. Time is not valid\n"); 220 return -EINVAL; 221 } 222 223 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F); 224 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F); 225 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */ 226 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F); 227 tm->tm_wday = rxbuf[4] & 0x07; 228 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */ 229 tm->tm_year = bcd2bin(rxbuf[6]); 230 if (tm->tm_year < 70) 231 tm->tm_year += 100; /* assume we are in 1970...2069 */ 232 233 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 234 "mday=%d, mon=%d, year=%d, wday=%d\n", 235 __func__, 236 tm->tm_sec, tm->tm_min, tm->tm_hour, 237 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 238 239 return 0; 240 } 241 242 static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm) 243 { 244 u8 txbuf[8]; 245 int ret; 246 247 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 248 "mday=%d, mon=%d, year=%d, wday=%d\n", 249 __func__, 250 tm->tm_sec, tm->tm_min, tm->tm_hour, 251 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 252 253 /* Stop the counter first */ 254 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP); 255 if (ret < 0) 256 return ret; 257 258 /* Set the new time */ 259 txbuf[0] = PCF2123_REG_SC; 260 txbuf[1] = bin2bcd(tm->tm_sec & 0x7F); 261 txbuf[2] = bin2bcd(tm->tm_min & 0x7F); 262 txbuf[3] = bin2bcd(tm->tm_hour & 0x3F); 263 txbuf[4] = bin2bcd(tm->tm_mday & 0x3F); 264 txbuf[5] = tm->tm_wday & 0x07; 265 txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */ 266 txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100); 267 268 ret = pcf2123_write(dev, txbuf, sizeof(txbuf)); 269 if (ret < 0) 270 return ret; 271 272 /* Start the counter */ 273 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR); 274 if (ret < 0) 275 return ret; 276 277 return 0; 278 } 279 280 static int pcf2123_reset(struct device *dev) 281 { 282 int ret; 283 u8 rxbuf[2]; 284 285 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET); 286 if (ret < 0) 287 return ret; 288 289 /* Stop the counter */ 290 dev_dbg(dev, "stopping RTC\n"); 291 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP); 292 if (ret < 0) 293 return ret; 294 295 /* See if the counter was actually stopped */ 296 dev_dbg(dev, "checking for presence of RTC\n"); 297 ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf)); 298 if (ret < 0) 299 return ret; 300 301 dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n", 302 rxbuf[0], rxbuf[1]); 303 if (!(rxbuf[0] & CTRL1_STOP)) 304 return -ENODEV; 305 306 /* Start the counter */ 307 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR); 308 if (ret < 0) 309 return ret; 310 311 return 0; 312 } 313 314 static const struct rtc_class_ops pcf2123_rtc_ops = { 315 .read_time = pcf2123_rtc_read_time, 316 .set_time = pcf2123_rtc_set_time, 317 .read_offset = pcf2123_read_offset, 318 .set_offset = pcf2123_set_offset, 319 320 }; 321 322 static int pcf2123_probe(struct spi_device *spi) 323 { 324 struct rtc_device *rtc; 325 struct rtc_time tm; 326 struct pcf2123_plat_data *pdata; 327 int ret; 328 329 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data), 330 GFP_KERNEL); 331 if (!pdata) 332 return -ENOMEM; 333 spi->dev.platform_data = pdata; 334 335 ret = pcf2123_rtc_read_time(&spi->dev, &tm); 336 if (ret < 0) { 337 ret = pcf2123_reset(&spi->dev); 338 if (ret < 0) { 339 dev_err(&spi->dev, "chip not found\n"); 340 goto kfree_exit; 341 } 342 } 343 344 dev_info(&spi->dev, "spiclk %u KHz.\n", 345 (spi->max_speed_hz + 500) / 1000); 346 347 /* Finalize the initialization */ 348 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name, 349 &pcf2123_rtc_ops, THIS_MODULE); 350 351 if (IS_ERR(rtc)) { 352 dev_err(&spi->dev, "failed to register.\n"); 353 ret = PTR_ERR(rtc); 354 goto kfree_exit; 355 } 356 357 pdata->rtc = rtc; 358 359 return 0; 360 361 kfree_exit: 362 spi->dev.platform_data = NULL; 363 return ret; 364 } 365 366 #ifdef CONFIG_OF 367 static const struct of_device_id pcf2123_dt_ids[] = { 368 { .compatible = "nxp,rtc-pcf2123", }, 369 { .compatible = "microcrystal,rv2123", }, 370 { /* sentinel */ } 371 }; 372 MODULE_DEVICE_TABLE(of, pcf2123_dt_ids); 373 #endif 374 375 static struct spi_driver pcf2123_driver = { 376 .driver = { 377 .name = "rtc-pcf2123", 378 .of_match_table = of_match_ptr(pcf2123_dt_ids), 379 }, 380 .probe = pcf2123_probe, 381 }; 382 383 module_spi_driver(pcf2123_driver); 384 385 MODULE_AUTHOR("Chris Verges <[email protected]>"); 386 MODULE_DESCRIPTION("NXP PCF2123 RTC driver"); 387 MODULE_LICENSE("GPL"); 388