1 /* 2 * "RTT as Real Time Clock" driver for AT91SAM9 SoC family 3 * 4 * (C) 2007 Michel Benoit 5 * 6 * Based on rtc-at91rm9200.c by Rick Bronson 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/interrupt.h> 16 #include <linux/ioctl.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/rtc.h> 25 #include <linux/slab.h> 26 #include <linux/suspend.h> 27 #include <linux/time.h> 28 29 /* 30 * This driver uses two configurable hardware resources that live in the 31 * AT91SAM9 backup power domain (intended to be powered at all times) 32 * to implement the Real Time Clock interfaces 33 * 34 * - A "Real-time Timer" (RTT) counts up in seconds from a base time. 35 * We can't assign the counter value (CRTV) ... but we can reset it. 36 * 37 * - One of the "General Purpose Backup Registers" (GPBRs) holds the 38 * base time, normally an offset from the beginning of the POSIX 39 * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the 40 * local timezone's offset. 41 * 42 * The RTC's value is the RTT counter plus that offset. The RTC's alarm 43 * is likewise a base (ALMV) plus that offset. 44 * 45 * Not all RTTs will be used as RTCs; some systems have multiple RTTs to 46 * choose from, or a "real" RTC module. All systems have multiple GPBR 47 * registers available, likewise usable for more than "RTC" support. 48 */ 49 50 #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ 51 #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ 52 #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ 53 #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ 54 #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ 55 56 #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ 57 #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ 58 59 #define AT91_RTT_VR 0x08 /* Real-time Value Register */ 60 #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ 61 62 #define AT91_RTT_SR 0x0c /* Real-time Status Register */ 63 #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ 64 #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ 65 66 /* 67 * We store ALARM_DISABLED in ALMV to record that no alarm is set. 68 * It's also the reset value for that field. 69 */ 70 #define ALARM_DISABLED ((u32)~0) 71 72 73 struct sam9_rtc { 74 void __iomem *rtt; 75 struct rtc_device *rtcdev; 76 u32 imr; 77 struct regmap *gpbr; 78 unsigned int gpbr_offset; 79 int irq; 80 struct clk *sclk; 81 bool suspended; 82 unsigned long events; 83 spinlock_t lock; 84 }; 85 86 #define rtt_readl(rtc, field) \ 87 readl((rtc)->rtt + AT91_RTT_ ## field) 88 #define rtt_writel(rtc, field, val) \ 89 writel((val), (rtc)->rtt + AT91_RTT_ ## field) 90 91 static inline unsigned int gpbr_readl(struct sam9_rtc *rtc) 92 { 93 unsigned int val; 94 95 regmap_read(rtc->gpbr, rtc->gpbr_offset, &val); 96 97 return val; 98 } 99 100 static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val) 101 { 102 regmap_write(rtc->gpbr, rtc->gpbr_offset, val); 103 } 104 105 /* 106 * Read current time and date in RTC 107 */ 108 static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) 109 { 110 struct sam9_rtc *rtc = dev_get_drvdata(dev); 111 u32 secs, secs2; 112 u32 offset; 113 114 /* read current time offset */ 115 offset = gpbr_readl(rtc); 116 if (offset == 0) 117 return -EILSEQ; 118 119 /* reread the counter to help sync the two clock domains */ 120 secs = rtt_readl(rtc, VR); 121 secs2 = rtt_readl(rtc, VR); 122 if (secs != secs2) 123 secs = rtt_readl(rtc, VR); 124 125 rtc_time64_to_tm(offset + secs, tm); 126 127 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 128 129 return 0; 130 } 131 132 /* 133 * Set current time and date in RTC 134 */ 135 static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) 136 { 137 struct sam9_rtc *rtc = dev_get_drvdata(dev); 138 u32 offset, alarm, mr; 139 unsigned long secs; 140 141 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 142 143 secs = rtc_tm_to_time64(tm); 144 145 mr = rtt_readl(rtc, MR); 146 147 /* disable interrupts */ 148 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 149 150 /* read current time offset */ 151 offset = gpbr_readl(rtc); 152 153 /* store the new base time in a battery backup register */ 154 secs += 1; 155 gpbr_writel(rtc, secs); 156 157 /* adjust the alarm time for the new base */ 158 alarm = rtt_readl(rtc, AR); 159 if (alarm != ALARM_DISABLED) { 160 if (offset > secs) { 161 /* time jumped backwards, increase time until alarm */ 162 alarm += (offset - secs); 163 } else if ((alarm + offset) > secs) { 164 /* time jumped forwards, decrease time until alarm */ 165 alarm -= (secs - offset); 166 } else { 167 /* time jumped past the alarm, disable alarm */ 168 alarm = ALARM_DISABLED; 169 mr &= ~AT91_RTT_ALMIEN; 170 } 171 rtt_writel(rtc, AR, alarm); 172 } 173 174 /* reset the timer, and re-enable interrupts */ 175 rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST); 176 177 return 0; 178 } 179 180 static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) 181 { 182 struct sam9_rtc *rtc = dev_get_drvdata(dev); 183 struct rtc_time *tm = &alrm->time; 184 u32 alarm = rtt_readl(rtc, AR); 185 u32 offset; 186 187 offset = gpbr_readl(rtc); 188 if (offset == 0) 189 return -EILSEQ; 190 191 memset(alrm, 0, sizeof(*alrm)); 192 if (alarm != ALARM_DISABLED && offset != 0) { 193 rtc_time64_to_tm(offset + alarm, tm); 194 195 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 196 197 if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN) 198 alrm->enabled = 1; 199 } 200 201 return 0; 202 } 203 204 static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) 205 { 206 struct sam9_rtc *rtc = dev_get_drvdata(dev); 207 struct rtc_time *tm = &alrm->time; 208 unsigned long secs; 209 u32 offset; 210 u32 mr; 211 212 secs = rtc_tm_to_time64(tm); 213 214 offset = gpbr_readl(rtc); 215 if (offset == 0) { 216 /* time is not set */ 217 return -EILSEQ; 218 } 219 mr = rtt_readl(rtc, MR); 220 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); 221 222 /* alarm in the past? finish and leave disabled */ 223 if (secs <= offset) { 224 rtt_writel(rtc, AR, ALARM_DISABLED); 225 return 0; 226 } 227 228 /* else set alarm and maybe enable it */ 229 rtt_writel(rtc, AR, secs - offset); 230 if (alrm->enabled) 231 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); 232 233 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 234 235 return 0; 236 } 237 238 static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 239 { 240 struct sam9_rtc *rtc = dev_get_drvdata(dev); 241 u32 mr = rtt_readl(rtc, MR); 242 243 dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr); 244 if (enabled) 245 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); 246 else 247 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); 248 return 0; 249 } 250 251 /* 252 * Provide additional RTC information in /proc/driver/rtc 253 */ 254 static int at91_rtc_proc(struct device *dev, struct seq_file *seq) 255 { 256 struct sam9_rtc *rtc = dev_get_drvdata(dev); 257 u32 mr = rtt_readl(rtc, MR); 258 259 seq_printf(seq, "update_IRQ\t: %s\n", 260 (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no"); 261 return 0; 262 } 263 264 static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc) 265 { 266 u32 sr, mr; 267 268 /* Shared interrupt may be for another device. Note: reading 269 * SR clears it, so we must only read it in this irq handler! 270 */ 271 mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 272 sr = rtt_readl(rtc, SR) & (mr >> 16); 273 if (!sr) 274 return IRQ_NONE; 275 276 /* alarm status */ 277 if (sr & AT91_RTT_ALMS) 278 rtc->events |= (RTC_AF | RTC_IRQF); 279 280 /* timer update/increment */ 281 if (sr & AT91_RTT_RTTINC) 282 rtc->events |= (RTC_UF | RTC_IRQF); 283 284 return IRQ_HANDLED; 285 } 286 287 static void at91_rtc_flush_events(struct sam9_rtc *rtc) 288 { 289 if (!rtc->events) 290 return; 291 292 rtc_update_irq(rtc->rtcdev, 1, rtc->events); 293 rtc->events = 0; 294 295 pr_debug("%s: num=%ld, events=0x%02lx\n", __func__, 296 rtc->events >> 8, rtc->events & 0x000000FF); 297 } 298 299 /* 300 * IRQ handler for the RTC 301 */ 302 static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc) 303 { 304 struct sam9_rtc *rtc = _rtc; 305 int ret; 306 307 spin_lock(&rtc->lock); 308 309 ret = at91_rtc_cache_events(rtc); 310 311 /* We're called in suspended state */ 312 if (rtc->suspended) { 313 /* Mask irqs coming from this peripheral */ 314 rtt_writel(rtc, MR, 315 rtt_readl(rtc, MR) & 316 ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 317 /* Trigger a system wakeup */ 318 pm_system_wakeup(); 319 } else { 320 at91_rtc_flush_events(rtc); 321 } 322 323 spin_unlock(&rtc->lock); 324 325 return ret; 326 } 327 328 static const struct rtc_class_ops at91_rtc_ops = { 329 .read_time = at91_rtc_readtime, 330 .set_time = at91_rtc_settime, 331 .read_alarm = at91_rtc_readalarm, 332 .set_alarm = at91_rtc_setalarm, 333 .proc = at91_rtc_proc, 334 .alarm_irq_enable = at91_rtc_alarm_irq_enable, 335 }; 336 337 /* 338 * Initialize and install RTC driver 339 */ 340 static int at91_rtc_probe(struct platform_device *pdev) 341 { 342 struct resource *r; 343 struct sam9_rtc *rtc; 344 int ret, irq; 345 u32 mr; 346 unsigned int sclk_rate; 347 struct of_phandle_args args; 348 349 irq = platform_get_irq(pdev, 0); 350 if (irq < 0) { 351 dev_err(&pdev->dev, "failed to get interrupt resource\n"); 352 return irq; 353 } 354 355 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 356 if (!rtc) 357 return -ENOMEM; 358 359 spin_lock_init(&rtc->lock); 360 rtc->irq = irq; 361 362 /* platform setup code should have handled this; sigh */ 363 if (!device_can_wakeup(&pdev->dev)) 364 device_init_wakeup(&pdev->dev, 1); 365 366 platform_set_drvdata(pdev, rtc); 367 368 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 369 rtc->rtt = devm_ioremap_resource(&pdev->dev, r); 370 if (IS_ERR(rtc->rtt)) 371 return PTR_ERR(rtc->rtt); 372 373 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 374 "atmel,rtt-rtc-time-reg", 1, 0, 375 &args); 376 if (ret) 377 return ret; 378 379 rtc->gpbr = syscon_node_to_regmap(args.np); 380 rtc->gpbr_offset = args.args[0]; 381 if (IS_ERR(rtc->gpbr)) { 382 dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n"); 383 return -ENOMEM; 384 } 385 386 rtc->sclk = devm_clk_get(&pdev->dev, NULL); 387 if (IS_ERR(rtc->sclk)) 388 return PTR_ERR(rtc->sclk); 389 390 ret = clk_prepare_enable(rtc->sclk); 391 if (ret) { 392 dev_err(&pdev->dev, "Could not enable slow clock\n"); 393 return ret; 394 } 395 396 sclk_rate = clk_get_rate(rtc->sclk); 397 if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) { 398 dev_err(&pdev->dev, "Invalid slow clock rate\n"); 399 ret = -EINVAL; 400 goto err_clk; 401 } 402 403 mr = rtt_readl(rtc, MR); 404 405 /* unless RTT is counting at 1 Hz, re-initialize it */ 406 if ((mr & AT91_RTT_RTPRES) != sclk_rate) { 407 mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES); 408 gpbr_writel(rtc, 0); 409 } 410 411 /* disable all interrupts (same as on shutdown path) */ 412 mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 413 rtt_writel(rtc, MR, mr); 414 415 rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev); 416 if (IS_ERR(rtc->rtcdev)) { 417 ret = PTR_ERR(rtc->rtcdev); 418 goto err_clk; 419 } 420 421 rtc->rtcdev->ops = &at91_rtc_ops; 422 rtc->rtcdev->range_max = U32_MAX; 423 424 /* register irq handler after we know what name we'll use */ 425 ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt, 426 IRQF_SHARED | IRQF_COND_SUSPEND, 427 dev_name(&rtc->rtcdev->dev), rtc); 428 if (ret) { 429 dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq); 430 goto err_clk; 431 } 432 433 /* NOTE: sam9260 rev A silicon has a ROM bug which resets the 434 * RTT on at least some reboots. If you have that chip, you must 435 * initialize the time from some external source like a GPS, wall 436 * clock, discrete RTC, etc 437 */ 438 439 if (gpbr_readl(rtc) == 0) 440 dev_warn(&pdev->dev, "%s: SET TIME!\n", 441 dev_name(&rtc->rtcdev->dev)); 442 443 return rtc_register_device(rtc->rtcdev); 444 445 err_clk: 446 clk_disable_unprepare(rtc->sclk); 447 448 return ret; 449 } 450 451 /* 452 * Disable and remove the RTC driver 453 */ 454 static int at91_rtc_remove(struct platform_device *pdev) 455 { 456 struct sam9_rtc *rtc = platform_get_drvdata(pdev); 457 u32 mr = rtt_readl(rtc, MR); 458 459 /* disable all interrupts */ 460 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 461 462 clk_disable_unprepare(rtc->sclk); 463 464 return 0; 465 } 466 467 static void at91_rtc_shutdown(struct platform_device *pdev) 468 { 469 struct sam9_rtc *rtc = platform_get_drvdata(pdev); 470 u32 mr = rtt_readl(rtc, MR); 471 472 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 473 rtt_writel(rtc, MR, mr & ~rtc->imr); 474 } 475 476 #ifdef CONFIG_PM_SLEEP 477 478 /* AT91SAM9 RTC Power management control */ 479 480 static int at91_rtc_suspend(struct device *dev) 481 { 482 struct sam9_rtc *rtc = dev_get_drvdata(dev); 483 u32 mr = rtt_readl(rtc, MR); 484 485 /* 486 * This IRQ is shared with DBGU and other hardware which isn't 487 * necessarily a wakeup event source. 488 */ 489 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 490 if (rtc->imr) { 491 if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) { 492 unsigned long flags; 493 494 enable_irq_wake(rtc->irq); 495 spin_lock_irqsave(&rtc->lock, flags); 496 rtc->suspended = true; 497 spin_unlock_irqrestore(&rtc->lock, flags); 498 /* don't let RTTINC cause wakeups */ 499 if (mr & AT91_RTT_RTTINCIEN) 500 rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN); 501 } else 502 rtt_writel(rtc, MR, mr & ~rtc->imr); 503 } 504 505 return 0; 506 } 507 508 static int at91_rtc_resume(struct device *dev) 509 { 510 struct sam9_rtc *rtc = dev_get_drvdata(dev); 511 u32 mr; 512 513 if (rtc->imr) { 514 unsigned long flags; 515 516 if (device_may_wakeup(dev)) 517 disable_irq_wake(rtc->irq); 518 mr = rtt_readl(rtc, MR); 519 rtt_writel(rtc, MR, mr | rtc->imr); 520 521 spin_lock_irqsave(&rtc->lock, flags); 522 rtc->suspended = false; 523 at91_rtc_cache_events(rtc); 524 at91_rtc_flush_events(rtc); 525 spin_unlock_irqrestore(&rtc->lock, flags); 526 } 527 528 return 0; 529 } 530 #endif 531 532 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume); 533 534 static const struct of_device_id at91_rtc_dt_ids[] = { 535 { .compatible = "atmel,at91sam9260-rtt" }, 536 { /* sentinel */ } 537 }; 538 MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids); 539 540 static struct platform_driver at91_rtc_driver = { 541 .probe = at91_rtc_probe, 542 .remove = at91_rtc_remove, 543 .shutdown = at91_rtc_shutdown, 544 .driver = { 545 .name = "rtc-at91sam9", 546 .pm = &at91_rtc_pm_ops, 547 .of_match_table = of_match_ptr(at91_rtc_dt_ids), 548 }, 549 }; 550 551 module_platform_driver(at91_rtc_driver); 552 553 MODULE_AUTHOR("Michel Benoit"); 554 MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x"); 555 MODULE_LICENSE("GPL"); 556