1 /* 2 * "RTT as Real Time Clock" driver for AT91SAM9 SoC family 3 * 4 * (C) 2007 Michel Benoit 5 * 6 * Based on rtc-at91rm9200.c by Rick Bronson 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/interrupt.h> 16 #include <linux/ioctl.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/rtc.h> 25 #include <linux/slab.h> 26 #include <linux/suspend.h> 27 #include <linux/time.h> 28 29 /* 30 * This driver uses two configurable hardware resources that live in the 31 * AT91SAM9 backup power domain (intended to be powered at all times) 32 * to implement the Real Time Clock interfaces 33 * 34 * - A "Real-time Timer" (RTT) counts up in seconds from a base time. 35 * We can't assign the counter value (CRTV) ... but we can reset it. 36 * 37 * - One of the "General Purpose Backup Registers" (GPBRs) holds the 38 * base time, normally an offset from the beginning of the POSIX 39 * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the 40 * local timezone's offset. 41 * 42 * The RTC's value is the RTT counter plus that offset. The RTC's alarm 43 * is likewise a base (ALMV) plus that offset. 44 * 45 * Not all RTTs will be used as RTCs; some systems have multiple RTTs to 46 * choose from, or a "real" RTC module. All systems have multiple GPBR 47 * registers available, likewise usable for more than "RTC" support. 48 */ 49 50 #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ 51 #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ 52 #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ 53 #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ 54 #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ 55 56 #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ 57 #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ 58 59 #define AT91_RTT_VR 0x08 /* Real-time Value Register */ 60 #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ 61 62 #define AT91_RTT_SR 0x0c /* Real-time Status Register */ 63 #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ 64 #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ 65 66 /* 67 * We store ALARM_DISABLED in ALMV to record that no alarm is set. 68 * It's also the reset value for that field. 69 */ 70 #define ALARM_DISABLED ((u32)~0) 71 72 73 struct sam9_rtc { 74 void __iomem *rtt; 75 struct rtc_device *rtcdev; 76 u32 imr; 77 struct regmap *gpbr; 78 unsigned int gpbr_offset; 79 int irq; 80 struct clk *sclk; 81 bool suspended; 82 unsigned long events; 83 spinlock_t lock; 84 }; 85 86 #define rtt_readl(rtc, field) \ 87 readl((rtc)->rtt + AT91_RTT_ ## field) 88 #define rtt_writel(rtc, field, val) \ 89 writel((val), (rtc)->rtt + AT91_RTT_ ## field) 90 91 static inline unsigned int gpbr_readl(struct sam9_rtc *rtc) 92 { 93 unsigned int val; 94 95 regmap_read(rtc->gpbr, rtc->gpbr_offset, &val); 96 97 return val; 98 } 99 100 static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val) 101 { 102 regmap_write(rtc->gpbr, rtc->gpbr_offset, val); 103 } 104 105 /* 106 * Read current time and date in RTC 107 */ 108 static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) 109 { 110 struct sam9_rtc *rtc = dev_get_drvdata(dev); 111 u32 secs, secs2; 112 u32 offset; 113 114 /* read current time offset */ 115 offset = gpbr_readl(rtc); 116 if (offset == 0) 117 return -EILSEQ; 118 119 /* reread the counter to help sync the two clock domains */ 120 secs = rtt_readl(rtc, VR); 121 secs2 = rtt_readl(rtc, VR); 122 if (secs != secs2) 123 secs = rtt_readl(rtc, VR); 124 125 rtc_time_to_tm(offset + secs, tm); 126 127 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 128 129 return 0; 130 } 131 132 /* 133 * Set current time and date in RTC 134 */ 135 static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) 136 { 137 struct sam9_rtc *rtc = dev_get_drvdata(dev); 138 int err; 139 u32 offset, alarm, mr; 140 unsigned long secs; 141 142 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 143 144 err = rtc_tm_to_time(tm, &secs); 145 if (err != 0) 146 return err; 147 148 mr = rtt_readl(rtc, MR); 149 150 /* disable interrupts */ 151 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 152 153 /* read current time offset */ 154 offset = gpbr_readl(rtc); 155 156 /* store the new base time in a battery backup register */ 157 secs += 1; 158 gpbr_writel(rtc, secs); 159 160 /* adjust the alarm time for the new base */ 161 alarm = rtt_readl(rtc, AR); 162 if (alarm != ALARM_DISABLED) { 163 if (offset > secs) { 164 /* time jumped backwards, increase time until alarm */ 165 alarm += (offset - secs); 166 } else if ((alarm + offset) > secs) { 167 /* time jumped forwards, decrease time until alarm */ 168 alarm -= (secs - offset); 169 } else { 170 /* time jumped past the alarm, disable alarm */ 171 alarm = ALARM_DISABLED; 172 mr &= ~AT91_RTT_ALMIEN; 173 } 174 rtt_writel(rtc, AR, alarm); 175 } 176 177 /* reset the timer, and re-enable interrupts */ 178 rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST); 179 180 return 0; 181 } 182 183 static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) 184 { 185 struct sam9_rtc *rtc = dev_get_drvdata(dev); 186 struct rtc_time *tm = &alrm->time; 187 u32 alarm = rtt_readl(rtc, AR); 188 u32 offset; 189 190 offset = gpbr_readl(rtc); 191 if (offset == 0) 192 return -EILSEQ; 193 194 memset(alrm, 0, sizeof(*alrm)); 195 if (alarm != ALARM_DISABLED && offset != 0) { 196 rtc_time_to_tm(offset + alarm, tm); 197 198 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 199 200 if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN) 201 alrm->enabled = 1; 202 } 203 204 return 0; 205 } 206 207 static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) 208 { 209 struct sam9_rtc *rtc = dev_get_drvdata(dev); 210 struct rtc_time *tm = &alrm->time; 211 unsigned long secs; 212 u32 offset; 213 u32 mr; 214 int err; 215 216 err = rtc_tm_to_time(tm, &secs); 217 if (err != 0) 218 return err; 219 220 offset = gpbr_readl(rtc); 221 if (offset == 0) { 222 /* time is not set */ 223 return -EILSEQ; 224 } 225 mr = rtt_readl(rtc, MR); 226 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); 227 228 /* alarm in the past? finish and leave disabled */ 229 if (secs <= offset) { 230 rtt_writel(rtc, AR, ALARM_DISABLED); 231 return 0; 232 } 233 234 /* else set alarm and maybe enable it */ 235 rtt_writel(rtc, AR, secs - offset); 236 if (alrm->enabled) 237 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); 238 239 dev_dbg(dev, "%s: %ptR\n", __func__, tm); 240 241 return 0; 242 } 243 244 static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 245 { 246 struct sam9_rtc *rtc = dev_get_drvdata(dev); 247 u32 mr = rtt_readl(rtc, MR); 248 249 dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr); 250 if (enabled) 251 rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); 252 else 253 rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); 254 return 0; 255 } 256 257 /* 258 * Provide additional RTC information in /proc/driver/rtc 259 */ 260 static int at91_rtc_proc(struct device *dev, struct seq_file *seq) 261 { 262 struct sam9_rtc *rtc = dev_get_drvdata(dev); 263 u32 mr = rtt_readl(rtc, MR); 264 265 seq_printf(seq, "update_IRQ\t: %s\n", 266 (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no"); 267 return 0; 268 } 269 270 static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc) 271 { 272 u32 sr, mr; 273 274 /* Shared interrupt may be for another device. Note: reading 275 * SR clears it, so we must only read it in this irq handler! 276 */ 277 mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 278 sr = rtt_readl(rtc, SR) & (mr >> 16); 279 if (!sr) 280 return IRQ_NONE; 281 282 /* alarm status */ 283 if (sr & AT91_RTT_ALMS) 284 rtc->events |= (RTC_AF | RTC_IRQF); 285 286 /* timer update/increment */ 287 if (sr & AT91_RTT_RTTINC) 288 rtc->events |= (RTC_UF | RTC_IRQF); 289 290 return IRQ_HANDLED; 291 } 292 293 static void at91_rtc_flush_events(struct sam9_rtc *rtc) 294 { 295 if (!rtc->events) 296 return; 297 298 rtc_update_irq(rtc->rtcdev, 1, rtc->events); 299 rtc->events = 0; 300 301 pr_debug("%s: num=%ld, events=0x%02lx\n", __func__, 302 rtc->events >> 8, rtc->events & 0x000000FF); 303 } 304 305 /* 306 * IRQ handler for the RTC 307 */ 308 static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc) 309 { 310 struct sam9_rtc *rtc = _rtc; 311 int ret; 312 313 spin_lock(&rtc->lock); 314 315 ret = at91_rtc_cache_events(rtc); 316 317 /* We're called in suspended state */ 318 if (rtc->suspended) { 319 /* Mask irqs coming from this peripheral */ 320 rtt_writel(rtc, MR, 321 rtt_readl(rtc, MR) & 322 ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 323 /* Trigger a system wakeup */ 324 pm_system_wakeup(); 325 } else { 326 at91_rtc_flush_events(rtc); 327 } 328 329 spin_unlock(&rtc->lock); 330 331 return ret; 332 } 333 334 static const struct rtc_class_ops at91_rtc_ops = { 335 .read_time = at91_rtc_readtime, 336 .set_time = at91_rtc_settime, 337 .read_alarm = at91_rtc_readalarm, 338 .set_alarm = at91_rtc_setalarm, 339 .proc = at91_rtc_proc, 340 .alarm_irq_enable = at91_rtc_alarm_irq_enable, 341 }; 342 343 /* 344 * Initialize and install RTC driver 345 */ 346 static int at91_rtc_probe(struct platform_device *pdev) 347 { 348 struct resource *r; 349 struct sam9_rtc *rtc; 350 int ret, irq; 351 u32 mr; 352 unsigned int sclk_rate; 353 struct of_phandle_args args; 354 355 irq = platform_get_irq(pdev, 0); 356 if (irq < 0) { 357 dev_err(&pdev->dev, "failed to get interrupt resource\n"); 358 return irq; 359 } 360 361 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 362 if (!rtc) 363 return -ENOMEM; 364 365 spin_lock_init(&rtc->lock); 366 rtc->irq = irq; 367 368 /* platform setup code should have handled this; sigh */ 369 if (!device_can_wakeup(&pdev->dev)) 370 device_init_wakeup(&pdev->dev, 1); 371 372 platform_set_drvdata(pdev, rtc); 373 374 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 375 rtc->rtt = devm_ioremap_resource(&pdev->dev, r); 376 if (IS_ERR(rtc->rtt)) 377 return PTR_ERR(rtc->rtt); 378 379 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 380 "atmel,rtt-rtc-time-reg", 1, 0, 381 &args); 382 if (ret) 383 return ret; 384 385 rtc->gpbr = syscon_node_to_regmap(args.np); 386 rtc->gpbr_offset = args.args[0]; 387 if (IS_ERR(rtc->gpbr)) { 388 dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n"); 389 return -ENOMEM; 390 } 391 392 rtc->sclk = devm_clk_get(&pdev->dev, NULL); 393 if (IS_ERR(rtc->sclk)) 394 return PTR_ERR(rtc->sclk); 395 396 ret = clk_prepare_enable(rtc->sclk); 397 if (ret) { 398 dev_err(&pdev->dev, "Could not enable slow clock\n"); 399 return ret; 400 } 401 402 sclk_rate = clk_get_rate(rtc->sclk); 403 if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) { 404 dev_err(&pdev->dev, "Invalid slow clock rate\n"); 405 ret = -EINVAL; 406 goto err_clk; 407 } 408 409 mr = rtt_readl(rtc, MR); 410 411 /* unless RTT is counting at 1 Hz, re-initialize it */ 412 if ((mr & AT91_RTT_RTPRES) != sclk_rate) { 413 mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES); 414 gpbr_writel(rtc, 0); 415 } 416 417 /* disable all interrupts (same as on shutdown path) */ 418 mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 419 rtt_writel(rtc, MR, mr); 420 421 rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name, 422 &at91_rtc_ops, THIS_MODULE); 423 if (IS_ERR(rtc->rtcdev)) { 424 ret = PTR_ERR(rtc->rtcdev); 425 goto err_clk; 426 } 427 428 /* register irq handler after we know what name we'll use */ 429 ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt, 430 IRQF_SHARED | IRQF_COND_SUSPEND, 431 dev_name(&rtc->rtcdev->dev), rtc); 432 if (ret) { 433 dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq); 434 goto err_clk; 435 } 436 437 /* NOTE: sam9260 rev A silicon has a ROM bug which resets the 438 * RTT on at least some reboots. If you have that chip, you must 439 * initialize the time from some external source like a GPS, wall 440 * clock, discrete RTC, etc 441 */ 442 443 if (gpbr_readl(rtc) == 0) 444 dev_warn(&pdev->dev, "%s: SET TIME!\n", 445 dev_name(&rtc->rtcdev->dev)); 446 447 return 0; 448 449 err_clk: 450 clk_disable_unprepare(rtc->sclk); 451 452 return ret; 453 } 454 455 /* 456 * Disable and remove the RTC driver 457 */ 458 static int at91_rtc_remove(struct platform_device *pdev) 459 { 460 struct sam9_rtc *rtc = platform_get_drvdata(pdev); 461 u32 mr = rtt_readl(rtc, MR); 462 463 /* disable all interrupts */ 464 rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); 465 466 clk_disable_unprepare(rtc->sclk); 467 468 return 0; 469 } 470 471 static void at91_rtc_shutdown(struct platform_device *pdev) 472 { 473 struct sam9_rtc *rtc = platform_get_drvdata(pdev); 474 u32 mr = rtt_readl(rtc, MR); 475 476 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 477 rtt_writel(rtc, MR, mr & ~rtc->imr); 478 } 479 480 #ifdef CONFIG_PM_SLEEP 481 482 /* AT91SAM9 RTC Power management control */ 483 484 static int at91_rtc_suspend(struct device *dev) 485 { 486 struct sam9_rtc *rtc = dev_get_drvdata(dev); 487 u32 mr = rtt_readl(rtc, MR); 488 489 /* 490 * This IRQ is shared with DBGU and other hardware which isn't 491 * necessarily a wakeup event source. 492 */ 493 rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); 494 if (rtc->imr) { 495 if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) { 496 unsigned long flags; 497 498 enable_irq_wake(rtc->irq); 499 spin_lock_irqsave(&rtc->lock, flags); 500 rtc->suspended = true; 501 spin_unlock_irqrestore(&rtc->lock, flags); 502 /* don't let RTTINC cause wakeups */ 503 if (mr & AT91_RTT_RTTINCIEN) 504 rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN); 505 } else 506 rtt_writel(rtc, MR, mr & ~rtc->imr); 507 } 508 509 return 0; 510 } 511 512 static int at91_rtc_resume(struct device *dev) 513 { 514 struct sam9_rtc *rtc = dev_get_drvdata(dev); 515 u32 mr; 516 517 if (rtc->imr) { 518 unsigned long flags; 519 520 if (device_may_wakeup(dev)) 521 disable_irq_wake(rtc->irq); 522 mr = rtt_readl(rtc, MR); 523 rtt_writel(rtc, MR, mr | rtc->imr); 524 525 spin_lock_irqsave(&rtc->lock, flags); 526 rtc->suspended = false; 527 at91_rtc_cache_events(rtc); 528 at91_rtc_flush_events(rtc); 529 spin_unlock_irqrestore(&rtc->lock, flags); 530 } 531 532 return 0; 533 } 534 #endif 535 536 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume); 537 538 static const struct of_device_id at91_rtc_dt_ids[] = { 539 { .compatible = "atmel,at91sam9260-rtt" }, 540 { /* sentinel */ } 541 }; 542 MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids); 543 544 static struct platform_driver at91_rtc_driver = { 545 .probe = at91_rtc_probe, 546 .remove = at91_rtc_remove, 547 .shutdown = at91_rtc_shutdown, 548 .driver = { 549 .name = "rtc-at91sam9", 550 .pm = &at91_rtc_pm_ops, 551 .of_match_table = of_match_ptr(at91_rtc_dt_ids), 552 }, 553 }; 554 555 module_platform_driver(at91_rtc_driver); 556 557 MODULE_AUTHOR("Michel Benoit"); 558 MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x"); 559 MODULE_LICENSE("GPL"); 560