1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <[email protected]> 9 */ 10 11 #include <asm/amd_nb.h> 12 #include <linux/debugfs.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 #include <linux/power_supply.h> 18 #include "pmf.h" 19 20 /* PMF-SMU communication registers */ 21 #define AMD_PMF_REGISTER_MESSAGE 0xA18 22 #define AMD_PMF_REGISTER_RESPONSE 0xA78 23 #define AMD_PMF_REGISTER_ARGUMENT 0xA58 24 25 /* Base address of SMU for mapping physical address to virtual address */ 26 #define AMD_PMF_MAPPING_SIZE 0x01000 27 #define AMD_PMF_BASE_ADDR_OFFSET 0x10000 28 #define AMD_PMF_BASE_ADDR_LO 0x13B102E8 29 #define AMD_PMF_BASE_ADDR_HI 0x13B102EC 30 #define AMD_PMF_BASE_ADDR_LO_MASK GENMASK(15, 0) 31 #define AMD_PMF_BASE_ADDR_HI_MASK GENMASK(31, 20) 32 33 /* SMU Response Codes */ 34 #define AMD_PMF_RESULT_OK 0x01 35 #define AMD_PMF_RESULT_CMD_REJECT_BUSY 0xFC 36 #define AMD_PMF_RESULT_CMD_REJECT_PREREQ 0xFD 37 #define AMD_PMF_RESULT_CMD_UNKNOWN 0xFE 38 #define AMD_PMF_RESULT_FAILED 0xFF 39 40 /* List of supported CPU ids */ 41 #define AMD_CPU_ID_RMB 0x14b5 42 #define AMD_CPU_ID_PS 0x14e8 43 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 44 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 45 46 #define PMF_MSG_DELAY_MIN_US 50 47 #define RESPONSE_REGISTER_LOOP_MAX 20000 48 49 #define DELAY_MIN_US 2000 50 #define DELAY_MAX_US 3000 51 52 /* override Metrics Table sample size time (in ms) */ 53 static int metrics_table_loop_ms = 1000; 54 module_param(metrics_table_loop_ms, int, 0644); 55 MODULE_PARM_DESC(metrics_table_loop_ms, "Metrics Table sample size time (default = 1000ms)"); 56 57 /* Force load on supported older platforms */ 58 static bool force_load; 59 module_param(force_load, bool, 0444); 60 MODULE_PARM_DESC(force_load, "Force load this driver on supported older platforms (experimental)"); 61 62 static int amd_pmf_pwr_src_notify_call(struct notifier_block *nb, unsigned long event, void *data) 63 { 64 struct amd_pmf_dev *pmf = container_of(nb, struct amd_pmf_dev, pwr_src_notifier); 65 66 if (event != PSY_EVENT_PROP_CHANGED) 67 return NOTIFY_OK; 68 69 if (is_apmf_func_supported(pmf, APMF_FUNC_AUTO_MODE) || 70 is_apmf_func_supported(pmf, APMF_FUNC_DYN_SLIDER_DC) || 71 is_apmf_func_supported(pmf, APMF_FUNC_DYN_SLIDER_AC)) { 72 if ((pmf->amt_enabled || pmf->cnqf_enabled) && is_pprof_balanced(pmf)) 73 return NOTIFY_DONE; 74 } 75 76 if (is_apmf_func_supported(pmf, APMF_FUNC_STATIC_SLIDER_GRANULAR)) 77 amd_pmf_set_sps_power_limits(pmf); 78 79 if (is_apmf_func_supported(pmf, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) 80 amd_pmf_power_slider_update_event(pmf); 81 82 return NOTIFY_OK; 83 } 84 85 static int current_power_limits_show(struct seq_file *seq, void *unused) 86 { 87 struct amd_pmf_dev *dev = seq->private; 88 struct amd_pmf_static_slider_granular table; 89 int mode, src = 0; 90 91 mode = amd_pmf_get_pprof_modes(dev); 92 if (mode < 0) 93 return mode; 94 95 src = amd_pmf_get_power_source(); 96 amd_pmf_update_slider(dev, SLIDER_OP_GET, mode, &table); 97 seq_printf(seq, "spl:%u fppt:%u sppt:%u sppt_apu_only:%u stt_min:%u stt[APU]:%u stt[HS2]: %u\n", 98 table.prop[src][mode].spl, 99 table.prop[src][mode].fppt, 100 table.prop[src][mode].sppt, 101 table.prop[src][mode].sppt_apu_only, 102 table.prop[src][mode].stt_min, 103 table.prop[src][mode].stt_skin_temp[STT_TEMP_APU], 104 table.prop[src][mode].stt_skin_temp[STT_TEMP_HS2]); 105 return 0; 106 } 107 DEFINE_SHOW_ATTRIBUTE(current_power_limits); 108 109 static void amd_pmf_dbgfs_unregister(struct amd_pmf_dev *dev) 110 { 111 debugfs_remove_recursive(dev->dbgfs_dir); 112 } 113 114 static void amd_pmf_dbgfs_register(struct amd_pmf_dev *dev) 115 { 116 dev->dbgfs_dir = debugfs_create_dir("amd_pmf", NULL); 117 if (dev->pmf_if_version == PMF_IF_V1) 118 debugfs_create_file("current_power_limits", 0644, dev->dbgfs_dir, dev, 119 ¤t_power_limits_fops); 120 } 121 122 int amd_pmf_get_power_source(void) 123 { 124 if (power_supply_is_system_supplied() > 0) 125 return POWER_SOURCE_AC; 126 else 127 return POWER_SOURCE_DC; 128 } 129 130 static void amd_pmf_get_metrics(struct work_struct *work) 131 { 132 struct amd_pmf_dev *dev = container_of(work, struct amd_pmf_dev, work_buffer.work); 133 ktime_t time_elapsed_ms; 134 int socket_power; 135 136 mutex_lock(&dev->update_mutex); 137 /* Transfer table contents */ 138 memset(dev->buf, 0, sizeof(dev->m_table)); 139 amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); 140 memcpy(&dev->m_table, dev->buf, sizeof(dev->m_table)); 141 142 time_elapsed_ms = ktime_to_ms(ktime_get()) - dev->start_time; 143 /* Calculate the avg SoC power consumption */ 144 socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; 145 146 if (dev->amt_enabled) { 147 /* Apply the Auto Mode transition */ 148 amd_pmf_trans_automode(dev, socket_power, time_elapsed_ms); 149 } 150 151 if (dev->cnqf_enabled) { 152 /* Apply the CnQF transition */ 153 amd_pmf_trans_cnqf(dev, socket_power, time_elapsed_ms); 154 } 155 156 dev->start_time = ktime_to_ms(ktime_get()); 157 schedule_delayed_work(&dev->work_buffer, msecs_to_jiffies(metrics_table_loop_ms)); 158 mutex_unlock(&dev->update_mutex); 159 } 160 161 static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset) 162 { 163 return ioread32(dev->regbase + reg_offset); 164 } 165 166 static inline void amd_pmf_reg_write(struct amd_pmf_dev *dev, int reg_offset, u32 val) 167 { 168 iowrite32(val, dev->regbase + reg_offset); 169 } 170 171 static void __maybe_unused amd_pmf_dump_registers(struct amd_pmf_dev *dev) 172 { 173 u32 value; 174 175 value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_RESPONSE); 176 dev_dbg(dev->dev, "AMD_PMF_REGISTER_RESPONSE:%x\n", value); 177 178 value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_ARGUMENT); 179 dev_dbg(dev->dev, "AMD_PMF_REGISTER_ARGUMENT:%d\n", value); 180 181 value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_MESSAGE); 182 dev_dbg(dev->dev, "AMD_PMF_REGISTER_MESSAGE:%x\n", value); 183 } 184 185 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data) 186 { 187 int rc; 188 u32 val; 189 190 mutex_lock(&dev->lock); 191 192 /* Wait until we get a valid response */ 193 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, 194 val, val != 0, PMF_MSG_DELAY_MIN_US, 195 PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 196 if (rc) { 197 dev_err(dev->dev, "failed to talk to SMU\n"); 198 goto out_unlock; 199 } 200 201 /* Write zero to response register */ 202 amd_pmf_reg_write(dev, AMD_PMF_REGISTER_RESPONSE, 0); 203 204 /* Write argument into argument register */ 205 amd_pmf_reg_write(dev, AMD_PMF_REGISTER_ARGUMENT, arg); 206 207 /* Write message ID to message ID register */ 208 amd_pmf_reg_write(dev, AMD_PMF_REGISTER_MESSAGE, message); 209 210 /* Wait until we get a valid response */ 211 rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, 212 val, val != 0, PMF_MSG_DELAY_MIN_US, 213 PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 214 if (rc) { 215 dev_err(dev->dev, "SMU response timed out\n"); 216 goto out_unlock; 217 } 218 219 switch (val) { 220 case AMD_PMF_RESULT_OK: 221 if (get) { 222 /* PMFW may take longer time to return back the data */ 223 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 224 *data = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_ARGUMENT); 225 } 226 break; 227 case AMD_PMF_RESULT_CMD_REJECT_BUSY: 228 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 229 rc = -EBUSY; 230 goto out_unlock; 231 case AMD_PMF_RESULT_CMD_UNKNOWN: 232 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 233 rc = -EINVAL; 234 goto out_unlock; 235 case AMD_PMF_RESULT_CMD_REJECT_PREREQ: 236 case AMD_PMF_RESULT_FAILED: 237 default: 238 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 239 rc = -EIO; 240 goto out_unlock; 241 } 242 243 out_unlock: 244 mutex_unlock(&dev->lock); 245 amd_pmf_dump_registers(dev); 246 return rc; 247 } 248 249 static const struct pci_device_id pmf_pci_ids[] = { 250 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RMB) }, 251 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, 252 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, 253 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) }, 254 { } 255 }; 256 257 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer) 258 { 259 u64 phys_addr; 260 u32 hi, low; 261 262 /* Get Metrics Table Address */ 263 if (alloc_buffer) { 264 dev->buf = kzalloc(sizeof(dev->m_table), GFP_KERNEL); 265 if (!dev->buf) 266 return -ENOMEM; 267 } 268 269 phys_addr = virt_to_phys(dev->buf); 270 hi = phys_addr >> 32; 271 low = phys_addr & GENMASK(31, 0); 272 273 amd_pmf_send_cmd(dev, SET_DRAM_ADDR_HIGH, 0, hi, NULL); 274 amd_pmf_send_cmd(dev, SET_DRAM_ADDR_LOW, 0, low, NULL); 275 276 return 0; 277 } 278 279 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev) 280 { 281 int ret; 282 283 INIT_DELAYED_WORK(&dev->work_buffer, amd_pmf_get_metrics); 284 285 ret = amd_pmf_set_dram_addr(dev, true); 286 if (ret) 287 return ret; 288 289 /* 290 * Start collecting the metrics data after a small delay 291 * or else, we might end up getting stale values from PMFW. 292 */ 293 schedule_delayed_work(&dev->work_buffer, msecs_to_jiffies(metrics_table_loop_ms * 3)); 294 295 return 0; 296 } 297 298 static int amd_pmf_suspend_handler(struct device *dev) 299 { 300 struct amd_pmf_dev *pdev = dev_get_drvdata(dev); 301 302 if (pdev->smart_pc_enabled) 303 cancel_delayed_work_sync(&pdev->pb_work); 304 305 if (is_apmf_func_supported(pdev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 306 amd_pmf_notify_sbios_heartbeat_event_v2(pdev, ON_SUSPEND); 307 308 return 0; 309 } 310 311 static int amd_pmf_resume_handler(struct device *dev) 312 { 313 struct amd_pmf_dev *pdev = dev_get_drvdata(dev); 314 int ret; 315 316 if (pdev->buf) { 317 ret = amd_pmf_set_dram_addr(pdev, false); 318 if (ret) 319 return ret; 320 } 321 322 if (is_apmf_func_supported(pdev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 323 amd_pmf_notify_sbios_heartbeat_event_v2(pdev, ON_RESUME); 324 325 if (pdev->smart_pc_enabled) 326 schedule_delayed_work(&pdev->pb_work, msecs_to_jiffies(2000)); 327 328 return 0; 329 } 330 331 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmf_pm, amd_pmf_suspend_handler, amd_pmf_resume_handler); 332 333 static void amd_pmf_init_features(struct amd_pmf_dev *dev) 334 { 335 int ret; 336 337 /* Enable Static Slider */ 338 if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) || 339 is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { 340 amd_pmf_init_sps(dev); 341 dev->pwr_src_notifier.notifier_call = amd_pmf_pwr_src_notify_call; 342 power_supply_reg_notifier(&dev->pwr_src_notifier); 343 dev_dbg(dev->dev, "SPS enabled and Platform Profiles registered\n"); 344 } 345 346 amd_pmf_init_smart_pc(dev); 347 if (dev->smart_pc_enabled) { 348 dev_dbg(dev->dev, "Smart PC Solution Enabled\n"); 349 /* If Smart PC is enabled, no need to check for other features */ 350 return; 351 } 352 353 if (is_apmf_func_supported(dev, APMF_FUNC_AUTO_MODE)) { 354 amd_pmf_init_auto_mode(dev); 355 dev_dbg(dev->dev, "Auto Mode Init done\n"); 356 } else if (is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_AC) || 357 is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_DC)) { 358 ret = amd_pmf_init_cnqf(dev); 359 if (ret) 360 dev_warn(dev->dev, "CnQF Init failed\n"); 361 } 362 } 363 364 static void amd_pmf_deinit_features(struct amd_pmf_dev *dev) 365 { 366 if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) || 367 is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { 368 power_supply_unreg_notifier(&dev->pwr_src_notifier); 369 amd_pmf_deinit_sps(dev); 370 } 371 372 if (dev->smart_pc_enabled) { 373 amd_pmf_deinit_smart_pc(dev); 374 } else if (is_apmf_func_supported(dev, APMF_FUNC_AUTO_MODE)) { 375 amd_pmf_deinit_auto_mode(dev); 376 } else if (is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_AC) || 377 is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_DC)) { 378 amd_pmf_deinit_cnqf(dev); 379 } 380 } 381 382 static const struct acpi_device_id amd_pmf_acpi_ids[] = { 383 {"AMDI0100", 0x100}, 384 {"AMDI0102", 0}, 385 {"AMDI0103", 0}, 386 {"AMDI0105", 0}, 387 {"AMDI0107", 0}, 388 { } 389 }; 390 MODULE_DEVICE_TABLE(acpi, amd_pmf_acpi_ids); 391 392 static int amd_pmf_probe(struct platform_device *pdev) 393 { 394 const struct acpi_device_id *id; 395 struct amd_pmf_dev *dev; 396 struct pci_dev *rdev; 397 u32 base_addr_lo; 398 u32 base_addr_hi; 399 u64 base_addr; 400 u32 val; 401 int err; 402 403 id = acpi_match_device(amd_pmf_acpi_ids, &pdev->dev); 404 if (!id) 405 return -ENODEV; 406 407 if (id->driver_data == 0x100 && !force_load) 408 return -ENODEV; 409 410 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 411 if (!dev) 412 return -ENOMEM; 413 414 dev->dev = &pdev->dev; 415 416 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 417 if (!rdev || !pci_match_id(pmf_pci_ids, rdev)) { 418 pci_dev_put(rdev); 419 return -ENODEV; 420 } 421 422 dev->cpu_id = rdev->device; 423 424 err = amd_smn_read(0, AMD_PMF_BASE_ADDR_LO, &val); 425 if (err) { 426 dev_err(dev->dev, "error in reading from 0x%x\n", AMD_PMF_BASE_ADDR_LO); 427 pci_dev_put(rdev); 428 return pcibios_err_to_errno(err); 429 } 430 431 base_addr_lo = val & AMD_PMF_BASE_ADDR_HI_MASK; 432 433 err = amd_smn_read(0, AMD_PMF_BASE_ADDR_HI, &val); 434 if (err) { 435 dev_err(dev->dev, "error in reading from 0x%x\n", AMD_PMF_BASE_ADDR_HI); 436 pci_dev_put(rdev); 437 return pcibios_err_to_errno(err); 438 } 439 440 base_addr_hi = val & AMD_PMF_BASE_ADDR_LO_MASK; 441 pci_dev_put(rdev); 442 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 443 444 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMF_BASE_ADDR_OFFSET, 445 AMD_PMF_MAPPING_SIZE); 446 if (!dev->regbase) 447 return -ENOMEM; 448 449 mutex_init(&dev->lock); 450 mutex_init(&dev->update_mutex); 451 452 amd_pmf_quirks_init(dev); 453 apmf_acpi_init(dev); 454 platform_set_drvdata(pdev, dev); 455 amd_pmf_dbgfs_register(dev); 456 amd_pmf_init_features(dev); 457 apmf_install_handler(dev); 458 if (is_apmf_func_supported(dev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 459 amd_pmf_notify_sbios_heartbeat_event_v2(dev, ON_LOAD); 460 461 dev_info(dev->dev, "registered PMF device successfully\n"); 462 463 return 0; 464 } 465 466 static void amd_pmf_remove(struct platform_device *pdev) 467 { 468 struct amd_pmf_dev *dev = platform_get_drvdata(pdev); 469 470 amd_pmf_deinit_features(dev); 471 if (is_apmf_func_supported(dev, APMF_FUNC_SBIOS_HEARTBEAT_V2)) 472 amd_pmf_notify_sbios_heartbeat_event_v2(dev, ON_UNLOAD); 473 apmf_acpi_deinit(dev); 474 amd_pmf_dbgfs_unregister(dev); 475 mutex_destroy(&dev->lock); 476 mutex_destroy(&dev->update_mutex); 477 kfree(dev->buf); 478 } 479 480 static const struct attribute_group *amd_pmf_driver_groups[] = { 481 &cnqf_feature_attribute_group, 482 NULL, 483 }; 484 485 static struct platform_driver amd_pmf_driver = { 486 .driver = { 487 .name = "amd-pmf", 488 .acpi_match_table = amd_pmf_acpi_ids, 489 .dev_groups = amd_pmf_driver_groups, 490 .pm = pm_sleep_ptr(&amd_pmf_pm), 491 }, 492 .probe = amd_pmf_probe, 493 .remove_new = amd_pmf_remove, 494 }; 495 module_platform_driver(amd_pmf_driver); 496 497 MODULE_LICENSE("GPL"); 498 MODULE_DESCRIPTION("AMD Platform Management Framework Driver"); 499 MODULE_SOFTDEP("pre: amdtee"); 500