1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cherryview/Braswell pinctrl driver 4 * 5 * Copyright (C) 2014, 2020 Intel Corporation 6 * Author: Mika Westerberg <[email protected]> 7 * 8 * This driver is based on the original Cherryview GPIO driver by 9 * Ning Li <[email protected]> 10 * Alan Cox <[email protected]> 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/array_size.h> 15 #include <linux/dmi.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/seq_file.h> 20 #include <linux/types.h> 21 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include "pinctrl-intel.h" 29 30 #define CHV_INTSTAT 0x300 31 #define CHV_INTMASK 0x380 32 33 #define FAMILY_PAD_REGS_OFF 0x4400 34 #define FAMILY_PAD_REGS_SIZE 0x400 35 #define MAX_FAMILY_PAD_GPIO_NO 15 36 #define GPIO_REGS_SIZE 8 37 38 #define CHV_PADCTRL0 0x000 39 #define CHV_PADCTRL0_INTSEL_SHIFT 28 40 #define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) 41 #define CHV_PADCTRL0_TERM_UP BIT(23) 42 #define CHV_PADCTRL0_TERM_SHIFT 20 43 #define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) 44 #define CHV_PADCTRL0_TERM_20K 1 45 #define CHV_PADCTRL0_TERM_5K 2 46 #define CHV_PADCTRL0_TERM_1K 4 47 #define CHV_PADCTRL0_PMODE_SHIFT 16 48 #define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) 49 #define CHV_PADCTRL0_GPIOEN BIT(15) 50 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 51 #define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) 52 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 53 #define CHV_PADCTRL0_GPIOCFG_GPO 1 54 #define CHV_PADCTRL0_GPIOCFG_GPI 2 55 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 56 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 57 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 58 59 #define CHV_PADCTRL1 0x004 60 #define CHV_PADCTRL1_CFGLOCK BIT(31) 61 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 62 #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) 63 #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7) 64 #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) 65 #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) 66 #define CHV_PADCTRL1_ODEN BIT(3) 67 #define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) 68 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 69 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 70 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 71 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 72 73 struct intel_pad_context { 74 u32 padctrl0; 75 u32 padctrl1; 76 }; 77 78 #define CHV_INVALID_HWIRQ (~0U) 79 80 /** 81 * struct intel_community_context - community context for Cherryview 82 * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) 83 * @saved_intmask: Interrupt mask saved for system sleep 84 */ 85 struct intel_community_context { 86 unsigned int intr_lines[16]; 87 u32 saved_intmask; 88 }; 89 90 #define PINMODE_INVERT_OE BIT(15) 91 92 #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) 93 94 #define CHV_GPP(start, end) \ 95 { \ 96 .base = (start), \ 97 .size = (end) - (start) + 1, \ 98 } 99 100 #define CHV_COMMUNITY(g, i, a) \ 101 { \ 102 .gpps = (g), \ 103 .ngpps = ARRAY_SIZE(g), \ 104 .nirqs = (i), \ 105 .acpi_space_id = (a), \ 106 } 107 108 static const struct pinctrl_pin_desc southwest_pins[] = { 109 PINCTRL_PIN(0, "FST_SPI_D2"), 110 PINCTRL_PIN(1, "FST_SPI_D0"), 111 PINCTRL_PIN(2, "FST_SPI_CLK"), 112 PINCTRL_PIN(3, "FST_SPI_D3"), 113 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 114 PINCTRL_PIN(5, "FST_SPI_D1"), 115 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 116 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 117 118 PINCTRL_PIN(15, "UART1_RTS_B"), 119 PINCTRL_PIN(16, "UART1_RXD"), 120 PINCTRL_PIN(17, "UART2_RXD"), 121 PINCTRL_PIN(18, "UART1_CTS_B"), 122 PINCTRL_PIN(19, "UART2_RTS_B"), 123 PINCTRL_PIN(20, "UART1_TXD"), 124 PINCTRL_PIN(21, "UART2_TXD"), 125 PINCTRL_PIN(22, "UART2_CTS_B"), 126 127 PINCTRL_PIN(30, "MF_HDA_CLK"), 128 PINCTRL_PIN(31, "MF_HDA_RSTB"), 129 PINCTRL_PIN(32, "MF_HDA_SDIO"), 130 PINCTRL_PIN(33, "MF_HDA_SDO"), 131 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 132 PINCTRL_PIN(35, "MF_HDA_SYNC"), 133 PINCTRL_PIN(36, "MF_HDA_SDI1"), 134 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 135 136 PINCTRL_PIN(45, "I2C5_SDA"), 137 PINCTRL_PIN(46, "I2C4_SDA"), 138 PINCTRL_PIN(47, "I2C6_SDA"), 139 PINCTRL_PIN(48, "I2C5_SCL"), 140 PINCTRL_PIN(49, "I2C_NFC_SDA"), 141 PINCTRL_PIN(50, "I2C4_SCL"), 142 PINCTRL_PIN(51, "I2C6_SCL"), 143 PINCTRL_PIN(52, "I2C_NFC_SCL"), 144 145 PINCTRL_PIN(60, "I2C1_SDA"), 146 PINCTRL_PIN(61, "I2C0_SDA"), 147 PINCTRL_PIN(62, "I2C2_SDA"), 148 PINCTRL_PIN(63, "I2C1_SCL"), 149 PINCTRL_PIN(64, "I2C3_SDA"), 150 PINCTRL_PIN(65, "I2C0_SCL"), 151 PINCTRL_PIN(66, "I2C2_SCL"), 152 PINCTRL_PIN(67, "I2C3_SCL"), 153 154 PINCTRL_PIN(75, "SATA_GP0"), 155 PINCTRL_PIN(76, "SATA_GP1"), 156 PINCTRL_PIN(77, "SATA_LEDN"), 157 PINCTRL_PIN(78, "SATA_GP2"), 158 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 159 PINCTRL_PIN(80, "SATA_GP3"), 160 PINCTRL_PIN(81, "MF_SMB_CLK"), 161 PINCTRL_PIN(82, "MF_SMB_DATA"), 162 163 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 164 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 165 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 166 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 167 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 168 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 169 PINCTRL_PIN(96, "GP_SSP_2_FS"), 170 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 171 }; 172 173 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 174 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 175 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 176 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 177 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 178 static const unsigned southwest_lpe_pins[] = { 179 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 180 }; 181 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 182 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 183 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 184 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 185 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 186 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 187 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 188 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 189 190 /* Some of LPE I2S TXD pins need to have OE inversion set */ 191 static const unsigned int southwest_lpe_altfuncs[] = { 192 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ 193 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ 194 PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ 195 }; 196 197 /* 198 * Two spi3 chipselects are available in different mode than the main spi3 199 * functionality, which is using mode 2. 200 */ 201 static const unsigned int southwest_spi3_altfuncs[] = { 202 PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ 203 PINMODE(2, 0), /* 82 */ 204 }; 205 206 static const struct intel_pingroup southwest_groups[] = { 207 PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), 208 PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), 209 PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), 210 PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), 211 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), 212 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), 213 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), 214 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), 215 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), 216 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), 217 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), 218 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), 219 PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), 220 PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), 221 }; 222 223 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 224 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 225 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 226 static const char * const southwest_hda_groups[] = { "hda_grp" }; 227 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 228 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 229 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 230 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 231 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 232 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 233 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 234 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 235 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 236 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 237 238 /* 239 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 240 * enabled only as GPIOs. 241 */ 242 static const struct intel_function southwest_functions[] = { 243 FUNCTION("uart0", southwest_uart0_groups), 244 FUNCTION("uart1", southwest_uart1_groups), 245 FUNCTION("uart2", southwest_uart2_groups), 246 FUNCTION("hda", southwest_hda_groups), 247 FUNCTION("lpe", southwest_lpe_groups), 248 FUNCTION("i2c0", southwest_i2c0_groups), 249 FUNCTION("i2c1", southwest_i2c1_groups), 250 FUNCTION("i2c2", southwest_i2c2_groups), 251 FUNCTION("i2c3", southwest_i2c3_groups), 252 FUNCTION("i2c4", southwest_i2c4_groups), 253 FUNCTION("i2c5", southwest_i2c5_groups), 254 FUNCTION("i2c6", southwest_i2c6_groups), 255 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 256 FUNCTION("spi3", southwest_spi3_groups), 257 }; 258 259 static const struct intel_padgroup southwest_gpps[] = { 260 CHV_GPP(0, 7), 261 CHV_GPP(15, 22), 262 CHV_GPP(30, 37), 263 CHV_GPP(45, 52), 264 CHV_GPP(60, 67), 265 CHV_GPP(75, 82), 266 CHV_GPP(90, 97), 267 }; 268 269 /* 270 * Southwest community can generate GPIO interrupts only for the first 8 271 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 272 */ 273 static const struct intel_community southwest_communities[] = { 274 CHV_COMMUNITY(southwest_gpps, 8, 0x91), 275 }; 276 277 static const struct intel_pinctrl_soc_data southwest_soc_data = { 278 .uid = "1", 279 .pins = southwest_pins, 280 .npins = ARRAY_SIZE(southwest_pins), 281 .groups = southwest_groups, 282 .ngroups = ARRAY_SIZE(southwest_groups), 283 .functions = southwest_functions, 284 .nfunctions = ARRAY_SIZE(southwest_functions), 285 .communities = southwest_communities, 286 .ncommunities = ARRAY_SIZE(southwest_communities), 287 }; 288 289 static const struct pinctrl_pin_desc north_pins[] = { 290 PINCTRL_PIN(0, "GPIO_DFX_0"), 291 PINCTRL_PIN(1, "GPIO_DFX_3"), 292 PINCTRL_PIN(2, "GPIO_DFX_7"), 293 PINCTRL_PIN(3, "GPIO_DFX_1"), 294 PINCTRL_PIN(4, "GPIO_DFX_5"), 295 PINCTRL_PIN(5, "GPIO_DFX_4"), 296 PINCTRL_PIN(6, "GPIO_DFX_8"), 297 PINCTRL_PIN(7, "GPIO_DFX_2"), 298 PINCTRL_PIN(8, "GPIO_DFX_6"), 299 300 PINCTRL_PIN(15, "GPIO_SUS0"), 301 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 302 PINCTRL_PIN(17, "GPIO_SUS3"), 303 PINCTRL_PIN(18, "GPIO_SUS7"), 304 PINCTRL_PIN(19, "GPIO_SUS1"), 305 PINCTRL_PIN(20, "GPIO_SUS5"), 306 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 307 PINCTRL_PIN(22, "GPIO_SUS4"), 308 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 309 PINCTRL_PIN(24, "GPIO_SUS2"), 310 PINCTRL_PIN(25, "GPIO_SUS6"), 311 PINCTRL_PIN(26, "CX_PREQ_B"), 312 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 313 314 PINCTRL_PIN(30, "TRST_B"), 315 PINCTRL_PIN(31, "TCK"), 316 PINCTRL_PIN(32, "PROCHOT_B"), 317 PINCTRL_PIN(33, "SVIDO_DATA"), 318 PINCTRL_PIN(34, "TMS"), 319 PINCTRL_PIN(35, "CX_PRDY_B_2"), 320 PINCTRL_PIN(36, "TDO_2"), 321 PINCTRL_PIN(37, "CX_PRDY_B"), 322 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 323 PINCTRL_PIN(39, "TDO"), 324 PINCTRL_PIN(40, "SVIDO_CLK"), 325 PINCTRL_PIN(41, "TDI"), 326 327 PINCTRL_PIN(45, "GP_CAMERASB_05"), 328 PINCTRL_PIN(46, "GP_CAMERASB_02"), 329 PINCTRL_PIN(47, "GP_CAMERASB_08"), 330 PINCTRL_PIN(48, "GP_CAMERASB_00"), 331 PINCTRL_PIN(49, "GP_CAMERASB_06"), 332 PINCTRL_PIN(50, "GP_CAMERASB_10"), 333 PINCTRL_PIN(51, "GP_CAMERASB_03"), 334 PINCTRL_PIN(52, "GP_CAMERASB_09"), 335 PINCTRL_PIN(53, "GP_CAMERASB_01"), 336 PINCTRL_PIN(54, "GP_CAMERASB_07"), 337 PINCTRL_PIN(55, "GP_CAMERASB_11"), 338 PINCTRL_PIN(56, "GP_CAMERASB_04"), 339 340 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 341 PINCTRL_PIN(61, "HV_DDI0_HPD"), 342 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 343 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 344 PINCTRL_PIN(64, "HV_DDI1_HPD"), 345 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 346 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 347 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 348 PINCTRL_PIN(68, "HV_DDI2_HPD"), 349 PINCTRL_PIN(69, "PANEL1_VDDEN"), 350 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 351 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 352 PINCTRL_PIN(72, "PANEL0_VDDEN"), 353 }; 354 355 static const struct intel_padgroup north_gpps[] = { 356 CHV_GPP(0, 8), 357 CHV_GPP(15, 27), 358 CHV_GPP(30, 41), 359 CHV_GPP(45, 56), 360 CHV_GPP(60, 72), 361 }; 362 363 /* 364 * North community can generate GPIO interrupts only for the first 8 365 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 366 */ 367 static const struct intel_community north_communities[] = { 368 CHV_COMMUNITY(north_gpps, 8, 0x92), 369 }; 370 371 static const struct intel_pinctrl_soc_data north_soc_data = { 372 .uid = "2", 373 .pins = north_pins, 374 .npins = ARRAY_SIZE(north_pins), 375 .communities = north_communities, 376 .ncommunities = ARRAY_SIZE(north_communities), 377 }; 378 379 static const struct pinctrl_pin_desc east_pins[] = { 380 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 381 PINCTRL_PIN(1, "PMU_BATLOW_B"), 382 PINCTRL_PIN(2, "SUS_STAT_B"), 383 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 384 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 385 PINCTRL_PIN(5, "PMU_PLTRST_B"), 386 PINCTRL_PIN(6, "PMU_SUSCLK"), 387 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 388 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 389 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 390 PINCTRL_PIN(10, "PMU_WAKE_B"), 391 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 392 393 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 394 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 395 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 396 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 397 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 398 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 399 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 400 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 401 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 402 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 403 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 404 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 405 }; 406 407 static const struct intel_padgroup east_gpps[] = { 408 CHV_GPP(0, 11), 409 CHV_GPP(15, 26), 410 }; 411 412 static const struct intel_community east_communities[] = { 413 CHV_COMMUNITY(east_gpps, 16, 0x93), 414 }; 415 416 static const struct intel_pinctrl_soc_data east_soc_data = { 417 .uid = "3", 418 .pins = east_pins, 419 .npins = ARRAY_SIZE(east_pins), 420 .communities = east_communities, 421 .ncommunities = ARRAY_SIZE(east_communities), 422 }; 423 424 static const struct pinctrl_pin_desc southeast_pins[] = { 425 PINCTRL_PIN(0, "MF_PLT_CLK0"), 426 PINCTRL_PIN(1, "PWM1"), 427 PINCTRL_PIN(2, "MF_PLT_CLK1"), 428 PINCTRL_PIN(3, "MF_PLT_CLK4"), 429 PINCTRL_PIN(4, "MF_PLT_CLK3"), 430 PINCTRL_PIN(5, "PWM0"), 431 PINCTRL_PIN(6, "MF_PLT_CLK5"), 432 PINCTRL_PIN(7, "MF_PLT_CLK2"), 433 434 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 435 PINCTRL_PIN(16, "SDMMC1_CLK"), 436 PINCTRL_PIN(17, "SDMMC1_D0"), 437 PINCTRL_PIN(18, "SDMMC2_D1"), 438 PINCTRL_PIN(19, "SDMMC2_CLK"), 439 PINCTRL_PIN(20, "SDMMC1_D2"), 440 PINCTRL_PIN(21, "SDMMC2_D2"), 441 PINCTRL_PIN(22, "SDMMC2_CMD"), 442 PINCTRL_PIN(23, "SDMMC1_CMD"), 443 PINCTRL_PIN(24, "SDMMC1_D1"), 444 PINCTRL_PIN(25, "SDMMC2_D0"), 445 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 446 447 PINCTRL_PIN(30, "SDMMC3_D1"), 448 PINCTRL_PIN(31, "SDMMC3_CLK"), 449 PINCTRL_PIN(32, "SDMMC3_D3"), 450 PINCTRL_PIN(33, "SDMMC3_D2"), 451 PINCTRL_PIN(34, "SDMMC3_CMD"), 452 PINCTRL_PIN(35, "SDMMC3_D0"), 453 454 PINCTRL_PIN(45, "MF_LPC_AD2"), 455 PINCTRL_PIN(46, "LPC_CLKRUNB"), 456 PINCTRL_PIN(47, "MF_LPC_AD0"), 457 PINCTRL_PIN(48, "LPC_FRAMEB"), 458 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 459 PINCTRL_PIN(50, "MF_LPC_AD3"), 460 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 461 PINCTRL_PIN(52, "MF_LPC_AD1"), 462 463 PINCTRL_PIN(60, "SPI1_MISO"), 464 PINCTRL_PIN(61, "SPI1_CSO_B"), 465 PINCTRL_PIN(62, "SPI1_CLK"), 466 PINCTRL_PIN(63, "MMC1_D6"), 467 PINCTRL_PIN(64, "SPI1_MOSI"), 468 PINCTRL_PIN(65, "MMC1_D5"), 469 PINCTRL_PIN(66, "SPI1_CS1_B"), 470 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 471 PINCTRL_PIN(68, "MMC1_D7"), 472 PINCTRL_PIN(69, "MMC1_RCLK"), 473 474 PINCTRL_PIN(75, "USB_OC1_B"), 475 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 476 PINCTRL_PIN(77, "GPIO_ALERT"), 477 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 478 PINCTRL_PIN(79, "ILB_SERIRQ"), 479 PINCTRL_PIN(80, "USB_OC0_B"), 480 PINCTRL_PIN(81, "SDMMC3_CD_B"), 481 PINCTRL_PIN(82, "SPKR"), 482 PINCTRL_PIN(83, "SUSPWRDNACK"), 483 PINCTRL_PIN(84, "SPARE_PIN"), 484 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 485 }; 486 487 static const unsigned southeast_pwm0_pins[] = { 5 }; 488 static const unsigned southeast_pwm1_pins[] = { 1 }; 489 static const unsigned southeast_sdmmc1_pins[] = { 490 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 491 }; 492 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 493 static const unsigned southeast_sdmmc3_pins[] = { 494 30, 31, 32, 33, 34, 35, 78, 81, 85, 495 }; 496 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 497 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 498 499 static const struct intel_pingroup southeast_groups[] = { 500 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), 501 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), 502 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), 503 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), 504 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), 505 PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), 506 PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), 507 }; 508 509 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 510 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 511 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 512 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 513 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 514 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 515 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 516 517 static const struct intel_function southeast_functions[] = { 518 FUNCTION("pwm0", southeast_pwm0_groups), 519 FUNCTION("pwm1", southeast_pwm1_groups), 520 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 521 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 522 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 523 FUNCTION("spi1", southeast_spi1_groups), 524 FUNCTION("spi2", southeast_spi2_groups), 525 }; 526 527 static const struct intel_padgroup southeast_gpps[] = { 528 CHV_GPP(0, 7), 529 CHV_GPP(15, 26), 530 CHV_GPP(30, 35), 531 CHV_GPP(45, 52), 532 CHV_GPP(60, 69), 533 CHV_GPP(75, 85), 534 }; 535 536 static const struct intel_community southeast_communities[] = { 537 CHV_COMMUNITY(southeast_gpps, 16, 0x94), 538 }; 539 540 static const struct intel_pinctrl_soc_data southeast_soc_data = { 541 .uid = "4", 542 .pins = southeast_pins, 543 .npins = ARRAY_SIZE(southeast_pins), 544 .groups = southeast_groups, 545 .ngroups = ARRAY_SIZE(southeast_groups), 546 .functions = southeast_functions, 547 .nfunctions = ARRAY_SIZE(southeast_functions), 548 .communities = southeast_communities, 549 .ncommunities = ARRAY_SIZE(southeast_communities), 550 }; 551 552 static const struct intel_pinctrl_soc_data *chv_soc_data[] = { 553 &southwest_soc_data, 554 &north_soc_data, 555 &east_soc_data, 556 &southeast_soc_data, 557 NULL 558 }; 559 560 /* 561 * Lock to serialize register accesses 562 * 563 * Due to a silicon issue, a shared lock must be used to prevent 564 * concurrent accesses across the 4 GPIO controllers. 565 * 566 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 567 * errata #CHT34, for further information. 568 */ 569 static DEFINE_RAW_SPINLOCK(chv_lock); 570 571 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset) 572 { 573 const struct intel_community *community = &pctrl->communities[0]; 574 575 return readl(community->regs + offset); 576 } 577 578 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value) 579 { 580 const struct intel_community *community = &pctrl->communities[0]; 581 void __iomem *reg = community->regs + offset; 582 583 /* Write and simple read back to confirm the bus transferring done */ 584 writel(value, reg); 585 readl(reg); 586 } 587 588 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset, 589 unsigned int reg) 590 { 591 const struct intel_community *community = &pctrl->communities[0]; 592 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 593 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 594 595 offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no; 596 597 return community->pad_regs + offset + reg; 598 } 599 600 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset) 601 { 602 return readl(chv_padreg(pctrl, pin, offset)); 603 } 604 605 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) 606 { 607 void __iomem *reg = chv_padreg(pctrl, pin, offset); 608 609 /* Write and simple read back to confirm the bus transferring done */ 610 writel(value, reg); 611 readl(reg); 612 } 613 614 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 615 static bool chv_pad_is_locked(u32 ctrl1) 616 { 617 return ctrl1 & CHV_PADCTRL1_CFGLOCK; 618 } 619 620 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) 621 { 622 return chv_pad_is_locked(chv_readl(pctrl, offset, CHV_PADCTRL1)); 623 } 624 625 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 626 unsigned int offset) 627 { 628 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 629 unsigned long flags; 630 u32 ctrl0, ctrl1; 631 632 raw_spin_lock_irqsave(&chv_lock, flags); 633 634 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 635 ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); 636 637 raw_spin_unlock_irqrestore(&chv_lock, flags); 638 639 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 640 seq_puts(s, "GPIO "); 641 } else { 642 u32 mode; 643 644 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 645 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 646 647 seq_printf(s, "mode %d ", mode); 648 } 649 650 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 651 652 if (chv_pad_is_locked(ctrl1)) 653 seq_puts(s, " [LOCKED]"); 654 } 655 656 static const struct pinctrl_ops chv_pinctrl_ops = { 657 .get_groups_count = intel_get_groups_count, 658 .get_group_name = intel_get_group_name, 659 .get_group_pins = intel_get_group_pins, 660 .pin_dbg_show = chv_pin_dbg_show, 661 }; 662 663 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 664 unsigned int function, unsigned int group) 665 { 666 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 667 struct device *dev = pctrl->dev; 668 const struct intel_pingroup *grp; 669 unsigned long flags; 670 int i; 671 672 grp = &pctrl->soc->groups[group]; 673 674 raw_spin_lock_irqsave(&chv_lock, flags); 675 676 /* Check first that the pad is not locked */ 677 for (i = 0; i < grp->grp.npins; i++) { 678 if (chv_pad_locked(pctrl, grp->grp.pins[i])) { 679 raw_spin_unlock_irqrestore(&chv_lock, flags); 680 dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]); 681 return -EBUSY; 682 } 683 } 684 685 for (i = 0; i < grp->grp.npins; i++) { 686 int pin = grp->grp.pins[i]; 687 unsigned int mode; 688 bool invert_oe; 689 u32 value; 690 691 /* Check if there is pin-specific config */ 692 if (grp->modes) 693 mode = grp->modes[i]; 694 else 695 mode = grp->mode; 696 697 /* Extract OE inversion */ 698 invert_oe = mode & PINMODE_INVERT_OE; 699 mode &= ~PINMODE_INVERT_OE; 700 701 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 702 /* Disable GPIO mode */ 703 value &= ~CHV_PADCTRL0_GPIOEN; 704 /* Set to desired mode */ 705 value &= ~CHV_PADCTRL0_PMODE_MASK; 706 value |= mode << CHV_PADCTRL0_PMODE_SHIFT; 707 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 708 709 /* Update for invert_oe */ 710 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK; 711 if (invert_oe) 712 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 713 chv_writel(pctrl, pin, CHV_PADCTRL1, value); 714 715 dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode, 716 invert_oe ? "" : "not "); 717 } 718 719 raw_spin_unlock_irqrestore(&chv_lock, flags); 720 721 return 0; 722 } 723 724 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl, 725 unsigned int offset) 726 { 727 u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK; 728 u32 value; 729 730 /* 731 * One some devices the GPIO should output the inverted value from what 732 * device-drivers / ACPI code expects (inverted external buffer?). The 733 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag, 734 * preserve this flag if the pin is already setup as GPIO. 735 */ 736 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 737 if (value & CHV_PADCTRL0_GPIOEN) 738 invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA; 739 740 value = chv_readl(pctrl, offset, CHV_PADCTRL1); 741 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 742 value &= ~invrxtx_mask; 743 chv_writel(pctrl, offset, CHV_PADCTRL1, value); 744 } 745 746 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 747 struct pinctrl_gpio_range *range, 748 unsigned int offset) 749 { 750 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 751 unsigned long flags; 752 u32 value; 753 754 raw_spin_lock_irqsave(&chv_lock, flags); 755 756 if (chv_pad_locked(pctrl, offset)) { 757 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 758 if (!(value & CHV_PADCTRL0_GPIOEN)) { 759 /* Locked so cannot enable */ 760 raw_spin_unlock_irqrestore(&chv_lock, flags); 761 return -EBUSY; 762 } 763 } else { 764 struct intel_community_context *cctx = &pctrl->context.communities[0]; 765 int i; 766 767 /* Reset the interrupt mapping */ 768 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) { 769 if (cctx->intr_lines[i] == offset) { 770 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 771 break; 772 } 773 } 774 775 /* Disable interrupt generation */ 776 chv_gpio_clear_triggering(pctrl, offset); 777 778 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 779 780 /* 781 * If the pin is in HiZ mode (both TX and RX buffers are 782 * disabled) we turn it to be input now. 783 */ 784 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 785 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 786 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 787 value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 788 } 789 790 /* Switch to a GPIO mode */ 791 value |= CHV_PADCTRL0_GPIOEN; 792 chv_writel(pctrl, offset, CHV_PADCTRL0, value); 793 } 794 795 raw_spin_unlock_irqrestore(&chv_lock, flags); 796 797 return 0; 798 } 799 800 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 801 struct pinctrl_gpio_range *range, 802 unsigned int offset) 803 { 804 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 805 unsigned long flags; 806 807 raw_spin_lock_irqsave(&chv_lock, flags); 808 809 if (!chv_pad_locked(pctrl, offset)) 810 chv_gpio_clear_triggering(pctrl, offset); 811 812 raw_spin_unlock_irqrestore(&chv_lock, flags); 813 } 814 815 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 816 struct pinctrl_gpio_range *range, 817 unsigned int offset, bool input) 818 { 819 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 820 unsigned long flags; 821 u32 ctrl0; 822 823 raw_spin_lock_irqsave(&chv_lock, flags); 824 825 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK; 826 if (input) 827 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 828 else 829 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 830 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 831 832 raw_spin_unlock_irqrestore(&chv_lock, flags); 833 834 return 0; 835 } 836 837 static const struct pinmux_ops chv_pinmux_ops = { 838 .get_functions_count = intel_get_functions_count, 839 .get_function_name = intel_get_function_name, 840 .get_function_groups = intel_get_function_groups, 841 .set_mux = chv_pinmux_set_mux, 842 .gpio_request_enable = chv_gpio_request_enable, 843 .gpio_disable_free = chv_gpio_disable_free, 844 .gpio_set_direction = chv_gpio_set_direction, 845 }; 846 847 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 848 unsigned long *config) 849 { 850 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 851 enum pin_config_param param = pinconf_to_config_param(*config); 852 unsigned long flags; 853 u32 ctrl0, ctrl1; 854 u16 arg = 0; 855 u32 term; 856 857 raw_spin_lock_irqsave(&chv_lock, flags); 858 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 859 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 860 raw_spin_unlock_irqrestore(&chv_lock, flags); 861 862 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 863 864 switch (param) { 865 case PIN_CONFIG_BIAS_DISABLE: 866 if (term) 867 return -EINVAL; 868 break; 869 870 case PIN_CONFIG_BIAS_PULL_UP: 871 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 872 return -EINVAL; 873 874 switch (term) { 875 case CHV_PADCTRL0_TERM_20K: 876 arg = 20000; 877 break; 878 case CHV_PADCTRL0_TERM_5K: 879 arg = 5000; 880 break; 881 case CHV_PADCTRL0_TERM_1K: 882 arg = 1000; 883 break; 884 } 885 886 break; 887 888 case PIN_CONFIG_BIAS_PULL_DOWN: 889 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 890 return -EINVAL; 891 892 switch (term) { 893 case CHV_PADCTRL0_TERM_20K: 894 arg = 20000; 895 break; 896 case CHV_PADCTRL0_TERM_5K: 897 arg = 5000; 898 break; 899 } 900 901 break; 902 903 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 904 u32 cfg; 905 906 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 907 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 908 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 909 return -EINVAL; 910 911 break; 912 913 case PIN_CONFIG_DRIVE_PUSH_PULL: 914 if (ctrl1 & CHV_PADCTRL1_ODEN) 915 return -EINVAL; 916 break; 917 918 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 919 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 920 return -EINVAL; 921 break; 922 } 923 924 default: 925 return -ENOTSUPP; 926 } 927 928 *config = pinconf_to_config_packed(param, arg); 929 return 0; 930 } 931 932 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 933 enum pin_config_param param, u32 arg) 934 { 935 unsigned long flags; 936 u32 ctrl0, pull; 937 938 raw_spin_lock_irqsave(&chv_lock, flags); 939 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 940 941 switch (param) { 942 case PIN_CONFIG_BIAS_DISABLE: 943 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 944 break; 945 946 case PIN_CONFIG_BIAS_PULL_UP: 947 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 948 949 switch (arg) { 950 case 1000: 951 /* For 1k there is only pull up */ 952 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 953 break; 954 case 5000: 955 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 956 break; 957 case 20000: 958 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 959 break; 960 default: 961 raw_spin_unlock_irqrestore(&chv_lock, flags); 962 return -EINVAL; 963 } 964 965 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 966 break; 967 968 case PIN_CONFIG_BIAS_PULL_DOWN: 969 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 970 971 switch (arg) { 972 case 5000: 973 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 974 break; 975 case 20000: 976 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 977 break; 978 default: 979 raw_spin_unlock_irqrestore(&chv_lock, flags); 980 return -EINVAL; 981 } 982 983 ctrl0 |= pull; 984 break; 985 986 default: 987 raw_spin_unlock_irqrestore(&chv_lock, flags); 988 return -EINVAL; 989 } 990 991 chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0); 992 raw_spin_unlock_irqrestore(&chv_lock, flags); 993 994 return 0; 995 } 996 997 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, 998 bool enable) 999 { 1000 unsigned long flags; 1001 u32 ctrl1; 1002 1003 raw_spin_lock_irqsave(&chv_lock, flags); 1004 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 1005 1006 if (enable) 1007 ctrl1 |= CHV_PADCTRL1_ODEN; 1008 else 1009 ctrl1 &= ~CHV_PADCTRL1_ODEN; 1010 1011 chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1); 1012 raw_spin_unlock_irqrestore(&chv_lock, flags); 1013 1014 return 0; 1015 } 1016 1017 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 1018 unsigned long *configs, unsigned int nconfigs) 1019 { 1020 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1021 struct device *dev = pctrl->dev; 1022 enum pin_config_param param; 1023 int i, ret; 1024 u32 arg; 1025 1026 if (chv_pad_locked(pctrl, pin)) 1027 return -EBUSY; 1028 1029 for (i = 0; i < nconfigs; i++) { 1030 param = pinconf_to_config_param(configs[i]); 1031 arg = pinconf_to_config_argument(configs[i]); 1032 1033 switch (param) { 1034 case PIN_CONFIG_BIAS_DISABLE: 1035 case PIN_CONFIG_BIAS_PULL_UP: 1036 case PIN_CONFIG_BIAS_PULL_DOWN: 1037 ret = chv_config_set_pull(pctrl, pin, param, arg); 1038 if (ret) 1039 return ret; 1040 break; 1041 1042 case PIN_CONFIG_DRIVE_PUSH_PULL: 1043 ret = chv_config_set_oden(pctrl, pin, false); 1044 if (ret) 1045 return ret; 1046 break; 1047 1048 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1049 ret = chv_config_set_oden(pctrl, pin, true); 1050 if (ret) 1051 return ret; 1052 break; 1053 1054 default: 1055 return -ENOTSUPP; 1056 } 1057 1058 dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg); 1059 } 1060 1061 return 0; 1062 } 1063 1064 static int chv_config_group_get(struct pinctrl_dev *pctldev, 1065 unsigned int group, 1066 unsigned long *config) 1067 { 1068 const unsigned int *pins; 1069 unsigned int npins; 1070 int ret; 1071 1072 ret = intel_get_group_pins(pctldev, group, &pins, &npins); 1073 if (ret) 1074 return ret; 1075 1076 ret = chv_config_get(pctldev, pins[0], config); 1077 if (ret) 1078 return ret; 1079 1080 return 0; 1081 } 1082 1083 static int chv_config_group_set(struct pinctrl_dev *pctldev, 1084 unsigned int group, unsigned long *configs, 1085 unsigned int num_configs) 1086 { 1087 const unsigned int *pins; 1088 unsigned int npins; 1089 int i, ret; 1090 1091 ret = intel_get_group_pins(pctldev, group, &pins, &npins); 1092 if (ret) 1093 return ret; 1094 1095 for (i = 0; i < npins; i++) { 1096 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1097 if (ret) 1098 return ret; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static const struct pinconf_ops chv_pinconf_ops = { 1105 .is_generic = true, 1106 .pin_config_set = chv_config_set, 1107 .pin_config_get = chv_config_get, 1108 .pin_config_group_get = chv_config_group_get, 1109 .pin_config_group_set = chv_config_group_set, 1110 }; 1111 1112 static struct pinctrl_desc chv_pinctrl_desc = { 1113 .pctlops = &chv_pinctrl_ops, 1114 .pmxops = &chv_pinmux_ops, 1115 .confops = &chv_pinconf_ops, 1116 .owner = THIS_MODULE, 1117 }; 1118 1119 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) 1120 { 1121 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1122 unsigned long flags; 1123 u32 ctrl0, cfg; 1124 1125 raw_spin_lock_irqsave(&chv_lock, flags); 1126 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1127 raw_spin_unlock_irqrestore(&chv_lock, flags); 1128 1129 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1130 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1131 1132 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1133 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1134 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1135 } 1136 1137 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1138 { 1139 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1140 unsigned long flags; 1141 u32 ctrl0; 1142 1143 raw_spin_lock_irqsave(&chv_lock, flags); 1144 1145 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1146 1147 if (value) 1148 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1149 else 1150 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1151 1152 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 1153 1154 raw_spin_unlock_irqrestore(&chv_lock, flags); 1155 } 1156 1157 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1158 { 1159 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1160 u32 ctrl0, direction; 1161 unsigned long flags; 1162 1163 raw_spin_lock_irqsave(&chv_lock, flags); 1164 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1165 raw_spin_unlock_irqrestore(&chv_lock, flags); 1166 1167 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1168 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1169 1170 if (direction == CHV_PADCTRL0_GPIOCFG_GPO) 1171 return GPIO_LINE_DIRECTION_OUT; 1172 1173 return GPIO_LINE_DIRECTION_IN; 1174 } 1175 1176 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1177 { 1178 return pinctrl_gpio_direction_input(chip->base + offset); 1179 } 1180 1181 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1182 int value) 1183 { 1184 chv_gpio_set(chip, offset, value); 1185 return pinctrl_gpio_direction_output(chip->base + offset); 1186 } 1187 1188 static const struct gpio_chip chv_gpio_chip = { 1189 .owner = THIS_MODULE, 1190 .request = gpiochip_generic_request, 1191 .free = gpiochip_generic_free, 1192 .get_direction = chv_gpio_get_direction, 1193 .direction_input = chv_gpio_direction_input, 1194 .direction_output = chv_gpio_direction_output, 1195 .get = chv_gpio_get, 1196 .set = chv_gpio_set, 1197 }; 1198 1199 static void chv_gpio_irq_ack(struct irq_data *d) 1200 { 1201 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1202 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1203 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1204 u32 intr_line; 1205 1206 raw_spin_lock(&chv_lock); 1207 1208 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1209 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1210 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1211 chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line)); 1212 1213 raw_spin_unlock(&chv_lock); 1214 } 1215 1216 static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1217 { 1218 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1219 u32 value, intr_line; 1220 unsigned long flags; 1221 1222 raw_spin_lock_irqsave(&chv_lock, flags); 1223 1224 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1225 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1226 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1227 1228 value = chv_pctrl_readl(pctrl, CHV_INTMASK); 1229 if (mask) 1230 value &= ~BIT(intr_line); 1231 else 1232 value |= BIT(intr_line); 1233 chv_pctrl_writel(pctrl, CHV_INTMASK, value); 1234 1235 raw_spin_unlock_irqrestore(&chv_lock, flags); 1236 } 1237 1238 static void chv_gpio_irq_mask(struct irq_data *d) 1239 { 1240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1241 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1242 1243 chv_gpio_irq_mask_unmask(gc, hwirq, true); 1244 gpiochip_disable_irq(gc, hwirq); 1245 } 1246 1247 static void chv_gpio_irq_unmask(struct irq_data *d) 1248 { 1249 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1250 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1251 1252 gpiochip_enable_irq(gc, hwirq); 1253 chv_gpio_irq_mask_unmask(gc, hwirq, false); 1254 } 1255 1256 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1257 { 1258 /* 1259 * Check if the interrupt has been requested with 0 as triggering 1260 * type. In that case it is assumed that the current values 1261 * programmed to the hardware are used (e.g BIOS configured 1262 * defaults). 1263 * 1264 * In that case ->irq_set_type() will never be called so we need to 1265 * read back the values from hardware now, set correct flow handler 1266 * and update mappings before the interrupt is being used. 1267 */ 1268 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1269 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1270 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1271 struct device *dev = pctrl->dev; 1272 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1273 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1274 irq_flow_handler_t handler; 1275 unsigned long flags; 1276 u32 intsel, value; 1277 1278 raw_spin_lock_irqsave(&chv_lock, flags); 1279 intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1280 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1281 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1282 1283 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1284 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1285 handler = handle_level_irq; 1286 else 1287 handler = handle_edge_irq; 1288 1289 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1290 irq_set_handler_locked(d, handler); 1291 dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n", 1292 intsel, hwirq); 1293 cctx->intr_lines[intsel] = hwirq; 1294 } 1295 raw_spin_unlock_irqrestore(&chv_lock, flags); 1296 } 1297 1298 chv_gpio_irq_unmask(d); 1299 return 0; 1300 } 1301 1302 static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) 1303 { 1304 struct device *dev = pctrl->dev; 1305 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1306 const struct intel_community *community = &pctrl->communities[0]; 1307 u32 value, intsel; 1308 int i; 1309 1310 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 1311 intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT; 1312 1313 if (cctx->intr_lines[intsel] == pin) 1314 return 0; 1315 1316 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1317 dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin); 1318 cctx->intr_lines[intsel] = pin; 1319 return 0; 1320 } 1321 1322 /* 1323 * The interrupt line selected by the BIOS is already in use by 1324 * another pin, this is a known BIOS bug found on several models. 1325 * But this may also be caused by Linux deciding to use a pin as 1326 * IRQ which was not expected to be used as such by the BIOS authors, 1327 * so log this at info level only. 1328 */ 1329 dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel, 1330 cctx->intr_lines[intsel], pin); 1331 1332 if (chv_pad_locked(pctrl, pin)) 1333 return -EBUSY; 1334 1335 /* 1336 * The BIOS fills the interrupt lines from 0 counting up, start at 1337 * the other end to find a free interrupt line to workaround this. 1338 */ 1339 for (i = community->nirqs - 1; i >= 0; i--) { 1340 if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ) 1341 break; 1342 } 1343 if (i < 0) 1344 return -EBUSY; 1345 1346 dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i); 1347 1348 value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT); 1349 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 1350 cctx->intr_lines[i] = pin; 1351 1352 return 0; 1353 } 1354 1355 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 1356 { 1357 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1358 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1359 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1360 unsigned long flags; 1361 u32 value; 1362 int ret; 1363 1364 raw_spin_lock_irqsave(&chv_lock, flags); 1365 1366 ret = chv_gpio_set_intr_line(pctrl, hwirq); 1367 if (ret) { 1368 raw_spin_unlock_irqrestore(&chv_lock, flags); 1369 return ret; 1370 } 1371 1372 /* 1373 * Pins which can be used as shared interrupt are configured in 1374 * BIOS. Driver trusts BIOS configurations and assigns different 1375 * handler according to the irq type. 1376 * 1377 * Driver needs to save the mapping between each pin and 1378 * its interrupt line. 1379 * 1. If the pin cfg is locked in BIOS: 1380 * Trust BIOS has programmed IntWakeCfg bits correctly, 1381 * driver just needs to save the mapping. 1382 * 2. If the pin cfg is not locked in BIOS: 1383 * Driver programs the IntWakeCfg bits and save the mapping. 1384 */ 1385 if (!chv_pad_locked(pctrl, hwirq)) { 1386 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1387 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1388 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1389 1390 if (type & IRQ_TYPE_EDGE_BOTH) { 1391 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1392 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1393 else if (type & IRQ_TYPE_EDGE_RISING) 1394 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1395 else if (type & IRQ_TYPE_EDGE_FALLING) 1396 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1397 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1398 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1399 if (type & IRQ_TYPE_LEVEL_LOW) 1400 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1401 } 1402 1403 chv_writel(pctrl, hwirq, CHV_PADCTRL1, value); 1404 } 1405 1406 if (type & IRQ_TYPE_EDGE_BOTH) 1407 irq_set_handler_locked(d, handle_edge_irq); 1408 else if (type & IRQ_TYPE_LEVEL_MASK) 1409 irq_set_handler_locked(d, handle_level_irq); 1410 1411 raw_spin_unlock_irqrestore(&chv_lock, flags); 1412 1413 return 0; 1414 } 1415 1416 static const struct irq_chip chv_gpio_irq_chip = { 1417 .name = "chv-gpio", 1418 .irq_startup = chv_gpio_irq_startup, 1419 .irq_ack = chv_gpio_irq_ack, 1420 .irq_mask = chv_gpio_irq_mask, 1421 .irq_unmask = chv_gpio_irq_unmask, 1422 .irq_set_type = chv_gpio_irq_type, 1423 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 1424 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1425 }; 1426 1427 static void chv_gpio_irq_handler(struct irq_desc *desc) 1428 { 1429 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1430 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1431 struct device *dev = pctrl->dev; 1432 const struct intel_community *community = &pctrl->communities[0]; 1433 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1434 struct irq_chip *chip = irq_desc_get_chip(desc); 1435 unsigned long pending; 1436 unsigned long flags; 1437 u32 intr_line; 1438 1439 chained_irq_enter(chip, desc); 1440 1441 raw_spin_lock_irqsave(&chv_lock, flags); 1442 pending = chv_pctrl_readl(pctrl, CHV_INTSTAT); 1443 raw_spin_unlock_irqrestore(&chv_lock, flags); 1444 1445 for_each_set_bit(intr_line, &pending, community->nirqs) { 1446 unsigned int offset; 1447 1448 offset = cctx->intr_lines[intr_line]; 1449 if (offset == CHV_INVALID_HWIRQ) { 1450 dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line); 1451 /* Some boards expect hwirq 0 to trigger in this case */ 1452 offset = 0; 1453 } 1454 1455 generic_handle_domain_irq(gc->irq.domain, offset); 1456 } 1457 1458 chained_irq_exit(chip, desc); 1459 } 1460 1461 /* 1462 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1463 * tables. Since we leave GPIOs that are not capable of generating 1464 * interrupts out of the irqdomain the numbering will be different and 1465 * cause devices using the hardcoded IRQ numbers fail. In order not to 1466 * break such machines we will only mask pins from irqdomain if the machine 1467 * is not listed below. 1468 */ 1469 static const struct dmi_system_id chv_no_valid_mask[] = { 1470 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1471 { 1472 .ident = "Intel_Strago based Chromebooks (All models)", 1473 .matches = { 1474 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1475 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1476 }, 1477 }, 1478 { 1479 .ident = "HP Chromebook 11 G5 (Setzer)", 1480 .matches = { 1481 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1482 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1483 }, 1484 }, 1485 { 1486 .ident = "Acer Chromebook R11 (Cyan)", 1487 .matches = { 1488 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1489 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1490 }, 1491 }, 1492 { 1493 .ident = "Samsung Chromebook 3 (Celes)", 1494 .matches = { 1495 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1496 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1497 }, 1498 }, 1499 {} 1500 }; 1501 1502 static void chv_init_irq_valid_mask(struct gpio_chip *chip, 1503 unsigned long *valid_mask, 1504 unsigned int ngpios) 1505 { 1506 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1507 const struct intel_community *community = &pctrl->communities[0]; 1508 int i; 1509 1510 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1511 for (i = 0; i < pctrl->soc->npins; i++) { 1512 const struct pinctrl_pin_desc *desc; 1513 u32 intsel; 1514 1515 desc = &pctrl->soc->pins[i]; 1516 1517 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1518 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1519 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1520 1521 if (intsel >= community->nirqs) 1522 clear_bit(desc->number, valid_mask); 1523 } 1524 } 1525 1526 static int chv_gpio_irq_init_hw(struct gpio_chip *chip) 1527 { 1528 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1529 const struct intel_community *community = &pctrl->communities[0]; 1530 1531 /* 1532 * The same set of machines in chv_no_valid_mask[] have incorrectly 1533 * configured GPIOs that generate spurious interrupts so we use 1534 * this same list to apply another quirk for them. 1535 * 1536 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1537 */ 1538 if (!pctrl->chip.irq.init_valid_mask) { 1539 /* 1540 * Mask all interrupts the community is able to generate 1541 * but leave the ones that can only generate GPEs unmasked. 1542 */ 1543 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs)); 1544 } 1545 1546 /* Clear all interrupts */ 1547 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1548 1549 return 0; 1550 } 1551 1552 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) 1553 { 1554 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1555 struct device *dev = pctrl->dev; 1556 const struct intel_community *community = &pctrl->communities[0]; 1557 const struct intel_padgroup *gpp; 1558 int ret, i; 1559 1560 for (i = 0; i < community->ngpps; i++) { 1561 gpp = &community->gpps[i]; 1562 ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size); 1563 if (ret) { 1564 dev_err(dev, "failed to add GPIO pin range\n"); 1565 return ret; 1566 } 1567 } 1568 1569 return 0; 1570 } 1571 1572 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1573 { 1574 const struct intel_community *community = &pctrl->communities[0]; 1575 const struct intel_padgroup *gpp; 1576 struct gpio_chip *chip = &pctrl->chip; 1577 struct device *dev = pctrl->dev; 1578 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1579 int ret, i, irq_base; 1580 1581 *chip = chv_gpio_chip; 1582 1583 chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; 1584 chip->label = dev_name(dev); 1585 chip->add_pin_ranges = chv_gpio_add_pin_ranges; 1586 chip->parent = dev; 1587 chip->base = -1; 1588 1589 pctrl->irq = irq; 1590 1591 gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip); 1592 chip->irq.init_hw = chv_gpio_irq_init_hw; 1593 chip->irq.parent_handler = chv_gpio_irq_handler; 1594 chip->irq.num_parents = 1; 1595 chip->irq.parents = &pctrl->irq; 1596 chip->irq.default_type = IRQ_TYPE_NONE; 1597 chip->irq.handler = handle_bad_irq; 1598 if (need_valid_mask) { 1599 chip->irq.init_valid_mask = chv_init_irq_valid_mask; 1600 } else { 1601 irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE); 1602 if (irq_base < 0) { 1603 dev_err(dev, "Failed to allocate IRQ numbers\n"); 1604 return irq_base; 1605 } 1606 } 1607 1608 ret = devm_gpiochip_add_data(dev, chip, pctrl); 1609 if (ret) { 1610 dev_err(dev, "Failed to register gpiochip\n"); 1611 return ret; 1612 } 1613 1614 if (!need_valid_mask) { 1615 for (i = 0; i < community->ngpps; i++) { 1616 gpp = &community->gpps[i]; 1617 1618 irq_domain_associate_many(chip->irq.domain, irq_base, 1619 gpp->base, gpp->size); 1620 irq_base += gpp->size; 1621 } 1622 } 1623 1624 return 0; 1625 } 1626 1627 static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1628 acpi_physical_address address, u32 bits, u64 *value, 1629 void *handler_context, void *region_context) 1630 { 1631 struct intel_pinctrl *pctrl = region_context; 1632 unsigned long flags; 1633 acpi_status ret = AE_OK; 1634 1635 raw_spin_lock_irqsave(&chv_lock, flags); 1636 1637 if (function == ACPI_WRITE) 1638 chv_pctrl_writel(pctrl, address, *value); 1639 else if (function == ACPI_READ) 1640 *value = chv_pctrl_readl(pctrl, address); 1641 else 1642 ret = AE_BAD_PARAMETER; 1643 1644 raw_spin_unlock_irqrestore(&chv_lock, flags); 1645 1646 return ret; 1647 } 1648 1649 static int chv_pinctrl_probe(struct platform_device *pdev) 1650 { 1651 const struct intel_pinctrl_soc_data *soc_data; 1652 struct intel_community_context *cctx; 1653 struct intel_community *community; 1654 struct device *dev = &pdev->dev; 1655 struct intel_pinctrl *pctrl; 1656 acpi_status status; 1657 unsigned int i; 1658 int ret, irq; 1659 1660 soc_data = intel_pinctrl_get_soc_data(pdev); 1661 if (IS_ERR(soc_data)) 1662 return PTR_ERR(soc_data); 1663 1664 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1665 if (!pctrl) 1666 return -ENOMEM; 1667 1668 pctrl->dev = dev; 1669 pctrl->soc = soc_data; 1670 1671 pctrl->ncommunities = pctrl->soc->ncommunities; 1672 pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities, 1673 pctrl->ncommunities * sizeof(*pctrl->communities), 1674 GFP_KERNEL); 1675 if (!pctrl->communities) 1676 return -ENOMEM; 1677 1678 community = &pctrl->communities[0]; 1679 community->regs = devm_platform_ioremap_resource(pdev, 0); 1680 if (IS_ERR(community->regs)) 1681 return PTR_ERR(community->regs); 1682 1683 community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF; 1684 1685 #ifdef CONFIG_PM_SLEEP 1686 pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins, 1687 sizeof(*pctrl->context.pads), 1688 GFP_KERNEL); 1689 if (!pctrl->context.pads) 1690 return -ENOMEM; 1691 #endif 1692 1693 pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities, 1694 sizeof(*pctrl->context.communities), 1695 GFP_KERNEL); 1696 if (!pctrl->context.communities) 1697 return -ENOMEM; 1698 1699 cctx = &pctrl->context.communities[0]; 1700 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) 1701 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 1702 1703 irq = platform_get_irq(pdev, 0); 1704 if (irq < 0) 1705 return irq; 1706 1707 pctrl->pctldesc = chv_pinctrl_desc; 1708 pctrl->pctldesc.name = dev_name(dev); 1709 pctrl->pctldesc.pins = pctrl->soc->pins; 1710 pctrl->pctldesc.npins = pctrl->soc->npins; 1711 1712 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1713 if (IS_ERR(pctrl->pctldev)) { 1714 dev_err(dev, "failed to register pinctrl driver\n"); 1715 return PTR_ERR(pctrl->pctldev); 1716 } 1717 1718 ret = chv_gpio_probe(pctrl, irq); 1719 if (ret) 1720 return ret; 1721 1722 status = acpi_install_address_space_handler(ACPI_HANDLE(dev), 1723 community->acpi_space_id, 1724 chv_pinctrl_mmio_access_handler, 1725 NULL, pctrl); 1726 if (ACPI_FAILURE(status)) 1727 dev_err(dev, "failed to install ACPI addr space handler\n"); 1728 1729 platform_set_drvdata(pdev, pctrl); 1730 1731 return 0; 1732 } 1733 1734 static int chv_pinctrl_remove(struct platform_device *pdev) 1735 { 1736 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1737 const struct intel_community *community = &pctrl->communities[0]; 1738 1739 acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev), 1740 community->acpi_space_id, 1741 chv_pinctrl_mmio_access_handler); 1742 1743 return 0; 1744 } 1745 1746 static int chv_pinctrl_suspend_noirq(struct device *dev) 1747 { 1748 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1749 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1750 unsigned long flags; 1751 int i; 1752 1753 raw_spin_lock_irqsave(&chv_lock, flags); 1754 1755 cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); 1756 1757 for (i = 0; i < pctrl->soc->npins; i++) { 1758 const struct pinctrl_pin_desc *desc; 1759 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1760 1761 desc = &pctrl->soc->pins[i]; 1762 if (chv_pad_locked(pctrl, desc->number)) 1763 continue; 1764 1765 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1766 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE; 1767 1768 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1769 } 1770 1771 raw_spin_unlock_irqrestore(&chv_lock, flags); 1772 1773 return 0; 1774 } 1775 1776 static int chv_pinctrl_resume_noirq(struct device *dev) 1777 { 1778 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1779 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1780 unsigned long flags; 1781 int i; 1782 1783 raw_spin_lock_irqsave(&chv_lock, flags); 1784 1785 /* 1786 * Mask all interrupts before restoring per-pin configuration 1787 * registers because we don't know in which state BIOS left them 1788 * upon exiting suspend. 1789 */ 1790 chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000); 1791 1792 for (i = 0; i < pctrl->soc->npins; i++) { 1793 const struct pinctrl_pin_desc *desc; 1794 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1795 u32 val; 1796 1797 desc = &pctrl->soc->pins[i]; 1798 if (chv_pad_locked(pctrl, desc->number)) 1799 continue; 1800 1801 /* Only restore if our saved state differs from the current */ 1802 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1803 val &= ~CHV_PADCTRL0_GPIORXSTATE; 1804 if (ctx->padctrl0 != val) { 1805 chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0); 1806 dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number, 1807 chv_readl(pctrl, desc->number, CHV_PADCTRL0)); 1808 } 1809 1810 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1811 if (ctx->padctrl1 != val) { 1812 chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1); 1813 dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number, 1814 chv_readl(pctrl, desc->number, CHV_PADCTRL1)); 1815 } 1816 } 1817 1818 /* 1819 * Now that all pins are restored to known state, we can restore 1820 * the interrupt mask register as well. 1821 */ 1822 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1823 chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask); 1824 1825 raw_spin_unlock_irqrestore(&chv_lock, flags); 1826 1827 return 0; 1828 } 1829 1830 static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops, 1831 chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq); 1832 1833 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1834 { "INT33FF", (kernel_ulong_t)chv_soc_data }, 1835 { } 1836 }; 1837 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1838 1839 static struct platform_driver chv_pinctrl_driver = { 1840 .probe = chv_pinctrl_probe, 1841 .remove = chv_pinctrl_remove, 1842 .driver = { 1843 .name = "cherryview-pinctrl", 1844 .pm = pm_sleep_ptr(&chv_pinctrl_pm_ops), 1845 .acpi_match_table = chv_pinctrl_acpi_match, 1846 }, 1847 }; 1848 1849 static int __init chv_pinctrl_init(void) 1850 { 1851 return platform_driver_register(&chv_pinctrl_driver); 1852 } 1853 subsys_initcall(chv_pinctrl_init); 1854 1855 static void __exit chv_pinctrl_exit(void) 1856 { 1857 platform_driver_unregister(&chv_pinctrl_driver); 1858 } 1859 module_exit(chv_pinctrl_exit); 1860 1861 MODULE_AUTHOR("Mika Westerberg <[email protected]>"); 1862 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1863 MODULE_LICENSE("GPL v2"); 1864 MODULE_IMPORT_NS(PINCTRL_INTEL); 1865