1# SPDX-License-Identifier: GPL-2.0 2# Intel pin control drivers 3 4if (X86 || COMPILE_TEST) 5 6config PINCTRL_BAYTRAIL 7 bool "Intel Baytrail GPIO pin control" 8 depends on ACPI 9 select GPIOLIB 10 select GPIOLIB_IRQCHIP 11 select PINMUX 12 select PINCONF 13 select GENERIC_PINCONF 14 help 15 driver for memory mapped GPIO functionality on Intel Baytrail 16 platforms. Supports 3 banks with 102, 28 and 44 gpios. 17 Most pins are usually muxed to some other functionality by firmware, 18 so only a small amount is available for gpio use. 19 20 Requires ACPI device enumeration code to set up a platform device. 21 22config PINCTRL_CHERRYVIEW 23 tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" 24 depends on ACPI 25 select PINMUX 26 select PINCONF 27 select GENERIC_PINCONF 28 select GPIOLIB 29 select GPIOLIB_IRQCHIP 30 help 31 Cherryview/Braswell pinctrl driver provides an interface that 32 allows configuring of SoC pins and using them as GPIOs. 33 34config PINCTRL_LYNXPOINT 35 tristate "Intel Lynxpoint pinctrl and GPIO driver" 36 depends on ACPI 37 select GPIOLIB 38 select GPIOLIB_IRQCHIP 39 help 40 Lynxpoint is the PCH of Intel Haswell. This pinctrl driver 41 provides an interface that allows configuring of PCH pins and 42 using them as GPIOs. 43 44config PINCTRL_MERRIFIELD 45 tristate "Intel Merrifield pinctrl driver" 46 depends on X86_INTEL_MID 47 select PINMUX 48 select PINCONF 49 select GENERIC_PINCONF 50 help 51 Merrifield Family-Level Interface Shim (FLIS) driver provides an 52 interface that allows configuring of SoC pins and using them as 53 GPIOs. 54 55config PINCTRL_INTEL 56 tristate 57 select PINMUX 58 select PINCONF 59 select GENERIC_PINCONF 60 select GPIOLIB 61 select GPIOLIB_IRQCHIP 62 63config PINCTRL_BROXTON 64 tristate "Intel Broxton pinctrl and GPIO driver" 65 depends on ACPI 66 select PINCTRL_INTEL 67 help 68 Broxton pinctrl driver provides an interface that allows 69 configuring of SoC pins and using them as GPIOs. 70 71config PINCTRL_CANNONLAKE 72 tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" 73 depends on ACPI 74 select PINCTRL_INTEL 75 help 76 This pinctrl driver provides an interface that allows configuring 77 of Intel Cannon Lake PCH pins and using them as GPIOs. 78 79config PINCTRL_CEDARFORK 80 tristate "Intel Cedar Fork pinctrl and GPIO driver" 81 depends on ACPI 82 select PINCTRL_INTEL 83 help 84 This pinctrl driver provides an interface that allows configuring 85 of Intel Cedar Fork PCH pins and using them as GPIOs. 86 87config PINCTRL_DENVERTON 88 tristate "Intel Denverton pinctrl and GPIO driver" 89 depends on ACPI 90 select PINCTRL_INTEL 91 help 92 This pinctrl driver provides an interface that allows configuring 93 of Intel Denverton SoC pins and using them as GPIOs. 94 95config PINCTRL_GEMINILAKE 96 tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" 97 depends on ACPI 98 select PINCTRL_INTEL 99 help 100 This pinctrl driver provides an interface that allows configuring 101 of Intel Gemini Lake SoC pins and using them as GPIOs. 102 103config PINCTRL_ICELAKE 104 tristate "Intel Ice Lake PCH pinctrl and GPIO driver" 105 depends on ACPI 106 select PINCTRL_INTEL 107 help 108 This pinctrl driver provides an interface that allows configuring 109 of Intel Ice Lake PCH pins and using them as GPIOs. 110 111config PINCTRL_LEWISBURG 112 tristate "Intel Lewisburg pinctrl and GPIO driver" 113 depends on ACPI 114 select PINCTRL_INTEL 115 help 116 This pinctrl driver provides an interface that allows configuring 117 of Intel Lewisburg pins and using them as GPIOs. 118 119config PINCTRL_SUNRISEPOINT 120 tristate "Intel Sunrisepoint pinctrl and GPIO driver" 121 depends on ACPI 122 select PINCTRL_INTEL 123 help 124 Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver 125 provides an interface that allows configuring of PCH pins and 126 using them as GPIOs. 127 128config PINCTRL_TIGERLAKE 129 tristate "Intel Tiger Lake pinctrl and GPIO driver" 130 depends on ACPI 131 select PINCTRL_INTEL 132 help 133 This pinctrl driver provides an interface that allows configuring 134 of Intel Tiger Lake PCH pins and using them as GPIOs. 135endif 136