1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/lxt.c 4 * 5 * Driver for Intel LXT PHYs 6 * 7 * Author: Andy Fleming 8 * 9 * Copyright (c) 2004 Freescale Semiconductor, Inc. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/errno.h> 14 #include <linux/unistd.h> 15 #include <linux/interrupt.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/netdevice.h> 19 #include <linux/etherdevice.h> 20 #include <linux/skbuff.h> 21 #include <linux/spinlock.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/mii.h> 25 #include <linux/ethtool.h> 26 #include <linux/phy.h> 27 28 #include <asm/io.h> 29 #include <asm/irq.h> 30 #include <linux/uaccess.h> 31 32 /* The Level one LXT970 is used by many boards */ 33 34 #define MII_LXT970_IER 17 /* Interrupt Enable Register */ 35 36 #define MII_LXT970_IER_IEN 0x0002 37 38 #define MII_LXT970_ISR 18 /* Interrupt Status Register */ 39 40 #define MII_LXT970_IRS_MINT BIT(15) 41 42 #define MII_LXT970_CONFIG 19 /* Configuration Register */ 43 44 /* ------------------------------------------------------------------------- */ 45 /* The Level one LXT971 is used on some of my custom boards */ 46 47 /* register definitions for the 971 */ 48 #define MII_LXT971_IER 18 /* Interrupt Enable Register */ 49 #define MII_LXT971_IER_IEN 0x00f2 50 51 #define MII_LXT971_ISR 19 /* Interrupt Status Register */ 52 #define MII_LXT971_ISR_MASK 0x00f0 53 54 /* register definitions for the 973 */ 55 #define MII_LXT973_PCR 16 /* Port Configuration Register */ 56 #define PCR_FIBER_SELECT 1 57 58 MODULE_DESCRIPTION("Intel LXT PHY driver"); 59 MODULE_AUTHOR("Andy Fleming"); 60 MODULE_LICENSE("GPL"); 61 62 static int lxt970_ack_interrupt(struct phy_device *phydev) 63 { 64 int err; 65 66 err = phy_read(phydev, MII_BMSR); 67 68 if (err < 0) 69 return err; 70 71 err = phy_read(phydev, MII_LXT970_ISR); 72 73 if (err < 0) 74 return err; 75 76 return 0; 77 } 78 79 static int lxt970_config_intr(struct phy_device *phydev) 80 { 81 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 82 return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); 83 else 84 return phy_write(phydev, MII_LXT970_IER, 0); 85 } 86 87 static irqreturn_t lxt970_handle_interrupt(struct phy_device *phydev) 88 { 89 int irq_status; 90 91 /* The interrupt status register is cleared by reading BMSR 92 * followed by MII_LXT970_ISR 93 */ 94 irq_status = phy_read(phydev, MII_BMSR); 95 if (irq_status < 0) { 96 phy_error(phydev); 97 return IRQ_NONE; 98 } 99 100 irq_status = phy_read(phydev, MII_LXT970_ISR); 101 if (irq_status < 0) { 102 phy_error(phydev); 103 return IRQ_NONE; 104 } 105 106 if (!(irq_status & MII_LXT970_IRS_MINT)) 107 return IRQ_NONE; 108 109 phy_trigger_machine(phydev); 110 111 return IRQ_HANDLED; 112 } 113 114 static int lxt970_config_init(struct phy_device *phydev) 115 { 116 return phy_write(phydev, MII_LXT970_CONFIG, 0); 117 } 118 119 120 static int lxt971_ack_interrupt(struct phy_device *phydev) 121 { 122 int err = phy_read(phydev, MII_LXT971_ISR); 123 124 if (err < 0) 125 return err; 126 127 return 0; 128 } 129 130 static int lxt971_config_intr(struct phy_device *phydev) 131 { 132 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 133 return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); 134 else 135 return phy_write(phydev, MII_LXT971_IER, 0); 136 } 137 138 static irqreturn_t lxt971_handle_interrupt(struct phy_device *phydev) 139 { 140 int irq_status; 141 142 irq_status = phy_read(phydev, MII_LXT971_ISR); 143 if (irq_status < 0) { 144 phy_error(phydev); 145 return IRQ_NONE; 146 } 147 148 if (!(irq_status & MII_LXT971_ISR_MASK)) 149 return IRQ_NONE; 150 151 phy_trigger_machine(phydev); 152 153 return IRQ_HANDLED; 154 } 155 156 /* 157 * A2 version of LXT973 chip has an ERRATA: it randomly return the contents 158 * of the previous even register when you read a odd register regularly 159 */ 160 161 static int lxt973a2_update_link(struct phy_device *phydev) 162 { 163 int status; 164 int control; 165 int retry = 8; /* we try 8 times */ 166 167 /* Do a fake read */ 168 status = phy_read(phydev, MII_BMSR); 169 170 if (status < 0) 171 return status; 172 173 control = phy_read(phydev, MII_BMCR); 174 if (control < 0) 175 return control; 176 177 do { 178 /* Read link and autonegotiation status */ 179 status = phy_read(phydev, MII_BMSR); 180 } while (status >= 0 && retry-- && status == control); 181 182 if (status < 0) 183 return status; 184 185 if ((status & BMSR_LSTATUS) == 0) 186 phydev->link = 0; 187 else 188 phydev->link = 1; 189 190 return 0; 191 } 192 193 static int lxt973a2_read_status(struct phy_device *phydev) 194 { 195 int adv; 196 int err; 197 int lpa; 198 199 /* Update the link, but return if there was an error */ 200 err = lxt973a2_update_link(phydev); 201 if (err) 202 return err; 203 204 if (AUTONEG_ENABLE == phydev->autoneg) { 205 int retry = 1; 206 207 adv = phy_read(phydev, MII_ADVERTISE); 208 209 if (adv < 0) 210 return adv; 211 212 do { 213 lpa = phy_read(phydev, MII_LPA); 214 215 if (lpa < 0) 216 return lpa; 217 218 /* If both registers are equal, it is suspect but not 219 * impossible, hence a new try 220 */ 221 } while (lpa == adv && retry--); 222 223 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa); 224 225 lpa &= adv; 226 227 phydev->speed = SPEED_10; 228 phydev->duplex = DUPLEX_HALF; 229 phydev->pause = phydev->asym_pause = 0; 230 231 if (lpa & (LPA_100FULL | LPA_100HALF)) { 232 phydev->speed = SPEED_100; 233 234 if (lpa & LPA_100FULL) 235 phydev->duplex = DUPLEX_FULL; 236 } else { 237 if (lpa & LPA_10FULL) 238 phydev->duplex = DUPLEX_FULL; 239 } 240 241 phy_resolve_aneg_pause(phydev); 242 } else { 243 err = genphy_read_status_fixed(phydev); 244 if (err < 0) 245 return err; 246 247 phydev->pause = phydev->asym_pause = 0; 248 linkmode_zero(phydev->lp_advertising); 249 } 250 251 return 0; 252 } 253 254 static int lxt973_probe(struct phy_device *phydev) 255 { 256 int val = phy_read(phydev, MII_LXT973_PCR); 257 258 if (val & PCR_FIBER_SELECT) { 259 /* 260 * If fiber is selected, then the only correct setting 261 * is 100Mbps, full duplex, and auto negotiation off. 262 */ 263 val = phy_read(phydev, MII_BMCR); 264 val |= (BMCR_SPEED100 | BMCR_FULLDPLX); 265 val &= ~BMCR_ANENABLE; 266 phy_write(phydev, MII_BMCR, val); 267 /* Remember that the port is in fiber mode. */ 268 phydev->priv = lxt973_probe; 269 } else { 270 phydev->priv = NULL; 271 } 272 return 0; 273 } 274 275 static int lxt973_config_aneg(struct phy_device *phydev) 276 { 277 /* Do nothing if port is in fiber mode. */ 278 return phydev->priv ? 0 : genphy_config_aneg(phydev); 279 } 280 281 static struct phy_driver lxt97x_driver[] = { 282 { 283 .phy_id = 0x78100000, 284 .name = "LXT970", 285 .phy_id_mask = 0xfffffff0, 286 /* PHY_BASIC_FEATURES */ 287 .config_init = lxt970_config_init, 288 .ack_interrupt = lxt970_ack_interrupt, 289 .config_intr = lxt970_config_intr, 290 .handle_interrupt = lxt970_handle_interrupt, 291 }, { 292 .phy_id = 0x001378e0, 293 .name = "LXT971", 294 .phy_id_mask = 0xfffffff0, 295 /* PHY_BASIC_FEATURES */ 296 .ack_interrupt = lxt971_ack_interrupt, 297 .config_intr = lxt971_config_intr, 298 .handle_interrupt = lxt971_handle_interrupt, 299 .suspend = genphy_suspend, 300 .resume = genphy_resume, 301 }, { 302 .phy_id = 0x00137a10, 303 .name = "LXT973-A2", 304 .phy_id_mask = 0xffffffff, 305 /* PHY_BASIC_FEATURES */ 306 .flags = 0, 307 .probe = lxt973_probe, 308 .config_aneg = lxt973_config_aneg, 309 .read_status = lxt973a2_read_status, 310 .suspend = genphy_suspend, 311 .resume = genphy_resume, 312 }, { 313 .phy_id = 0x00137a10, 314 .name = "LXT973", 315 .phy_id_mask = 0xfffffff0, 316 /* PHY_BASIC_FEATURES */ 317 .flags = 0, 318 .probe = lxt973_probe, 319 .config_aneg = lxt973_config_aneg, 320 .suspend = genphy_suspend, 321 .resume = genphy_resume, 322 } }; 323 324 module_phy_driver(lxt97x_driver); 325 326 static struct mdio_device_id __maybe_unused lxt_tbl[] = { 327 { 0x78100000, 0xfffffff0 }, 328 { 0x001378e0, 0xfffffff0 }, 329 { 0x00137a10, 0xfffffff0 }, 330 { } 331 }; 332 333 MODULE_DEVICE_TABLE(mdio, lxt_tbl); 334