1*2c7b9b93SAlex Elder // SPDX-License-Identifier: GPL-2.0 2*2c7b9b93SAlex Elder 3*2c7b9b93SAlex Elder /* Copyright (C) 2021 Linaro Ltd. */ 4*2c7b9b93SAlex Elder 5*2c7b9b93SAlex Elder #include <linux/log2.h> 6*2c7b9b93SAlex Elder 7*2c7b9b93SAlex Elder #include "gsi.h" 8*2c7b9b93SAlex Elder #include "ipa_data.h" 9*2c7b9b93SAlex Elder #include "ipa_endpoint.h" 10*2c7b9b93SAlex Elder #include "ipa_mem.h" 11*2c7b9b93SAlex Elder 12*2c7b9b93SAlex Elder /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */ 13*2c7b9b93SAlex Elder enum ipa_resource_type { 14*2c7b9b93SAlex Elder /* Source resource types; first must have value 0 */ 15*2c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 16*2c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 17*2c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 18*2c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 19*2c7b9b93SAlex Elder IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 20*2c7b9b93SAlex Elder 21*2c7b9b93SAlex Elder /* Destination resource types; first must have value 0 */ 22*2c7b9b93SAlex Elder IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 23*2c7b9b93SAlex Elder IPA_RESOURCE_TYPE_DST_DPS_DMARS, 24*2c7b9b93SAlex Elder }; 25*2c7b9b93SAlex Elder 26*2c7b9b93SAlex Elder /* Resource groups used for an SoC having IPA v4.5 */ 27*2c7b9b93SAlex Elder enum ipa_rsrc_group_id { 28*2c7b9b93SAlex Elder /* Source resource group identifiers */ 29*2c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_0 = 0, 30*2c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UL_DL, 31*2c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_2, 32*2c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_3, 33*2c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_UC_RX_Q, 34*2c7b9b93SAlex Elder IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 35*2c7b9b93SAlex Elder 36*2c7b9b93SAlex Elder /* Destination resource group identifiers */ 37*2c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UNUSED_0 = 0, 38*2c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UL_DL_DPL, 39*2c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UNUSED_2, 40*2c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UNUSED_3, 41*2c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_UC, 42*2c7b9b93SAlex Elder IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 43*2c7b9b93SAlex Elder }; 44*2c7b9b93SAlex Elder 45*2c7b9b93SAlex Elder /* QSB configuration data for an SoC having IPA v4.5 */ 46*2c7b9b93SAlex Elder static const struct ipa_qsb_data ipa_qsb_data[] = { 47*2c7b9b93SAlex Elder [IPA_QSB_MASTER_DDR] = { 48*2c7b9b93SAlex Elder .max_writes = 8, 49*2c7b9b93SAlex Elder .max_reads = 0, /* no limit (hardware max) */ 50*2c7b9b93SAlex Elder .max_reads_beats = 120, 51*2c7b9b93SAlex Elder }, 52*2c7b9b93SAlex Elder [IPA_QSB_MASTER_PCIE] = { 53*2c7b9b93SAlex Elder .max_writes = 8, 54*2c7b9b93SAlex Elder .max_reads = 12, 55*2c7b9b93SAlex Elder /* no outstanding read byte (beat) limit */ 56*2c7b9b93SAlex Elder }, 57*2c7b9b93SAlex Elder }; 58*2c7b9b93SAlex Elder 59*2c7b9b93SAlex Elder /* Endpoint configuration data for an SoC having IPA v4.5 */ 60*2c7b9b93SAlex Elder static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 61*2c7b9b93SAlex Elder [IPA_ENDPOINT_AP_COMMAND_TX] = { 62*2c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 63*2c7b9b93SAlex Elder .channel_id = 9, 64*2c7b9b93SAlex Elder .endpoint_id = 7, 65*2c7b9b93SAlex Elder .toward_ipa = true, 66*2c7b9b93SAlex Elder .channel = { 67*2c7b9b93SAlex Elder .tre_count = 256, 68*2c7b9b93SAlex Elder .event_count = 256, 69*2c7b9b93SAlex Elder .tlv_count = 20, 70*2c7b9b93SAlex Elder }, 71*2c7b9b93SAlex Elder .endpoint = { 72*2c7b9b93SAlex Elder .config = { 73*2c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 74*2c7b9b93SAlex Elder .dma_mode = true, 75*2c7b9b93SAlex Elder .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 76*2c7b9b93SAlex Elder .tx = { 77*2c7b9b93SAlex Elder .seq_type = IPA_SEQ_DMA, 78*2c7b9b93SAlex Elder }, 79*2c7b9b93SAlex Elder }, 80*2c7b9b93SAlex Elder }, 81*2c7b9b93SAlex Elder }, 82*2c7b9b93SAlex Elder [IPA_ENDPOINT_AP_LAN_RX] = { 83*2c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 84*2c7b9b93SAlex Elder .channel_id = 10, 85*2c7b9b93SAlex Elder .endpoint_id = 16, 86*2c7b9b93SAlex Elder .toward_ipa = false, 87*2c7b9b93SAlex Elder .channel = { 88*2c7b9b93SAlex Elder .tre_count = 256, 89*2c7b9b93SAlex Elder .event_count = 256, 90*2c7b9b93SAlex Elder .tlv_count = 9, 91*2c7b9b93SAlex Elder }, 92*2c7b9b93SAlex Elder .endpoint = { 93*2c7b9b93SAlex Elder .config = { 94*2c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 95*2c7b9b93SAlex Elder .aggregation = true, 96*2c7b9b93SAlex Elder .status_enable = true, 97*2c7b9b93SAlex Elder .rx = { 98*2c7b9b93SAlex Elder .buffer_size = 8192, 99*2c7b9b93SAlex Elder .pad_align = ilog2(sizeof(u32)), 100*2c7b9b93SAlex Elder .aggr_time_limit = 500, 101*2c7b9b93SAlex Elder }, 102*2c7b9b93SAlex Elder }, 103*2c7b9b93SAlex Elder }, 104*2c7b9b93SAlex Elder }, 105*2c7b9b93SAlex Elder [IPA_ENDPOINT_AP_MODEM_TX] = { 106*2c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 107*2c7b9b93SAlex Elder .channel_id = 7, 108*2c7b9b93SAlex Elder .endpoint_id = 2, 109*2c7b9b93SAlex Elder .toward_ipa = true, 110*2c7b9b93SAlex Elder .channel = { 111*2c7b9b93SAlex Elder .tre_count = 512, 112*2c7b9b93SAlex Elder .event_count = 512, 113*2c7b9b93SAlex Elder .tlv_count = 16, 114*2c7b9b93SAlex Elder }, 115*2c7b9b93SAlex Elder .endpoint = { 116*2c7b9b93SAlex Elder .filter_support = true, 117*2c7b9b93SAlex Elder .config = { 118*2c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 119*2c7b9b93SAlex Elder .checksum = true, 120*2c7b9b93SAlex Elder .qmap = true, 121*2c7b9b93SAlex Elder .status_enable = true, 122*2c7b9b93SAlex Elder .tx = { 123*2c7b9b93SAlex Elder .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 124*2c7b9b93SAlex Elder .status_endpoint = 125*2c7b9b93SAlex Elder IPA_ENDPOINT_MODEM_AP_RX, 126*2c7b9b93SAlex Elder }, 127*2c7b9b93SAlex Elder }, 128*2c7b9b93SAlex Elder }, 129*2c7b9b93SAlex Elder }, 130*2c7b9b93SAlex Elder [IPA_ENDPOINT_AP_MODEM_RX] = { 131*2c7b9b93SAlex Elder .ee_id = GSI_EE_AP, 132*2c7b9b93SAlex Elder .channel_id = 1, 133*2c7b9b93SAlex Elder .endpoint_id = 14, 134*2c7b9b93SAlex Elder .toward_ipa = false, 135*2c7b9b93SAlex Elder .channel = { 136*2c7b9b93SAlex Elder .tre_count = 256, 137*2c7b9b93SAlex Elder .event_count = 256, 138*2c7b9b93SAlex Elder .tlv_count = 9, 139*2c7b9b93SAlex Elder }, 140*2c7b9b93SAlex Elder .endpoint = { 141*2c7b9b93SAlex Elder .config = { 142*2c7b9b93SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 143*2c7b9b93SAlex Elder .checksum = true, 144*2c7b9b93SAlex Elder .qmap = true, 145*2c7b9b93SAlex Elder .aggregation = true, 146*2c7b9b93SAlex Elder .rx = { 147*2c7b9b93SAlex Elder .buffer_size = 8192, 148*2c7b9b93SAlex Elder .aggr_time_limit = 500, 149*2c7b9b93SAlex Elder .aggr_close_eof = true, 150*2c7b9b93SAlex Elder }, 151*2c7b9b93SAlex Elder }, 152*2c7b9b93SAlex Elder }, 153*2c7b9b93SAlex Elder }, 154*2c7b9b93SAlex Elder [IPA_ENDPOINT_MODEM_AP_TX] = { 155*2c7b9b93SAlex Elder .ee_id = GSI_EE_MODEM, 156*2c7b9b93SAlex Elder .channel_id = 0, 157*2c7b9b93SAlex Elder .endpoint_id = 5, 158*2c7b9b93SAlex Elder .toward_ipa = true, 159*2c7b9b93SAlex Elder .endpoint = { 160*2c7b9b93SAlex Elder .filter_support = true, 161*2c7b9b93SAlex Elder }, 162*2c7b9b93SAlex Elder }, 163*2c7b9b93SAlex Elder [IPA_ENDPOINT_MODEM_AP_RX] = { 164*2c7b9b93SAlex Elder .ee_id = GSI_EE_MODEM, 165*2c7b9b93SAlex Elder .channel_id = 7, 166*2c7b9b93SAlex Elder .endpoint_id = 21, 167*2c7b9b93SAlex Elder .toward_ipa = false, 168*2c7b9b93SAlex Elder }, 169*2c7b9b93SAlex Elder [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 170*2c7b9b93SAlex Elder .ee_id = GSI_EE_MODEM, 171*2c7b9b93SAlex Elder .channel_id = 2, 172*2c7b9b93SAlex Elder .endpoint_id = 8, 173*2c7b9b93SAlex Elder .toward_ipa = true, 174*2c7b9b93SAlex Elder .endpoint = { 175*2c7b9b93SAlex Elder .filter_support = true, 176*2c7b9b93SAlex Elder }, 177*2c7b9b93SAlex Elder }, 178*2c7b9b93SAlex Elder }; 179*2c7b9b93SAlex Elder 180*2c7b9b93SAlex Elder /* Source resource configuration data for an SoC having IPA v4.5 */ 181*2c7b9b93SAlex Elder static const struct ipa_resource ipa_resource_src[] = { 182*2c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 183*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 184*2c7b9b93SAlex Elder .min = 1, .max = 11, 185*2c7b9b93SAlex Elder }, 186*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 187*2c7b9b93SAlex Elder .min = 1, .max = 63, 188*2c7b9b93SAlex Elder }, 189*2c7b9b93SAlex Elder }, 190*2c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 191*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 192*2c7b9b93SAlex Elder .min = 14, .max = 14, 193*2c7b9b93SAlex Elder }, 194*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 195*2c7b9b93SAlex Elder .min = 3, .max = 3, 196*2c7b9b93SAlex Elder }, 197*2c7b9b93SAlex Elder }, 198*2c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 199*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 200*2c7b9b93SAlex Elder .min = 18, .max = 18, 201*2c7b9b93SAlex Elder }, 202*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 203*2c7b9b93SAlex Elder .min = 8, .max = 8, 204*2c7b9b93SAlex Elder }, 205*2c7b9b93SAlex Elder }, 206*2c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 207*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = { 208*2c7b9b93SAlex Elder .min = 0, .max = 63, 209*2c7b9b93SAlex Elder }, 210*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 211*2c7b9b93SAlex Elder .min = 0, .max = 63, 212*2c7b9b93SAlex Elder }, 213*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = { 214*2c7b9b93SAlex Elder .min = 0, .max = 63, 215*2c7b9b93SAlex Elder }, 216*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = { 217*2c7b9b93SAlex Elder .min = 0, .max = 63, 218*2c7b9b93SAlex Elder }, 219*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 220*2c7b9b93SAlex Elder .min = 0, .max = 63, 221*2c7b9b93SAlex Elder }, 222*2c7b9b93SAlex Elder }, 223*2c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 224*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 225*2c7b9b93SAlex Elder .min = 24, .max = 24, 226*2c7b9b93SAlex Elder }, 227*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { 228*2c7b9b93SAlex Elder .min = 8, .max = 8, 229*2c7b9b93SAlex Elder }, 230*2c7b9b93SAlex Elder }, 231*2c7b9b93SAlex Elder }; 232*2c7b9b93SAlex Elder 233*2c7b9b93SAlex Elder /* Destination resource configuration data for an SoC having IPA v4.5 */ 234*2c7b9b93SAlex Elder static const struct ipa_resource ipa_resource_dst[] = { 235*2c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 236*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 237*2c7b9b93SAlex Elder .min = 16, .max = 16, 238*2c7b9b93SAlex Elder }, 239*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { 240*2c7b9b93SAlex Elder .min = 2, .max = 2, 241*2c7b9b93SAlex Elder }, 242*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { 243*2c7b9b93SAlex Elder .min = 2, .max = 2, 244*2c7b9b93SAlex Elder }, 245*2c7b9b93SAlex Elder }, 246*2c7b9b93SAlex Elder [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 247*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 248*2c7b9b93SAlex Elder .min = 2, .max = 63, 249*2c7b9b93SAlex Elder }, 250*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = { 251*2c7b9b93SAlex Elder .min = 1, .max = 2, 252*2c7b9b93SAlex Elder }, 253*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = { 254*2c7b9b93SAlex Elder .min = 1, .max = 2, 255*2c7b9b93SAlex Elder }, 256*2c7b9b93SAlex Elder .limits[IPA_RSRC_GROUP_DST_UC] = { 257*2c7b9b93SAlex Elder .min = 0, .max = 2, 258*2c7b9b93SAlex Elder }, 259*2c7b9b93SAlex Elder }, 260*2c7b9b93SAlex Elder }; 261*2c7b9b93SAlex Elder 262*2c7b9b93SAlex Elder /* Resource configuration data for an SoC having IPA v4.5 */ 263*2c7b9b93SAlex Elder static const struct ipa_resource_data ipa_resource_data = { 264*2c7b9b93SAlex Elder .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 265*2c7b9b93SAlex Elder .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 266*2c7b9b93SAlex Elder .resource_src_count = ARRAY_SIZE(ipa_resource_src), 267*2c7b9b93SAlex Elder .resource_src = ipa_resource_src, 268*2c7b9b93SAlex Elder .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 269*2c7b9b93SAlex Elder .resource_dst = ipa_resource_dst, 270*2c7b9b93SAlex Elder }; 271*2c7b9b93SAlex Elder 272*2c7b9b93SAlex Elder /* IPA-resident memory region data for an SoC having IPA v4.5 */ 273*2c7b9b93SAlex Elder static const struct ipa_mem ipa_mem_local_data[] = { 274*2c7b9b93SAlex Elder { 275*2c7b9b93SAlex Elder .id = IPA_MEM_UC_SHARED, 276*2c7b9b93SAlex Elder .offset = 0x0000, 277*2c7b9b93SAlex Elder .size = 0x0080, 278*2c7b9b93SAlex Elder .canary_count = 0, 279*2c7b9b93SAlex Elder }, 280*2c7b9b93SAlex Elder { 281*2c7b9b93SAlex Elder .id = IPA_MEM_UC_INFO, 282*2c7b9b93SAlex Elder .offset = 0x0080, 283*2c7b9b93SAlex Elder .size = 0x0200, 284*2c7b9b93SAlex Elder .canary_count = 0, 285*2c7b9b93SAlex Elder }, 286*2c7b9b93SAlex Elder { 287*2c7b9b93SAlex Elder .id = IPA_MEM_V4_FILTER_HASHED, 288*2c7b9b93SAlex Elder .offset = 0x0288, 289*2c7b9b93SAlex Elder .size = 0x0078, 290*2c7b9b93SAlex Elder .canary_count = 2, 291*2c7b9b93SAlex Elder }, 292*2c7b9b93SAlex Elder { 293*2c7b9b93SAlex Elder .id = IPA_MEM_V4_FILTER, 294*2c7b9b93SAlex Elder .offset = 0x0308, 295*2c7b9b93SAlex Elder .size = 0x0078, 296*2c7b9b93SAlex Elder .canary_count = 2, 297*2c7b9b93SAlex Elder }, 298*2c7b9b93SAlex Elder { 299*2c7b9b93SAlex Elder .id = IPA_MEM_V6_FILTER_HASHED, 300*2c7b9b93SAlex Elder .offset = 0x0388, 301*2c7b9b93SAlex Elder .size = 0x0078, 302*2c7b9b93SAlex Elder .canary_count = 2, 303*2c7b9b93SAlex Elder }, 304*2c7b9b93SAlex Elder { 305*2c7b9b93SAlex Elder .id = IPA_MEM_V6_FILTER, 306*2c7b9b93SAlex Elder .offset = 0x0408, 307*2c7b9b93SAlex Elder .size = 0x0078, 308*2c7b9b93SAlex Elder .canary_count = 2, 309*2c7b9b93SAlex Elder }, 310*2c7b9b93SAlex Elder { 311*2c7b9b93SAlex Elder .id = IPA_MEM_V4_ROUTE_HASHED, 312*2c7b9b93SAlex Elder .offset = 0x0488, 313*2c7b9b93SAlex Elder .size = 0x0078, 314*2c7b9b93SAlex Elder .canary_count = 2, 315*2c7b9b93SAlex Elder }, 316*2c7b9b93SAlex Elder { 317*2c7b9b93SAlex Elder .id = IPA_MEM_V4_ROUTE, 318*2c7b9b93SAlex Elder .offset = 0x0508, 319*2c7b9b93SAlex Elder .size = 0x0078, 320*2c7b9b93SAlex Elder .canary_count = 2, 321*2c7b9b93SAlex Elder }, 322*2c7b9b93SAlex Elder { 323*2c7b9b93SAlex Elder .id = IPA_MEM_V6_ROUTE_HASHED, 324*2c7b9b93SAlex Elder .offset = 0x0588, 325*2c7b9b93SAlex Elder .size = 0x0078, 326*2c7b9b93SAlex Elder .canary_count = 2, 327*2c7b9b93SAlex Elder }, 328*2c7b9b93SAlex Elder { 329*2c7b9b93SAlex Elder .id = IPA_MEM_V6_ROUTE, 330*2c7b9b93SAlex Elder .offset = 0x0608, 331*2c7b9b93SAlex Elder .size = 0x0078, 332*2c7b9b93SAlex Elder .canary_count = 2, 333*2c7b9b93SAlex Elder }, 334*2c7b9b93SAlex Elder { 335*2c7b9b93SAlex Elder .id = IPA_MEM_MODEM_HEADER, 336*2c7b9b93SAlex Elder .offset = 0x0688, 337*2c7b9b93SAlex Elder .size = 0x0240, 338*2c7b9b93SAlex Elder .canary_count = 2, 339*2c7b9b93SAlex Elder }, 340*2c7b9b93SAlex Elder { 341*2c7b9b93SAlex Elder .id = IPA_MEM_AP_HEADER, 342*2c7b9b93SAlex Elder .offset = 0x08c8, 343*2c7b9b93SAlex Elder .size = 0x0200, 344*2c7b9b93SAlex Elder .canary_count = 0, 345*2c7b9b93SAlex Elder }, 346*2c7b9b93SAlex Elder { 347*2c7b9b93SAlex Elder .id = IPA_MEM_MODEM_PROC_CTX, 348*2c7b9b93SAlex Elder .offset = 0x0ad0, 349*2c7b9b93SAlex Elder .size = 0x0b20, 350*2c7b9b93SAlex Elder .canary_count = 2, 351*2c7b9b93SAlex Elder }, 352*2c7b9b93SAlex Elder { 353*2c7b9b93SAlex Elder .id = IPA_MEM_AP_PROC_CTX, 354*2c7b9b93SAlex Elder .offset = 0x15f0, 355*2c7b9b93SAlex Elder .size = 0x0200, 356*2c7b9b93SAlex Elder .canary_count = 0, 357*2c7b9b93SAlex Elder }, 358*2c7b9b93SAlex Elder { 359*2c7b9b93SAlex Elder .id = IPA_MEM_NAT_TABLE, 360*2c7b9b93SAlex Elder .offset = 0x1800, 361*2c7b9b93SAlex Elder .size = 0x0d00, 362*2c7b9b93SAlex Elder .canary_count = 4, 363*2c7b9b93SAlex Elder }, 364*2c7b9b93SAlex Elder { 365*2c7b9b93SAlex Elder .id = IPA_MEM_STATS_QUOTA_MODEM, 366*2c7b9b93SAlex Elder .offset = 0x2510, 367*2c7b9b93SAlex Elder .size = 0x0030, 368*2c7b9b93SAlex Elder .canary_count = 4, 369*2c7b9b93SAlex Elder }, 370*2c7b9b93SAlex Elder { 371*2c7b9b93SAlex Elder .id = IPA_MEM_STATS_QUOTA_AP, 372*2c7b9b93SAlex Elder .offset = 0x2540, 373*2c7b9b93SAlex Elder .size = 0x0048, 374*2c7b9b93SAlex Elder .canary_count = 0, 375*2c7b9b93SAlex Elder }, 376*2c7b9b93SAlex Elder { 377*2c7b9b93SAlex Elder .id = IPA_MEM_STATS_TETHERING, 378*2c7b9b93SAlex Elder .offset = 0x2588, 379*2c7b9b93SAlex Elder .size = 0x0238, 380*2c7b9b93SAlex Elder .canary_count = 0, 381*2c7b9b93SAlex Elder }, 382*2c7b9b93SAlex Elder { 383*2c7b9b93SAlex Elder .id = IPA_MEM_STATS_FILTER_ROUTE, 384*2c7b9b93SAlex Elder .offset = 0x27c0, 385*2c7b9b93SAlex Elder .size = 0x0800, 386*2c7b9b93SAlex Elder .canary_count = 0, 387*2c7b9b93SAlex Elder }, 388*2c7b9b93SAlex Elder { 389*2c7b9b93SAlex Elder .id = IPA_MEM_STATS_DROP, 390*2c7b9b93SAlex Elder .offset = 0x2fc0, 391*2c7b9b93SAlex Elder .size = 0x0020, 392*2c7b9b93SAlex Elder .canary_count = 0, 393*2c7b9b93SAlex Elder }, 394*2c7b9b93SAlex Elder { 395*2c7b9b93SAlex Elder .id = IPA_MEM_MODEM, 396*2c7b9b93SAlex Elder .offset = 0x2fe8, 397*2c7b9b93SAlex Elder .size = 0x0800, 398*2c7b9b93SAlex Elder .canary_count = 2, 399*2c7b9b93SAlex Elder }, 400*2c7b9b93SAlex Elder { 401*2c7b9b93SAlex Elder .id = IPA_MEM_UC_EVENT_RING, 402*2c7b9b93SAlex Elder .offset = 0x3800, 403*2c7b9b93SAlex Elder .size = 0x1000, 404*2c7b9b93SAlex Elder .canary_count = 1, 405*2c7b9b93SAlex Elder }, 406*2c7b9b93SAlex Elder { 407*2c7b9b93SAlex Elder .id = IPA_MEM_PDN_CONFIG, 408*2c7b9b93SAlex Elder .offset = 0x4800, 409*2c7b9b93SAlex Elder .size = 0x0050, 410*2c7b9b93SAlex Elder .canary_count = 0, 411*2c7b9b93SAlex Elder }, 412*2c7b9b93SAlex Elder }; 413*2c7b9b93SAlex Elder 414*2c7b9b93SAlex Elder /* Memory configuration data for an SoC having IPA v4.5 */ 415*2c7b9b93SAlex Elder static const struct ipa_mem_data ipa_mem_data = { 416*2c7b9b93SAlex Elder .local_count = ARRAY_SIZE(ipa_mem_local_data), 417*2c7b9b93SAlex Elder .local = ipa_mem_local_data, 418*2c7b9b93SAlex Elder .imem_addr = 0x14688000, 419*2c7b9b93SAlex Elder .imem_size = 0x00003000, 420*2c7b9b93SAlex Elder .smem_id = 497, 421*2c7b9b93SAlex Elder .smem_size = 0x00009000, 422*2c7b9b93SAlex Elder }; 423*2c7b9b93SAlex Elder 424*2c7b9b93SAlex Elder /* Interconnect rates are in 1000 byte/second units */ 425*2c7b9b93SAlex Elder static const struct ipa_interconnect_data ipa_interconnect_data[] = { 426*2c7b9b93SAlex Elder { 427*2c7b9b93SAlex Elder .name = "memory", 428*2c7b9b93SAlex Elder .peak_bandwidth = 600000, /* 600 MBps */ 429*2c7b9b93SAlex Elder .average_bandwidth = 150000, /* 150 MBps */ 430*2c7b9b93SAlex Elder }, 431*2c7b9b93SAlex Elder /* Average rate is unused for the next two interconnects */ 432*2c7b9b93SAlex Elder { 433*2c7b9b93SAlex Elder .name = "imem", 434*2c7b9b93SAlex Elder .peak_bandwidth = 450000, /* 450 MBps */ 435*2c7b9b93SAlex Elder .average_bandwidth = 75000, /* 75 MBps (unused?) */ 436*2c7b9b93SAlex Elder }, 437*2c7b9b93SAlex Elder { 438*2c7b9b93SAlex Elder .name = "config", 439*2c7b9b93SAlex Elder .peak_bandwidth = 171400, /* 171.4 MBps */ 440*2c7b9b93SAlex Elder .average_bandwidth = 0, /* unused */ 441*2c7b9b93SAlex Elder }, 442*2c7b9b93SAlex Elder }; 443*2c7b9b93SAlex Elder 444*2c7b9b93SAlex Elder /* Clock and interconnect configuration data for an SoC having IPA v4.5 */ 445*2c7b9b93SAlex Elder static const struct ipa_power_data ipa_power_data = { 446*2c7b9b93SAlex Elder .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */ 447*2c7b9b93SAlex Elder .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 448*2c7b9b93SAlex Elder .interconnect_data = ipa_interconnect_data, 449*2c7b9b93SAlex Elder }; 450*2c7b9b93SAlex Elder 451*2c7b9b93SAlex Elder /* Configuration data for an SoC having IPA v4.5 */ 452*2c7b9b93SAlex Elder const struct ipa_data ipa_data_v4_5 = { 453*2c7b9b93SAlex Elder .version = IPA_VERSION_4_5, 454*2c7b9b93SAlex Elder .qsb_count = ARRAY_SIZE(ipa_qsb_data), 455*2c7b9b93SAlex Elder .qsb_data = ipa_qsb_data, 456*2c7b9b93SAlex Elder .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 457*2c7b9b93SAlex Elder .endpoint_data = ipa_gsi_endpoint_data, 458*2c7b9b93SAlex Elder .resource_data = &ipa_resource_data, 459*2c7b9b93SAlex Elder .mem_data = &ipa_mem_data, 460*2c7b9b93SAlex Elder .power_data = &ipa_power_data, 461*2c7b9b93SAlex Elder }; 462