1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #ifndef _IONIC_DEV_H_ 5 #define _IONIC_DEV_H_ 6 7 #include <linux/atomic.h> 8 #include <linux/mutex.h> 9 #include <linux/workqueue.h> 10 #include <linux/skbuff.h> 11 #include <linux/bpf_trace.h> 12 13 #include "ionic_if.h" 14 #include "ionic_regs.h" 15 16 #define IONIC_MAX_TX_DESC 8192 17 #define IONIC_MAX_RX_DESC 16384 18 #define IONIC_MIN_TXRX_DESC 64 19 #define IONIC_DEF_TXRX_DESC 4096 20 #define IONIC_RX_FILL_THRESHOLD 16 21 #define IONIC_RX_FILL_DIV 8 22 #define IONIC_LIFS_MAX 1024 23 #define IONIC_WATCHDOG_SECS 5 24 #define IONIC_ITR_COAL_USEC_DEFAULT 64 25 26 #define IONIC_DEV_CMD_REG_VERSION 1 27 #define IONIC_DEV_INFO_REG_COUNT 32 28 #define IONIC_DEV_CMD_REG_COUNT 32 29 30 #define IONIC_NAPI_DEADLINE (HZ / 200) /* 5ms */ 31 #define IONIC_ADMIN_DOORBELL_DEADLINE (HZ / 2) /* 500ms */ 32 #define IONIC_TX_DOORBELL_DEADLINE (HZ / 100) /* 10ms */ 33 #define IONIC_RX_MIN_DOORBELL_DEADLINE (HZ / 100) /* 10ms */ 34 #define IONIC_RX_MAX_DOORBELL_DEADLINE (HZ * 5) /* 5s */ 35 36 struct ionic_dev_bar { 37 void __iomem *vaddr; 38 phys_addr_t bus_addr; 39 unsigned long len; 40 int res_index; 41 }; 42 43 #ifndef __CHECKER__ 44 /* Registers */ 45 static_assert(sizeof(struct ionic_intr) == 32); 46 47 static_assert(sizeof(struct ionic_doorbell) == 8); 48 static_assert(sizeof(struct ionic_intr_status) == 8); 49 static_assert(sizeof(union ionic_dev_regs) == 4096); 50 static_assert(sizeof(union ionic_dev_info_regs) == 2048); 51 static_assert(sizeof(union ionic_dev_cmd_regs) == 2048); 52 static_assert(sizeof(struct ionic_lif_stats) == 1024); 53 54 static_assert(sizeof(struct ionic_admin_cmd) == 64); 55 static_assert(sizeof(struct ionic_admin_comp) == 16); 56 static_assert(sizeof(struct ionic_nop_cmd) == 64); 57 static_assert(sizeof(struct ionic_nop_comp) == 16); 58 59 /* Device commands */ 60 static_assert(sizeof(struct ionic_dev_identify_cmd) == 64); 61 static_assert(sizeof(struct ionic_dev_identify_comp) == 16); 62 static_assert(sizeof(struct ionic_dev_init_cmd) == 64); 63 static_assert(sizeof(struct ionic_dev_init_comp) == 16); 64 static_assert(sizeof(struct ionic_dev_reset_cmd) == 64); 65 static_assert(sizeof(struct ionic_dev_reset_comp) == 16); 66 static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64); 67 static_assert(sizeof(struct ionic_dev_getattr_comp) == 16); 68 static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64); 69 static_assert(sizeof(struct ionic_dev_setattr_comp) == 16); 70 static_assert(sizeof(struct ionic_lif_setphc_cmd) == 64); 71 72 /* Port commands */ 73 static_assert(sizeof(struct ionic_port_identify_cmd) == 64); 74 static_assert(sizeof(struct ionic_port_identify_comp) == 16); 75 static_assert(sizeof(struct ionic_port_init_cmd) == 64); 76 static_assert(sizeof(struct ionic_port_init_comp) == 16); 77 static_assert(sizeof(struct ionic_port_reset_cmd) == 64); 78 static_assert(sizeof(struct ionic_port_reset_comp) == 16); 79 static_assert(sizeof(struct ionic_port_getattr_cmd) == 64); 80 static_assert(sizeof(struct ionic_port_getattr_comp) == 16); 81 static_assert(sizeof(struct ionic_port_setattr_cmd) == 64); 82 static_assert(sizeof(struct ionic_port_setattr_comp) == 16); 83 84 /* LIF commands */ 85 static_assert(sizeof(struct ionic_lif_init_cmd) == 64); 86 static_assert(sizeof(struct ionic_lif_init_comp) == 16); 87 static_assert(sizeof(struct ionic_lif_reset_cmd) == 64); 88 static_assert(sizeof(ionic_lif_reset_comp) == 16); 89 static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64); 90 static_assert(sizeof(struct ionic_lif_getattr_comp) == 16); 91 static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64); 92 static_assert(sizeof(struct ionic_lif_setattr_comp) == 16); 93 94 static_assert(sizeof(struct ionic_q_init_cmd) == 64); 95 static_assert(sizeof(struct ionic_q_init_comp) == 16); 96 static_assert(sizeof(struct ionic_q_control_cmd) == 64); 97 static_assert(sizeof(ionic_q_control_comp) == 16); 98 static_assert(sizeof(struct ionic_q_identify_cmd) == 64); 99 static_assert(sizeof(struct ionic_q_identify_comp) == 16); 100 101 static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64); 102 static_assert(sizeof(ionic_rx_mode_set_comp) == 16); 103 static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64); 104 static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16); 105 static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64); 106 static_assert(sizeof(ionic_rx_filter_del_comp) == 16); 107 108 /* RDMA commands */ 109 static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64); 110 static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64); 111 112 /* Events */ 113 static_assert(sizeof(struct ionic_notifyq_cmd) == 4); 114 static_assert(sizeof(union ionic_notifyq_comp) == 64); 115 static_assert(sizeof(struct ionic_notifyq_event) == 64); 116 static_assert(sizeof(struct ionic_link_change_event) == 64); 117 static_assert(sizeof(struct ionic_reset_event) == 64); 118 static_assert(sizeof(struct ionic_heartbeat_event) == 64); 119 static_assert(sizeof(struct ionic_log_event) == 64); 120 121 /* I/O */ 122 static_assert(sizeof(struct ionic_txq_desc) == 16); 123 static_assert(sizeof(struct ionic_txq_sg_desc) == 128); 124 static_assert(sizeof(struct ionic_txq_comp) == 16); 125 126 static_assert(sizeof(struct ionic_rxq_desc) == 16); 127 static_assert(sizeof(struct ionic_rxq_sg_desc) == 128); 128 static_assert(sizeof(struct ionic_rxq_comp) == 16); 129 130 /* SR/IOV */ 131 static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64); 132 static_assert(sizeof(struct ionic_vf_setattr_comp) == 16); 133 static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64); 134 static_assert(sizeof(struct ionic_vf_getattr_comp) == 16); 135 static_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64); 136 static_assert(sizeof(struct ionic_vf_ctrl_comp) == 16); 137 #endif /* __CHECKER__ */ 138 139 struct ionic_devinfo { 140 u8 asic_type; 141 u8 asic_rev; 142 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1]; 143 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1]; 144 }; 145 146 struct ionic_dev { 147 union ionic_dev_info_regs __iomem *dev_info_regs; 148 union ionic_dev_cmd_regs __iomem *dev_cmd_regs; 149 struct ionic_hwstamp_regs __iomem *hwstamp_regs; 150 151 atomic_long_t last_check_time; 152 unsigned long last_hb_time; 153 u32 last_fw_hb; 154 bool fw_hb_ready; 155 bool fw_status_ready; 156 u8 fw_generation; 157 u8 opcode; 158 159 u64 __iomem *db_pages; 160 dma_addr_t phy_db_pages; 161 162 struct ionic_intr __iomem *intr_ctrl; 163 u64 __iomem *intr_status; 164 165 struct mutex cmb_inuse_lock; /* for cmb_inuse */ 166 unsigned long *cmb_inuse; 167 dma_addr_t phy_cmb_pages; 168 u32 cmb_npages; 169 170 u32 port_info_sz; 171 struct ionic_port_info *port_info; 172 dma_addr_t port_info_pa; 173 174 struct ionic_devinfo dev_info; 175 }; 176 177 struct ionic_cq_info { 178 union { 179 void *cq_desc; 180 struct ionic_admin_comp *admincq; 181 struct ionic_notifyq_event *notifyq; 182 }; 183 }; 184 185 struct ionic_queue; 186 struct ionic_qcq; 187 struct ionic_desc_info; 188 189 typedef void (*ionic_desc_cb)(struct ionic_queue *q, 190 struct ionic_desc_info *desc_info, 191 struct ionic_cq_info *cq_info, void *cb_arg); 192 193 #define IONIC_MAX_BUF_LEN ((u16)-1) 194 #define IONIC_PAGE_SIZE PAGE_SIZE 195 #define IONIC_PAGE_SPLIT_SZ (PAGE_SIZE / 2) 196 #define IONIC_PAGE_GFP_MASK (GFP_ATOMIC | __GFP_NOWARN |\ 197 __GFP_COMP | __GFP_MEMALLOC) 198 199 #define IONIC_XDP_MAX_LINEAR_MTU (IONIC_PAGE_SIZE - \ 200 (VLAN_ETH_HLEN + \ 201 XDP_PACKET_HEADROOM + \ 202 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))) 203 204 struct ionic_buf_info { 205 struct page *page; 206 dma_addr_t dma_addr; 207 u32 page_offset; 208 u32 len; 209 }; 210 211 #define IONIC_MAX_FRAGS (1 + IONIC_TX_MAX_SG_ELEMS_V1) 212 213 struct ionic_desc_info { 214 union { 215 void *desc; 216 struct ionic_txq_desc *txq_desc; 217 struct ionic_rxq_desc *rxq_desc; 218 struct ionic_admin_cmd *adminq_desc; 219 }; 220 void __iomem *cmb_desc; 221 union { 222 void *sg_desc; 223 struct ionic_txq_sg_desc *txq_sg_desc; 224 struct ionic_rxq_sg_desc *rxq_sgl_desc; 225 }; 226 unsigned int bytes; 227 unsigned int nbufs; 228 struct ionic_buf_info bufs[MAX_SKB_FRAGS + 1]; 229 ionic_desc_cb cb; 230 void *cb_arg; 231 }; 232 233 #define IONIC_QUEUE_NAME_MAX_SZ 16 234 235 struct ionic_queue { 236 struct device *dev; 237 struct ionic_lif *lif; 238 struct ionic_desc_info *info; 239 u64 dbval; 240 unsigned long dbell_deadline; 241 unsigned long dbell_jiffies; 242 u16 head_idx; 243 u16 tail_idx; 244 unsigned int index; 245 unsigned int num_descs; 246 unsigned int max_sg_elems; 247 u64 features; 248 u64 drop; 249 struct ionic_dev *idev; 250 unsigned int type; 251 unsigned int hw_index; 252 unsigned int hw_type; 253 union { 254 void *base; 255 struct ionic_txq_desc *txq; 256 struct ionic_rxq_desc *rxq; 257 struct ionic_admin_cmd *adminq; 258 }; 259 void __iomem *cmb_base; 260 union { 261 void *sg_base; 262 struct ionic_txq_sg_desc *txq_sgl; 263 struct ionic_rxq_sg_desc *rxq_sgl; 264 }; 265 struct xdp_rxq_info *xdp_rxq_info; 266 dma_addr_t base_pa; 267 dma_addr_t cmb_base_pa; 268 dma_addr_t sg_base_pa; 269 unsigned int desc_size; 270 unsigned int sg_desc_size; 271 unsigned int pid; 272 char name[IONIC_QUEUE_NAME_MAX_SZ]; 273 } ____cacheline_aligned_in_smp; 274 275 #define IONIC_INTR_INDEX_NOT_ASSIGNED -1 276 #define IONIC_INTR_NAME_MAX_SZ 32 277 278 struct ionic_intr_info { 279 char name[IONIC_INTR_NAME_MAX_SZ]; 280 u64 rearm_count; 281 unsigned int index; 282 unsigned int vector; 283 unsigned int cpu; 284 u32 dim_coal_hw; 285 cpumask_t affinity_mask; 286 }; 287 288 struct ionic_cq { 289 struct ionic_lif *lif; 290 struct ionic_cq_info *info; 291 struct ionic_queue *bound_q; 292 struct ionic_intr_info *bound_intr; 293 u16 tail_idx; 294 bool done_color; 295 unsigned int num_descs; 296 unsigned int desc_size; 297 void *base; 298 dma_addr_t base_pa; 299 } ____cacheline_aligned_in_smp; 300 301 struct ionic; 302 303 static inline void ionic_intr_init(struct ionic_dev *idev, 304 struct ionic_intr_info *intr, 305 unsigned long index) 306 { 307 ionic_intr_clean(idev->intr_ctrl, index); 308 intr->index = index; 309 } 310 311 static inline unsigned int ionic_q_space_avail(struct ionic_queue *q) 312 { 313 unsigned int avail = q->tail_idx; 314 315 if (q->head_idx >= avail) 316 avail += q->num_descs - q->head_idx - 1; 317 else 318 avail -= q->head_idx + 1; 319 320 return avail; 321 } 322 323 static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want) 324 { 325 return ionic_q_space_avail(q) >= want; 326 } 327 328 void ionic_init_devinfo(struct ionic *ionic); 329 int ionic_dev_setup(struct ionic *ionic); 330 void ionic_dev_teardown(struct ionic *ionic); 331 332 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 333 u8 ionic_dev_cmd_status(struct ionic_dev *idev); 334 bool ionic_dev_cmd_done(struct ionic_dev *idev); 335 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp); 336 337 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver); 338 void ionic_dev_cmd_init(struct ionic_dev *idev); 339 void ionic_dev_cmd_reset(struct ionic_dev *idev); 340 341 void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 342 void ionic_dev_cmd_port_init(struct ionic_dev *idev); 343 void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 344 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state); 345 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed); 346 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable); 347 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type); 348 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type); 349 350 int ionic_set_vf_config(struct ionic *ionic, int vf, 351 struct ionic_vf_setattr_cmd *vfc); 352 353 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 354 u16 lif_type, u8 qtype, u8 qver); 355 void ionic_vf_start(struct ionic *ionic); 356 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver); 357 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 358 dma_addr_t addr); 359 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index); 360 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 361 u16 lif_index, u16 intr_index); 362 363 int ionic_db_page_num(struct ionic_lif *lif, int pid); 364 365 int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order); 366 void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order); 367 368 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 369 struct ionic_intr_info *intr, 370 unsigned int num_descs, size_t desc_size); 371 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa); 372 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q); 373 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 374 typedef void (*ionic_cq_done_cb)(void *done_arg); 375 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 376 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 377 void *done_arg); 378 379 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 380 struct ionic_queue *q, unsigned int index, const char *name, 381 unsigned int num_descs, size_t desc_size, 382 size_t sg_desc_size, unsigned int pid); 383 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); 384 void ionic_q_cmb_map(struct ionic_queue *q, void __iomem *base, dma_addr_t base_pa); 385 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); 386 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 387 void *cb_arg); 388 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 389 unsigned int stop_index); 390 int ionic_heartbeat_check(struct ionic *ionic); 391 bool ionic_is_fw_running(struct ionic_dev *idev); 392 393 bool ionic_adminq_poke_doorbell(struct ionic_queue *q); 394 bool ionic_txq_poke_doorbell(struct ionic_queue *q); 395 bool ionic_rxq_poke_doorbell(struct ionic_queue *q); 396 397 #endif /* _IONIC_DEV_H_ */ 398