1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/kernel.h> 5 #include <linux/types.h> 6 #include <linux/errno.h> 7 #include <linux/io.h> 8 #include <linux/slab.h> 9 #include <linux/etherdevice.h> 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_lif.h" 13 14 static void ionic_watchdog_cb(struct timer_list *t) 15 { 16 struct ionic *ionic = from_timer(ionic, t, watchdog_timer); 17 struct ionic_lif *lif = ionic->lif; 18 struct ionic_deferred_work *work; 19 int hb; 20 21 mod_timer(&ionic->watchdog_timer, 22 round_jiffies(jiffies + ionic->watchdog_period)); 23 24 if (!lif) 25 return; 26 27 hb = ionic_heartbeat_check(ionic); 28 dev_dbg(ionic->dev, "%s: hb %d running %d UP %d\n", 29 __func__, hb, netif_running(lif->netdev), 30 test_bit(IONIC_LIF_F_UP, lif->state)); 31 32 if (hb >= 0 && 33 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 34 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 35 36 if (test_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state) && 37 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 38 work = kzalloc(sizeof(*work), GFP_ATOMIC); 39 if (!work) { 40 netdev_err(lif->netdev, "rxmode change dropped\n"); 41 return; 42 } 43 44 work->type = IONIC_DW_TYPE_RX_MODE; 45 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 46 ionic_lif_deferred_enqueue(&lif->deferred, work); 47 } 48 } 49 50 static void ionic_watchdog_init(struct ionic *ionic) 51 { 52 struct ionic_dev *idev = &ionic->idev; 53 54 timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0); 55 ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ; 56 57 /* set times to ensure the first check will proceed */ 58 atomic_long_set(&idev->last_check_time, jiffies - 2 * HZ); 59 idev->last_hb_time = jiffies - 2 * ionic->watchdog_period; 60 /* init as ready, so no transition if the first check succeeds */ 61 idev->last_fw_hb = 0; 62 idev->fw_hb_ready = true; 63 idev->fw_status_ready = true; 64 idev->fw_generation = IONIC_FW_STS_F_GENERATION & 65 ioread8(&idev->dev_info_regs->fw_status); 66 } 67 68 void ionic_init_devinfo(struct ionic *ionic) 69 { 70 struct ionic_dev *idev = &ionic->idev; 71 72 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); 73 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); 74 75 memcpy_fromio(idev->dev_info.fw_version, 76 idev->dev_info_regs->fw_version, 77 IONIC_DEVINFO_FWVERS_BUFLEN); 78 79 memcpy_fromio(idev->dev_info.serial_num, 80 idev->dev_info_regs->serial_num, 81 IONIC_DEVINFO_SERIAL_BUFLEN); 82 83 idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0; 84 idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0; 85 86 dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); 87 } 88 89 int ionic_dev_setup(struct ionic *ionic) 90 { 91 struct ionic_dev_bar *bar = ionic->bars; 92 unsigned int num_bars = ionic->num_bars; 93 struct ionic_dev *idev = &ionic->idev; 94 struct device *dev = ionic->dev; 95 u32 sig; 96 97 /* BAR0: dev_cmd and interrupts */ 98 if (num_bars < 1) { 99 dev_err(dev, "No bars found, aborting\n"); 100 return -EFAULT; 101 } 102 103 if (bar->len < IONIC_BAR0_SIZE) { 104 dev_err(dev, "Resource bar size %lu too small, aborting\n", 105 bar->len); 106 return -EFAULT; 107 } 108 109 idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET; 110 idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET; 111 idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET; 112 idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET; 113 114 idev->hwstamp_regs = &idev->dev_info_regs->hwstamp; 115 116 sig = ioread32(&idev->dev_info_regs->signature); 117 if (sig != IONIC_DEV_INFO_SIGNATURE) { 118 dev_err(dev, "Incompatible firmware signature %x", sig); 119 return -EFAULT; 120 } 121 122 ionic_init_devinfo(ionic); 123 124 /* BAR1: doorbells */ 125 bar++; 126 if (num_bars < 2) { 127 dev_err(dev, "Doorbell bar missing, aborting\n"); 128 return -EFAULT; 129 } 130 131 ionic_watchdog_init(ionic); 132 133 idev->db_pages = bar->vaddr; 134 idev->phy_db_pages = bar->bus_addr; 135 136 return 0; 137 } 138 139 /* Devcmd Interface */ 140 bool ionic_is_fw_running(struct ionic_dev *idev) 141 { 142 u8 fw_status = ioread8(&idev->dev_info_regs->fw_status); 143 144 /* firmware is useful only if the running bit is set and 145 * fw_status != 0xff (bad PCI read) 146 */ 147 return (fw_status != 0xff) && (fw_status & IONIC_FW_STS_F_RUNNING); 148 } 149 150 int ionic_heartbeat_check(struct ionic *ionic) 151 { 152 unsigned long check_time, last_check_time; 153 struct ionic_dev *idev = &ionic->idev; 154 struct ionic_lif *lif = ionic->lif; 155 bool fw_status_ready = true; 156 bool fw_hb_ready; 157 u8 fw_generation; 158 u8 fw_status; 159 u32 fw_hb; 160 161 /* wait a least one second before testing again */ 162 check_time = jiffies; 163 last_check_time = atomic_long_read(&idev->last_check_time); 164 do_check_time: 165 if (time_before(check_time, last_check_time + HZ)) 166 return 0; 167 if (!atomic_long_try_cmpxchg_relaxed(&idev->last_check_time, 168 &last_check_time, check_time)) { 169 /* if called concurrently, only the first should proceed. */ 170 dev_dbg(ionic->dev, "%s: do_check_time again\n", __func__); 171 goto do_check_time; 172 } 173 174 fw_status = ioread8(&idev->dev_info_regs->fw_status); 175 176 /* If fw_status is not ready don't bother with the generation */ 177 if (!ionic_is_fw_running(idev)) { 178 fw_status_ready = false; 179 } else { 180 fw_generation = fw_status & IONIC_FW_STS_F_GENERATION; 181 if (idev->fw_generation != fw_generation) { 182 dev_info(ionic->dev, "FW generation 0x%02x -> 0x%02x\n", 183 idev->fw_generation, fw_generation); 184 185 idev->fw_generation = fw_generation; 186 187 /* If the generation changed, the fw status is not 188 * ready so we need to trigger a fw-down cycle. After 189 * the down, the next watchdog will see the fw is up 190 * and the generation value stable, so will trigger 191 * the fw-up activity. 192 * 193 * If we had already moved to FW_RESET from a RESET event, 194 * it is possible that we never saw the fw_status go to 0, 195 * so we fake the current idev->fw_status_ready here to 196 * force the transition and get FW up again. 197 */ 198 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 199 idev->fw_status_ready = false; /* go to running */ 200 else 201 fw_status_ready = false; /* go to down */ 202 } 203 } 204 205 /* is this a transition? */ 206 if (fw_status_ready != idev->fw_status_ready) { 207 bool trigger = false; 208 209 if (!fw_status_ready && lif && 210 !test_bit(IONIC_LIF_F_FW_RESET, lif->state) && 211 !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 212 dev_info(ionic->dev, "FW stopped 0x%02x\n", fw_status); 213 trigger = true; 214 215 } else if (fw_status_ready && lif && 216 test_bit(IONIC_LIF_F_FW_RESET, lif->state) && 217 !test_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 218 dev_info(ionic->dev, "FW running 0x%02x\n", fw_status); 219 trigger = true; 220 } 221 222 if (trigger) { 223 struct ionic_deferred_work *work; 224 225 idev->fw_status_ready = fw_status_ready; 226 227 work = kzalloc(sizeof(*work), GFP_ATOMIC); 228 if (work) { 229 work->type = IONIC_DW_TYPE_LIF_RESET; 230 work->fw_status = fw_status_ready; 231 ionic_lif_deferred_enqueue(&lif->deferred, work); 232 } 233 } 234 } 235 236 if (!idev->fw_status_ready) 237 return -ENXIO; 238 239 /* wait at least one watchdog period since the last heartbeat */ 240 last_check_time = idev->last_hb_time; 241 if (time_before(check_time, last_check_time + ionic->watchdog_period)) 242 return 0; 243 244 fw_hb = ioread32(&idev->dev_info_regs->fw_heartbeat); 245 fw_hb_ready = fw_hb != idev->last_fw_hb; 246 247 /* early FW version had no heartbeat, so fake it */ 248 if (!fw_hb_ready && !fw_hb) 249 fw_hb_ready = true; 250 251 dev_dbg(ionic->dev, "%s: fw_hb %u last_fw_hb %u ready %u\n", 252 __func__, fw_hb, idev->last_fw_hb, fw_hb_ready); 253 254 idev->last_fw_hb = fw_hb; 255 256 /* log a transition */ 257 if (fw_hb_ready != idev->fw_hb_ready) { 258 idev->fw_hb_ready = fw_hb_ready; 259 if (!fw_hb_ready) 260 dev_info(ionic->dev, "FW heartbeat stalled at %d\n", fw_hb); 261 else 262 dev_info(ionic->dev, "FW heartbeat restored at %d\n", fw_hb); 263 } 264 265 if (!fw_hb_ready) 266 return -ENXIO; 267 268 idev->last_hb_time = check_time; 269 270 return 0; 271 } 272 273 u8 ionic_dev_cmd_status(struct ionic_dev *idev) 274 { 275 return ioread8(&idev->dev_cmd_regs->comp.comp.status); 276 } 277 278 bool ionic_dev_cmd_done(struct ionic_dev *idev) 279 { 280 return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE; 281 } 282 283 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp) 284 { 285 memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp)); 286 } 287 288 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 289 { 290 memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd)); 291 iowrite32(0, &idev->dev_cmd_regs->done); 292 iowrite32(1, &idev->dev_cmd_regs->doorbell); 293 } 294 295 /* Device commands */ 296 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver) 297 { 298 union ionic_dev_cmd cmd = { 299 .identify.opcode = IONIC_CMD_IDENTIFY, 300 .identify.ver = ver, 301 }; 302 303 ionic_dev_cmd_go(idev, &cmd); 304 } 305 306 void ionic_dev_cmd_init(struct ionic_dev *idev) 307 { 308 union ionic_dev_cmd cmd = { 309 .init.opcode = IONIC_CMD_INIT, 310 .init.type = 0, 311 }; 312 313 ionic_dev_cmd_go(idev, &cmd); 314 } 315 316 void ionic_dev_cmd_reset(struct ionic_dev *idev) 317 { 318 union ionic_dev_cmd cmd = { 319 .reset.opcode = IONIC_CMD_RESET, 320 }; 321 322 ionic_dev_cmd_go(idev, &cmd); 323 } 324 325 /* Port commands */ 326 void ionic_dev_cmd_port_identify(struct ionic_dev *idev) 327 { 328 union ionic_dev_cmd cmd = { 329 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 330 .port_init.index = 0, 331 }; 332 333 ionic_dev_cmd_go(idev, &cmd); 334 } 335 336 void ionic_dev_cmd_port_init(struct ionic_dev *idev) 337 { 338 union ionic_dev_cmd cmd = { 339 .port_init.opcode = IONIC_CMD_PORT_INIT, 340 .port_init.index = 0, 341 .port_init.info_pa = cpu_to_le64(idev->port_info_pa), 342 }; 343 344 ionic_dev_cmd_go(idev, &cmd); 345 } 346 347 void ionic_dev_cmd_port_reset(struct ionic_dev *idev) 348 { 349 union ionic_dev_cmd cmd = { 350 .port_reset.opcode = IONIC_CMD_PORT_RESET, 351 .port_reset.index = 0, 352 }; 353 354 ionic_dev_cmd_go(idev, &cmd); 355 } 356 357 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state) 358 { 359 union ionic_dev_cmd cmd = { 360 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 361 .port_setattr.index = 0, 362 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 363 .port_setattr.state = state, 364 }; 365 366 ionic_dev_cmd_go(idev, &cmd); 367 } 368 369 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed) 370 { 371 union ionic_dev_cmd cmd = { 372 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 373 .port_setattr.index = 0, 374 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 375 .port_setattr.speed = cpu_to_le32(speed), 376 }; 377 378 ionic_dev_cmd_go(idev, &cmd); 379 } 380 381 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable) 382 { 383 union ionic_dev_cmd cmd = { 384 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 385 .port_setattr.index = 0, 386 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 387 .port_setattr.an_enable = an_enable, 388 }; 389 390 ionic_dev_cmd_go(idev, &cmd); 391 } 392 393 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type) 394 { 395 union ionic_dev_cmd cmd = { 396 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 397 .port_setattr.index = 0, 398 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 399 .port_setattr.fec_type = fec_type, 400 }; 401 402 ionic_dev_cmd_go(idev, &cmd); 403 } 404 405 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type) 406 { 407 union ionic_dev_cmd cmd = { 408 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 409 .port_setattr.index = 0, 410 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 411 .port_setattr.pause_type = pause_type, 412 }; 413 414 ionic_dev_cmd_go(idev, &cmd); 415 } 416 417 /* VF commands */ 418 int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data) 419 { 420 union ionic_dev_cmd cmd = { 421 .vf_setattr.opcode = IONIC_CMD_VF_SETATTR, 422 .vf_setattr.attr = attr, 423 .vf_setattr.vf_index = cpu_to_le16(vf), 424 }; 425 int err; 426 427 switch (attr) { 428 case IONIC_VF_ATTR_SPOOFCHK: 429 cmd.vf_setattr.spoofchk = *data; 430 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 431 __func__, vf, *data); 432 break; 433 case IONIC_VF_ATTR_TRUST: 434 cmd.vf_setattr.trust = *data; 435 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 436 __func__, vf, *data); 437 break; 438 case IONIC_VF_ATTR_LINKSTATE: 439 cmd.vf_setattr.linkstate = *data; 440 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 441 __func__, vf, *data); 442 break; 443 case IONIC_VF_ATTR_MAC: 444 ether_addr_copy(cmd.vf_setattr.macaddr, data); 445 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 446 __func__, vf, data); 447 break; 448 case IONIC_VF_ATTR_VLAN: 449 cmd.vf_setattr.vlanid = cpu_to_le16(*(u16 *)data); 450 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 451 __func__, vf, *(u16 *)data); 452 break; 453 case IONIC_VF_ATTR_RATE: 454 cmd.vf_setattr.maxrate = cpu_to_le32(*(u32 *)data); 455 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 456 __func__, vf, *(u32 *)data); 457 break; 458 case IONIC_VF_ATTR_STATSADDR: 459 cmd.vf_setattr.stats_pa = cpu_to_le64(*(u64 *)data); 460 dev_dbg(ionic->dev, "%s: vf %d stats_pa 0x%08llx\n", 461 __func__, vf, *(u64 *)data); 462 break; 463 default: 464 return -EINVAL; 465 } 466 467 mutex_lock(&ionic->dev_cmd_lock); 468 ionic_dev_cmd_go(&ionic->idev, &cmd); 469 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 470 mutex_unlock(&ionic->dev_cmd_lock); 471 472 return err; 473 } 474 475 int ionic_dev_cmd_vf_getattr(struct ionic *ionic, int vf, u8 attr, 476 struct ionic_vf_getattr_comp *comp) 477 { 478 union ionic_dev_cmd cmd = { 479 .vf_getattr.opcode = IONIC_CMD_VF_GETATTR, 480 .vf_getattr.attr = attr, 481 .vf_getattr.vf_index = cpu_to_le16(vf), 482 }; 483 int err; 484 485 if (vf >= ionic->num_vfs) 486 return -EINVAL; 487 488 switch (attr) { 489 case IONIC_VF_ATTR_SPOOFCHK: 490 case IONIC_VF_ATTR_TRUST: 491 case IONIC_VF_ATTR_LINKSTATE: 492 case IONIC_VF_ATTR_MAC: 493 case IONIC_VF_ATTR_VLAN: 494 case IONIC_VF_ATTR_RATE: 495 break; 496 case IONIC_VF_ATTR_STATSADDR: 497 default: 498 return -EINVAL; 499 } 500 501 mutex_lock(&ionic->dev_cmd_lock); 502 ionic_dev_cmd_go(&ionic->idev, &cmd); 503 err = ionic_dev_cmd_wait_nomsg(ionic, DEVCMD_TIMEOUT); 504 memcpy_fromio(comp, &ionic->idev.dev_cmd_regs->comp.vf_getattr, 505 sizeof(*comp)); 506 mutex_unlock(&ionic->dev_cmd_lock); 507 508 if (err && comp->status != IONIC_RC_ENOSUPP) 509 ionic_dev_cmd_dev_err_print(ionic, cmd.vf_getattr.opcode, 510 comp->status, err); 511 512 return err; 513 } 514 515 /* LIF commands */ 516 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 517 u16 lif_type, u8 qtype, u8 qver) 518 { 519 union ionic_dev_cmd cmd = { 520 .q_identify.opcode = IONIC_CMD_Q_IDENTIFY, 521 .q_identify.lif_type = cpu_to_le16(lif_type), 522 .q_identify.type = qtype, 523 .q_identify.ver = qver, 524 }; 525 526 ionic_dev_cmd_go(idev, &cmd); 527 } 528 529 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) 530 { 531 union ionic_dev_cmd cmd = { 532 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 533 .lif_identify.type = type, 534 .lif_identify.ver = ver, 535 }; 536 537 ionic_dev_cmd_go(idev, &cmd); 538 } 539 540 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 541 dma_addr_t info_pa) 542 { 543 union ionic_dev_cmd cmd = { 544 .lif_init.opcode = IONIC_CMD_LIF_INIT, 545 .lif_init.index = cpu_to_le16(lif_index), 546 .lif_init.info_pa = cpu_to_le64(info_pa), 547 }; 548 549 ionic_dev_cmd_go(idev, &cmd); 550 } 551 552 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index) 553 { 554 union ionic_dev_cmd cmd = { 555 .lif_init.opcode = IONIC_CMD_LIF_RESET, 556 .lif_init.index = cpu_to_le16(lif_index), 557 }; 558 559 ionic_dev_cmd_go(idev, &cmd); 560 } 561 562 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 563 u16 lif_index, u16 intr_index) 564 { 565 struct ionic_queue *q = &qcq->q; 566 struct ionic_cq *cq = &qcq->cq; 567 568 union ionic_dev_cmd cmd = { 569 .q_init.opcode = IONIC_CMD_Q_INIT, 570 .q_init.lif_index = cpu_to_le16(lif_index), 571 .q_init.type = q->type, 572 .q_init.ver = qcq->q.lif->qtype_info[q->type].version, 573 .q_init.index = cpu_to_le32(q->index), 574 .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 575 IONIC_QINIT_F_ENA), 576 .q_init.pid = cpu_to_le16(q->pid), 577 .q_init.intr_index = cpu_to_le16(intr_index), 578 .q_init.ring_size = ilog2(q->num_descs), 579 .q_init.ring_base = cpu_to_le64(q->base_pa), 580 .q_init.cq_ring_base = cpu_to_le64(cq->base_pa), 581 }; 582 583 ionic_dev_cmd_go(idev, &cmd); 584 } 585 586 int ionic_db_page_num(struct ionic_lif *lif, int pid) 587 { 588 return (lif->hw_index * lif->dbid_count) + pid; 589 } 590 591 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 592 struct ionic_intr_info *intr, 593 unsigned int num_descs, size_t desc_size) 594 { 595 unsigned int ring_size; 596 597 if (desc_size == 0 || !is_power_of_2(num_descs)) 598 return -EINVAL; 599 600 ring_size = ilog2(num_descs); 601 if (ring_size < 2 || ring_size > 16) 602 return -EINVAL; 603 604 cq->lif = lif; 605 cq->bound_intr = intr; 606 cq->num_descs = num_descs; 607 cq->desc_size = desc_size; 608 cq->tail_idx = 0; 609 cq->done_color = 1; 610 611 return 0; 612 } 613 614 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa) 615 { 616 struct ionic_cq_info *cur; 617 unsigned int i; 618 619 cq->base = base; 620 cq->base_pa = base_pa; 621 622 for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++) 623 cur->cq_desc = base + (i * cq->desc_size); 624 } 625 626 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) 627 { 628 cq->bound_q = q; 629 } 630 631 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 632 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 633 void *done_arg) 634 { 635 struct ionic_cq_info *cq_info; 636 unsigned int work_done = 0; 637 638 if (work_to_do == 0) 639 return 0; 640 641 cq_info = &cq->info[cq->tail_idx]; 642 while (cb(cq, cq_info)) { 643 if (cq->tail_idx == cq->num_descs - 1) 644 cq->done_color = !cq->done_color; 645 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 646 cq_info = &cq->info[cq->tail_idx]; 647 648 if (++work_done >= work_to_do) 649 break; 650 } 651 652 if (work_done && done_cb) 653 done_cb(done_arg); 654 655 return work_done; 656 } 657 658 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 659 struct ionic_queue *q, unsigned int index, const char *name, 660 unsigned int num_descs, size_t desc_size, 661 size_t sg_desc_size, unsigned int pid) 662 { 663 unsigned int ring_size; 664 665 if (desc_size == 0 || !is_power_of_2(num_descs)) 666 return -EINVAL; 667 668 ring_size = ilog2(num_descs); 669 if (ring_size < 2 || ring_size > 16) 670 return -EINVAL; 671 672 q->lif = lif; 673 q->idev = idev; 674 q->index = index; 675 q->num_descs = num_descs; 676 q->desc_size = desc_size; 677 q->sg_desc_size = sg_desc_size; 678 q->tail_idx = 0; 679 q->head_idx = 0; 680 q->pid = pid; 681 682 snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index); 683 684 return 0; 685 } 686 687 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 688 { 689 struct ionic_desc_info *cur; 690 unsigned int i; 691 692 q->base = base; 693 q->base_pa = base_pa; 694 695 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 696 cur->desc = base + (i * q->desc_size); 697 } 698 699 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 700 { 701 struct ionic_desc_info *cur; 702 unsigned int i; 703 704 q->sg_base = base; 705 q->sg_base_pa = base_pa; 706 707 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 708 cur->sg_desc = base + (i * q->sg_desc_size); 709 } 710 711 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 712 void *cb_arg) 713 { 714 struct ionic_desc_info *desc_info; 715 struct ionic_lif *lif = q->lif; 716 struct device *dev = q->dev; 717 718 desc_info = &q->info[q->head_idx]; 719 desc_info->cb = cb; 720 desc_info->cb_arg = cb_arg; 721 722 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); 723 724 dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n", 725 q->lif->index, q->name, q->hw_type, q->hw_index, 726 q->head_idx, ring_doorbell); 727 728 if (ring_doorbell) 729 ionic_dbell_ring(lif->kern_dbpage, q->hw_type, 730 q->dbval | q->head_idx); 731 } 732 733 static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos) 734 { 735 unsigned int mask, tail, head; 736 737 mask = q->num_descs - 1; 738 tail = q->tail_idx; 739 head = q->head_idx; 740 741 return ((pos - tail) & mask) < ((head - tail) & mask); 742 } 743 744 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 745 unsigned int stop_index) 746 { 747 struct ionic_desc_info *desc_info; 748 ionic_desc_cb cb; 749 void *cb_arg; 750 u16 index; 751 752 /* check for empty queue */ 753 if (q->tail_idx == q->head_idx) 754 return; 755 756 /* stop index must be for a descriptor that is not yet completed */ 757 if (unlikely(!ionic_q_is_posted(q, stop_index))) 758 dev_err(q->dev, 759 "ionic stop is not posted %s stop %u tail %u head %u\n", 760 q->name, stop_index, q->tail_idx, q->head_idx); 761 762 do { 763 desc_info = &q->info[q->tail_idx]; 764 index = q->tail_idx; 765 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 766 767 cb = desc_info->cb; 768 cb_arg = desc_info->cb_arg; 769 770 desc_info->cb = NULL; 771 desc_info->cb_arg = NULL; 772 773 if (cb) 774 cb(q, desc_info, cq_info, cb_arg); 775 } while (index != stop_index); 776 } 777