1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/kernel.h> 5 #include <linux/types.h> 6 #include <linux/errno.h> 7 #include <linux/io.h> 8 #include <linux/slab.h> 9 #include <linux/etherdevice.h> 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_lif.h" 13 14 static void ionic_watchdog_cb(struct timer_list *t) 15 { 16 struct ionic *ionic = from_timer(ionic, t, watchdog_timer); 17 struct ionic_lif *lif = ionic->lif; 18 struct ionic_deferred_work *work; 19 int hb; 20 21 mod_timer(&ionic->watchdog_timer, 22 round_jiffies(jiffies + ionic->watchdog_period)); 23 24 if (!lif) 25 return; 26 27 hb = ionic_heartbeat_check(ionic); 28 dev_dbg(ionic->dev, "%s: hb %d running %d UP %d\n", 29 __func__, hb, netif_running(lif->netdev), 30 test_bit(IONIC_LIF_F_UP, lif->state)); 31 32 if (hb >= 0 && 33 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 34 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 35 36 if (test_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state) && 37 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 38 work = kzalloc(sizeof(*work), GFP_ATOMIC); 39 if (!work) { 40 netdev_err(lif->netdev, "rxmode change dropped\n"); 41 return; 42 } 43 44 work->type = IONIC_DW_TYPE_RX_MODE; 45 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 46 ionic_lif_deferred_enqueue(&lif->deferred, work); 47 } 48 } 49 50 static void ionic_watchdog_init(struct ionic *ionic) 51 { 52 struct ionic_dev *idev = &ionic->idev; 53 54 timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0); 55 ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ; 56 57 /* set times to ensure the first check will proceed */ 58 atomic_long_set(&idev->last_check_time, jiffies - 2 * HZ); 59 idev->last_hb_time = jiffies - 2 * ionic->watchdog_period; 60 /* init as ready, so no transition if the first check succeeds */ 61 idev->last_fw_hb = 0; 62 idev->fw_hb_ready = true; 63 idev->fw_status_ready = true; 64 idev->fw_generation = IONIC_FW_STS_F_GENERATION & 65 ioread8(&idev->dev_info_regs->fw_status); 66 } 67 68 void ionic_init_devinfo(struct ionic *ionic) 69 { 70 struct ionic_dev *idev = &ionic->idev; 71 72 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); 73 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); 74 75 memcpy_fromio(idev->dev_info.fw_version, 76 idev->dev_info_regs->fw_version, 77 IONIC_DEVINFO_FWVERS_BUFLEN); 78 79 memcpy_fromio(idev->dev_info.serial_num, 80 idev->dev_info_regs->serial_num, 81 IONIC_DEVINFO_SERIAL_BUFLEN); 82 83 idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0; 84 idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0; 85 86 dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); 87 } 88 89 int ionic_dev_setup(struct ionic *ionic) 90 { 91 struct ionic_dev_bar *bar = ionic->bars; 92 unsigned int num_bars = ionic->num_bars; 93 struct ionic_dev *idev = &ionic->idev; 94 struct device *dev = ionic->dev; 95 int size; 96 u32 sig; 97 98 /* BAR0: dev_cmd and interrupts */ 99 if (num_bars < 1) { 100 dev_err(dev, "No bars found, aborting\n"); 101 return -EFAULT; 102 } 103 104 if (bar->len < IONIC_BAR0_SIZE) { 105 dev_err(dev, "Resource bar size %lu too small, aborting\n", 106 bar->len); 107 return -EFAULT; 108 } 109 110 idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET; 111 idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET; 112 idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET; 113 idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET; 114 115 idev->hwstamp_regs = &idev->dev_info_regs->hwstamp; 116 117 sig = ioread32(&idev->dev_info_regs->signature); 118 if (sig != IONIC_DEV_INFO_SIGNATURE) { 119 dev_err(dev, "Incompatible firmware signature %x", sig); 120 return -EFAULT; 121 } 122 123 ionic_init_devinfo(ionic); 124 125 /* BAR1: doorbells */ 126 bar++; 127 if (num_bars < 2) { 128 dev_err(dev, "Doorbell bar missing, aborting\n"); 129 return -EFAULT; 130 } 131 132 ionic_watchdog_init(ionic); 133 134 idev->db_pages = bar->vaddr; 135 idev->phy_db_pages = bar->bus_addr; 136 137 /* BAR2: optional controller memory mapping */ 138 bar++; 139 mutex_init(&idev->cmb_inuse_lock); 140 if (num_bars < 3 || !ionic->bars[IONIC_PCI_BAR_CMB].len) { 141 idev->cmb_inuse = NULL; 142 return 0; 143 } 144 145 idev->phy_cmb_pages = bar->bus_addr; 146 idev->cmb_npages = bar->len / PAGE_SIZE; 147 size = BITS_TO_LONGS(idev->cmb_npages) * sizeof(long); 148 idev->cmb_inuse = kzalloc(size, GFP_KERNEL); 149 if (!idev->cmb_inuse) 150 dev_warn(dev, "No memory for CMB, disabling\n"); 151 152 return 0; 153 } 154 155 void ionic_dev_teardown(struct ionic *ionic) 156 { 157 struct ionic_dev *idev = &ionic->idev; 158 159 kfree(idev->cmb_inuse); 160 idev->cmb_inuse = NULL; 161 idev->phy_cmb_pages = 0; 162 idev->cmb_npages = 0; 163 164 mutex_destroy(&idev->cmb_inuse_lock); 165 } 166 167 /* Devcmd Interface */ 168 bool ionic_is_fw_running(struct ionic_dev *idev) 169 { 170 u8 fw_status = ioread8(&idev->dev_info_regs->fw_status); 171 172 /* firmware is useful only if the running bit is set and 173 * fw_status != 0xff (bad PCI read) 174 */ 175 return (fw_status != 0xff) && (fw_status & IONIC_FW_STS_F_RUNNING); 176 } 177 178 int ionic_heartbeat_check(struct ionic *ionic) 179 { 180 unsigned long check_time, last_check_time; 181 struct ionic_dev *idev = &ionic->idev; 182 struct ionic_lif *lif = ionic->lif; 183 bool fw_status_ready = true; 184 bool fw_hb_ready; 185 u8 fw_generation; 186 u8 fw_status; 187 u32 fw_hb; 188 189 /* wait a least one second before testing again */ 190 check_time = jiffies; 191 last_check_time = atomic_long_read(&idev->last_check_time); 192 do_check_time: 193 if (time_before(check_time, last_check_time + HZ)) 194 return 0; 195 if (!atomic_long_try_cmpxchg_relaxed(&idev->last_check_time, 196 &last_check_time, check_time)) { 197 /* if called concurrently, only the first should proceed. */ 198 dev_dbg(ionic->dev, "%s: do_check_time again\n", __func__); 199 goto do_check_time; 200 } 201 202 fw_status = ioread8(&idev->dev_info_regs->fw_status); 203 204 /* If fw_status is not ready don't bother with the generation */ 205 if (!ionic_is_fw_running(idev)) { 206 fw_status_ready = false; 207 } else { 208 fw_generation = fw_status & IONIC_FW_STS_F_GENERATION; 209 if (idev->fw_generation != fw_generation) { 210 dev_info(ionic->dev, "FW generation 0x%02x -> 0x%02x\n", 211 idev->fw_generation, fw_generation); 212 213 idev->fw_generation = fw_generation; 214 215 /* If the generation changed, the fw status is not 216 * ready so we need to trigger a fw-down cycle. After 217 * the down, the next watchdog will see the fw is up 218 * and the generation value stable, so will trigger 219 * the fw-up activity. 220 * 221 * If we had already moved to FW_RESET from a RESET event, 222 * it is possible that we never saw the fw_status go to 0, 223 * so we fake the current idev->fw_status_ready here to 224 * force the transition and get FW up again. 225 */ 226 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 227 idev->fw_status_ready = false; /* go to running */ 228 else 229 fw_status_ready = false; /* go to down */ 230 } 231 } 232 233 dev_dbg(ionic->dev, "fw_status 0x%02x ready %d idev->ready %d last_hb 0x%x state 0x%02lx\n", 234 fw_status, fw_status_ready, idev->fw_status_ready, 235 idev->last_fw_hb, lif->state[0]); 236 237 /* is this a transition? */ 238 if (fw_status_ready != idev->fw_status_ready && 239 !test_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 240 bool trigger = false; 241 242 idev->fw_status_ready = fw_status_ready; 243 244 if (!fw_status_ready && 245 !test_bit(IONIC_LIF_F_FW_RESET, lif->state) && 246 !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 247 dev_info(ionic->dev, "FW stopped 0x%02x\n", fw_status); 248 trigger = true; 249 250 } else if (fw_status_ready && 251 test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 252 dev_info(ionic->dev, "FW running 0x%02x\n", fw_status); 253 trigger = true; 254 } 255 256 if (trigger) { 257 struct ionic_deferred_work *work; 258 259 work = kzalloc(sizeof(*work), GFP_ATOMIC); 260 if (work) { 261 work->type = IONIC_DW_TYPE_LIF_RESET; 262 work->fw_status = fw_status_ready; 263 ionic_lif_deferred_enqueue(&lif->deferred, work); 264 } 265 } 266 } 267 268 if (!idev->fw_status_ready) 269 return -ENXIO; 270 271 /* Because of some variability in the actual FW heartbeat, we 272 * wait longer than the DEVCMD_TIMEOUT before checking again. 273 */ 274 last_check_time = idev->last_hb_time; 275 if (time_before(check_time, last_check_time + DEVCMD_TIMEOUT * 2 * HZ)) 276 return 0; 277 278 fw_hb = ioread32(&idev->dev_info_regs->fw_heartbeat); 279 fw_hb_ready = fw_hb != idev->last_fw_hb; 280 281 /* early FW version had no heartbeat, so fake it */ 282 if (!fw_hb_ready && !fw_hb) 283 fw_hb_ready = true; 284 285 dev_dbg(ionic->dev, "%s: fw_hb %u last_fw_hb %u ready %u\n", 286 __func__, fw_hb, idev->last_fw_hb, fw_hb_ready); 287 288 idev->last_fw_hb = fw_hb; 289 290 /* log a transition */ 291 if (fw_hb_ready != idev->fw_hb_ready) { 292 idev->fw_hb_ready = fw_hb_ready; 293 if (!fw_hb_ready) 294 dev_info(ionic->dev, "FW heartbeat stalled at %d\n", fw_hb); 295 else 296 dev_info(ionic->dev, "FW heartbeat restored at %d\n", fw_hb); 297 } 298 299 if (!fw_hb_ready) 300 return -ENXIO; 301 302 idev->last_hb_time = check_time; 303 304 return 0; 305 } 306 307 u8 ionic_dev_cmd_status(struct ionic_dev *idev) 308 { 309 return ioread8(&idev->dev_cmd_regs->comp.comp.status); 310 } 311 312 bool ionic_dev_cmd_done(struct ionic_dev *idev) 313 { 314 return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE; 315 } 316 317 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp) 318 { 319 memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp)); 320 } 321 322 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 323 { 324 memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd)); 325 iowrite32(0, &idev->dev_cmd_regs->done); 326 iowrite32(1, &idev->dev_cmd_regs->doorbell); 327 } 328 329 /* Device commands */ 330 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver) 331 { 332 union ionic_dev_cmd cmd = { 333 .identify.opcode = IONIC_CMD_IDENTIFY, 334 .identify.ver = ver, 335 }; 336 337 ionic_dev_cmd_go(idev, &cmd); 338 } 339 340 void ionic_dev_cmd_init(struct ionic_dev *idev) 341 { 342 union ionic_dev_cmd cmd = { 343 .init.opcode = IONIC_CMD_INIT, 344 .init.type = 0, 345 }; 346 347 ionic_dev_cmd_go(idev, &cmd); 348 } 349 350 void ionic_dev_cmd_reset(struct ionic_dev *idev) 351 { 352 union ionic_dev_cmd cmd = { 353 .reset.opcode = IONIC_CMD_RESET, 354 }; 355 356 ionic_dev_cmd_go(idev, &cmd); 357 } 358 359 /* Port commands */ 360 void ionic_dev_cmd_port_identify(struct ionic_dev *idev) 361 { 362 union ionic_dev_cmd cmd = { 363 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 364 .port_init.index = 0, 365 }; 366 367 ionic_dev_cmd_go(idev, &cmd); 368 } 369 370 void ionic_dev_cmd_port_init(struct ionic_dev *idev) 371 { 372 union ionic_dev_cmd cmd = { 373 .port_init.opcode = IONIC_CMD_PORT_INIT, 374 .port_init.index = 0, 375 .port_init.info_pa = cpu_to_le64(idev->port_info_pa), 376 }; 377 378 ionic_dev_cmd_go(idev, &cmd); 379 } 380 381 void ionic_dev_cmd_port_reset(struct ionic_dev *idev) 382 { 383 union ionic_dev_cmd cmd = { 384 .port_reset.opcode = IONIC_CMD_PORT_RESET, 385 .port_reset.index = 0, 386 }; 387 388 ionic_dev_cmd_go(idev, &cmd); 389 } 390 391 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state) 392 { 393 union ionic_dev_cmd cmd = { 394 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 395 .port_setattr.index = 0, 396 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 397 .port_setattr.state = state, 398 }; 399 400 ionic_dev_cmd_go(idev, &cmd); 401 } 402 403 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed) 404 { 405 union ionic_dev_cmd cmd = { 406 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 407 .port_setattr.index = 0, 408 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 409 .port_setattr.speed = cpu_to_le32(speed), 410 }; 411 412 ionic_dev_cmd_go(idev, &cmd); 413 } 414 415 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable) 416 { 417 union ionic_dev_cmd cmd = { 418 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 419 .port_setattr.index = 0, 420 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 421 .port_setattr.an_enable = an_enable, 422 }; 423 424 ionic_dev_cmd_go(idev, &cmd); 425 } 426 427 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type) 428 { 429 union ionic_dev_cmd cmd = { 430 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 431 .port_setattr.index = 0, 432 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 433 .port_setattr.fec_type = fec_type, 434 }; 435 436 ionic_dev_cmd_go(idev, &cmd); 437 } 438 439 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type) 440 { 441 union ionic_dev_cmd cmd = { 442 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 443 .port_setattr.index = 0, 444 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 445 .port_setattr.pause_type = pause_type, 446 }; 447 448 ionic_dev_cmd_go(idev, &cmd); 449 } 450 451 /* VF commands */ 452 int ionic_set_vf_config(struct ionic *ionic, int vf, 453 struct ionic_vf_setattr_cmd *vfc) 454 { 455 union ionic_dev_cmd cmd = { 456 .vf_setattr.opcode = IONIC_CMD_VF_SETATTR, 457 .vf_setattr.attr = vfc->attr, 458 .vf_setattr.vf_index = cpu_to_le16(vf), 459 }; 460 int err; 461 462 memcpy(cmd.vf_setattr.pad, vfc->pad, sizeof(vfc->pad)); 463 464 mutex_lock(&ionic->dev_cmd_lock); 465 ionic_dev_cmd_go(&ionic->idev, &cmd); 466 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 467 mutex_unlock(&ionic->dev_cmd_lock); 468 469 return err; 470 } 471 472 void ionic_vf_start(struct ionic *ionic) 473 { 474 union ionic_dev_cmd cmd = { 475 .vf_ctrl.opcode = IONIC_CMD_VF_CTRL, 476 .vf_ctrl.ctrl_opcode = IONIC_VF_CTRL_START_ALL, 477 }; 478 479 if (!(ionic->ident.dev.capabilities & cpu_to_le64(IONIC_DEV_CAP_VF_CTRL))) 480 return; 481 482 ionic_dev_cmd_go(&ionic->idev, &cmd); 483 ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 484 } 485 486 /* LIF commands */ 487 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 488 u16 lif_type, u8 qtype, u8 qver) 489 { 490 union ionic_dev_cmd cmd = { 491 .q_identify.opcode = IONIC_CMD_Q_IDENTIFY, 492 .q_identify.lif_type = cpu_to_le16(lif_type), 493 .q_identify.type = qtype, 494 .q_identify.ver = qver, 495 }; 496 497 ionic_dev_cmd_go(idev, &cmd); 498 } 499 500 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) 501 { 502 union ionic_dev_cmd cmd = { 503 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 504 .lif_identify.type = type, 505 .lif_identify.ver = ver, 506 }; 507 508 ionic_dev_cmd_go(idev, &cmd); 509 } 510 511 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 512 dma_addr_t info_pa) 513 { 514 union ionic_dev_cmd cmd = { 515 .lif_init.opcode = IONIC_CMD_LIF_INIT, 516 .lif_init.index = cpu_to_le16(lif_index), 517 .lif_init.info_pa = cpu_to_le64(info_pa), 518 }; 519 520 ionic_dev_cmd_go(idev, &cmd); 521 } 522 523 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index) 524 { 525 union ionic_dev_cmd cmd = { 526 .lif_init.opcode = IONIC_CMD_LIF_RESET, 527 .lif_init.index = cpu_to_le16(lif_index), 528 }; 529 530 ionic_dev_cmd_go(idev, &cmd); 531 } 532 533 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 534 u16 lif_index, u16 intr_index) 535 { 536 struct ionic_queue *q = &qcq->q; 537 struct ionic_cq *cq = &qcq->cq; 538 539 union ionic_dev_cmd cmd = { 540 .q_init.opcode = IONIC_CMD_Q_INIT, 541 .q_init.lif_index = cpu_to_le16(lif_index), 542 .q_init.type = q->type, 543 .q_init.ver = qcq->q.lif->qtype_info[q->type].version, 544 .q_init.index = cpu_to_le32(q->index), 545 .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 546 IONIC_QINIT_F_ENA), 547 .q_init.pid = cpu_to_le16(q->pid), 548 .q_init.intr_index = cpu_to_le16(intr_index), 549 .q_init.ring_size = ilog2(q->num_descs), 550 .q_init.ring_base = cpu_to_le64(q->base_pa), 551 .q_init.cq_ring_base = cpu_to_le64(cq->base_pa), 552 }; 553 554 ionic_dev_cmd_go(idev, &cmd); 555 } 556 557 int ionic_db_page_num(struct ionic_lif *lif, int pid) 558 { 559 return (lif->hw_index * lif->dbid_count) + pid; 560 } 561 562 int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order) 563 { 564 struct ionic_dev *idev = &lif->ionic->idev; 565 int ret; 566 567 mutex_lock(&idev->cmb_inuse_lock); 568 ret = bitmap_find_free_region(idev->cmb_inuse, idev->cmb_npages, order); 569 mutex_unlock(&idev->cmb_inuse_lock); 570 571 if (ret < 0) 572 return ret; 573 574 *pgid = ret; 575 *pgaddr = idev->phy_cmb_pages + ret * PAGE_SIZE; 576 577 return 0; 578 } 579 580 void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order) 581 { 582 struct ionic_dev *idev = &lif->ionic->idev; 583 584 mutex_lock(&idev->cmb_inuse_lock); 585 bitmap_release_region(idev->cmb_inuse, pgid, order); 586 mutex_unlock(&idev->cmb_inuse_lock); 587 } 588 589 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 590 struct ionic_intr_info *intr, 591 unsigned int num_descs, size_t desc_size) 592 { 593 unsigned int ring_size; 594 595 if (desc_size == 0 || !is_power_of_2(num_descs)) 596 return -EINVAL; 597 598 ring_size = ilog2(num_descs); 599 if (ring_size < 2 || ring_size > 16) 600 return -EINVAL; 601 602 cq->lif = lif; 603 cq->bound_intr = intr; 604 cq->num_descs = num_descs; 605 cq->desc_size = desc_size; 606 cq->tail_idx = 0; 607 cq->done_color = 1; 608 609 return 0; 610 } 611 612 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa) 613 { 614 struct ionic_cq_info *cur; 615 unsigned int i; 616 617 cq->base = base; 618 cq->base_pa = base_pa; 619 620 for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++) 621 cur->cq_desc = base + (i * cq->desc_size); 622 } 623 624 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) 625 { 626 cq->bound_q = q; 627 } 628 629 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 630 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 631 void *done_arg) 632 { 633 struct ionic_cq_info *cq_info; 634 unsigned int work_done = 0; 635 636 if (work_to_do == 0) 637 return 0; 638 639 cq_info = &cq->info[cq->tail_idx]; 640 while (cb(cq, cq_info)) { 641 if (cq->tail_idx == cq->num_descs - 1) 642 cq->done_color = !cq->done_color; 643 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 644 cq_info = &cq->info[cq->tail_idx]; 645 646 if (++work_done >= work_to_do) 647 break; 648 } 649 650 if (work_done && done_cb) 651 done_cb(done_arg); 652 653 return work_done; 654 } 655 656 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 657 struct ionic_queue *q, unsigned int index, const char *name, 658 unsigned int num_descs, size_t desc_size, 659 size_t sg_desc_size, unsigned int pid) 660 { 661 unsigned int ring_size; 662 663 if (desc_size == 0 || !is_power_of_2(num_descs)) 664 return -EINVAL; 665 666 ring_size = ilog2(num_descs); 667 if (ring_size < 2 || ring_size > 16) 668 return -EINVAL; 669 670 q->lif = lif; 671 q->idev = idev; 672 q->index = index; 673 q->num_descs = num_descs; 674 q->desc_size = desc_size; 675 q->sg_desc_size = sg_desc_size; 676 q->tail_idx = 0; 677 q->head_idx = 0; 678 q->pid = pid; 679 680 snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index); 681 682 return 0; 683 } 684 685 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 686 { 687 struct ionic_desc_info *cur; 688 unsigned int i; 689 690 q->base = base; 691 q->base_pa = base_pa; 692 693 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 694 cur->desc = base + (i * q->desc_size); 695 } 696 697 void ionic_q_cmb_map(struct ionic_queue *q, void __iomem *base, dma_addr_t base_pa) 698 { 699 struct ionic_desc_info *cur; 700 unsigned int i; 701 702 q->cmb_base = base; 703 q->cmb_base_pa = base_pa; 704 705 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 706 cur->cmb_desc = base + (i * q->desc_size); 707 } 708 709 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 710 { 711 struct ionic_desc_info *cur; 712 unsigned int i; 713 714 q->sg_base = base; 715 q->sg_base_pa = base_pa; 716 717 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 718 cur->sg_desc = base + (i * q->sg_desc_size); 719 } 720 721 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 722 void *cb_arg) 723 { 724 struct ionic_desc_info *desc_info; 725 struct ionic_lif *lif = q->lif; 726 struct device *dev = q->dev; 727 728 desc_info = &q->info[q->head_idx]; 729 desc_info->cb = cb; 730 desc_info->cb_arg = cb_arg; 731 732 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); 733 734 dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n", 735 q->lif->index, q->name, q->hw_type, q->hw_index, 736 q->head_idx, ring_doorbell); 737 738 if (ring_doorbell) { 739 ionic_dbell_ring(lif->kern_dbpage, q->hw_type, 740 q->dbval | q->head_idx); 741 742 q->dbell_jiffies = jiffies; 743 744 if (q_to_qcq(q)->napi_qcq) 745 mod_timer(&q_to_qcq(q)->napi_qcq->napi_deadline, 746 jiffies + IONIC_NAPI_DEADLINE); 747 } 748 } 749 750 static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos) 751 { 752 unsigned int mask, tail, head; 753 754 mask = q->num_descs - 1; 755 tail = q->tail_idx; 756 head = q->head_idx; 757 758 return ((pos - tail) & mask) < ((head - tail) & mask); 759 } 760 761 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 762 unsigned int stop_index) 763 { 764 struct ionic_desc_info *desc_info; 765 ionic_desc_cb cb; 766 void *cb_arg; 767 u16 index; 768 769 /* check for empty queue */ 770 if (q->tail_idx == q->head_idx) 771 return; 772 773 /* stop index must be for a descriptor that is not yet completed */ 774 if (unlikely(!ionic_q_is_posted(q, stop_index))) 775 dev_err(q->dev, 776 "ionic stop is not posted %s stop %u tail %u head %u\n", 777 q->name, stop_index, q->tail_idx, q->head_idx); 778 779 do { 780 desc_info = &q->info[q->tail_idx]; 781 index = q->tail_idx; 782 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 783 784 cb = desc_info->cb; 785 cb_arg = desc_info->cb_arg; 786 787 desc_info->cb = NULL; 788 desc_info->cb_arg = NULL; 789 790 if (cb) 791 cb(q, desc_info, cq_info, cb_arg); 792 } while (index != stop_index); 793 } 794