1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <[email protected]> 5 * Copyright (C) 2016 Florian Fainelli <[email protected]> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 } 435 436 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 437 { 438 u32 port_mask = 0; 439 u16 max_size = JMS_MIN_SIZE; 440 441 if (is5325(dev) || is5365(dev)) 442 return -EINVAL; 443 444 if (enable) { 445 port_mask = dev->enabled_ports; 446 max_size = JMS_MAX_SIZE; 447 if (allow_10_100) 448 port_mask |= JPM_10_100_JUMBO_EN; 449 } 450 451 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 452 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 453 } 454 455 static int b53_flush_arl(struct b53_device *dev, u8 mask) 456 { 457 unsigned int i; 458 459 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 460 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 461 462 for (i = 0; i < 10; i++) { 463 u8 fast_age_ctrl; 464 465 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 466 &fast_age_ctrl); 467 468 if (!(fast_age_ctrl & FAST_AGE_DONE)) 469 goto out; 470 471 msleep(1); 472 } 473 474 return -ETIMEDOUT; 475 out: 476 /* Only age dynamic entries (default behavior) */ 477 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 478 return 0; 479 } 480 481 static int b53_fast_age_port(struct b53_device *dev, int port) 482 { 483 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 484 485 return b53_flush_arl(dev, FAST_AGE_PORT); 486 } 487 488 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 489 { 490 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 491 492 return b53_flush_arl(dev, FAST_AGE_VLAN); 493 } 494 495 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 496 { 497 struct b53_device *dev = ds->priv; 498 unsigned int i; 499 u16 pvlan; 500 501 /* Enable the IMP port to be in the same VLAN as the other ports 502 * on a per-port basis such that we only have Port i and IMP in 503 * the same VLAN. 504 */ 505 b53_for_each_port(dev, i) { 506 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 507 pvlan |= BIT(cpu_port); 508 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 509 } 510 } 511 EXPORT_SYMBOL(b53_imp_vlan_setup); 512 513 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 514 bool unicast) 515 { 516 u16 uc; 517 518 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 519 if (unicast) 520 uc |= BIT(port); 521 else 522 uc &= ~BIT(port); 523 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 524 } 525 526 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 527 bool multicast) 528 { 529 u16 mc; 530 531 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 532 if (multicast) 533 mc |= BIT(port); 534 else 535 mc &= ~BIT(port); 536 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 537 538 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 539 if (multicast) 540 mc |= BIT(port); 541 else 542 mc &= ~BIT(port); 543 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 544 } 545 546 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 547 { 548 struct b53_device *dev = ds->priv; 549 unsigned int cpu_port; 550 int ret = 0; 551 u16 pvlan; 552 553 if (!dsa_is_user_port(ds, port)) 554 return 0; 555 556 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 557 558 b53_port_set_ucast_flood(dev, port, true); 559 b53_port_set_mcast_flood(dev, port, true); 560 561 if (dev->ops->irq_enable) 562 ret = dev->ops->irq_enable(dev, port); 563 if (ret) 564 return ret; 565 566 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 567 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 568 569 /* Set this port, and only this one to be in the default VLAN, 570 * if member of a bridge, restore its membership prior to 571 * bringing down this port. 572 */ 573 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 574 pvlan &= ~0x1ff; 575 pvlan |= BIT(port); 576 pvlan |= dev->ports[port].vlan_ctl_mask; 577 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 578 579 b53_imp_vlan_setup(ds, cpu_port); 580 581 /* If EEE was enabled, restore it */ 582 if (dev->ports[port].eee.eee_enabled) 583 b53_eee_enable_set(ds, port, true); 584 585 return 0; 586 } 587 EXPORT_SYMBOL(b53_enable_port); 588 589 void b53_disable_port(struct dsa_switch *ds, int port) 590 { 591 struct b53_device *dev = ds->priv; 592 u8 reg; 593 594 /* Disable Tx/Rx for the port */ 595 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 596 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 597 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 598 599 if (dev->ops->irq_disable) 600 dev->ops->irq_disable(dev, port); 601 } 602 EXPORT_SYMBOL(b53_disable_port); 603 604 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 605 { 606 struct b53_device *dev = ds->priv; 607 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 608 u8 hdr_ctl, val; 609 u16 reg; 610 611 /* Resolve which bit controls the Broadcom tag */ 612 switch (port) { 613 case 8: 614 val = BRCM_HDR_P8_EN; 615 break; 616 case 7: 617 val = BRCM_HDR_P7_EN; 618 break; 619 case 5: 620 val = BRCM_HDR_P5_EN; 621 break; 622 default: 623 val = 0; 624 break; 625 } 626 627 /* Enable management mode if tagging is requested */ 628 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 629 if (tag_en) 630 hdr_ctl |= SM_SW_FWD_MODE; 631 else 632 hdr_ctl &= ~SM_SW_FWD_MODE; 633 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 634 635 /* Configure the appropriate IMP port */ 636 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 637 if (port == 8) 638 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 639 else if (port == 5) 640 hdr_ctl |= GC_FRM_MGMT_PORT_M; 641 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 642 643 /* Enable Broadcom tags for IMP port */ 644 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 645 if (tag_en) 646 hdr_ctl |= val; 647 else 648 hdr_ctl &= ~val; 649 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 650 651 /* Registers below are only accessible on newer devices */ 652 if (!is58xx(dev)) 653 return; 654 655 /* Enable reception Broadcom tag for CPU TX (switch RX) to 656 * allow us to tag outgoing frames 657 */ 658 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 659 if (tag_en) 660 reg &= ~BIT(port); 661 else 662 reg |= BIT(port); 663 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 664 665 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 666 * allow delivering frames to the per-port net_devices 667 */ 668 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 669 if (tag_en) 670 reg &= ~BIT(port); 671 else 672 reg |= BIT(port); 673 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 674 } 675 EXPORT_SYMBOL(b53_brcm_hdr_setup); 676 677 static void b53_enable_cpu_port(struct b53_device *dev, int port) 678 { 679 u8 port_ctrl; 680 681 /* BCM5325 CPU port is at 8 */ 682 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 683 port = B53_CPU_PORT; 684 685 port_ctrl = PORT_CTRL_RX_BCST_EN | 686 PORT_CTRL_RX_MCST_EN | 687 PORT_CTRL_RX_UCST_EN; 688 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 689 690 b53_brcm_hdr_setup(dev->ds, port); 691 692 b53_port_set_ucast_flood(dev, port, true); 693 b53_port_set_mcast_flood(dev, port, true); 694 } 695 696 static void b53_enable_mib(struct b53_device *dev) 697 { 698 u8 gc; 699 700 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 701 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 702 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 703 } 704 705 static u16 b53_default_pvid(struct b53_device *dev) 706 { 707 if (is5325(dev) || is5365(dev)) 708 return 1; 709 else 710 return 0; 711 } 712 713 int b53_configure_vlan(struct dsa_switch *ds) 714 { 715 struct b53_device *dev = ds->priv; 716 struct b53_vlan vl = { 0 }; 717 struct b53_vlan *v; 718 int i, def_vid; 719 u16 vid; 720 721 def_vid = b53_default_pvid(dev); 722 723 /* clear all vlan entries */ 724 if (is5325(dev) || is5365(dev)) { 725 for (i = def_vid; i < dev->num_vlans; i++) 726 b53_set_vlan_entry(dev, i, &vl); 727 } else { 728 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 729 } 730 731 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering); 732 733 b53_for_each_port(dev, i) 734 b53_write16(dev, B53_VLAN_PAGE, 735 B53_VLAN_PORT_DEF_TAG(i), def_vid); 736 737 /* Upon initial call we have not set-up any VLANs, but upon 738 * system resume, we need to restore all VLAN entries. 739 */ 740 for (vid = def_vid; vid < dev->num_vlans; vid++) { 741 v = &dev->vlans[vid]; 742 743 if (!v->members) 744 continue; 745 746 b53_set_vlan_entry(dev, vid, v); 747 b53_fast_age_vlan(dev, vid); 748 } 749 750 return 0; 751 } 752 EXPORT_SYMBOL(b53_configure_vlan); 753 754 static void b53_switch_reset_gpio(struct b53_device *dev) 755 { 756 int gpio = dev->reset_gpio; 757 758 if (gpio < 0) 759 return; 760 761 /* Reset sequence: RESET low(50ms)->high(20ms) 762 */ 763 gpio_set_value(gpio, 0); 764 mdelay(50); 765 766 gpio_set_value(gpio, 1); 767 mdelay(20); 768 769 dev->current_page = 0xff; 770 } 771 772 static int b53_switch_reset(struct b53_device *dev) 773 { 774 unsigned int timeout = 1000; 775 u8 mgmt, reg; 776 777 b53_switch_reset_gpio(dev); 778 779 if (is539x(dev)) { 780 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 781 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 782 } 783 784 /* This is specific to 58xx devices here, do not use is58xx() which 785 * covers the larger Starfigther 2 family, including 7445/7278 which 786 * still use this driver as a library and need to perform the reset 787 * earlier. 788 */ 789 if (dev->chip_id == BCM58XX_DEVICE_ID || 790 dev->chip_id == BCM583XX_DEVICE_ID) { 791 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 792 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 793 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 794 795 do { 796 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 797 if (!(reg & SW_RST)) 798 break; 799 800 usleep_range(1000, 2000); 801 } while (timeout-- > 0); 802 803 if (timeout == 0) { 804 dev_err(dev->dev, 805 "Timeout waiting for SW_RST to clear!\n"); 806 return -ETIMEDOUT; 807 } 808 } 809 810 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 811 812 if (!(mgmt & SM_SW_FWD_EN)) { 813 mgmt &= ~SM_SW_FWD_MODE; 814 mgmt |= SM_SW_FWD_EN; 815 816 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 817 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 818 819 if (!(mgmt & SM_SW_FWD_EN)) { 820 dev_err(dev->dev, "Failed to enable switch!\n"); 821 return -EINVAL; 822 } 823 } 824 825 b53_enable_mib(dev); 826 827 return b53_flush_arl(dev, FAST_AGE_STATIC); 828 } 829 830 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 831 { 832 struct b53_device *priv = ds->priv; 833 u16 value = 0; 834 int ret; 835 836 if (priv->ops->phy_read16) 837 ret = priv->ops->phy_read16(priv, addr, reg, &value); 838 else 839 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 840 reg * 2, &value); 841 842 return ret ? ret : value; 843 } 844 845 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 846 { 847 struct b53_device *priv = ds->priv; 848 849 if (priv->ops->phy_write16) 850 return priv->ops->phy_write16(priv, addr, reg, val); 851 852 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 853 } 854 855 static int b53_reset_switch(struct b53_device *priv) 856 { 857 /* reset vlans */ 858 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 859 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 860 861 priv->serdes_lane = B53_INVALID_LANE; 862 863 return b53_switch_reset(priv); 864 } 865 866 static int b53_apply_config(struct b53_device *priv) 867 { 868 /* disable switching */ 869 b53_set_forwarding(priv, 0); 870 871 b53_configure_vlan(priv->ds); 872 873 /* enable switching */ 874 b53_set_forwarding(priv, 1); 875 876 return 0; 877 } 878 879 static void b53_reset_mib(struct b53_device *priv) 880 { 881 u8 gc; 882 883 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 884 885 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 886 msleep(1); 887 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 888 msleep(1); 889 } 890 891 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 892 { 893 if (is5365(dev)) 894 return b53_mibs_65; 895 else if (is63xx(dev)) 896 return b53_mibs_63xx; 897 else if (is58xx(dev)) 898 return b53_mibs_58xx; 899 else 900 return b53_mibs; 901 } 902 903 static unsigned int b53_get_mib_size(struct b53_device *dev) 904 { 905 if (is5365(dev)) 906 return B53_MIBS_65_SIZE; 907 else if (is63xx(dev)) 908 return B53_MIBS_63XX_SIZE; 909 else if (is58xx(dev)) 910 return B53_MIBS_58XX_SIZE; 911 else 912 return B53_MIBS_SIZE; 913 } 914 915 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 916 { 917 /* These ports typically do not have built-in PHYs */ 918 switch (port) { 919 case B53_CPU_PORT_25: 920 case 7: 921 case B53_CPU_PORT: 922 return NULL; 923 } 924 925 return mdiobus_get_phy(ds->slave_mii_bus, port); 926 } 927 928 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 929 uint8_t *data) 930 { 931 struct b53_device *dev = ds->priv; 932 const struct b53_mib_desc *mibs = b53_get_mib(dev); 933 unsigned int mib_size = b53_get_mib_size(dev); 934 struct phy_device *phydev; 935 unsigned int i; 936 937 if (stringset == ETH_SS_STATS) { 938 for (i = 0; i < mib_size; i++) 939 strlcpy(data + i * ETH_GSTRING_LEN, 940 mibs[i].name, ETH_GSTRING_LEN); 941 } else if (stringset == ETH_SS_PHY_STATS) { 942 phydev = b53_get_phy_device(ds, port); 943 if (!phydev) 944 return; 945 946 phy_ethtool_get_strings(phydev, data); 947 } 948 } 949 EXPORT_SYMBOL(b53_get_strings); 950 951 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 952 { 953 struct b53_device *dev = ds->priv; 954 const struct b53_mib_desc *mibs = b53_get_mib(dev); 955 unsigned int mib_size = b53_get_mib_size(dev); 956 const struct b53_mib_desc *s; 957 unsigned int i; 958 u64 val = 0; 959 960 if (is5365(dev) && port == 5) 961 port = 8; 962 963 mutex_lock(&dev->stats_mutex); 964 965 for (i = 0; i < mib_size; i++) { 966 s = &mibs[i]; 967 968 if (s->size == 8) { 969 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 970 } else { 971 u32 val32; 972 973 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 974 &val32); 975 val = val32; 976 } 977 data[i] = (u64)val; 978 } 979 980 mutex_unlock(&dev->stats_mutex); 981 } 982 EXPORT_SYMBOL(b53_get_ethtool_stats); 983 984 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 985 { 986 struct phy_device *phydev; 987 988 phydev = b53_get_phy_device(ds, port); 989 if (!phydev) 990 return; 991 992 phy_ethtool_get_stats(phydev, NULL, data); 993 } 994 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 995 996 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 997 { 998 struct b53_device *dev = ds->priv; 999 struct phy_device *phydev; 1000 1001 if (sset == ETH_SS_STATS) { 1002 return b53_get_mib_size(dev); 1003 } else if (sset == ETH_SS_PHY_STATS) { 1004 phydev = b53_get_phy_device(ds, port); 1005 if (!phydev) 1006 return 0; 1007 1008 return phy_ethtool_get_sset_count(phydev); 1009 } 1010 1011 return 0; 1012 } 1013 EXPORT_SYMBOL(b53_get_sset_count); 1014 1015 enum b53_devlink_resource_id { 1016 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1017 }; 1018 1019 static u64 b53_devlink_vlan_table_get(void *priv) 1020 { 1021 struct b53_device *dev = priv; 1022 struct b53_vlan *vl; 1023 unsigned int i; 1024 u64 count = 0; 1025 1026 for (i = 0; i < dev->num_vlans; i++) { 1027 vl = &dev->vlans[i]; 1028 if (vl->members) 1029 count++; 1030 } 1031 1032 return count; 1033 } 1034 1035 int b53_setup_devlink_resources(struct dsa_switch *ds) 1036 { 1037 struct devlink_resource_size_params size_params; 1038 struct b53_device *dev = ds->priv; 1039 int err; 1040 1041 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1042 dev->num_vlans, 1043 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1044 1045 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1046 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1047 DEVLINK_RESOURCE_ID_PARENT_TOP, 1048 &size_params); 1049 if (err) 1050 goto out; 1051 1052 dsa_devlink_resource_occ_get_register(ds, 1053 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1054 b53_devlink_vlan_table_get, dev); 1055 1056 return 0; 1057 out: 1058 dsa_devlink_resources_unregister(ds); 1059 return err; 1060 } 1061 EXPORT_SYMBOL(b53_setup_devlink_resources); 1062 1063 static int b53_setup(struct dsa_switch *ds) 1064 { 1065 struct b53_device *dev = ds->priv; 1066 unsigned int port; 1067 int ret; 1068 1069 ret = b53_reset_switch(dev); 1070 if (ret) { 1071 dev_err(ds->dev, "failed to reset switch\n"); 1072 return ret; 1073 } 1074 1075 b53_reset_mib(dev); 1076 1077 ret = b53_apply_config(dev); 1078 if (ret) { 1079 dev_err(ds->dev, "failed to apply configuration\n"); 1080 return ret; 1081 } 1082 1083 /* Configure IMP/CPU port, disable all other ports. Enabled 1084 * ports will be configured with .port_enable 1085 */ 1086 for (port = 0; port < dev->num_ports; port++) { 1087 if (dsa_is_cpu_port(ds, port)) 1088 b53_enable_cpu_port(dev, port); 1089 else 1090 b53_disable_port(ds, port); 1091 } 1092 1093 /* Let DSA handle the case were multiple bridges span the same switch 1094 * device and different VLAN awareness settings are requested, which 1095 * would be breaking filtering semantics for any of the other bridge 1096 * devices. (not hardware supported) 1097 */ 1098 ds->vlan_filtering_is_global = true; 1099 1100 return b53_setup_devlink_resources(ds); 1101 } 1102 1103 static void b53_teardown(struct dsa_switch *ds) 1104 { 1105 dsa_devlink_resources_unregister(ds); 1106 } 1107 1108 static void b53_force_link(struct b53_device *dev, int port, int link) 1109 { 1110 u8 reg, val, off; 1111 1112 /* Override the port settings */ 1113 if (port == dev->cpu_port) { 1114 off = B53_PORT_OVERRIDE_CTRL; 1115 val = PORT_OVERRIDE_EN; 1116 } else { 1117 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1118 val = GMII_PO_EN; 1119 } 1120 1121 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1122 reg |= val; 1123 if (link) 1124 reg |= PORT_OVERRIDE_LINK; 1125 else 1126 reg &= ~PORT_OVERRIDE_LINK; 1127 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1128 } 1129 1130 static void b53_force_port_config(struct b53_device *dev, int port, 1131 int speed, int duplex, 1132 bool tx_pause, bool rx_pause) 1133 { 1134 u8 reg, val, off; 1135 1136 /* Override the port settings */ 1137 if (port == dev->cpu_port) { 1138 off = B53_PORT_OVERRIDE_CTRL; 1139 val = PORT_OVERRIDE_EN; 1140 } else { 1141 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1142 val = GMII_PO_EN; 1143 } 1144 1145 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1146 reg |= val; 1147 if (duplex == DUPLEX_FULL) 1148 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1149 else 1150 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1151 1152 switch (speed) { 1153 case 2000: 1154 reg |= PORT_OVERRIDE_SPEED_2000M; 1155 fallthrough; 1156 case SPEED_1000: 1157 reg |= PORT_OVERRIDE_SPEED_1000M; 1158 break; 1159 case SPEED_100: 1160 reg |= PORT_OVERRIDE_SPEED_100M; 1161 break; 1162 case SPEED_10: 1163 reg |= PORT_OVERRIDE_SPEED_10M; 1164 break; 1165 default: 1166 dev_err(dev->dev, "unknown speed: %d\n", speed); 1167 return; 1168 } 1169 1170 if (rx_pause) 1171 reg |= PORT_OVERRIDE_RX_FLOW; 1172 if (tx_pause) 1173 reg |= PORT_OVERRIDE_TX_FLOW; 1174 1175 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1176 } 1177 1178 static void b53_adjust_link(struct dsa_switch *ds, int port, 1179 struct phy_device *phydev) 1180 { 1181 struct b53_device *dev = ds->priv; 1182 struct ethtool_eee *p = &dev->ports[port].eee; 1183 u8 rgmii_ctrl = 0, reg = 0, off; 1184 bool tx_pause = false; 1185 bool rx_pause = false; 1186 1187 if (!phy_is_pseudo_fixed_link(phydev)) 1188 return; 1189 1190 /* Enable flow control on BCM5301x's CPU port */ 1191 if (is5301x(dev) && port == dev->cpu_port) 1192 tx_pause = rx_pause = true; 1193 1194 if (phydev->pause) { 1195 if (phydev->asym_pause) 1196 tx_pause = true; 1197 rx_pause = true; 1198 } 1199 1200 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1201 tx_pause, rx_pause); 1202 b53_force_link(dev, port, phydev->link); 1203 1204 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1205 if (port == 8) 1206 off = B53_RGMII_CTRL_IMP; 1207 else 1208 off = B53_RGMII_CTRL_P(port); 1209 1210 /* Configure the port RGMII clock delay by DLL disabled and 1211 * tx_clk aligned timing (restoring to reset defaults) 1212 */ 1213 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1214 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1215 RGMII_CTRL_TIMING_SEL); 1216 1217 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1218 * sure that we enable the port TX clock internal delay to 1219 * account for this internal delay that is inserted, otherwise 1220 * the switch won't be able to receive correctly. 1221 * 1222 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1223 * any delay neither on transmission nor reception, so the 1224 * BCM53125 must also be configured accordingly to account for 1225 * the lack of delay and introduce 1226 * 1227 * The BCM53125 switch has its RX clock and TX clock control 1228 * swapped, hence the reason why we modify the TX clock path in 1229 * the "RGMII" case 1230 */ 1231 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1232 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1233 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1234 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1235 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1236 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1237 1238 dev_info(ds->dev, "Configured port %d for %s\n", port, 1239 phy_modes(phydev->interface)); 1240 } 1241 1242 /* configure MII port if necessary */ 1243 if (is5325(dev)) { 1244 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1245 ®); 1246 1247 /* reverse mii needs to be enabled */ 1248 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1249 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1250 reg | PORT_OVERRIDE_RV_MII_25); 1251 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1252 ®); 1253 1254 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1255 dev_err(ds->dev, 1256 "Failed to enable reverse MII mode\n"); 1257 return; 1258 } 1259 } 1260 } else if (is5301x(dev)) { 1261 if (port != dev->cpu_port) { 1262 b53_force_port_config(dev, dev->cpu_port, 2000, 1263 DUPLEX_FULL, true, true); 1264 b53_force_link(dev, dev->cpu_port, 1); 1265 } 1266 } 1267 1268 /* Re-negotiate EEE if it was enabled already */ 1269 p->eee_enabled = b53_eee_init(ds, port, phydev); 1270 } 1271 1272 void b53_port_event(struct dsa_switch *ds, int port) 1273 { 1274 struct b53_device *dev = ds->priv; 1275 bool link; 1276 u16 sts; 1277 1278 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1279 link = !!(sts & BIT(port)); 1280 dsa_port_phylink_mac_change(ds, port, link); 1281 } 1282 EXPORT_SYMBOL(b53_port_event); 1283 1284 void b53_phylink_validate(struct dsa_switch *ds, int port, 1285 unsigned long *supported, 1286 struct phylink_link_state *state) 1287 { 1288 struct b53_device *dev = ds->priv; 1289 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1290 1291 if (dev->ops->serdes_phylink_validate) 1292 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1293 1294 /* Allow all the expected bits */ 1295 phylink_set(mask, Autoneg); 1296 phylink_set_port_modes(mask); 1297 phylink_set(mask, Pause); 1298 phylink_set(mask, Asym_Pause); 1299 1300 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1301 * support Gigabit, including Half duplex. 1302 */ 1303 if (state->interface != PHY_INTERFACE_MODE_MII && 1304 state->interface != PHY_INTERFACE_MODE_REVMII && 1305 !phy_interface_mode_is_8023z(state->interface) && 1306 !(is5325(dev) || is5365(dev))) { 1307 phylink_set(mask, 1000baseT_Full); 1308 phylink_set(mask, 1000baseT_Half); 1309 } 1310 1311 if (!phy_interface_mode_is_8023z(state->interface)) { 1312 phylink_set(mask, 10baseT_Half); 1313 phylink_set(mask, 10baseT_Full); 1314 phylink_set(mask, 100baseT_Half); 1315 phylink_set(mask, 100baseT_Full); 1316 } 1317 1318 bitmap_and(supported, supported, mask, 1319 __ETHTOOL_LINK_MODE_MASK_NBITS); 1320 bitmap_and(state->advertising, state->advertising, mask, 1321 __ETHTOOL_LINK_MODE_MASK_NBITS); 1322 1323 phylink_helper_basex_speed(state); 1324 } 1325 EXPORT_SYMBOL(b53_phylink_validate); 1326 1327 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1328 struct phylink_link_state *state) 1329 { 1330 struct b53_device *dev = ds->priv; 1331 int ret = -EOPNOTSUPP; 1332 1333 if ((phy_interface_mode_is_8023z(state->interface) || 1334 state->interface == PHY_INTERFACE_MODE_SGMII) && 1335 dev->ops->serdes_link_state) 1336 ret = dev->ops->serdes_link_state(dev, port, state); 1337 1338 return ret; 1339 } 1340 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1341 1342 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1343 unsigned int mode, 1344 const struct phylink_link_state *state) 1345 { 1346 struct b53_device *dev = ds->priv; 1347 1348 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) 1349 return; 1350 1351 if ((phy_interface_mode_is_8023z(state->interface) || 1352 state->interface == PHY_INTERFACE_MODE_SGMII) && 1353 dev->ops->serdes_config) 1354 dev->ops->serdes_config(dev, port, mode, state); 1355 } 1356 EXPORT_SYMBOL(b53_phylink_mac_config); 1357 1358 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1359 { 1360 struct b53_device *dev = ds->priv; 1361 1362 if (dev->ops->serdes_an_restart) 1363 dev->ops->serdes_an_restart(dev, port); 1364 } 1365 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1366 1367 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1368 unsigned int mode, 1369 phy_interface_t interface) 1370 { 1371 struct b53_device *dev = ds->priv; 1372 1373 if (mode == MLO_AN_PHY) 1374 return; 1375 1376 if (mode == MLO_AN_FIXED) { 1377 b53_force_link(dev, port, false); 1378 return; 1379 } 1380 1381 if (phy_interface_mode_is_8023z(interface) && 1382 dev->ops->serdes_link_set) 1383 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1384 } 1385 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1386 1387 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1388 unsigned int mode, 1389 phy_interface_t interface, 1390 struct phy_device *phydev, 1391 int speed, int duplex, 1392 bool tx_pause, bool rx_pause) 1393 { 1394 struct b53_device *dev = ds->priv; 1395 1396 if (mode == MLO_AN_PHY) 1397 return; 1398 1399 if (mode == MLO_AN_FIXED) { 1400 b53_force_port_config(dev, port, speed, duplex, 1401 tx_pause, rx_pause); 1402 b53_force_link(dev, port, true); 1403 return; 1404 } 1405 1406 if (phy_interface_mode_is_8023z(interface) && 1407 dev->ops->serdes_link_set) 1408 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1409 } 1410 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1411 1412 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1413 { 1414 struct b53_device *dev = ds->priv; 1415 1416 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1417 1418 return 0; 1419 } 1420 EXPORT_SYMBOL(b53_vlan_filtering); 1421 1422 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1423 const struct switchdev_obj_port_vlan *vlan) 1424 { 1425 struct b53_device *dev = ds->priv; 1426 1427 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1428 return -EOPNOTSUPP; 1429 1430 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1431 * receiving VLAN tagged frames at all, we can still allow the port to 1432 * be configured for egress untagged. 1433 */ 1434 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1435 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1436 return -EINVAL; 1437 1438 if (vlan->vid >= dev->num_vlans) 1439 return -ERANGE; 1440 1441 b53_enable_vlan(dev, true, ds->vlan_filtering); 1442 1443 return 0; 1444 } 1445 1446 int b53_vlan_add(struct dsa_switch *ds, int port, 1447 const struct switchdev_obj_port_vlan *vlan) 1448 { 1449 struct b53_device *dev = ds->priv; 1450 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1451 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1452 struct b53_vlan *vl; 1453 int err; 1454 1455 err = b53_vlan_prepare(ds, port, vlan); 1456 if (err) 1457 return err; 1458 1459 vl = &dev->vlans[vlan->vid]; 1460 1461 b53_get_vlan_entry(dev, vlan->vid, vl); 1462 1463 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1464 untagged = true; 1465 1466 vl->members |= BIT(port); 1467 if (untagged && !dsa_is_cpu_port(ds, port)) 1468 vl->untag |= BIT(port); 1469 else 1470 vl->untag &= ~BIT(port); 1471 1472 b53_set_vlan_entry(dev, vlan->vid, vl); 1473 b53_fast_age_vlan(dev, vlan->vid); 1474 1475 if (pvid && !dsa_is_cpu_port(ds, port)) { 1476 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1477 vlan->vid); 1478 b53_fast_age_vlan(dev, vlan->vid); 1479 } 1480 1481 return 0; 1482 } 1483 EXPORT_SYMBOL(b53_vlan_add); 1484 1485 int b53_vlan_del(struct dsa_switch *ds, int port, 1486 const struct switchdev_obj_port_vlan *vlan) 1487 { 1488 struct b53_device *dev = ds->priv; 1489 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1490 struct b53_vlan *vl; 1491 u16 pvid; 1492 1493 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1494 1495 vl = &dev->vlans[vlan->vid]; 1496 1497 b53_get_vlan_entry(dev, vlan->vid, vl); 1498 1499 vl->members &= ~BIT(port); 1500 1501 if (pvid == vlan->vid) 1502 pvid = b53_default_pvid(dev); 1503 1504 if (untagged && !dsa_is_cpu_port(ds, port)) 1505 vl->untag &= ~(BIT(port)); 1506 1507 b53_set_vlan_entry(dev, vlan->vid, vl); 1508 b53_fast_age_vlan(dev, vlan->vid); 1509 1510 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1511 b53_fast_age_vlan(dev, pvid); 1512 1513 return 0; 1514 } 1515 EXPORT_SYMBOL(b53_vlan_del); 1516 1517 /* Address Resolution Logic routines */ 1518 static int b53_arl_op_wait(struct b53_device *dev) 1519 { 1520 unsigned int timeout = 10; 1521 u8 reg; 1522 1523 do { 1524 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1525 if (!(reg & ARLTBL_START_DONE)) 1526 return 0; 1527 1528 usleep_range(1000, 2000); 1529 } while (timeout--); 1530 1531 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1532 1533 return -ETIMEDOUT; 1534 } 1535 1536 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1537 { 1538 u8 reg; 1539 1540 if (op > ARLTBL_RW) 1541 return -EINVAL; 1542 1543 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1544 reg |= ARLTBL_START_DONE; 1545 if (op) 1546 reg |= ARLTBL_RW; 1547 else 1548 reg &= ~ARLTBL_RW; 1549 if (dev->vlan_enabled) 1550 reg &= ~ARLTBL_IVL_SVL_SELECT; 1551 else 1552 reg |= ARLTBL_IVL_SVL_SELECT; 1553 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1554 1555 return b53_arl_op_wait(dev); 1556 } 1557 1558 static int b53_arl_read(struct b53_device *dev, u64 mac, 1559 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1560 { 1561 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1562 unsigned int i; 1563 int ret; 1564 1565 ret = b53_arl_op_wait(dev); 1566 if (ret) 1567 return ret; 1568 1569 bitmap_zero(free_bins, dev->num_arl_bins); 1570 1571 /* Read the bins */ 1572 for (i = 0; i < dev->num_arl_bins; i++) { 1573 u64 mac_vid; 1574 u32 fwd_entry; 1575 1576 b53_read64(dev, B53_ARLIO_PAGE, 1577 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1578 b53_read32(dev, B53_ARLIO_PAGE, 1579 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1580 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1581 1582 if (!(fwd_entry & ARLTBL_VALID)) { 1583 set_bit(i, free_bins); 1584 continue; 1585 } 1586 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1587 continue; 1588 if (dev->vlan_enabled && 1589 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1590 continue; 1591 *idx = i; 1592 return 0; 1593 } 1594 1595 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1596 return -ENOSPC; 1597 1598 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1599 1600 return -ENOENT; 1601 } 1602 1603 static int b53_arl_op(struct b53_device *dev, int op, int port, 1604 const unsigned char *addr, u16 vid, bool is_valid) 1605 { 1606 struct b53_arl_entry ent; 1607 u32 fwd_entry; 1608 u64 mac, mac_vid = 0; 1609 u8 idx = 0; 1610 int ret; 1611 1612 /* Convert the array into a 64-bit MAC */ 1613 mac = ether_addr_to_u64(addr); 1614 1615 /* Perform a read for the given MAC and VID */ 1616 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1617 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1618 1619 /* Issue a read operation for this MAC */ 1620 ret = b53_arl_rw_op(dev, 1); 1621 if (ret) 1622 return ret; 1623 1624 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1625 1626 /* If this is a read, just finish now */ 1627 if (op) 1628 return ret; 1629 1630 switch (ret) { 1631 case -ETIMEDOUT: 1632 return ret; 1633 case -ENOSPC: 1634 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1635 addr, vid); 1636 return is_valid ? ret : 0; 1637 case -ENOENT: 1638 /* We could not find a matching MAC, so reset to a new entry */ 1639 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1640 addr, vid, idx); 1641 fwd_entry = 0; 1642 break; 1643 default: 1644 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1645 addr, vid, idx); 1646 break; 1647 } 1648 1649 /* For multicast address, the port is a bitmask and the validity 1650 * is determined by having at least one port being still active 1651 */ 1652 if (!is_multicast_ether_addr(addr)) { 1653 ent.port = port; 1654 ent.is_valid = is_valid; 1655 } else { 1656 if (is_valid) 1657 ent.port |= BIT(port); 1658 else 1659 ent.port &= ~BIT(port); 1660 1661 ent.is_valid = !!(ent.port); 1662 } 1663 1664 ent.vid = vid; 1665 ent.is_static = true; 1666 ent.is_age = false; 1667 memcpy(ent.mac, addr, ETH_ALEN); 1668 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1669 1670 b53_write64(dev, B53_ARLIO_PAGE, 1671 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1672 b53_write32(dev, B53_ARLIO_PAGE, 1673 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1674 1675 return b53_arl_rw_op(dev, 0); 1676 } 1677 1678 int b53_fdb_add(struct dsa_switch *ds, int port, 1679 const unsigned char *addr, u16 vid) 1680 { 1681 struct b53_device *priv = ds->priv; 1682 1683 /* 5325 and 5365 require some more massaging, but could 1684 * be supported eventually 1685 */ 1686 if (is5325(priv) || is5365(priv)) 1687 return -EOPNOTSUPP; 1688 1689 return b53_arl_op(priv, 0, port, addr, vid, true); 1690 } 1691 EXPORT_SYMBOL(b53_fdb_add); 1692 1693 int b53_fdb_del(struct dsa_switch *ds, int port, 1694 const unsigned char *addr, u16 vid) 1695 { 1696 struct b53_device *priv = ds->priv; 1697 1698 return b53_arl_op(priv, 0, port, addr, vid, false); 1699 } 1700 EXPORT_SYMBOL(b53_fdb_del); 1701 1702 static int b53_arl_search_wait(struct b53_device *dev) 1703 { 1704 unsigned int timeout = 1000; 1705 u8 reg; 1706 1707 do { 1708 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1709 if (!(reg & ARL_SRCH_STDN)) 1710 return 0; 1711 1712 if (reg & ARL_SRCH_VLID) 1713 return 0; 1714 1715 usleep_range(1000, 2000); 1716 } while (timeout--); 1717 1718 return -ETIMEDOUT; 1719 } 1720 1721 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1722 struct b53_arl_entry *ent) 1723 { 1724 u64 mac_vid; 1725 u32 fwd_entry; 1726 1727 b53_read64(dev, B53_ARLIO_PAGE, 1728 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1729 b53_read32(dev, B53_ARLIO_PAGE, 1730 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1731 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1732 } 1733 1734 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1735 dsa_fdb_dump_cb_t *cb, void *data) 1736 { 1737 if (!ent->is_valid) 1738 return 0; 1739 1740 if (port != ent->port) 1741 return 0; 1742 1743 return cb(ent->mac, ent->vid, ent->is_static, data); 1744 } 1745 1746 int b53_fdb_dump(struct dsa_switch *ds, int port, 1747 dsa_fdb_dump_cb_t *cb, void *data) 1748 { 1749 struct b53_device *priv = ds->priv; 1750 struct b53_arl_entry results[2]; 1751 unsigned int count = 0; 1752 int ret; 1753 u8 reg; 1754 1755 /* Start search operation */ 1756 reg = ARL_SRCH_STDN; 1757 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1758 1759 do { 1760 ret = b53_arl_search_wait(priv); 1761 if (ret) 1762 return ret; 1763 1764 b53_arl_search_rd(priv, 0, &results[0]); 1765 ret = b53_fdb_copy(port, &results[0], cb, data); 1766 if (ret) 1767 return ret; 1768 1769 if (priv->num_arl_bins > 2) { 1770 b53_arl_search_rd(priv, 1, &results[1]); 1771 ret = b53_fdb_copy(port, &results[1], cb, data); 1772 if (ret) 1773 return ret; 1774 1775 if (!results[0].is_valid && !results[1].is_valid) 1776 break; 1777 } 1778 1779 } while (count++ < b53_max_arl_entries(priv) / 2); 1780 1781 return 0; 1782 } 1783 EXPORT_SYMBOL(b53_fdb_dump); 1784 1785 int b53_mdb_add(struct dsa_switch *ds, int port, 1786 const struct switchdev_obj_port_mdb *mdb) 1787 { 1788 struct b53_device *priv = ds->priv; 1789 1790 /* 5325 and 5365 require some more massaging, but could 1791 * be supported eventually 1792 */ 1793 if (is5325(priv) || is5365(priv)) 1794 return -EOPNOTSUPP; 1795 1796 return b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1797 } 1798 EXPORT_SYMBOL(b53_mdb_add); 1799 1800 int b53_mdb_del(struct dsa_switch *ds, int port, 1801 const struct switchdev_obj_port_mdb *mdb) 1802 { 1803 struct b53_device *priv = ds->priv; 1804 int ret; 1805 1806 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1807 if (ret) 1808 dev_err(ds->dev, "failed to delete MDB entry\n"); 1809 1810 return ret; 1811 } 1812 EXPORT_SYMBOL(b53_mdb_del); 1813 1814 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1815 { 1816 struct b53_device *dev = ds->priv; 1817 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1818 u16 pvlan, reg; 1819 unsigned int i; 1820 1821 /* On 7278, port 7 which connects to the ASP should only receive 1822 * traffic from matching CFP rules. 1823 */ 1824 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1825 return -EINVAL; 1826 1827 /* Make this port leave the all VLANs join since we will have proper 1828 * VLAN entries from now on 1829 */ 1830 if (is58xx(dev)) { 1831 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1832 reg &= ~BIT(port); 1833 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1834 reg &= ~BIT(cpu_port); 1835 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1836 } 1837 1838 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1839 1840 b53_for_each_port(dev, i) { 1841 if (dsa_to_port(ds, i)->bridge_dev != br) 1842 continue; 1843 1844 /* Add this local port to the remote port VLAN control 1845 * membership and update the remote port bitmask 1846 */ 1847 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1848 reg |= BIT(port); 1849 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1850 dev->ports[i].vlan_ctl_mask = reg; 1851 1852 pvlan |= BIT(i); 1853 } 1854 1855 /* Configure the local port VLAN control membership to include 1856 * remote ports and update the local port bitmask 1857 */ 1858 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1859 dev->ports[port].vlan_ctl_mask = pvlan; 1860 1861 return 0; 1862 } 1863 EXPORT_SYMBOL(b53_br_join); 1864 1865 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1866 { 1867 struct b53_device *dev = ds->priv; 1868 struct b53_vlan *vl = &dev->vlans[0]; 1869 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1870 unsigned int i; 1871 u16 pvlan, reg, pvid; 1872 1873 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1874 1875 b53_for_each_port(dev, i) { 1876 /* Don't touch the remaining ports */ 1877 if (dsa_to_port(ds, i)->bridge_dev != br) 1878 continue; 1879 1880 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1881 reg &= ~BIT(port); 1882 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1883 dev->ports[port].vlan_ctl_mask = reg; 1884 1885 /* Prevent self removal to preserve isolation */ 1886 if (port != i) 1887 pvlan &= ~BIT(i); 1888 } 1889 1890 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1891 dev->ports[port].vlan_ctl_mask = pvlan; 1892 1893 pvid = b53_default_pvid(dev); 1894 1895 /* Make this port join all VLANs without VLAN entries */ 1896 if (is58xx(dev)) { 1897 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1898 reg |= BIT(port); 1899 if (!(reg & BIT(cpu_port))) 1900 reg |= BIT(cpu_port); 1901 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1902 } else { 1903 b53_get_vlan_entry(dev, pvid, vl); 1904 vl->members |= BIT(port) | BIT(cpu_port); 1905 vl->untag |= BIT(port) | BIT(cpu_port); 1906 b53_set_vlan_entry(dev, pvid, vl); 1907 } 1908 } 1909 EXPORT_SYMBOL(b53_br_leave); 1910 1911 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1912 { 1913 struct b53_device *dev = ds->priv; 1914 u8 hw_state; 1915 u8 reg; 1916 1917 switch (state) { 1918 case BR_STATE_DISABLED: 1919 hw_state = PORT_CTRL_DIS_STATE; 1920 break; 1921 case BR_STATE_LISTENING: 1922 hw_state = PORT_CTRL_LISTEN_STATE; 1923 break; 1924 case BR_STATE_LEARNING: 1925 hw_state = PORT_CTRL_LEARN_STATE; 1926 break; 1927 case BR_STATE_FORWARDING: 1928 hw_state = PORT_CTRL_FWD_STATE; 1929 break; 1930 case BR_STATE_BLOCKING: 1931 hw_state = PORT_CTRL_BLOCK_STATE; 1932 break; 1933 default: 1934 dev_err(ds->dev, "invalid STP state: %d\n", state); 1935 return; 1936 } 1937 1938 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1939 reg &= ~PORT_CTRL_STP_STATE_MASK; 1940 reg |= hw_state; 1941 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1942 } 1943 EXPORT_SYMBOL(b53_br_set_stp_state); 1944 1945 void b53_br_fast_age(struct dsa_switch *ds, int port) 1946 { 1947 struct b53_device *dev = ds->priv; 1948 1949 if (b53_fast_age_port(dev, port)) 1950 dev_err(ds->dev, "fast ageing failed\n"); 1951 } 1952 EXPORT_SYMBOL(b53_br_fast_age); 1953 1954 static int b53_br_flags_pre(struct dsa_switch *ds, int port, 1955 struct switchdev_brport_flags flags, 1956 struct netlink_ext_ack *extack) 1957 { 1958 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD)) 1959 return -EINVAL; 1960 1961 return 0; 1962 } 1963 1964 static int b53_br_flags(struct dsa_switch *ds, int port, 1965 struct switchdev_brport_flags flags, 1966 struct netlink_ext_ack *extack) 1967 { 1968 if (flags.mask & BR_FLOOD) 1969 b53_port_set_ucast_flood(ds->priv, port, 1970 !!(flags.val & BR_FLOOD)); 1971 if (flags.mask & BR_MCAST_FLOOD) 1972 b53_port_set_mcast_flood(ds->priv, port, 1973 !!(flags.val & BR_MCAST_FLOOD)); 1974 1975 return 0; 1976 } 1977 1978 static int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 1979 struct netlink_ext_ack *extack) 1980 { 1981 b53_port_set_mcast_flood(ds->priv, port, mrouter); 1982 1983 return 0; 1984 } 1985 1986 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1987 { 1988 /* Broadcom switches will accept enabling Broadcom tags on the 1989 * following ports: 5, 7 and 8, any other port is not supported 1990 */ 1991 switch (port) { 1992 case B53_CPU_PORT_25: 1993 case 7: 1994 case B53_CPU_PORT: 1995 return true; 1996 } 1997 1998 return false; 1999 } 2000 2001 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2002 enum dsa_tag_protocol tag_protocol) 2003 { 2004 bool ret = b53_possible_cpu_port(ds, port); 2005 2006 if (!ret) { 2007 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2008 port); 2009 return ret; 2010 } 2011 2012 switch (tag_protocol) { 2013 case DSA_TAG_PROTO_BRCM: 2014 case DSA_TAG_PROTO_BRCM_PREPEND: 2015 dev_warn(ds->dev, 2016 "Port %d is stacked to Broadcom tag switch\n", port); 2017 ret = false; 2018 break; 2019 default: 2020 ret = true; 2021 break; 2022 } 2023 2024 return ret; 2025 } 2026 2027 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2028 enum dsa_tag_protocol mprot) 2029 { 2030 struct b53_device *dev = ds->priv; 2031 2032 /* Older models (5325, 5365) support a different tag format that we do 2033 * not support in net/dsa/tag_brcm.c yet. 2034 */ 2035 if (is5325(dev) || is5365(dev) || 2036 !b53_can_enable_brcm_tags(ds, port, mprot)) { 2037 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2038 goto out; 2039 } 2040 2041 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2042 * which requires us to use the prepended Broadcom tag type 2043 */ 2044 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2045 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2046 goto out; 2047 } 2048 2049 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2050 out: 2051 return dev->tag_protocol; 2052 } 2053 EXPORT_SYMBOL(b53_get_tag_protocol); 2054 2055 int b53_mirror_add(struct dsa_switch *ds, int port, 2056 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 2057 { 2058 struct b53_device *dev = ds->priv; 2059 u16 reg, loc; 2060 2061 if (ingress) 2062 loc = B53_IG_MIR_CTL; 2063 else 2064 loc = B53_EG_MIR_CTL; 2065 2066 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2067 reg |= BIT(port); 2068 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2069 2070 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2071 reg &= ~CAP_PORT_MASK; 2072 reg |= mirror->to_local_port; 2073 reg |= MIRROR_EN; 2074 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2075 2076 return 0; 2077 } 2078 EXPORT_SYMBOL(b53_mirror_add); 2079 2080 void b53_mirror_del(struct dsa_switch *ds, int port, 2081 struct dsa_mall_mirror_tc_entry *mirror) 2082 { 2083 struct b53_device *dev = ds->priv; 2084 bool loc_disable = false, other_loc_disable = false; 2085 u16 reg, loc; 2086 2087 if (mirror->ingress) 2088 loc = B53_IG_MIR_CTL; 2089 else 2090 loc = B53_EG_MIR_CTL; 2091 2092 /* Update the desired ingress/egress register */ 2093 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2094 reg &= ~BIT(port); 2095 if (!(reg & MIRROR_MASK)) 2096 loc_disable = true; 2097 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2098 2099 /* Now look at the other one to know if we can disable mirroring 2100 * entirely 2101 */ 2102 if (mirror->ingress) 2103 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2104 else 2105 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2106 if (!(reg & MIRROR_MASK)) 2107 other_loc_disable = true; 2108 2109 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2110 /* Both no longer have ports, let's disable mirroring */ 2111 if (loc_disable && other_loc_disable) { 2112 reg &= ~MIRROR_EN; 2113 reg &= ~mirror->to_local_port; 2114 } 2115 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2116 } 2117 EXPORT_SYMBOL(b53_mirror_del); 2118 2119 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2120 { 2121 struct b53_device *dev = ds->priv; 2122 u16 reg; 2123 2124 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2125 if (enable) 2126 reg |= BIT(port); 2127 else 2128 reg &= ~BIT(port); 2129 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2130 } 2131 EXPORT_SYMBOL(b53_eee_enable_set); 2132 2133 2134 /* Returns 0 if EEE was not enabled, or 1 otherwise 2135 */ 2136 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2137 { 2138 int ret; 2139 2140 ret = phy_init_eee(phy, 0); 2141 if (ret) 2142 return 0; 2143 2144 b53_eee_enable_set(ds, port, true); 2145 2146 return 1; 2147 } 2148 EXPORT_SYMBOL(b53_eee_init); 2149 2150 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2151 { 2152 struct b53_device *dev = ds->priv; 2153 struct ethtool_eee *p = &dev->ports[port].eee; 2154 u16 reg; 2155 2156 if (is5325(dev) || is5365(dev)) 2157 return -EOPNOTSUPP; 2158 2159 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2160 e->eee_enabled = p->eee_enabled; 2161 e->eee_active = !!(reg & BIT(port)); 2162 2163 return 0; 2164 } 2165 EXPORT_SYMBOL(b53_get_mac_eee); 2166 2167 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2168 { 2169 struct b53_device *dev = ds->priv; 2170 struct ethtool_eee *p = &dev->ports[port].eee; 2171 2172 if (is5325(dev) || is5365(dev)) 2173 return -EOPNOTSUPP; 2174 2175 p->eee_enabled = e->eee_enabled; 2176 b53_eee_enable_set(ds, port, e->eee_enabled); 2177 2178 return 0; 2179 } 2180 EXPORT_SYMBOL(b53_set_mac_eee); 2181 2182 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2183 { 2184 struct b53_device *dev = ds->priv; 2185 bool enable_jumbo; 2186 bool allow_10_100; 2187 2188 if (is5325(dev) || is5365(dev)) 2189 return -EOPNOTSUPP; 2190 2191 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2192 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2193 2194 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2195 } 2196 2197 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2198 { 2199 return JMS_MAX_SIZE; 2200 } 2201 2202 static const struct dsa_switch_ops b53_switch_ops = { 2203 .get_tag_protocol = b53_get_tag_protocol, 2204 .setup = b53_setup, 2205 .teardown = b53_teardown, 2206 .get_strings = b53_get_strings, 2207 .get_ethtool_stats = b53_get_ethtool_stats, 2208 .get_sset_count = b53_get_sset_count, 2209 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2210 .phy_read = b53_phy_read16, 2211 .phy_write = b53_phy_write16, 2212 .adjust_link = b53_adjust_link, 2213 .phylink_validate = b53_phylink_validate, 2214 .phylink_mac_link_state = b53_phylink_mac_link_state, 2215 .phylink_mac_config = b53_phylink_mac_config, 2216 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2217 .phylink_mac_link_down = b53_phylink_mac_link_down, 2218 .phylink_mac_link_up = b53_phylink_mac_link_up, 2219 .port_enable = b53_enable_port, 2220 .port_disable = b53_disable_port, 2221 .get_mac_eee = b53_get_mac_eee, 2222 .set_mac_eee = b53_set_mac_eee, 2223 .port_bridge_join = b53_br_join, 2224 .port_bridge_leave = b53_br_leave, 2225 .port_pre_bridge_flags = b53_br_flags_pre, 2226 .port_bridge_flags = b53_br_flags, 2227 .port_set_mrouter = b53_set_mrouter, 2228 .port_stp_state_set = b53_br_set_stp_state, 2229 .port_fast_age = b53_br_fast_age, 2230 .port_vlan_filtering = b53_vlan_filtering, 2231 .port_vlan_add = b53_vlan_add, 2232 .port_vlan_del = b53_vlan_del, 2233 .port_fdb_dump = b53_fdb_dump, 2234 .port_fdb_add = b53_fdb_add, 2235 .port_fdb_del = b53_fdb_del, 2236 .port_mirror_add = b53_mirror_add, 2237 .port_mirror_del = b53_mirror_del, 2238 .port_mdb_add = b53_mdb_add, 2239 .port_mdb_del = b53_mdb_del, 2240 .port_max_mtu = b53_get_max_mtu, 2241 .port_change_mtu = b53_change_mtu, 2242 }; 2243 2244 struct b53_chip_data { 2245 u32 chip_id; 2246 const char *dev_name; 2247 u16 vlans; 2248 u16 enabled_ports; 2249 u8 cpu_port; 2250 u8 vta_regs[3]; 2251 u8 arl_bins; 2252 u16 arl_buckets; 2253 u8 duplex_reg; 2254 u8 jumbo_pm_reg; 2255 u8 jumbo_size_reg; 2256 }; 2257 2258 #define B53_VTA_REGS \ 2259 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2260 #define B53_VTA_REGS_9798 \ 2261 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2262 #define B53_VTA_REGS_63XX \ 2263 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2264 2265 static const struct b53_chip_data b53_switch_chips[] = { 2266 { 2267 .chip_id = BCM5325_DEVICE_ID, 2268 .dev_name = "BCM5325", 2269 .vlans = 16, 2270 .enabled_ports = 0x1f, 2271 .arl_bins = 2, 2272 .arl_buckets = 1024, 2273 .cpu_port = B53_CPU_PORT_25, 2274 .duplex_reg = B53_DUPLEX_STAT_FE, 2275 }, 2276 { 2277 .chip_id = BCM5365_DEVICE_ID, 2278 .dev_name = "BCM5365", 2279 .vlans = 256, 2280 .enabled_ports = 0x1f, 2281 .arl_bins = 2, 2282 .arl_buckets = 1024, 2283 .cpu_port = B53_CPU_PORT_25, 2284 .duplex_reg = B53_DUPLEX_STAT_FE, 2285 }, 2286 { 2287 .chip_id = BCM5389_DEVICE_ID, 2288 .dev_name = "BCM5389", 2289 .vlans = 4096, 2290 .enabled_ports = 0x1f, 2291 .arl_bins = 4, 2292 .arl_buckets = 1024, 2293 .cpu_port = B53_CPU_PORT, 2294 .vta_regs = B53_VTA_REGS, 2295 .duplex_reg = B53_DUPLEX_STAT_GE, 2296 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2297 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2298 }, 2299 { 2300 .chip_id = BCM5395_DEVICE_ID, 2301 .dev_name = "BCM5395", 2302 .vlans = 4096, 2303 .enabled_ports = 0x1f, 2304 .arl_bins = 4, 2305 .arl_buckets = 1024, 2306 .cpu_port = B53_CPU_PORT, 2307 .vta_regs = B53_VTA_REGS, 2308 .duplex_reg = B53_DUPLEX_STAT_GE, 2309 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2310 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2311 }, 2312 { 2313 .chip_id = BCM5397_DEVICE_ID, 2314 .dev_name = "BCM5397", 2315 .vlans = 4096, 2316 .enabled_ports = 0x1f, 2317 .arl_bins = 4, 2318 .arl_buckets = 1024, 2319 .cpu_port = B53_CPU_PORT, 2320 .vta_regs = B53_VTA_REGS_9798, 2321 .duplex_reg = B53_DUPLEX_STAT_GE, 2322 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2323 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2324 }, 2325 { 2326 .chip_id = BCM5398_DEVICE_ID, 2327 .dev_name = "BCM5398", 2328 .vlans = 4096, 2329 .enabled_ports = 0x7f, 2330 .arl_bins = 4, 2331 .arl_buckets = 1024, 2332 .cpu_port = B53_CPU_PORT, 2333 .vta_regs = B53_VTA_REGS_9798, 2334 .duplex_reg = B53_DUPLEX_STAT_GE, 2335 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2336 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2337 }, 2338 { 2339 .chip_id = BCM53115_DEVICE_ID, 2340 .dev_name = "BCM53115", 2341 .vlans = 4096, 2342 .enabled_ports = 0x1f, 2343 .arl_bins = 4, 2344 .arl_buckets = 1024, 2345 .vta_regs = B53_VTA_REGS, 2346 .cpu_port = B53_CPU_PORT, 2347 .duplex_reg = B53_DUPLEX_STAT_GE, 2348 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2349 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2350 }, 2351 { 2352 .chip_id = BCM53125_DEVICE_ID, 2353 .dev_name = "BCM53125", 2354 .vlans = 4096, 2355 .enabled_ports = 0xff, 2356 .arl_bins = 4, 2357 .arl_buckets = 1024, 2358 .cpu_port = B53_CPU_PORT, 2359 .vta_regs = B53_VTA_REGS, 2360 .duplex_reg = B53_DUPLEX_STAT_GE, 2361 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2362 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2363 }, 2364 { 2365 .chip_id = BCM53128_DEVICE_ID, 2366 .dev_name = "BCM53128", 2367 .vlans = 4096, 2368 .enabled_ports = 0x1ff, 2369 .arl_bins = 4, 2370 .arl_buckets = 1024, 2371 .cpu_port = B53_CPU_PORT, 2372 .vta_regs = B53_VTA_REGS, 2373 .duplex_reg = B53_DUPLEX_STAT_GE, 2374 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2375 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2376 }, 2377 { 2378 .chip_id = BCM63XX_DEVICE_ID, 2379 .dev_name = "BCM63xx", 2380 .vlans = 4096, 2381 .enabled_ports = 0, /* pdata must provide them */ 2382 .arl_bins = 4, 2383 .arl_buckets = 1024, 2384 .cpu_port = B53_CPU_PORT, 2385 .vta_regs = B53_VTA_REGS_63XX, 2386 .duplex_reg = B53_DUPLEX_STAT_63XX, 2387 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2388 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2389 }, 2390 { 2391 .chip_id = BCM53010_DEVICE_ID, 2392 .dev_name = "BCM53010", 2393 .vlans = 4096, 2394 .enabled_ports = 0x1f, 2395 .arl_bins = 4, 2396 .arl_buckets = 1024, 2397 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2398 .vta_regs = B53_VTA_REGS, 2399 .duplex_reg = B53_DUPLEX_STAT_GE, 2400 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2401 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2402 }, 2403 { 2404 .chip_id = BCM53011_DEVICE_ID, 2405 .dev_name = "BCM53011", 2406 .vlans = 4096, 2407 .enabled_ports = 0x1bf, 2408 .arl_bins = 4, 2409 .arl_buckets = 1024, 2410 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2411 .vta_regs = B53_VTA_REGS, 2412 .duplex_reg = B53_DUPLEX_STAT_GE, 2413 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2414 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2415 }, 2416 { 2417 .chip_id = BCM53012_DEVICE_ID, 2418 .dev_name = "BCM53012", 2419 .vlans = 4096, 2420 .enabled_ports = 0x1bf, 2421 .arl_bins = 4, 2422 .arl_buckets = 1024, 2423 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2424 .vta_regs = B53_VTA_REGS, 2425 .duplex_reg = B53_DUPLEX_STAT_GE, 2426 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2427 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2428 }, 2429 { 2430 .chip_id = BCM53018_DEVICE_ID, 2431 .dev_name = "BCM53018", 2432 .vlans = 4096, 2433 .enabled_ports = 0x1f, 2434 .arl_bins = 4, 2435 .arl_buckets = 1024, 2436 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2437 .vta_regs = B53_VTA_REGS, 2438 .duplex_reg = B53_DUPLEX_STAT_GE, 2439 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2440 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2441 }, 2442 { 2443 .chip_id = BCM53019_DEVICE_ID, 2444 .dev_name = "BCM53019", 2445 .vlans = 4096, 2446 .enabled_ports = 0x1f, 2447 .arl_bins = 4, 2448 .arl_buckets = 1024, 2449 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2450 .vta_regs = B53_VTA_REGS, 2451 .duplex_reg = B53_DUPLEX_STAT_GE, 2452 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2453 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2454 }, 2455 { 2456 .chip_id = BCM58XX_DEVICE_ID, 2457 .dev_name = "BCM585xx/586xx/88312", 2458 .vlans = 4096, 2459 .enabled_ports = 0x1ff, 2460 .arl_bins = 4, 2461 .arl_buckets = 1024, 2462 .cpu_port = B53_CPU_PORT, 2463 .vta_regs = B53_VTA_REGS, 2464 .duplex_reg = B53_DUPLEX_STAT_GE, 2465 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2466 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2467 }, 2468 { 2469 .chip_id = BCM583XX_DEVICE_ID, 2470 .dev_name = "BCM583xx/11360", 2471 .vlans = 4096, 2472 .enabled_ports = 0x103, 2473 .arl_bins = 4, 2474 .arl_buckets = 1024, 2475 .cpu_port = B53_CPU_PORT, 2476 .vta_regs = B53_VTA_REGS, 2477 .duplex_reg = B53_DUPLEX_STAT_GE, 2478 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2479 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2480 }, 2481 /* Starfighter 2 */ 2482 { 2483 .chip_id = BCM4908_DEVICE_ID, 2484 .dev_name = "BCM4908", 2485 .vlans = 4096, 2486 .enabled_ports = 0x1bf, 2487 .arl_bins = 4, 2488 .arl_buckets = 256, 2489 .cpu_port = 8, /* TODO: ports 4, 5, 8 */ 2490 .vta_regs = B53_VTA_REGS, 2491 .duplex_reg = B53_DUPLEX_STAT_GE, 2492 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2493 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2494 }, 2495 { 2496 .chip_id = BCM7445_DEVICE_ID, 2497 .dev_name = "BCM7445", 2498 .vlans = 4096, 2499 .enabled_ports = 0x1ff, 2500 .arl_bins = 4, 2501 .arl_buckets = 1024, 2502 .cpu_port = B53_CPU_PORT, 2503 .vta_regs = B53_VTA_REGS, 2504 .duplex_reg = B53_DUPLEX_STAT_GE, 2505 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2506 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2507 }, 2508 { 2509 .chip_id = BCM7278_DEVICE_ID, 2510 .dev_name = "BCM7278", 2511 .vlans = 4096, 2512 .enabled_ports = 0x1ff, 2513 .arl_bins = 4, 2514 .arl_buckets = 256, 2515 .cpu_port = B53_CPU_PORT, 2516 .vta_regs = B53_VTA_REGS, 2517 .duplex_reg = B53_DUPLEX_STAT_GE, 2518 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2519 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2520 }, 2521 }; 2522 2523 static int b53_switch_init(struct b53_device *dev) 2524 { 2525 unsigned int i; 2526 int ret; 2527 2528 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2529 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2530 2531 if (chip->chip_id == dev->chip_id) { 2532 if (!dev->enabled_ports) 2533 dev->enabled_ports = chip->enabled_ports; 2534 dev->name = chip->dev_name; 2535 dev->duplex_reg = chip->duplex_reg; 2536 dev->vta_regs[0] = chip->vta_regs[0]; 2537 dev->vta_regs[1] = chip->vta_regs[1]; 2538 dev->vta_regs[2] = chip->vta_regs[2]; 2539 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2540 dev->cpu_port = chip->cpu_port; 2541 dev->num_vlans = chip->vlans; 2542 dev->num_arl_bins = chip->arl_bins; 2543 dev->num_arl_buckets = chip->arl_buckets; 2544 break; 2545 } 2546 } 2547 2548 /* check which BCM5325x version we have */ 2549 if (is5325(dev)) { 2550 u8 vc4; 2551 2552 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2553 2554 /* check reserved bits */ 2555 switch (vc4 & 3) { 2556 case 1: 2557 /* BCM5325E */ 2558 break; 2559 case 3: 2560 /* BCM5325F - do not use port 4 */ 2561 dev->enabled_ports &= ~BIT(4); 2562 break; 2563 default: 2564 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2565 #ifndef CONFIG_BCM47XX 2566 /* BCM5325M */ 2567 return -EINVAL; 2568 #else 2569 break; 2570 #endif 2571 } 2572 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2573 u64 strap_value; 2574 2575 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2576 /* use second IMP port if GMII is enabled */ 2577 if (strap_value & SV_GMII_CTRL_115) 2578 dev->cpu_port = 5; 2579 } 2580 2581 /* cpu port is always last */ 2582 dev->num_ports = dev->cpu_port + 1; 2583 dev->enabled_ports |= BIT(dev->cpu_port); 2584 2585 /* Include non standard CPU port built-in PHYs to be probed */ 2586 if (is539x(dev) || is531x5(dev)) { 2587 for (i = 0; i < dev->num_ports; i++) { 2588 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2589 !b53_possible_cpu_port(dev->ds, i)) 2590 dev->ds->phys_mii_mask |= BIT(i); 2591 } 2592 } 2593 2594 dev->ports = devm_kcalloc(dev->dev, 2595 dev->num_ports, sizeof(struct b53_port), 2596 GFP_KERNEL); 2597 if (!dev->ports) 2598 return -ENOMEM; 2599 2600 dev->vlans = devm_kcalloc(dev->dev, 2601 dev->num_vlans, sizeof(struct b53_vlan), 2602 GFP_KERNEL); 2603 if (!dev->vlans) 2604 return -ENOMEM; 2605 2606 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2607 if (dev->reset_gpio >= 0) { 2608 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2609 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2610 if (ret) 2611 return ret; 2612 } 2613 2614 return 0; 2615 } 2616 2617 struct b53_device *b53_switch_alloc(struct device *base, 2618 const struct b53_io_ops *ops, 2619 void *priv) 2620 { 2621 struct dsa_switch *ds; 2622 struct b53_device *dev; 2623 2624 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2625 if (!ds) 2626 return NULL; 2627 2628 ds->dev = base; 2629 ds->num_ports = DSA_MAX_PORTS; 2630 2631 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2632 if (!dev) 2633 return NULL; 2634 2635 ds->priv = dev; 2636 dev->dev = base; 2637 2638 dev->ds = ds; 2639 dev->priv = priv; 2640 dev->ops = ops; 2641 ds->ops = &b53_switch_ops; 2642 ds->untag_bridge_pvid = true; 2643 dev->vlan_enabled = true; 2644 mutex_init(&dev->reg_mutex); 2645 mutex_init(&dev->stats_mutex); 2646 2647 return dev; 2648 } 2649 EXPORT_SYMBOL(b53_switch_alloc); 2650 2651 int b53_switch_detect(struct b53_device *dev) 2652 { 2653 u32 id32; 2654 u16 tmp; 2655 u8 id8; 2656 int ret; 2657 2658 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2659 if (ret) 2660 return ret; 2661 2662 switch (id8) { 2663 case 0: 2664 /* BCM5325 and BCM5365 do not have this register so reads 2665 * return 0. But the read operation did succeed, so assume this 2666 * is one of them. 2667 * 2668 * Next check if we can write to the 5325's VTA register; for 2669 * 5365 it is read only. 2670 */ 2671 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2672 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2673 2674 if (tmp == 0xf) 2675 dev->chip_id = BCM5325_DEVICE_ID; 2676 else 2677 dev->chip_id = BCM5365_DEVICE_ID; 2678 break; 2679 case BCM5389_DEVICE_ID: 2680 case BCM5395_DEVICE_ID: 2681 case BCM5397_DEVICE_ID: 2682 case BCM5398_DEVICE_ID: 2683 dev->chip_id = id8; 2684 break; 2685 default: 2686 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2687 if (ret) 2688 return ret; 2689 2690 switch (id32) { 2691 case BCM53115_DEVICE_ID: 2692 case BCM53125_DEVICE_ID: 2693 case BCM53128_DEVICE_ID: 2694 case BCM53010_DEVICE_ID: 2695 case BCM53011_DEVICE_ID: 2696 case BCM53012_DEVICE_ID: 2697 case BCM53018_DEVICE_ID: 2698 case BCM53019_DEVICE_ID: 2699 dev->chip_id = id32; 2700 break; 2701 default: 2702 dev_err(dev->dev, 2703 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2704 id8, id32); 2705 return -ENODEV; 2706 } 2707 } 2708 2709 if (dev->chip_id == BCM5325_DEVICE_ID) 2710 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2711 &dev->core_rev); 2712 else 2713 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2714 &dev->core_rev); 2715 } 2716 EXPORT_SYMBOL(b53_switch_detect); 2717 2718 int b53_switch_register(struct b53_device *dev) 2719 { 2720 int ret; 2721 2722 if (dev->pdata) { 2723 dev->chip_id = dev->pdata->chip_id; 2724 dev->enabled_ports = dev->pdata->enabled_ports; 2725 } 2726 2727 if (!dev->chip_id && b53_switch_detect(dev)) 2728 return -EINVAL; 2729 2730 ret = b53_switch_init(dev); 2731 if (ret) 2732 return ret; 2733 2734 dev_info(dev->dev, "found switch: %s, rev %i\n", 2735 dev->name, dev->core_rev); 2736 2737 return dsa_register_switch(dev->ds); 2738 } 2739 EXPORT_SYMBOL(b53_switch_register); 2740 2741 MODULE_AUTHOR("Jonas Gorski <[email protected]>"); 2742 MODULE_DESCRIPTION("B53 switch library"); 2743 MODULE_LICENSE("Dual BSD/GPL"); 2744