1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <[email protected]> 5 * Copyright (C) 2016 Florian Fainelli <[email protected]> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <linux/if_vlan.h> 31 #include <net/dsa.h> 32 33 #include "b53_regs.h" 34 #include "b53_priv.h" 35 36 struct b53_mib_desc { 37 u8 size; 38 u8 offset; 39 const char *name; 40 }; 41 42 /* BCM5365 MIB counters */ 43 static const struct b53_mib_desc b53_mibs_65[] = { 44 { 8, 0x00, "TxOctets" }, 45 { 4, 0x08, "TxDropPkts" }, 46 { 4, 0x10, "TxBroadcastPkts" }, 47 { 4, 0x14, "TxMulticastPkts" }, 48 { 4, 0x18, "TxUnicastPkts" }, 49 { 4, 0x1c, "TxCollisions" }, 50 { 4, 0x20, "TxSingleCollision" }, 51 { 4, 0x24, "TxMultipleCollision" }, 52 { 4, 0x28, "TxDeferredTransmit" }, 53 { 4, 0x2c, "TxLateCollision" }, 54 { 4, 0x30, "TxExcessiveCollision" }, 55 { 4, 0x38, "TxPausePkts" }, 56 { 8, 0x44, "RxOctets" }, 57 { 4, 0x4c, "RxUndersizePkts" }, 58 { 4, 0x50, "RxPausePkts" }, 59 { 4, 0x54, "Pkts64Octets" }, 60 { 4, 0x58, "Pkts65to127Octets" }, 61 { 4, 0x5c, "Pkts128to255Octets" }, 62 { 4, 0x60, "Pkts256to511Octets" }, 63 { 4, 0x64, "Pkts512to1023Octets" }, 64 { 4, 0x68, "Pkts1024to1522Octets" }, 65 { 4, 0x6c, "RxOversizePkts" }, 66 { 4, 0x70, "RxJabbers" }, 67 { 4, 0x74, "RxAlignmentErrors" }, 68 { 4, 0x78, "RxFCSErrors" }, 69 { 8, 0x7c, "RxGoodOctets" }, 70 { 4, 0x84, "RxDropPkts" }, 71 { 4, 0x88, "RxUnicastPkts" }, 72 { 4, 0x8c, "RxMulticastPkts" }, 73 { 4, 0x90, "RxBroadcastPkts" }, 74 { 4, 0x94, "RxSAChanges" }, 75 { 4, 0x98, "RxFragments" }, 76 }; 77 78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 79 80 /* BCM63xx MIB counters */ 81 static const struct b53_mib_desc b53_mibs_63xx[] = { 82 { 8, 0x00, "TxOctets" }, 83 { 4, 0x08, "TxDropPkts" }, 84 { 4, 0x0c, "TxQoSPkts" }, 85 { 4, 0x10, "TxBroadcastPkts" }, 86 { 4, 0x14, "TxMulticastPkts" }, 87 { 4, 0x18, "TxUnicastPkts" }, 88 { 4, 0x1c, "TxCollisions" }, 89 { 4, 0x20, "TxSingleCollision" }, 90 { 4, 0x24, "TxMultipleCollision" }, 91 { 4, 0x28, "TxDeferredTransmit" }, 92 { 4, 0x2c, "TxLateCollision" }, 93 { 4, 0x30, "TxExcessiveCollision" }, 94 { 4, 0x38, "TxPausePkts" }, 95 { 8, 0x3c, "TxQoSOctets" }, 96 { 8, 0x44, "RxOctets" }, 97 { 4, 0x4c, "RxUndersizePkts" }, 98 { 4, 0x50, "RxPausePkts" }, 99 { 4, 0x54, "Pkts64Octets" }, 100 { 4, 0x58, "Pkts65to127Octets" }, 101 { 4, 0x5c, "Pkts128to255Octets" }, 102 { 4, 0x60, "Pkts256to511Octets" }, 103 { 4, 0x64, "Pkts512to1023Octets" }, 104 { 4, 0x68, "Pkts1024to1522Octets" }, 105 { 4, 0x6c, "RxOversizePkts" }, 106 { 4, 0x70, "RxJabbers" }, 107 { 4, 0x74, "RxAlignmentErrors" }, 108 { 4, 0x78, "RxFCSErrors" }, 109 { 8, 0x7c, "RxGoodOctets" }, 110 { 4, 0x84, "RxDropPkts" }, 111 { 4, 0x88, "RxUnicastPkts" }, 112 { 4, 0x8c, "RxMulticastPkts" }, 113 { 4, 0x90, "RxBroadcastPkts" }, 114 { 4, 0x94, "RxSAChanges" }, 115 { 4, 0x98, "RxFragments" }, 116 { 4, 0xa0, "RxSymbolErrors" }, 117 { 4, 0xa4, "RxQoSPkts" }, 118 { 8, 0xa8, "RxQoSOctets" }, 119 { 4, 0xb0, "Pkts1523to2047Octets" }, 120 { 4, 0xb4, "Pkts2048to4095Octets" }, 121 { 4, 0xb8, "Pkts4096to8191Octets" }, 122 { 4, 0xbc, "Pkts8192to9728Octets" }, 123 { 4, 0xc0, "RxDiscarded" }, 124 }; 125 126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 127 128 /* MIB counters */ 129 static const struct b53_mib_desc b53_mibs[] = { 130 { 8, 0x00, "TxOctets" }, 131 { 4, 0x08, "TxDropPkts" }, 132 { 4, 0x10, "TxBroadcastPkts" }, 133 { 4, 0x14, "TxMulticastPkts" }, 134 { 4, 0x18, "TxUnicastPkts" }, 135 { 4, 0x1c, "TxCollisions" }, 136 { 4, 0x20, "TxSingleCollision" }, 137 { 4, 0x24, "TxMultipleCollision" }, 138 { 4, 0x28, "TxDeferredTransmit" }, 139 { 4, 0x2c, "TxLateCollision" }, 140 { 4, 0x30, "TxExcessiveCollision" }, 141 { 4, 0x38, "TxPausePkts" }, 142 { 8, 0x50, "RxOctets" }, 143 { 4, 0x58, "RxUndersizePkts" }, 144 { 4, 0x5c, "RxPausePkts" }, 145 { 4, 0x60, "Pkts64Octets" }, 146 { 4, 0x64, "Pkts65to127Octets" }, 147 { 4, 0x68, "Pkts128to255Octets" }, 148 { 4, 0x6c, "Pkts256to511Octets" }, 149 { 4, 0x70, "Pkts512to1023Octets" }, 150 { 4, 0x74, "Pkts1024to1522Octets" }, 151 { 4, 0x78, "RxOversizePkts" }, 152 { 4, 0x7c, "RxJabbers" }, 153 { 4, 0x80, "RxAlignmentErrors" }, 154 { 4, 0x84, "RxFCSErrors" }, 155 { 8, 0x88, "RxGoodOctets" }, 156 { 4, 0x90, "RxDropPkts" }, 157 { 4, 0x94, "RxUnicastPkts" }, 158 { 4, 0x98, "RxMulticastPkts" }, 159 { 4, 0x9c, "RxBroadcastPkts" }, 160 { 4, 0xa0, "RxSAChanges" }, 161 { 4, 0xa4, "RxFragments" }, 162 { 4, 0xa8, "RxJumboPkts" }, 163 { 4, 0xac, "RxSymbolErrors" }, 164 { 4, 0xc0, "RxDiscarded" }, 165 }; 166 167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 168 169 static const struct b53_mib_desc b53_mibs_58xx[] = { 170 { 8, 0x00, "TxOctets" }, 171 { 4, 0x08, "TxDropPkts" }, 172 { 4, 0x0c, "TxQPKTQ0" }, 173 { 4, 0x10, "TxBroadcastPkts" }, 174 { 4, 0x14, "TxMulticastPkts" }, 175 { 4, 0x18, "TxUnicastPKts" }, 176 { 4, 0x1c, "TxCollisions" }, 177 { 4, 0x20, "TxSingleCollision" }, 178 { 4, 0x24, "TxMultipleCollision" }, 179 { 4, 0x28, "TxDeferredCollision" }, 180 { 4, 0x2c, "TxLateCollision" }, 181 { 4, 0x30, "TxExcessiveCollision" }, 182 { 4, 0x34, "TxFrameInDisc" }, 183 { 4, 0x38, "TxPausePkts" }, 184 { 4, 0x3c, "TxQPKTQ1" }, 185 { 4, 0x40, "TxQPKTQ2" }, 186 { 4, 0x44, "TxQPKTQ3" }, 187 { 4, 0x48, "TxQPKTQ4" }, 188 { 4, 0x4c, "TxQPKTQ5" }, 189 { 8, 0x50, "RxOctets" }, 190 { 4, 0x58, "RxUndersizePkts" }, 191 { 4, 0x5c, "RxPausePkts" }, 192 { 4, 0x60, "RxPkts64Octets" }, 193 { 4, 0x64, "RxPkts65to127Octets" }, 194 { 4, 0x68, "RxPkts128to255Octets" }, 195 { 4, 0x6c, "RxPkts256to511Octets" }, 196 { 4, 0x70, "RxPkts512to1023Octets" }, 197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 198 { 4, 0x78, "RxOversizePkts" }, 199 { 4, 0x7c, "RxJabbers" }, 200 { 4, 0x80, "RxAlignmentErrors" }, 201 { 4, 0x84, "RxFCSErrors" }, 202 { 8, 0x88, "RxGoodOctets" }, 203 { 4, 0x90, "RxDropPkts" }, 204 { 4, 0x94, "RxUnicastPkts" }, 205 { 4, 0x98, "RxMulticastPkts" }, 206 { 4, 0x9c, "RxBroadcastPkts" }, 207 { 4, 0xa0, "RxSAChanges" }, 208 { 4, 0xa4, "RxFragments" }, 209 { 4, 0xa8, "RxJumboPkt" }, 210 { 4, 0xac, "RxSymblErr" }, 211 { 4, 0xb0, "InRangeErrCount" }, 212 { 4, 0xb4, "OutRangeErrCount" }, 213 { 4, 0xb8, "EEELpiEvent" }, 214 { 4, 0xbc, "EEELpiDuration" }, 215 { 4, 0xc0, "RxDiscard" }, 216 { 4, 0xc8, "TxQPKTQ6" }, 217 { 4, 0xcc, "TxQPKTQ7" }, 218 { 4, 0xd0, "TxPkts64Octets" }, 219 { 4, 0xd4, "TxPkts65to127Octets" }, 220 { 4, 0xd8, "TxPkts128to255Octets" }, 221 { 4, 0xdc, "TxPkts256to511Ocets" }, 222 { 4, 0xe0, "TxPkts512to1023Ocets" }, 223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 224 }; 225 226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 227 228 #define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 229 #define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) 230 231 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 232 { 233 unsigned int i; 234 235 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 236 237 for (i = 0; i < 10; i++) { 238 u8 vta; 239 240 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 241 if (!(vta & VTA_START_CMD)) 242 return 0; 243 244 usleep_range(100, 200); 245 } 246 247 return -EIO; 248 } 249 250 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 251 struct b53_vlan *vlan) 252 { 253 if (is5325(dev)) { 254 u32 entry = 0; 255 256 if (vlan->members) { 257 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 258 VA_UNTAG_S_25) | vlan->members; 259 if (dev->core_rev >= 3) 260 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 261 else 262 entry |= VA_VALID_25; 263 } 264 265 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 266 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 267 VTA_RW_STATE_WR | VTA_RW_OP_EN); 268 } else if (is5365(dev)) { 269 u16 entry = 0; 270 271 if (vlan->members) 272 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 273 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 274 275 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 276 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 277 VTA_RW_STATE_WR | VTA_RW_OP_EN); 278 } else { 279 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 280 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 281 (vlan->untag << VTE_UNTAG_S) | vlan->members); 282 283 b53_do_vlan_op(dev, VTA_CMD_WRITE); 284 } 285 286 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 287 vid, vlan->members, vlan->untag); 288 } 289 290 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 291 struct b53_vlan *vlan) 292 { 293 if (is5325(dev)) { 294 u32 entry = 0; 295 296 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 297 VTA_RW_STATE_RD | VTA_RW_OP_EN); 298 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 299 300 if (dev->core_rev >= 3) 301 vlan->valid = !!(entry & VA_VALID_25_R4); 302 else 303 vlan->valid = !!(entry & VA_VALID_25); 304 vlan->members = entry & VA_MEMBER_MASK; 305 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 306 307 } else if (is5365(dev)) { 308 u16 entry = 0; 309 310 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 311 VTA_RW_STATE_WR | VTA_RW_OP_EN); 312 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 313 314 vlan->valid = !!(entry & VA_VALID_65); 315 vlan->members = entry & VA_MEMBER_MASK; 316 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 317 } else { 318 u32 entry = 0; 319 320 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 321 b53_do_vlan_op(dev, VTA_CMD_READ); 322 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 323 vlan->members = entry & VTE_MEMBERS; 324 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 325 vlan->valid = true; 326 } 327 } 328 329 static void b53_set_forwarding(struct b53_device *dev, int enable) 330 { 331 u8 mgmt; 332 333 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 334 335 if (enable) 336 mgmt |= SM_SW_FWD_EN; 337 else 338 mgmt &= ~SM_SW_FWD_EN; 339 340 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 341 342 /* Include IMP port in dumb forwarding mode 343 */ 344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 345 mgmt |= B53_MII_DUMB_FWDG_EN; 346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 347 348 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 349 * frames should be flooded or not. 350 */ 351 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 352 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 353 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 354 } 355 356 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 357 bool enable_filtering) 358 { 359 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 360 361 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 364 365 if (is5325(dev) || is5365(dev)) { 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 368 } else if (is63xx(dev)) { 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 371 } else { 372 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 373 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 374 } 375 376 vc1 &= ~VC1_RX_MCST_FWD_EN; 377 378 if (enable) { 379 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 380 vc1 |= VC1_RX_MCST_UNTAG_EN; 381 vc4 &= ~VC4_ING_VID_CHECK_MASK; 382 if (enable_filtering) { 383 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 384 vc5 |= VC5_DROP_VTABLE_MISS; 385 } else { 386 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 387 vc5 &= ~VC5_DROP_VTABLE_MISS; 388 } 389 390 if (is5325(dev)) 391 vc0 &= ~VC0_RESERVED_1; 392 393 if (is5325(dev) || is5365(dev)) 394 vc1 |= VC1_RX_MCST_TAG_EN; 395 396 } else { 397 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 398 vc1 &= ~VC1_RX_MCST_UNTAG_EN; 399 vc4 &= ~VC4_ING_VID_CHECK_MASK; 400 vc5 &= ~VC5_DROP_VTABLE_MISS; 401 402 if (is5325(dev) || is5365(dev)) 403 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 404 else 405 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 406 407 if (is5325(dev) || is5365(dev)) 408 vc1 &= ~VC1_RX_MCST_TAG_EN; 409 } 410 411 if (!is5325(dev) && !is5365(dev)) 412 vc5 &= ~VC5_VID_FFF_EN; 413 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 416 417 if (is5325(dev) || is5365(dev)) { 418 /* enable the high 8 bit vid check on 5325 */ 419 if (is5325(dev) && enable) 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 421 VC3_HIGH_8BIT_EN); 422 else 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 424 425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 426 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 427 } else if (is63xx(dev)) { 428 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 429 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 430 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 431 } else { 432 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 433 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 434 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 435 } 436 437 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 438 439 dev->vlan_enabled = enable; 440 441 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 442 port, enable, enable_filtering); 443 } 444 445 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 446 { 447 u32 port_mask = 0; 448 u16 max_size = JMS_MIN_SIZE; 449 450 if (is5325(dev) || is5365(dev)) 451 return -EINVAL; 452 453 if (enable) { 454 port_mask = dev->enabled_ports; 455 max_size = JMS_MAX_SIZE; 456 if (allow_10_100) 457 port_mask |= JPM_10_100_JUMBO_EN; 458 } 459 460 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 461 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 462 } 463 464 static int b53_flush_arl(struct b53_device *dev, u8 mask) 465 { 466 unsigned int i; 467 468 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 469 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 470 471 for (i = 0; i < 10; i++) { 472 u8 fast_age_ctrl; 473 474 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 475 &fast_age_ctrl); 476 477 if (!(fast_age_ctrl & FAST_AGE_DONE)) 478 goto out; 479 480 msleep(1); 481 } 482 483 return -ETIMEDOUT; 484 out: 485 /* Only age dynamic entries (default behavior) */ 486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 487 return 0; 488 } 489 490 static int b53_fast_age_port(struct b53_device *dev, int port) 491 { 492 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 493 494 return b53_flush_arl(dev, FAST_AGE_PORT); 495 } 496 497 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 498 { 499 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 500 501 return b53_flush_arl(dev, FAST_AGE_VLAN); 502 } 503 504 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 505 { 506 struct b53_device *dev = ds->priv; 507 unsigned int i; 508 u16 pvlan; 509 510 /* Enable the IMP port to be in the same VLAN as the other ports 511 * on a per-port basis such that we only have Port i and IMP in 512 * the same VLAN. 513 */ 514 b53_for_each_port(dev, i) { 515 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 516 pvlan |= BIT(cpu_port); 517 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 518 } 519 } 520 EXPORT_SYMBOL(b53_imp_vlan_setup); 521 522 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 523 bool unicast) 524 { 525 u16 uc; 526 527 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 528 if (unicast) 529 uc |= BIT(port); 530 else 531 uc &= ~BIT(port); 532 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 533 } 534 535 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 536 bool multicast) 537 { 538 u16 mc; 539 540 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 541 if (multicast) 542 mc |= BIT(port); 543 else 544 mc &= ~BIT(port); 545 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 546 547 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 548 if (multicast) 549 mc |= BIT(port); 550 else 551 mc &= ~BIT(port); 552 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 553 } 554 555 static void b53_port_set_learning(struct b53_device *dev, int port, 556 bool learning) 557 { 558 u16 reg; 559 560 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 561 if (learning) 562 reg &= ~BIT(port); 563 else 564 reg |= BIT(port); 565 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 566 } 567 568 static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 569 { 570 struct b53_device *dev = ds->priv; 571 u16 reg; 572 573 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 574 if (enable) 575 reg |= BIT(port); 576 else 577 reg &= ~BIT(port); 578 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 579 } 580 581 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 582 { 583 struct b53_device *dev = ds->priv; 584 unsigned int cpu_port; 585 int ret = 0; 586 u16 pvlan; 587 588 if (!dsa_is_user_port(ds, port)) 589 return 0; 590 591 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 592 593 b53_port_set_ucast_flood(dev, port, true); 594 b53_port_set_mcast_flood(dev, port, true); 595 b53_port_set_learning(dev, port, false); 596 597 if (dev->ops->irq_enable) 598 ret = dev->ops->irq_enable(dev, port); 599 if (ret) 600 return ret; 601 602 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 603 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 604 605 /* Set this port, and only this one to be in the default VLAN, 606 * if member of a bridge, restore its membership prior to 607 * bringing down this port. 608 */ 609 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 610 pvlan &= ~0x1ff; 611 pvlan |= BIT(port); 612 pvlan |= dev->ports[port].vlan_ctl_mask; 613 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 614 615 b53_imp_vlan_setup(ds, cpu_port); 616 617 /* If EEE was enabled, restore it */ 618 if (dev->ports[port].eee.eee_enabled) 619 b53_eee_enable_set(ds, port, true); 620 621 return 0; 622 } 623 EXPORT_SYMBOL(b53_enable_port); 624 625 void b53_disable_port(struct dsa_switch *ds, int port) 626 { 627 struct b53_device *dev = ds->priv; 628 u8 reg; 629 630 /* Disable Tx/Rx for the port */ 631 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 632 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 633 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 634 635 if (dev->ops->irq_disable) 636 dev->ops->irq_disable(dev, port); 637 } 638 EXPORT_SYMBOL(b53_disable_port); 639 640 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 641 { 642 struct b53_device *dev = ds->priv; 643 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 644 u8 hdr_ctl, val; 645 u16 reg; 646 647 /* Resolve which bit controls the Broadcom tag */ 648 switch (port) { 649 case 8: 650 val = BRCM_HDR_P8_EN; 651 break; 652 case 7: 653 val = BRCM_HDR_P7_EN; 654 break; 655 case 5: 656 val = BRCM_HDR_P5_EN; 657 break; 658 default: 659 val = 0; 660 break; 661 } 662 663 /* Enable management mode if tagging is requested */ 664 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 665 if (tag_en) 666 hdr_ctl |= SM_SW_FWD_MODE; 667 else 668 hdr_ctl &= ~SM_SW_FWD_MODE; 669 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 670 671 /* Configure the appropriate IMP port */ 672 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 673 if (port == 8) 674 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 675 else if (port == 5) 676 hdr_ctl |= GC_FRM_MGMT_PORT_M; 677 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 678 679 /* Enable Broadcom tags for IMP port */ 680 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 681 if (tag_en) 682 hdr_ctl |= val; 683 else 684 hdr_ctl &= ~val; 685 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 686 687 /* Registers below are only accessible on newer devices */ 688 if (!is58xx(dev)) 689 return; 690 691 /* Enable reception Broadcom tag for CPU TX (switch RX) to 692 * allow us to tag outgoing frames 693 */ 694 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 695 if (tag_en) 696 reg &= ~BIT(port); 697 else 698 reg |= BIT(port); 699 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 700 701 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 702 * allow delivering frames to the per-port net_devices 703 */ 704 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 705 if (tag_en) 706 reg &= ~BIT(port); 707 else 708 reg |= BIT(port); 709 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 710 } 711 EXPORT_SYMBOL(b53_brcm_hdr_setup); 712 713 static void b53_enable_cpu_port(struct b53_device *dev, int port) 714 { 715 u8 port_ctrl; 716 717 /* BCM5325 CPU port is at 8 */ 718 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 719 port = B53_CPU_PORT; 720 721 port_ctrl = PORT_CTRL_RX_BCST_EN | 722 PORT_CTRL_RX_MCST_EN | 723 PORT_CTRL_RX_UCST_EN; 724 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 725 726 b53_brcm_hdr_setup(dev->ds, port); 727 728 b53_port_set_ucast_flood(dev, port, true); 729 b53_port_set_mcast_flood(dev, port, true); 730 b53_port_set_learning(dev, port, false); 731 } 732 733 static void b53_enable_mib(struct b53_device *dev) 734 { 735 u8 gc; 736 737 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 738 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 739 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 740 } 741 742 static void b53_enable_stp(struct b53_device *dev) 743 { 744 u8 gc; 745 746 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 747 gc |= GC_RX_BPDU_EN; 748 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 749 } 750 751 static u16 b53_default_pvid(struct b53_device *dev) 752 { 753 if (is5325(dev) || is5365(dev)) 754 return 1; 755 else 756 return 0; 757 } 758 759 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 760 { 761 struct b53_device *dev = ds->priv; 762 763 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 764 } 765 766 int b53_configure_vlan(struct dsa_switch *ds) 767 { 768 struct b53_device *dev = ds->priv; 769 struct b53_vlan vl = { 0 }; 770 struct b53_vlan *v; 771 int i, def_vid; 772 u16 vid; 773 774 def_vid = b53_default_pvid(dev); 775 776 /* clear all vlan entries */ 777 if (is5325(dev) || is5365(dev)) { 778 for (i = def_vid; i < dev->num_vlans; i++) 779 b53_set_vlan_entry(dev, i, &vl); 780 } else { 781 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 782 } 783 784 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 785 786 /* Create an untagged VLAN entry for the default PVID in case 787 * CONFIG_VLAN_8021Q is disabled and there are no calls to 788 * dsa_user_vlan_rx_add_vid() to create the default VLAN 789 * entry. Do this only when the tagging protocol is not 790 * DSA_TAG_PROTO_NONE 791 */ 792 b53_for_each_port(dev, i) { 793 v = &dev->vlans[def_vid]; 794 v->members |= BIT(i); 795 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 796 v->untag = v->members; 797 b53_write16(dev, B53_VLAN_PAGE, 798 B53_VLAN_PORT_DEF_TAG(i), def_vid); 799 } 800 801 /* Upon initial call we have not set-up any VLANs, but upon 802 * system resume, we need to restore all VLAN entries. 803 */ 804 for (vid = def_vid; vid < dev->num_vlans; vid++) { 805 v = &dev->vlans[vid]; 806 807 if (!v->members) 808 continue; 809 810 b53_set_vlan_entry(dev, vid, v); 811 b53_fast_age_vlan(dev, vid); 812 } 813 814 return 0; 815 } 816 EXPORT_SYMBOL(b53_configure_vlan); 817 818 static void b53_switch_reset_gpio(struct b53_device *dev) 819 { 820 int gpio = dev->reset_gpio; 821 822 if (gpio < 0) 823 return; 824 825 /* Reset sequence: RESET low(50ms)->high(20ms) 826 */ 827 gpio_set_value(gpio, 0); 828 mdelay(50); 829 830 gpio_set_value(gpio, 1); 831 mdelay(20); 832 833 dev->current_page = 0xff; 834 } 835 836 static int b53_switch_reset(struct b53_device *dev) 837 { 838 unsigned int timeout = 1000; 839 u8 mgmt, reg; 840 841 b53_switch_reset_gpio(dev); 842 843 if (is539x(dev)) { 844 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 845 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 846 } 847 848 /* This is specific to 58xx devices here, do not use is58xx() which 849 * covers the larger Starfigther 2 family, including 7445/7278 which 850 * still use this driver as a library and need to perform the reset 851 * earlier. 852 */ 853 if (dev->chip_id == BCM58XX_DEVICE_ID || 854 dev->chip_id == BCM583XX_DEVICE_ID) { 855 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 856 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 857 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 858 859 do { 860 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 861 if (!(reg & SW_RST)) 862 break; 863 864 usleep_range(1000, 2000); 865 } while (timeout-- > 0); 866 867 if (timeout == 0) { 868 dev_err(dev->dev, 869 "Timeout waiting for SW_RST to clear!\n"); 870 return -ETIMEDOUT; 871 } 872 } 873 874 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 875 876 if (!(mgmt & SM_SW_FWD_EN)) { 877 mgmt &= ~SM_SW_FWD_MODE; 878 mgmt |= SM_SW_FWD_EN; 879 880 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 881 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 882 883 if (!(mgmt & SM_SW_FWD_EN)) { 884 dev_err(dev->dev, "Failed to enable switch!\n"); 885 return -EINVAL; 886 } 887 } 888 889 b53_enable_mib(dev); 890 b53_enable_stp(dev); 891 892 return b53_flush_arl(dev, FAST_AGE_STATIC); 893 } 894 895 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 896 { 897 struct b53_device *priv = ds->priv; 898 u16 value = 0; 899 int ret; 900 901 if (priv->ops->phy_read16) 902 ret = priv->ops->phy_read16(priv, addr, reg, &value); 903 else 904 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 905 reg * 2, &value); 906 907 return ret ? ret : value; 908 } 909 910 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 911 { 912 struct b53_device *priv = ds->priv; 913 914 if (priv->ops->phy_write16) 915 return priv->ops->phy_write16(priv, addr, reg, val); 916 917 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 918 } 919 920 static int b53_reset_switch(struct b53_device *priv) 921 { 922 /* reset vlans */ 923 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 924 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 925 926 priv->serdes_lane = B53_INVALID_LANE; 927 928 return b53_switch_reset(priv); 929 } 930 931 static int b53_apply_config(struct b53_device *priv) 932 { 933 /* disable switching */ 934 b53_set_forwarding(priv, 0); 935 936 b53_configure_vlan(priv->ds); 937 938 /* enable switching */ 939 b53_set_forwarding(priv, 1); 940 941 return 0; 942 } 943 944 static void b53_reset_mib(struct b53_device *priv) 945 { 946 u8 gc; 947 948 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 949 950 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 951 msleep(1); 952 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 953 msleep(1); 954 } 955 956 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 957 { 958 if (is5365(dev)) 959 return b53_mibs_65; 960 else if (is63xx(dev)) 961 return b53_mibs_63xx; 962 else if (is58xx(dev)) 963 return b53_mibs_58xx; 964 else 965 return b53_mibs; 966 } 967 968 static unsigned int b53_get_mib_size(struct b53_device *dev) 969 { 970 if (is5365(dev)) 971 return B53_MIBS_65_SIZE; 972 else if (is63xx(dev)) 973 return B53_MIBS_63XX_SIZE; 974 else if (is58xx(dev)) 975 return B53_MIBS_58XX_SIZE; 976 else 977 return B53_MIBS_SIZE; 978 } 979 980 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 981 { 982 /* These ports typically do not have built-in PHYs */ 983 switch (port) { 984 case B53_CPU_PORT_25: 985 case 7: 986 case B53_CPU_PORT: 987 return NULL; 988 } 989 990 return mdiobus_get_phy(ds->user_mii_bus, port); 991 } 992 993 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 994 uint8_t *data) 995 { 996 struct b53_device *dev = ds->priv; 997 const struct b53_mib_desc *mibs = b53_get_mib(dev); 998 unsigned int mib_size = b53_get_mib_size(dev); 999 struct phy_device *phydev; 1000 unsigned int i; 1001 1002 if (stringset == ETH_SS_STATS) { 1003 for (i = 0; i < mib_size; i++) 1004 ethtool_puts(&data, mibs[i].name); 1005 } else if (stringset == ETH_SS_PHY_STATS) { 1006 phydev = b53_get_phy_device(ds, port); 1007 if (!phydev) 1008 return; 1009 1010 phy_ethtool_get_strings(phydev, data); 1011 } 1012 } 1013 EXPORT_SYMBOL(b53_get_strings); 1014 1015 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 1016 { 1017 struct b53_device *dev = ds->priv; 1018 const struct b53_mib_desc *mibs = b53_get_mib(dev); 1019 unsigned int mib_size = b53_get_mib_size(dev); 1020 const struct b53_mib_desc *s; 1021 unsigned int i; 1022 u64 val = 0; 1023 1024 if (is5365(dev) && port == 5) 1025 port = 8; 1026 1027 mutex_lock(&dev->stats_mutex); 1028 1029 for (i = 0; i < mib_size; i++) { 1030 s = &mibs[i]; 1031 1032 if (s->size == 8) { 1033 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1034 } else { 1035 u32 val32; 1036 1037 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1038 &val32); 1039 val = val32; 1040 } 1041 data[i] = (u64)val; 1042 } 1043 1044 mutex_unlock(&dev->stats_mutex); 1045 } 1046 EXPORT_SYMBOL(b53_get_ethtool_stats); 1047 1048 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1049 { 1050 struct phy_device *phydev; 1051 1052 phydev = b53_get_phy_device(ds, port); 1053 if (!phydev) 1054 return; 1055 1056 phy_ethtool_get_stats(phydev, NULL, data); 1057 } 1058 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1059 1060 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1061 { 1062 struct b53_device *dev = ds->priv; 1063 struct phy_device *phydev; 1064 1065 if (sset == ETH_SS_STATS) { 1066 return b53_get_mib_size(dev); 1067 } else if (sset == ETH_SS_PHY_STATS) { 1068 phydev = b53_get_phy_device(ds, port); 1069 if (!phydev) 1070 return 0; 1071 1072 return phy_ethtool_get_sset_count(phydev); 1073 } 1074 1075 return 0; 1076 } 1077 EXPORT_SYMBOL(b53_get_sset_count); 1078 1079 enum b53_devlink_resource_id { 1080 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1081 }; 1082 1083 static u64 b53_devlink_vlan_table_get(void *priv) 1084 { 1085 struct b53_device *dev = priv; 1086 struct b53_vlan *vl; 1087 unsigned int i; 1088 u64 count = 0; 1089 1090 for (i = 0; i < dev->num_vlans; i++) { 1091 vl = &dev->vlans[i]; 1092 if (vl->members) 1093 count++; 1094 } 1095 1096 return count; 1097 } 1098 1099 int b53_setup_devlink_resources(struct dsa_switch *ds) 1100 { 1101 struct devlink_resource_size_params size_params; 1102 struct b53_device *dev = ds->priv; 1103 int err; 1104 1105 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1106 dev->num_vlans, 1107 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1108 1109 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1110 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1111 DEVLINK_RESOURCE_ID_PARENT_TOP, 1112 &size_params); 1113 if (err) 1114 goto out; 1115 1116 dsa_devlink_resource_occ_get_register(ds, 1117 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1118 b53_devlink_vlan_table_get, dev); 1119 1120 return 0; 1121 out: 1122 dsa_devlink_resources_unregister(ds); 1123 return err; 1124 } 1125 EXPORT_SYMBOL(b53_setup_devlink_resources); 1126 1127 static int b53_setup(struct dsa_switch *ds) 1128 { 1129 struct b53_device *dev = ds->priv; 1130 unsigned int port; 1131 int ret; 1132 1133 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1134 * which forces the CPU port to be tagged in all VLANs. 1135 */ 1136 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1137 1138 /* The switch does not tell us the original VLAN for untagged 1139 * packets, so keep the CPU port always tagged. 1140 */ 1141 ds->untag_vlan_aware_bridge_pvid = true; 1142 1143 ret = b53_reset_switch(dev); 1144 if (ret) { 1145 dev_err(ds->dev, "failed to reset switch\n"); 1146 return ret; 1147 } 1148 1149 b53_reset_mib(dev); 1150 1151 ret = b53_apply_config(dev); 1152 if (ret) { 1153 dev_err(ds->dev, "failed to apply configuration\n"); 1154 return ret; 1155 } 1156 1157 /* Configure IMP/CPU port, disable all other ports. Enabled 1158 * ports will be configured with .port_enable 1159 */ 1160 for (port = 0; port < dev->num_ports; port++) { 1161 if (dsa_is_cpu_port(ds, port)) 1162 b53_enable_cpu_port(dev, port); 1163 else 1164 b53_disable_port(ds, port); 1165 } 1166 1167 return b53_setup_devlink_resources(ds); 1168 } 1169 1170 static void b53_teardown(struct dsa_switch *ds) 1171 { 1172 dsa_devlink_resources_unregister(ds); 1173 } 1174 1175 static void b53_force_link(struct b53_device *dev, int port, int link) 1176 { 1177 u8 reg, val, off; 1178 1179 /* Override the port settings */ 1180 if (port == dev->imp_port) { 1181 off = B53_PORT_OVERRIDE_CTRL; 1182 val = PORT_OVERRIDE_EN; 1183 } else { 1184 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1185 val = GMII_PO_EN; 1186 } 1187 1188 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1189 reg |= val; 1190 if (link) 1191 reg |= PORT_OVERRIDE_LINK; 1192 else 1193 reg &= ~PORT_OVERRIDE_LINK; 1194 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1195 } 1196 1197 static void b53_force_port_config(struct b53_device *dev, int port, 1198 int speed, int duplex, 1199 bool tx_pause, bool rx_pause) 1200 { 1201 u8 reg, val, off; 1202 1203 /* Override the port settings */ 1204 if (port == dev->imp_port) { 1205 off = B53_PORT_OVERRIDE_CTRL; 1206 val = PORT_OVERRIDE_EN; 1207 } else { 1208 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1209 val = GMII_PO_EN; 1210 } 1211 1212 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1213 reg |= val; 1214 if (duplex == DUPLEX_FULL) 1215 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1216 else 1217 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1218 1219 switch (speed) { 1220 case 2000: 1221 reg |= PORT_OVERRIDE_SPEED_2000M; 1222 fallthrough; 1223 case SPEED_1000: 1224 reg |= PORT_OVERRIDE_SPEED_1000M; 1225 break; 1226 case SPEED_100: 1227 reg |= PORT_OVERRIDE_SPEED_100M; 1228 break; 1229 case SPEED_10: 1230 reg |= PORT_OVERRIDE_SPEED_10M; 1231 break; 1232 default: 1233 dev_err(dev->dev, "unknown speed: %d\n", speed); 1234 return; 1235 } 1236 1237 if (rx_pause) 1238 reg |= PORT_OVERRIDE_RX_FLOW; 1239 if (tx_pause) 1240 reg |= PORT_OVERRIDE_TX_FLOW; 1241 1242 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1243 } 1244 1245 static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, 1246 phy_interface_t interface) 1247 { 1248 struct b53_device *dev = ds->priv; 1249 u8 rgmii_ctrl = 0, off; 1250 1251 if (port == dev->imp_port) 1252 off = B53_RGMII_CTRL_IMP; 1253 else 1254 off = B53_RGMII_CTRL_P(port); 1255 1256 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1257 1258 switch (interface) { 1259 case PHY_INTERFACE_MODE_RGMII_ID: 1260 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1261 break; 1262 case PHY_INTERFACE_MODE_RGMII_RXID: 1263 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC); 1264 rgmii_ctrl |= RGMII_CTRL_DLL_RXC; 1265 break; 1266 case PHY_INTERFACE_MODE_RGMII_TXID: 1267 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC); 1268 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1269 break; 1270 case PHY_INTERFACE_MODE_RGMII: 1271 default: 1272 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); 1273 break; 1274 } 1275 1276 if (port != dev->imp_port) { 1277 if (is63268(dev)) 1278 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE; 1279 1280 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; 1281 } 1282 1283 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1284 1285 dev_dbg(ds->dev, "Configured port %d for %s\n", port, 1286 phy_modes(interface)); 1287 } 1288 1289 static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port, 1290 phy_interface_t interface) 1291 { 1292 struct b53_device *dev = ds->priv; 1293 u8 rgmii_ctrl = 0, off; 1294 1295 if (port == dev->imp_port) 1296 off = B53_RGMII_CTRL_IMP; 1297 else 1298 off = B53_RGMII_CTRL_P(port); 1299 1300 /* Configure the port RGMII clock delay by DLL disabled and 1301 * tx_clk aligned timing (restoring to reset defaults) 1302 */ 1303 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1304 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1305 RGMII_CTRL_TIMING_SEL); 1306 1307 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1308 * sure that we enable the port TX clock internal delay to 1309 * account for this internal delay that is inserted, otherwise 1310 * the switch won't be able to receive correctly. 1311 * 1312 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1313 * any delay neither on transmission nor reception, so the 1314 * BCM53125 must also be configured accordingly to account for 1315 * the lack of delay and introduce 1316 * 1317 * The BCM53125 switch has its RX clock and TX clock control 1318 * swapped, hence the reason why we modify the TX clock path in 1319 * the "RGMII" case 1320 */ 1321 if (interface == PHY_INTERFACE_MODE_RGMII_TXID) 1322 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1323 if (interface == PHY_INTERFACE_MODE_RGMII) 1324 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1325 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1326 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1327 1328 dev_info(ds->dev, "Configured port %d for %s\n", port, 1329 phy_modes(interface)); 1330 } 1331 1332 static void b53_adjust_5325_mii(struct dsa_switch *ds, int port) 1333 { 1334 struct b53_device *dev = ds->priv; 1335 u8 reg = 0; 1336 1337 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1338 ®); 1339 1340 /* reverse mii needs to be enabled */ 1341 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1342 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1343 reg | PORT_OVERRIDE_RV_MII_25); 1344 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1345 ®); 1346 1347 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1348 dev_err(ds->dev, 1349 "Failed to enable reverse MII mode\n"); 1350 return; 1351 } 1352 } 1353 } 1354 1355 void b53_port_event(struct dsa_switch *ds, int port) 1356 { 1357 struct b53_device *dev = ds->priv; 1358 bool link; 1359 u16 sts; 1360 1361 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1362 link = !!(sts & BIT(port)); 1363 dsa_port_phylink_mac_change(ds, port, link); 1364 } 1365 EXPORT_SYMBOL(b53_port_event); 1366 1367 static void b53_phylink_get_caps(struct dsa_switch *ds, int port, 1368 struct phylink_config *config) 1369 { 1370 struct b53_device *dev = ds->priv; 1371 1372 /* Internal ports need GMII for PHYLIB */ 1373 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); 1374 1375 /* These switches appear to support MII and RevMII too, but beyond 1376 * this, the code gives very few clues. FIXME: We probably need more 1377 * interface modes here. 1378 * 1379 * According to b53_srab_mux_init(), ports 3..5 can support: 1380 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting. 1381 * However, the interface mode read from the MUX configuration is 1382 * not passed back to DSA, so phylink uses NA. 1383 * DT can specify RGMII for ports 0, 1. 1384 * For MDIO, port 8 can be RGMII_TXID. 1385 */ 1386 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1387 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces); 1388 1389 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1390 MAC_10 | MAC_100; 1391 1392 /* 5325/5365 are not capable of gigabit speeds, everything else is. 1393 * Note: the original code also exclulded Gigagbit for MII, RevMII 1394 * and 802.3z modes. MII and RevMII are not able to work above 100M, 1395 * so will be excluded by the generic validator implementation. 1396 * However, the exclusion of Gigabit for 802.3z just seems wrong. 1397 */ 1398 if (!(is5325(dev) || is5365(dev))) 1399 config->mac_capabilities |= MAC_1000; 1400 1401 /* Get the implementation specific capabilities */ 1402 if (dev->ops->phylink_get_caps) 1403 dev->ops->phylink_get_caps(dev, port, config); 1404 } 1405 1406 static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config, 1407 phy_interface_t interface) 1408 { 1409 struct dsa_port *dp = dsa_phylink_to_port(config); 1410 struct b53_device *dev = dp->ds->priv; 1411 1412 if (!dev->ops->phylink_mac_select_pcs) 1413 return NULL; 1414 1415 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface); 1416 } 1417 1418 static void b53_phylink_mac_config(struct phylink_config *config, 1419 unsigned int mode, 1420 const struct phylink_link_state *state) 1421 { 1422 struct dsa_port *dp = dsa_phylink_to_port(config); 1423 phy_interface_t interface = state->interface; 1424 struct dsa_switch *ds = dp->ds; 1425 struct b53_device *dev = ds->priv; 1426 int port = dp->index; 1427 1428 if (is63xx(dev) && port >= B53_63XX_RGMII0) 1429 b53_adjust_63xx_rgmii(ds, port, interface); 1430 1431 if (mode == MLO_AN_FIXED) { 1432 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface)) 1433 b53_adjust_531x5_rgmii(ds, port, interface); 1434 1435 /* configure MII port if necessary */ 1436 if (is5325(dev)) 1437 b53_adjust_5325_mii(ds, port); 1438 } 1439 } 1440 1441 static void b53_phylink_mac_link_down(struct phylink_config *config, 1442 unsigned int mode, 1443 phy_interface_t interface) 1444 { 1445 struct dsa_port *dp = dsa_phylink_to_port(config); 1446 struct b53_device *dev = dp->ds->priv; 1447 int port = dp->index; 1448 1449 if (mode == MLO_AN_PHY) 1450 return; 1451 1452 if (mode == MLO_AN_FIXED) { 1453 b53_force_link(dev, port, false); 1454 return; 1455 } 1456 1457 if (phy_interface_mode_is_8023z(interface) && 1458 dev->ops->serdes_link_set) 1459 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1460 } 1461 1462 static void b53_phylink_mac_link_up(struct phylink_config *config, 1463 struct phy_device *phydev, 1464 unsigned int mode, 1465 phy_interface_t interface, 1466 int speed, int duplex, 1467 bool tx_pause, bool rx_pause) 1468 { 1469 struct dsa_port *dp = dsa_phylink_to_port(config); 1470 struct dsa_switch *ds = dp->ds; 1471 struct b53_device *dev = ds->priv; 1472 struct ethtool_keee *p = &dev->ports[dp->index].eee; 1473 int port = dp->index; 1474 1475 if (mode == MLO_AN_PHY) { 1476 /* Re-negotiate EEE if it was enabled already */ 1477 p->eee_enabled = b53_eee_init(ds, port, phydev); 1478 return; 1479 } 1480 1481 if (mode == MLO_AN_FIXED) { 1482 /* Force flow control on BCM5301x's CPU port */ 1483 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1484 tx_pause = rx_pause = true; 1485 1486 b53_force_port_config(dev, port, speed, duplex, 1487 tx_pause, rx_pause); 1488 b53_force_link(dev, port, true); 1489 return; 1490 } 1491 1492 if (phy_interface_mode_is_8023z(interface) && 1493 dev->ops->serdes_link_set) 1494 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1495 } 1496 1497 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1498 struct netlink_ext_ack *extack) 1499 { 1500 struct b53_device *dev = ds->priv; 1501 1502 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1503 1504 return 0; 1505 } 1506 EXPORT_SYMBOL(b53_vlan_filtering); 1507 1508 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1509 const struct switchdev_obj_port_vlan *vlan) 1510 { 1511 struct b53_device *dev = ds->priv; 1512 1513 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1514 return -EOPNOTSUPP; 1515 1516 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1517 * receiving VLAN tagged frames at all, we can still allow the port to 1518 * be configured for egress untagged. 1519 */ 1520 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1521 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1522 return -EINVAL; 1523 1524 if (vlan->vid >= dev->num_vlans) 1525 return -ERANGE; 1526 1527 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1528 1529 return 0; 1530 } 1531 1532 int b53_vlan_add(struct dsa_switch *ds, int port, 1533 const struct switchdev_obj_port_vlan *vlan, 1534 struct netlink_ext_ack *extack) 1535 { 1536 struct b53_device *dev = ds->priv; 1537 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1538 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1539 struct b53_vlan *vl; 1540 u16 old_pvid, new_pvid; 1541 int err; 1542 1543 err = b53_vlan_prepare(ds, port, vlan); 1544 if (err) 1545 return err; 1546 1547 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &old_pvid); 1548 if (pvid) 1549 new_pvid = vlan->vid; 1550 else if (!pvid && vlan->vid == old_pvid) 1551 new_pvid = b53_default_pvid(dev); 1552 else 1553 new_pvid = old_pvid; 1554 1555 vl = &dev->vlans[vlan->vid]; 1556 1557 b53_get_vlan_entry(dev, vlan->vid, vl); 1558 1559 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1560 untagged = true; 1561 1562 if (vlan->vid > 0 && dsa_is_cpu_port(ds, port)) 1563 untagged = false; 1564 1565 vl->members |= BIT(port); 1566 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1567 vl->untag |= BIT(port); 1568 else 1569 vl->untag &= ~BIT(port); 1570 1571 b53_set_vlan_entry(dev, vlan->vid, vl); 1572 b53_fast_age_vlan(dev, vlan->vid); 1573 1574 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) { 1575 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1576 new_pvid); 1577 b53_fast_age_vlan(dev, old_pvid); 1578 } 1579 1580 return 0; 1581 } 1582 EXPORT_SYMBOL(b53_vlan_add); 1583 1584 int b53_vlan_del(struct dsa_switch *ds, int port, 1585 const struct switchdev_obj_port_vlan *vlan) 1586 { 1587 struct b53_device *dev = ds->priv; 1588 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1589 struct b53_vlan *vl; 1590 u16 pvid; 1591 1592 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1593 1594 vl = &dev->vlans[vlan->vid]; 1595 1596 b53_get_vlan_entry(dev, vlan->vid, vl); 1597 1598 vl->members &= ~BIT(port); 1599 1600 if (pvid == vlan->vid) 1601 pvid = b53_default_pvid(dev); 1602 1603 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1604 vl->untag &= ~(BIT(port)); 1605 1606 b53_set_vlan_entry(dev, vlan->vid, vl); 1607 b53_fast_age_vlan(dev, vlan->vid); 1608 1609 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1610 b53_fast_age_vlan(dev, pvid); 1611 1612 return 0; 1613 } 1614 EXPORT_SYMBOL(b53_vlan_del); 1615 1616 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1617 static int b53_arl_op_wait(struct b53_device *dev) 1618 { 1619 unsigned int timeout = 10; 1620 u8 reg; 1621 1622 do { 1623 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1624 if (!(reg & ARLTBL_START_DONE)) 1625 return 0; 1626 1627 usleep_range(1000, 2000); 1628 } while (timeout--); 1629 1630 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1631 1632 return -ETIMEDOUT; 1633 } 1634 1635 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1636 { 1637 u8 reg; 1638 1639 if (op > ARLTBL_RW) 1640 return -EINVAL; 1641 1642 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1643 reg |= ARLTBL_START_DONE; 1644 if (op) 1645 reg |= ARLTBL_RW; 1646 else 1647 reg &= ~ARLTBL_RW; 1648 if (dev->vlan_enabled) 1649 reg &= ~ARLTBL_IVL_SVL_SELECT; 1650 else 1651 reg |= ARLTBL_IVL_SVL_SELECT; 1652 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1653 1654 return b53_arl_op_wait(dev); 1655 } 1656 1657 static int b53_arl_read(struct b53_device *dev, u64 mac, 1658 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1659 { 1660 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1661 unsigned int i; 1662 int ret; 1663 1664 ret = b53_arl_op_wait(dev); 1665 if (ret) 1666 return ret; 1667 1668 bitmap_zero(free_bins, dev->num_arl_bins); 1669 1670 /* Read the bins */ 1671 for (i = 0; i < dev->num_arl_bins; i++) { 1672 u64 mac_vid; 1673 u32 fwd_entry; 1674 1675 b53_read64(dev, B53_ARLIO_PAGE, 1676 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1677 b53_read32(dev, B53_ARLIO_PAGE, 1678 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1679 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1680 1681 if (!(fwd_entry & ARLTBL_VALID)) { 1682 set_bit(i, free_bins); 1683 continue; 1684 } 1685 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1686 continue; 1687 if (dev->vlan_enabled && 1688 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1689 continue; 1690 *idx = i; 1691 return 0; 1692 } 1693 1694 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1695 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT; 1696 } 1697 1698 static int b53_arl_op(struct b53_device *dev, int op, int port, 1699 const unsigned char *addr, u16 vid, bool is_valid) 1700 { 1701 struct b53_arl_entry ent; 1702 u32 fwd_entry; 1703 u64 mac, mac_vid = 0; 1704 u8 idx = 0; 1705 int ret; 1706 1707 /* Convert the array into a 64-bit MAC */ 1708 mac = ether_addr_to_u64(addr); 1709 1710 /* Perform a read for the given MAC and VID */ 1711 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1712 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1713 1714 /* Issue a read operation for this MAC */ 1715 ret = b53_arl_rw_op(dev, 1); 1716 if (ret) 1717 return ret; 1718 1719 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1720 1721 /* If this is a read, just finish now */ 1722 if (op) 1723 return ret; 1724 1725 switch (ret) { 1726 case -ETIMEDOUT: 1727 return ret; 1728 case -ENOSPC: 1729 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1730 addr, vid); 1731 return is_valid ? ret : 0; 1732 case -ENOENT: 1733 /* We could not find a matching MAC, so reset to a new entry */ 1734 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1735 addr, vid, idx); 1736 fwd_entry = 0; 1737 break; 1738 default: 1739 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1740 addr, vid, idx); 1741 break; 1742 } 1743 1744 /* For multicast address, the port is a bitmask and the validity 1745 * is determined by having at least one port being still active 1746 */ 1747 if (!is_multicast_ether_addr(addr)) { 1748 ent.port = port; 1749 ent.is_valid = is_valid; 1750 } else { 1751 if (is_valid) 1752 ent.port |= BIT(port); 1753 else 1754 ent.port &= ~BIT(port); 1755 1756 ent.is_valid = !!(ent.port); 1757 } 1758 1759 ent.vid = vid; 1760 ent.is_static = true; 1761 ent.is_age = false; 1762 memcpy(ent.mac, addr, ETH_ALEN); 1763 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1764 1765 b53_write64(dev, B53_ARLIO_PAGE, 1766 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1767 b53_write32(dev, B53_ARLIO_PAGE, 1768 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1769 1770 return b53_arl_rw_op(dev, 0); 1771 } 1772 1773 int b53_fdb_add(struct dsa_switch *ds, int port, 1774 const unsigned char *addr, u16 vid, 1775 struct dsa_db db) 1776 { 1777 struct b53_device *priv = ds->priv; 1778 int ret; 1779 1780 /* 5325 and 5365 require some more massaging, but could 1781 * be supported eventually 1782 */ 1783 if (is5325(priv) || is5365(priv)) 1784 return -EOPNOTSUPP; 1785 1786 mutex_lock(&priv->arl_mutex); 1787 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1788 mutex_unlock(&priv->arl_mutex); 1789 1790 return ret; 1791 } 1792 EXPORT_SYMBOL(b53_fdb_add); 1793 1794 int b53_fdb_del(struct dsa_switch *ds, int port, 1795 const unsigned char *addr, u16 vid, 1796 struct dsa_db db) 1797 { 1798 struct b53_device *priv = ds->priv; 1799 int ret; 1800 1801 mutex_lock(&priv->arl_mutex); 1802 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1803 mutex_unlock(&priv->arl_mutex); 1804 1805 return ret; 1806 } 1807 EXPORT_SYMBOL(b53_fdb_del); 1808 1809 static int b53_arl_search_wait(struct b53_device *dev) 1810 { 1811 unsigned int timeout = 1000; 1812 u8 reg; 1813 1814 do { 1815 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1816 if (!(reg & ARL_SRCH_STDN)) 1817 return 0; 1818 1819 if (reg & ARL_SRCH_VLID) 1820 return 0; 1821 1822 usleep_range(1000, 2000); 1823 } while (timeout--); 1824 1825 return -ETIMEDOUT; 1826 } 1827 1828 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1829 struct b53_arl_entry *ent) 1830 { 1831 u64 mac_vid; 1832 u32 fwd_entry; 1833 1834 b53_read64(dev, B53_ARLIO_PAGE, 1835 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1836 b53_read32(dev, B53_ARLIO_PAGE, 1837 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1838 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1839 } 1840 1841 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1842 dsa_fdb_dump_cb_t *cb, void *data) 1843 { 1844 if (!ent->is_valid) 1845 return 0; 1846 1847 if (port != ent->port) 1848 return 0; 1849 1850 return cb(ent->mac, ent->vid, ent->is_static, data); 1851 } 1852 1853 int b53_fdb_dump(struct dsa_switch *ds, int port, 1854 dsa_fdb_dump_cb_t *cb, void *data) 1855 { 1856 struct b53_device *priv = ds->priv; 1857 struct b53_arl_entry results[2]; 1858 unsigned int count = 0; 1859 int ret; 1860 u8 reg; 1861 1862 mutex_lock(&priv->arl_mutex); 1863 1864 /* Start search operation */ 1865 reg = ARL_SRCH_STDN; 1866 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1867 1868 do { 1869 ret = b53_arl_search_wait(priv); 1870 if (ret) 1871 break; 1872 1873 b53_arl_search_rd(priv, 0, &results[0]); 1874 ret = b53_fdb_copy(port, &results[0], cb, data); 1875 if (ret) 1876 break; 1877 1878 if (priv->num_arl_bins > 2) { 1879 b53_arl_search_rd(priv, 1, &results[1]); 1880 ret = b53_fdb_copy(port, &results[1], cb, data); 1881 if (ret) 1882 break; 1883 1884 if (!results[0].is_valid && !results[1].is_valid) 1885 break; 1886 } 1887 1888 } while (count++ < b53_max_arl_entries(priv) / 2); 1889 1890 mutex_unlock(&priv->arl_mutex); 1891 1892 return 0; 1893 } 1894 EXPORT_SYMBOL(b53_fdb_dump); 1895 1896 int b53_mdb_add(struct dsa_switch *ds, int port, 1897 const struct switchdev_obj_port_mdb *mdb, 1898 struct dsa_db db) 1899 { 1900 struct b53_device *priv = ds->priv; 1901 int ret; 1902 1903 /* 5325 and 5365 require some more massaging, but could 1904 * be supported eventually 1905 */ 1906 if (is5325(priv) || is5365(priv)) 1907 return -EOPNOTSUPP; 1908 1909 mutex_lock(&priv->arl_mutex); 1910 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1911 mutex_unlock(&priv->arl_mutex); 1912 1913 return ret; 1914 } 1915 EXPORT_SYMBOL(b53_mdb_add); 1916 1917 int b53_mdb_del(struct dsa_switch *ds, int port, 1918 const struct switchdev_obj_port_mdb *mdb, 1919 struct dsa_db db) 1920 { 1921 struct b53_device *priv = ds->priv; 1922 int ret; 1923 1924 mutex_lock(&priv->arl_mutex); 1925 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1926 mutex_unlock(&priv->arl_mutex); 1927 if (ret) 1928 dev_err(ds->dev, "failed to delete MDB entry\n"); 1929 1930 return ret; 1931 } 1932 EXPORT_SYMBOL(b53_mdb_del); 1933 1934 int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, 1935 bool *tx_fwd_offload, struct netlink_ext_ack *extack) 1936 { 1937 struct b53_device *dev = ds->priv; 1938 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1939 u16 pvlan, reg; 1940 unsigned int i; 1941 1942 /* On 7278, port 7 which connects to the ASP should only receive 1943 * traffic from matching CFP rules. 1944 */ 1945 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1946 return -EINVAL; 1947 1948 /* Make this port leave the all VLANs join since we will have proper 1949 * VLAN entries from now on 1950 */ 1951 if (is58xx(dev)) { 1952 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1953 reg &= ~BIT(port); 1954 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1955 reg &= ~BIT(cpu_port); 1956 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1957 } 1958 1959 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1960 1961 b53_for_each_port(dev, i) { 1962 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1963 continue; 1964 1965 /* Add this local port to the remote port VLAN control 1966 * membership and update the remote port bitmask 1967 */ 1968 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1969 reg |= BIT(port); 1970 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1971 dev->ports[i].vlan_ctl_mask = reg; 1972 1973 pvlan |= BIT(i); 1974 } 1975 1976 /* Configure the local port VLAN control membership to include 1977 * remote ports and update the local port bitmask 1978 */ 1979 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1980 dev->ports[port].vlan_ctl_mask = pvlan; 1981 1982 return 0; 1983 } 1984 EXPORT_SYMBOL(b53_br_join); 1985 1986 void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge) 1987 { 1988 struct b53_device *dev = ds->priv; 1989 struct b53_vlan *vl; 1990 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1991 unsigned int i; 1992 u16 pvlan, reg, pvid; 1993 1994 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1995 1996 b53_for_each_port(dev, i) { 1997 /* Don't touch the remaining ports */ 1998 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1999 continue; 2000 2001 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 2002 reg &= ~BIT(port); 2003 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 2004 dev->ports[port].vlan_ctl_mask = reg; 2005 2006 /* Prevent self removal to preserve isolation */ 2007 if (port != i) 2008 pvlan &= ~BIT(i); 2009 } 2010 2011 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 2012 dev->ports[port].vlan_ctl_mask = pvlan; 2013 2014 pvid = b53_default_pvid(dev); 2015 vl = &dev->vlans[pvid]; 2016 2017 /* Make this port join all VLANs without VLAN entries */ 2018 if (is58xx(dev)) { 2019 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 2020 reg |= BIT(port); 2021 if (!(reg & BIT(cpu_port))) 2022 reg |= BIT(cpu_port); 2023 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 2024 } else { 2025 b53_get_vlan_entry(dev, pvid, vl); 2026 vl->members |= BIT(port) | BIT(cpu_port); 2027 vl->untag |= BIT(port) | BIT(cpu_port); 2028 b53_set_vlan_entry(dev, pvid, vl); 2029 } 2030 } 2031 EXPORT_SYMBOL(b53_br_leave); 2032 2033 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 2034 { 2035 struct b53_device *dev = ds->priv; 2036 u8 hw_state; 2037 u8 reg; 2038 2039 switch (state) { 2040 case BR_STATE_DISABLED: 2041 hw_state = PORT_CTRL_DIS_STATE; 2042 break; 2043 case BR_STATE_LISTENING: 2044 hw_state = PORT_CTRL_LISTEN_STATE; 2045 break; 2046 case BR_STATE_LEARNING: 2047 hw_state = PORT_CTRL_LEARN_STATE; 2048 break; 2049 case BR_STATE_FORWARDING: 2050 hw_state = PORT_CTRL_FWD_STATE; 2051 break; 2052 case BR_STATE_BLOCKING: 2053 hw_state = PORT_CTRL_BLOCK_STATE; 2054 break; 2055 default: 2056 dev_err(ds->dev, "invalid STP state: %d\n", state); 2057 return; 2058 } 2059 2060 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 2061 reg &= ~PORT_CTRL_STP_STATE_MASK; 2062 reg |= hw_state; 2063 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 2064 } 2065 EXPORT_SYMBOL(b53_br_set_stp_state); 2066 2067 void b53_br_fast_age(struct dsa_switch *ds, int port) 2068 { 2069 struct b53_device *dev = ds->priv; 2070 2071 if (b53_fast_age_port(dev, port)) 2072 dev_err(ds->dev, "fast ageing failed\n"); 2073 } 2074 EXPORT_SYMBOL(b53_br_fast_age); 2075 2076 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2077 struct switchdev_brport_flags flags, 2078 struct netlink_ext_ack *extack) 2079 { 2080 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 2081 return -EINVAL; 2082 2083 return 0; 2084 } 2085 EXPORT_SYMBOL(b53_br_flags_pre); 2086 2087 int b53_br_flags(struct dsa_switch *ds, int port, 2088 struct switchdev_brport_flags flags, 2089 struct netlink_ext_ack *extack) 2090 { 2091 if (flags.mask & BR_FLOOD) 2092 b53_port_set_ucast_flood(ds->priv, port, 2093 !!(flags.val & BR_FLOOD)); 2094 if (flags.mask & BR_MCAST_FLOOD) 2095 b53_port_set_mcast_flood(ds->priv, port, 2096 !!(flags.val & BR_MCAST_FLOOD)); 2097 if (flags.mask & BR_LEARNING) 2098 b53_port_set_learning(ds->priv, port, 2099 !!(flags.val & BR_LEARNING)); 2100 2101 return 0; 2102 } 2103 EXPORT_SYMBOL(b53_br_flags); 2104 2105 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2106 { 2107 /* Broadcom switches will accept enabling Broadcom tags on the 2108 * following ports: 5, 7 and 8, any other port is not supported 2109 */ 2110 switch (port) { 2111 case B53_CPU_PORT_25: 2112 case 7: 2113 case B53_CPU_PORT: 2114 return true; 2115 } 2116 2117 return false; 2118 } 2119 2120 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2121 enum dsa_tag_protocol tag_protocol) 2122 { 2123 bool ret = b53_possible_cpu_port(ds, port); 2124 2125 if (!ret) { 2126 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2127 port); 2128 return ret; 2129 } 2130 2131 switch (tag_protocol) { 2132 case DSA_TAG_PROTO_BRCM: 2133 case DSA_TAG_PROTO_BRCM_PREPEND: 2134 dev_warn(ds->dev, 2135 "Port %d is stacked to Broadcom tag switch\n", port); 2136 ret = false; 2137 break; 2138 default: 2139 ret = true; 2140 break; 2141 } 2142 2143 return ret; 2144 } 2145 2146 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2147 enum dsa_tag_protocol mprot) 2148 { 2149 struct b53_device *dev = ds->priv; 2150 2151 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2152 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2153 goto out; 2154 } 2155 2156 /* Older models require a different 6 byte tag */ 2157 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2158 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2159 goto out; 2160 } 2161 2162 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2163 * which requires us to use the prepended Broadcom tag type 2164 */ 2165 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2166 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2167 goto out; 2168 } 2169 2170 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2171 out: 2172 return dev->tag_protocol; 2173 } 2174 EXPORT_SYMBOL(b53_get_tag_protocol); 2175 2176 int b53_mirror_add(struct dsa_switch *ds, int port, 2177 struct dsa_mall_mirror_tc_entry *mirror, bool ingress, 2178 struct netlink_ext_ack *extack) 2179 { 2180 struct b53_device *dev = ds->priv; 2181 u16 reg, loc; 2182 2183 if (ingress) 2184 loc = B53_IG_MIR_CTL; 2185 else 2186 loc = B53_EG_MIR_CTL; 2187 2188 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2189 reg |= BIT(port); 2190 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2191 2192 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2193 reg &= ~CAP_PORT_MASK; 2194 reg |= mirror->to_local_port; 2195 reg |= MIRROR_EN; 2196 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2197 2198 return 0; 2199 } 2200 EXPORT_SYMBOL(b53_mirror_add); 2201 2202 void b53_mirror_del(struct dsa_switch *ds, int port, 2203 struct dsa_mall_mirror_tc_entry *mirror) 2204 { 2205 struct b53_device *dev = ds->priv; 2206 bool loc_disable = false, other_loc_disable = false; 2207 u16 reg, loc; 2208 2209 if (mirror->ingress) 2210 loc = B53_IG_MIR_CTL; 2211 else 2212 loc = B53_EG_MIR_CTL; 2213 2214 /* Update the desired ingress/egress register */ 2215 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2216 reg &= ~BIT(port); 2217 if (!(reg & MIRROR_MASK)) 2218 loc_disable = true; 2219 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2220 2221 /* Now look at the other one to know if we can disable mirroring 2222 * entirely 2223 */ 2224 if (mirror->ingress) 2225 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2226 else 2227 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2228 if (!(reg & MIRROR_MASK)) 2229 other_loc_disable = true; 2230 2231 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2232 /* Both no longer have ports, let's disable mirroring */ 2233 if (loc_disable && other_loc_disable) { 2234 reg &= ~MIRROR_EN; 2235 reg &= ~mirror->to_local_port; 2236 } 2237 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2238 } 2239 EXPORT_SYMBOL(b53_mirror_del); 2240 2241 /* Returns 0 if EEE was not enabled, or 1 otherwise 2242 */ 2243 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2244 { 2245 int ret; 2246 2247 ret = phy_init_eee(phy, false); 2248 if (ret) 2249 return 0; 2250 2251 b53_eee_enable_set(ds, port, true); 2252 2253 return 1; 2254 } 2255 EXPORT_SYMBOL(b53_eee_init); 2256 2257 bool b53_support_eee(struct dsa_switch *ds, int port) 2258 { 2259 struct b53_device *dev = ds->priv; 2260 2261 return !is5325(dev) && !is5365(dev); 2262 } 2263 EXPORT_SYMBOL(b53_support_eee); 2264 2265 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 2266 { 2267 struct b53_device *dev = ds->priv; 2268 struct ethtool_keee *p = &dev->ports[port].eee; 2269 2270 p->eee_enabled = e->eee_enabled; 2271 b53_eee_enable_set(ds, port, e->eee_enabled); 2272 2273 return 0; 2274 } 2275 EXPORT_SYMBOL(b53_set_mac_eee); 2276 2277 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2278 { 2279 struct b53_device *dev = ds->priv; 2280 bool enable_jumbo; 2281 bool allow_10_100; 2282 2283 if (is5325(dev) || is5365(dev)) 2284 return 0; 2285 2286 if (!dsa_is_cpu_port(ds, port)) 2287 return 0; 2288 2289 enable_jumbo = (mtu > ETH_DATA_LEN); 2290 allow_10_100 = !is63xx(dev); 2291 2292 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2293 } 2294 2295 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2296 { 2297 struct b53_device *dev = ds->priv; 2298 2299 if (is5325(dev) || is5365(dev)) 2300 return B53_MAX_MTU_25; 2301 2302 return B53_MAX_MTU; 2303 } 2304 2305 static const struct phylink_mac_ops b53_phylink_mac_ops = { 2306 .mac_select_pcs = b53_phylink_mac_select_pcs, 2307 .mac_config = b53_phylink_mac_config, 2308 .mac_link_down = b53_phylink_mac_link_down, 2309 .mac_link_up = b53_phylink_mac_link_up, 2310 }; 2311 2312 static const struct dsa_switch_ops b53_switch_ops = { 2313 .get_tag_protocol = b53_get_tag_protocol, 2314 .setup = b53_setup, 2315 .teardown = b53_teardown, 2316 .get_strings = b53_get_strings, 2317 .get_ethtool_stats = b53_get_ethtool_stats, 2318 .get_sset_count = b53_get_sset_count, 2319 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2320 .phy_read = b53_phy_read16, 2321 .phy_write = b53_phy_write16, 2322 .phylink_get_caps = b53_phylink_get_caps, 2323 .port_enable = b53_enable_port, 2324 .port_disable = b53_disable_port, 2325 .support_eee = b53_support_eee, 2326 .set_mac_eee = b53_set_mac_eee, 2327 .port_bridge_join = b53_br_join, 2328 .port_bridge_leave = b53_br_leave, 2329 .port_pre_bridge_flags = b53_br_flags_pre, 2330 .port_bridge_flags = b53_br_flags, 2331 .port_stp_state_set = b53_br_set_stp_state, 2332 .port_fast_age = b53_br_fast_age, 2333 .port_vlan_filtering = b53_vlan_filtering, 2334 .port_vlan_add = b53_vlan_add, 2335 .port_vlan_del = b53_vlan_del, 2336 .port_fdb_dump = b53_fdb_dump, 2337 .port_fdb_add = b53_fdb_add, 2338 .port_fdb_del = b53_fdb_del, 2339 .port_mirror_add = b53_mirror_add, 2340 .port_mirror_del = b53_mirror_del, 2341 .port_mdb_add = b53_mdb_add, 2342 .port_mdb_del = b53_mdb_del, 2343 .port_max_mtu = b53_get_max_mtu, 2344 .port_change_mtu = b53_change_mtu, 2345 }; 2346 2347 struct b53_chip_data { 2348 u32 chip_id; 2349 const char *dev_name; 2350 u16 vlans; 2351 u16 enabled_ports; 2352 u8 imp_port; 2353 u8 cpu_port; 2354 u8 vta_regs[3]; 2355 u8 arl_bins; 2356 u16 arl_buckets; 2357 u8 duplex_reg; 2358 u8 jumbo_pm_reg; 2359 u8 jumbo_size_reg; 2360 }; 2361 2362 #define B53_VTA_REGS \ 2363 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2364 #define B53_VTA_REGS_9798 \ 2365 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2366 #define B53_VTA_REGS_63XX \ 2367 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2368 2369 static const struct b53_chip_data b53_switch_chips[] = { 2370 { 2371 .chip_id = BCM5325_DEVICE_ID, 2372 .dev_name = "BCM5325", 2373 .vlans = 16, 2374 .enabled_ports = 0x3f, 2375 .arl_bins = 2, 2376 .arl_buckets = 1024, 2377 .imp_port = 5, 2378 .duplex_reg = B53_DUPLEX_STAT_FE, 2379 }, 2380 { 2381 .chip_id = BCM5365_DEVICE_ID, 2382 .dev_name = "BCM5365", 2383 .vlans = 256, 2384 .enabled_ports = 0x3f, 2385 .arl_bins = 2, 2386 .arl_buckets = 1024, 2387 .imp_port = 5, 2388 .duplex_reg = B53_DUPLEX_STAT_FE, 2389 }, 2390 { 2391 .chip_id = BCM5389_DEVICE_ID, 2392 .dev_name = "BCM5389", 2393 .vlans = 4096, 2394 .enabled_ports = 0x11f, 2395 .arl_bins = 4, 2396 .arl_buckets = 1024, 2397 .imp_port = 8, 2398 .vta_regs = B53_VTA_REGS, 2399 .duplex_reg = B53_DUPLEX_STAT_GE, 2400 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2401 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2402 }, 2403 { 2404 .chip_id = BCM5395_DEVICE_ID, 2405 .dev_name = "BCM5395", 2406 .vlans = 4096, 2407 .enabled_ports = 0x11f, 2408 .arl_bins = 4, 2409 .arl_buckets = 1024, 2410 .imp_port = 8, 2411 .vta_regs = B53_VTA_REGS, 2412 .duplex_reg = B53_DUPLEX_STAT_GE, 2413 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2414 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2415 }, 2416 { 2417 .chip_id = BCM5397_DEVICE_ID, 2418 .dev_name = "BCM5397", 2419 .vlans = 4096, 2420 .enabled_ports = 0x11f, 2421 .arl_bins = 4, 2422 .arl_buckets = 1024, 2423 .imp_port = 8, 2424 .vta_regs = B53_VTA_REGS_9798, 2425 .duplex_reg = B53_DUPLEX_STAT_GE, 2426 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2427 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2428 }, 2429 { 2430 .chip_id = BCM5398_DEVICE_ID, 2431 .dev_name = "BCM5398", 2432 .vlans = 4096, 2433 .enabled_ports = 0x17f, 2434 .arl_bins = 4, 2435 .arl_buckets = 1024, 2436 .imp_port = 8, 2437 .vta_regs = B53_VTA_REGS_9798, 2438 .duplex_reg = B53_DUPLEX_STAT_GE, 2439 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2440 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2441 }, 2442 { 2443 .chip_id = BCM53101_DEVICE_ID, 2444 .dev_name = "BCM53101", 2445 .vlans = 4096, 2446 .enabled_ports = 0x11f, 2447 .arl_bins = 4, 2448 .arl_buckets = 512, 2449 .vta_regs = B53_VTA_REGS, 2450 .imp_port = 8, 2451 .duplex_reg = B53_DUPLEX_STAT_GE, 2452 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2453 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2454 }, 2455 { 2456 .chip_id = BCM53115_DEVICE_ID, 2457 .dev_name = "BCM53115", 2458 .vlans = 4096, 2459 .enabled_ports = 0x11f, 2460 .arl_bins = 4, 2461 .arl_buckets = 1024, 2462 .vta_regs = B53_VTA_REGS, 2463 .imp_port = 8, 2464 .duplex_reg = B53_DUPLEX_STAT_GE, 2465 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2466 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2467 }, 2468 { 2469 .chip_id = BCM53125_DEVICE_ID, 2470 .dev_name = "BCM53125", 2471 .vlans = 4096, 2472 .enabled_ports = 0x1ff, 2473 .arl_bins = 4, 2474 .arl_buckets = 1024, 2475 .imp_port = 8, 2476 .vta_regs = B53_VTA_REGS, 2477 .duplex_reg = B53_DUPLEX_STAT_GE, 2478 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2479 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2480 }, 2481 { 2482 .chip_id = BCM53128_DEVICE_ID, 2483 .dev_name = "BCM53128", 2484 .vlans = 4096, 2485 .enabled_ports = 0x1ff, 2486 .arl_bins = 4, 2487 .arl_buckets = 1024, 2488 .imp_port = 8, 2489 .vta_regs = B53_VTA_REGS, 2490 .duplex_reg = B53_DUPLEX_STAT_GE, 2491 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2492 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2493 }, 2494 { 2495 .chip_id = BCM63XX_DEVICE_ID, 2496 .dev_name = "BCM63xx", 2497 .vlans = 4096, 2498 .enabled_ports = 0, /* pdata must provide them */ 2499 .arl_bins = 4, 2500 .arl_buckets = 1024, 2501 .imp_port = 8, 2502 .vta_regs = B53_VTA_REGS_63XX, 2503 .duplex_reg = B53_DUPLEX_STAT_63XX, 2504 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2505 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2506 }, 2507 { 2508 .chip_id = BCM63268_DEVICE_ID, 2509 .dev_name = "BCM63268", 2510 .vlans = 4096, 2511 .enabled_ports = 0, /* pdata must provide them */ 2512 .arl_bins = 4, 2513 .arl_buckets = 1024, 2514 .imp_port = 8, 2515 .vta_regs = B53_VTA_REGS_63XX, 2516 .duplex_reg = B53_DUPLEX_STAT_63XX, 2517 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2518 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2519 }, 2520 { 2521 .chip_id = BCM53010_DEVICE_ID, 2522 .dev_name = "BCM53010", 2523 .vlans = 4096, 2524 .enabled_ports = 0x1bf, 2525 .arl_bins = 4, 2526 .arl_buckets = 1024, 2527 .imp_port = 8, 2528 .vta_regs = B53_VTA_REGS, 2529 .duplex_reg = B53_DUPLEX_STAT_GE, 2530 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2531 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2532 }, 2533 { 2534 .chip_id = BCM53011_DEVICE_ID, 2535 .dev_name = "BCM53011", 2536 .vlans = 4096, 2537 .enabled_ports = 0x1bf, 2538 .arl_bins = 4, 2539 .arl_buckets = 1024, 2540 .imp_port = 8, 2541 .vta_regs = B53_VTA_REGS, 2542 .duplex_reg = B53_DUPLEX_STAT_GE, 2543 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2544 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2545 }, 2546 { 2547 .chip_id = BCM53012_DEVICE_ID, 2548 .dev_name = "BCM53012", 2549 .vlans = 4096, 2550 .enabled_ports = 0x1bf, 2551 .arl_bins = 4, 2552 .arl_buckets = 1024, 2553 .imp_port = 8, 2554 .vta_regs = B53_VTA_REGS, 2555 .duplex_reg = B53_DUPLEX_STAT_GE, 2556 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2557 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2558 }, 2559 { 2560 .chip_id = BCM53018_DEVICE_ID, 2561 .dev_name = "BCM53018", 2562 .vlans = 4096, 2563 .enabled_ports = 0x1bf, 2564 .arl_bins = 4, 2565 .arl_buckets = 1024, 2566 .imp_port = 8, 2567 .vta_regs = B53_VTA_REGS, 2568 .duplex_reg = B53_DUPLEX_STAT_GE, 2569 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2570 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2571 }, 2572 { 2573 .chip_id = BCM53019_DEVICE_ID, 2574 .dev_name = "BCM53019", 2575 .vlans = 4096, 2576 .enabled_ports = 0x1bf, 2577 .arl_bins = 4, 2578 .arl_buckets = 1024, 2579 .imp_port = 8, 2580 .vta_regs = B53_VTA_REGS, 2581 .duplex_reg = B53_DUPLEX_STAT_GE, 2582 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2583 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2584 }, 2585 { 2586 .chip_id = BCM58XX_DEVICE_ID, 2587 .dev_name = "BCM585xx/586xx/88312", 2588 .vlans = 4096, 2589 .enabled_ports = 0x1ff, 2590 .arl_bins = 4, 2591 .arl_buckets = 1024, 2592 .imp_port = 8, 2593 .vta_regs = B53_VTA_REGS, 2594 .duplex_reg = B53_DUPLEX_STAT_GE, 2595 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2596 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2597 }, 2598 { 2599 .chip_id = BCM583XX_DEVICE_ID, 2600 .dev_name = "BCM583xx/11360", 2601 .vlans = 4096, 2602 .enabled_ports = 0x103, 2603 .arl_bins = 4, 2604 .arl_buckets = 1024, 2605 .imp_port = 8, 2606 .vta_regs = B53_VTA_REGS, 2607 .duplex_reg = B53_DUPLEX_STAT_GE, 2608 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2609 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2610 }, 2611 /* Starfighter 2 */ 2612 { 2613 .chip_id = BCM4908_DEVICE_ID, 2614 .dev_name = "BCM4908", 2615 .vlans = 4096, 2616 .enabled_ports = 0x1bf, 2617 .arl_bins = 4, 2618 .arl_buckets = 256, 2619 .imp_port = 8, 2620 .vta_regs = B53_VTA_REGS, 2621 .duplex_reg = B53_DUPLEX_STAT_GE, 2622 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2623 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2624 }, 2625 { 2626 .chip_id = BCM7445_DEVICE_ID, 2627 .dev_name = "BCM7445", 2628 .vlans = 4096, 2629 .enabled_ports = 0x1ff, 2630 .arl_bins = 4, 2631 .arl_buckets = 1024, 2632 .imp_port = 8, 2633 .vta_regs = B53_VTA_REGS, 2634 .duplex_reg = B53_DUPLEX_STAT_GE, 2635 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2636 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2637 }, 2638 { 2639 .chip_id = BCM7278_DEVICE_ID, 2640 .dev_name = "BCM7278", 2641 .vlans = 4096, 2642 .enabled_ports = 0x1ff, 2643 .arl_bins = 4, 2644 .arl_buckets = 256, 2645 .imp_port = 8, 2646 .vta_regs = B53_VTA_REGS, 2647 .duplex_reg = B53_DUPLEX_STAT_GE, 2648 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2649 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2650 }, 2651 { 2652 .chip_id = BCM53134_DEVICE_ID, 2653 .dev_name = "BCM53134", 2654 .vlans = 4096, 2655 .enabled_ports = 0x12f, 2656 .imp_port = 8, 2657 .cpu_port = B53_CPU_PORT, 2658 .vta_regs = B53_VTA_REGS, 2659 .arl_bins = 4, 2660 .arl_buckets = 1024, 2661 .duplex_reg = B53_DUPLEX_STAT_GE, 2662 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2663 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2664 }, 2665 }; 2666 2667 static int b53_switch_init(struct b53_device *dev) 2668 { 2669 unsigned int i; 2670 int ret; 2671 2672 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2673 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2674 2675 if (chip->chip_id == dev->chip_id) { 2676 if (!dev->enabled_ports) 2677 dev->enabled_ports = chip->enabled_ports; 2678 dev->name = chip->dev_name; 2679 dev->duplex_reg = chip->duplex_reg; 2680 dev->vta_regs[0] = chip->vta_regs[0]; 2681 dev->vta_regs[1] = chip->vta_regs[1]; 2682 dev->vta_regs[2] = chip->vta_regs[2]; 2683 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2684 dev->imp_port = chip->imp_port; 2685 dev->num_vlans = chip->vlans; 2686 dev->num_arl_bins = chip->arl_bins; 2687 dev->num_arl_buckets = chip->arl_buckets; 2688 break; 2689 } 2690 } 2691 2692 /* check which BCM5325x version we have */ 2693 if (is5325(dev)) { 2694 u8 vc4; 2695 2696 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2697 2698 /* check reserved bits */ 2699 switch (vc4 & 3) { 2700 case 1: 2701 /* BCM5325E */ 2702 break; 2703 case 3: 2704 /* BCM5325F - do not use port 4 */ 2705 dev->enabled_ports &= ~BIT(4); 2706 break; 2707 default: 2708 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2709 #ifndef CONFIG_BCM47XX 2710 /* BCM5325M */ 2711 return -EINVAL; 2712 #else 2713 break; 2714 #endif 2715 } 2716 } 2717 2718 dev->num_ports = fls(dev->enabled_ports); 2719 2720 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2721 2722 /* Include non standard CPU port built-in PHYs to be probed */ 2723 if (is539x(dev) || is531x5(dev)) { 2724 for (i = 0; i < dev->num_ports; i++) { 2725 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2726 !b53_possible_cpu_port(dev->ds, i)) 2727 dev->ds->phys_mii_mask |= BIT(i); 2728 } 2729 } 2730 2731 dev->ports = devm_kcalloc(dev->dev, 2732 dev->num_ports, sizeof(struct b53_port), 2733 GFP_KERNEL); 2734 if (!dev->ports) 2735 return -ENOMEM; 2736 2737 dev->vlans = devm_kcalloc(dev->dev, 2738 dev->num_vlans, sizeof(struct b53_vlan), 2739 GFP_KERNEL); 2740 if (!dev->vlans) 2741 return -ENOMEM; 2742 2743 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2744 if (dev->reset_gpio >= 0) { 2745 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2746 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2747 if (ret) 2748 return ret; 2749 } 2750 2751 return 0; 2752 } 2753 2754 struct b53_device *b53_switch_alloc(struct device *base, 2755 const struct b53_io_ops *ops, 2756 void *priv) 2757 { 2758 struct dsa_switch *ds; 2759 struct b53_device *dev; 2760 2761 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2762 if (!ds) 2763 return NULL; 2764 2765 ds->dev = base; 2766 2767 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2768 if (!dev) 2769 return NULL; 2770 2771 ds->priv = dev; 2772 dev->dev = base; 2773 2774 dev->ds = ds; 2775 dev->priv = priv; 2776 dev->ops = ops; 2777 ds->ops = &b53_switch_ops; 2778 ds->phylink_mac_ops = &b53_phylink_mac_ops; 2779 dev->vlan_enabled = true; 2780 /* Let DSA handle the case were multiple bridges span the same switch 2781 * device and different VLAN awareness settings are requested, which 2782 * would be breaking filtering semantics for any of the other bridge 2783 * devices. (not hardware supported) 2784 */ 2785 ds->vlan_filtering_is_global = true; 2786 2787 mutex_init(&dev->reg_mutex); 2788 mutex_init(&dev->stats_mutex); 2789 mutex_init(&dev->arl_mutex); 2790 2791 return dev; 2792 } 2793 EXPORT_SYMBOL(b53_switch_alloc); 2794 2795 int b53_switch_detect(struct b53_device *dev) 2796 { 2797 u32 id32; 2798 u16 tmp; 2799 u8 id8; 2800 int ret; 2801 2802 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2803 if (ret) 2804 return ret; 2805 2806 switch (id8) { 2807 case 0: 2808 /* BCM5325 and BCM5365 do not have this register so reads 2809 * return 0. But the read operation did succeed, so assume this 2810 * is one of them. 2811 * 2812 * Next check if we can write to the 5325's VTA register; for 2813 * 5365 it is read only. 2814 */ 2815 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2816 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2817 2818 if (tmp == 0xf) 2819 dev->chip_id = BCM5325_DEVICE_ID; 2820 else 2821 dev->chip_id = BCM5365_DEVICE_ID; 2822 break; 2823 case BCM5389_DEVICE_ID: 2824 case BCM5395_DEVICE_ID: 2825 case BCM5397_DEVICE_ID: 2826 case BCM5398_DEVICE_ID: 2827 dev->chip_id = id8; 2828 break; 2829 default: 2830 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2831 if (ret) 2832 return ret; 2833 2834 switch (id32) { 2835 case BCM53101_DEVICE_ID: 2836 case BCM53115_DEVICE_ID: 2837 case BCM53125_DEVICE_ID: 2838 case BCM53128_DEVICE_ID: 2839 case BCM53010_DEVICE_ID: 2840 case BCM53011_DEVICE_ID: 2841 case BCM53012_DEVICE_ID: 2842 case BCM53018_DEVICE_ID: 2843 case BCM53019_DEVICE_ID: 2844 case BCM53134_DEVICE_ID: 2845 dev->chip_id = id32; 2846 break; 2847 default: 2848 dev_err(dev->dev, 2849 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2850 id8, id32); 2851 return -ENODEV; 2852 } 2853 } 2854 2855 if (dev->chip_id == BCM5325_DEVICE_ID) 2856 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2857 &dev->core_rev); 2858 else 2859 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2860 &dev->core_rev); 2861 } 2862 EXPORT_SYMBOL(b53_switch_detect); 2863 2864 int b53_switch_register(struct b53_device *dev) 2865 { 2866 int ret; 2867 2868 if (dev->pdata) { 2869 dev->chip_id = dev->pdata->chip_id; 2870 dev->enabled_ports = dev->pdata->enabled_ports; 2871 } 2872 2873 if (!dev->chip_id && b53_switch_detect(dev)) 2874 return -EINVAL; 2875 2876 ret = b53_switch_init(dev); 2877 if (ret) 2878 return ret; 2879 2880 dev_info(dev->dev, "found switch: %s, rev %i\n", 2881 dev->name, dev->core_rev); 2882 2883 return dsa_register_switch(dev->ds); 2884 } 2885 EXPORT_SYMBOL(b53_switch_register); 2886 2887 MODULE_AUTHOR("Jonas Gorski <[email protected]>"); 2888 MODULE_DESCRIPTION("B53 switch library"); 2889 MODULE_LICENSE("Dual BSD/GPL"); 2890