1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx SDFEC 4 * 5 * Copyright (C) 2019 Xilinx, Inc. 6 * 7 * Description: 8 * This driver is developed for SDFEC16 (Soft Decision FEC 16nm) 9 * IP. It exposes a char device which supports file operations 10 * like open(), close() and ioctl(). 11 */ 12 13 #include <linux/miscdevice.h> 14 #include <linux/io.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of_platform.h> 19 #include <linux/poll.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/compat.h> 23 #include <linux/highmem.h> 24 25 #include <uapi/misc/xilinx_sdfec.h> 26 27 #define DEV_NAME_LEN 12 28 29 static DEFINE_IDA(dev_nrs); 30 31 /* Xilinx SDFEC Register Map */ 32 /* CODE_WRI_PROTECT Register */ 33 #define XSDFEC_CODE_WR_PROTECT_ADDR (0x4) 34 35 /* ACTIVE Register */ 36 #define XSDFEC_ACTIVE_ADDR (0x8) 37 #define XSDFEC_IS_ACTIVITY_SET (0x1) 38 39 /* AXIS_WIDTH Register */ 40 #define XSDFEC_AXIS_WIDTH_ADDR (0xC) 41 #define XSDFEC_AXIS_DOUT_WORDS_LSB (5) 42 #define XSDFEC_AXIS_DOUT_WIDTH_LSB (3) 43 #define XSDFEC_AXIS_DIN_WORDS_LSB (2) 44 #define XSDFEC_AXIS_DIN_WIDTH_LSB (0) 45 46 /* AXIS_ENABLE Register */ 47 #define XSDFEC_AXIS_ENABLE_ADDR (0x10) 48 #define XSDFEC_AXIS_OUT_ENABLE_MASK (0x38) 49 #define XSDFEC_AXIS_IN_ENABLE_MASK (0x7) 50 #define XSDFEC_AXIS_ENABLE_MASK \ 51 (XSDFEC_AXIS_OUT_ENABLE_MASK | XSDFEC_AXIS_IN_ENABLE_MASK) 52 53 /* FEC_CODE Register */ 54 #define XSDFEC_FEC_CODE_ADDR (0x14) 55 56 /* ORDER Register Map */ 57 #define XSDFEC_ORDER_ADDR (0x18) 58 59 /* Interrupt Status Register */ 60 #define XSDFEC_ISR_ADDR (0x1C) 61 /* Interrupt Status Register Bit Mask */ 62 #define XSDFEC_ISR_MASK (0x3F) 63 64 /* Write Only - Interrupt Enable Register */ 65 #define XSDFEC_IER_ADDR (0x20) 66 /* Write Only - Interrupt Disable Register */ 67 #define XSDFEC_IDR_ADDR (0x24) 68 /* Read Only - Interrupt Mask Register */ 69 #define XSDFEC_IMR_ADDR (0x28) 70 71 /* ECC Interrupt Status Register */ 72 #define XSDFEC_ECC_ISR_ADDR (0x2C) 73 /* Single Bit Errors */ 74 #define XSDFEC_ECC_ISR_SBE_MASK (0x7FF) 75 /* PL Initialize Single Bit Errors */ 76 #define XSDFEC_PL_INIT_ECC_ISR_SBE_MASK (0x3C00000) 77 /* Multi Bit Errors */ 78 #define XSDFEC_ECC_ISR_MBE_MASK (0x3FF800) 79 /* PL Initialize Multi Bit Errors */ 80 #define XSDFEC_PL_INIT_ECC_ISR_MBE_MASK (0x3C000000) 81 /* Multi Bit Error to Event Shift */ 82 #define XSDFEC_ECC_ISR_MBE_TO_EVENT_SHIFT (11) 83 /* PL Initialize Multi Bit Error to Event Shift */ 84 #define XSDFEC_PL_INIT_ECC_ISR_MBE_TO_EVENT_SHIFT (4) 85 /* ECC Interrupt Status Bit Mask */ 86 #define XSDFEC_ECC_ISR_MASK (XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_ECC_ISR_MBE_MASK) 87 /* ECC Interrupt Status PL Initialize Bit Mask */ 88 #define XSDFEC_PL_INIT_ECC_ISR_MASK \ 89 (XSDFEC_PL_INIT_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK) 90 /* ECC Interrupt Status All Bit Mask */ 91 #define XSDFEC_ALL_ECC_ISR_MASK \ 92 (XSDFEC_ECC_ISR_MASK | XSDFEC_PL_INIT_ECC_ISR_MASK) 93 /* ECC Interrupt Status Single Bit Errors Mask */ 94 #define XSDFEC_ALL_ECC_ISR_SBE_MASK \ 95 (XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_SBE_MASK) 96 /* ECC Interrupt Status Multi Bit Errors Mask */ 97 #define XSDFEC_ALL_ECC_ISR_MBE_MASK \ 98 (XSDFEC_ECC_ISR_MBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK) 99 100 /* Write Only - ECC Interrupt Enable Register */ 101 #define XSDFEC_ECC_IER_ADDR (0x30) 102 /* Write Only - ECC Interrupt Disable Register */ 103 #define XSDFEC_ECC_IDR_ADDR (0x34) 104 /* Read Only - ECC Interrupt Mask Register */ 105 #define XSDFEC_ECC_IMR_ADDR (0x38) 106 107 /* BYPASS Register */ 108 #define XSDFEC_BYPASS_ADDR (0x3C) 109 110 /* Turbo Code Register */ 111 #define XSDFEC_TURBO_ADDR (0x100) 112 #define XSDFEC_TURBO_SCALE_MASK (0xFFF) 113 #define XSDFEC_TURBO_SCALE_BIT_POS (8) 114 #define XSDFEC_TURBO_SCALE_MAX (15) 115 116 /* REG0 Register */ 117 #define XSDFEC_LDPC_CODE_REG0_ADDR_BASE (0x2000) 118 #define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH (0x27F0) 119 #define XSDFEC_REG0_N_MIN (4) 120 #define XSDFEC_REG0_N_MAX (32768) 121 #define XSDFEC_REG0_N_MUL_P (256) 122 #define XSDFEC_REG0_N_LSB (0) 123 #define XSDFEC_REG0_K_MIN (2) 124 #define XSDFEC_REG0_K_MAX (32766) 125 #define XSDFEC_REG0_K_MUL_P (256) 126 #define XSDFEC_REG0_K_LSB (16) 127 128 /* REG1 Register */ 129 #define XSDFEC_LDPC_CODE_REG1_ADDR_BASE (0x2004) 130 #define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH (0x27f4) 131 #define XSDFEC_REG1_PSIZE_MIN (2) 132 #define XSDFEC_REG1_PSIZE_MAX (512) 133 #define XSDFEC_REG1_NO_PACKING_MASK (0x400) 134 #define XSDFEC_REG1_NO_PACKING_LSB (10) 135 #define XSDFEC_REG1_NM_MASK (0xFF800) 136 #define XSDFEC_REG1_NM_LSB (11) 137 #define XSDFEC_REG1_BYPASS_MASK (0x100000) 138 139 /* REG2 Register */ 140 #define XSDFEC_LDPC_CODE_REG2_ADDR_BASE (0x2008) 141 #define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH (0x27f8) 142 #define XSDFEC_REG2_NLAYERS_MIN (1) 143 #define XSDFEC_REG2_NLAYERS_MAX (256) 144 #define XSDFEC_REG2_NNMQC_MASK (0xFFE00) 145 #define XSDFEC_REG2_NMQC_LSB (9) 146 #define XSDFEC_REG2_NORM_TYPE_MASK (0x100000) 147 #define XSDFEC_REG2_NORM_TYPE_LSB (20) 148 #define XSDFEC_REG2_SPECIAL_QC_MASK (0x200000) 149 #define XSDFEC_REG2_SPEICAL_QC_LSB (21) 150 #define XSDFEC_REG2_NO_FINAL_PARITY_MASK (0x400000) 151 #define XSDFEC_REG2_NO_FINAL_PARITY_LSB (22) 152 #define XSDFEC_REG2_MAX_SCHEDULE_MASK (0x1800000) 153 #define XSDFEC_REG2_MAX_SCHEDULE_LSB (23) 154 155 /* REG3 Register */ 156 #define XSDFEC_LDPC_CODE_REG3_ADDR_BASE (0x200C) 157 #define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH (0x27FC) 158 #define XSDFEC_REG3_LA_OFF_LSB (8) 159 #define XSDFEC_REG3_QC_OFF_LSB (16) 160 161 #define XSDFEC_LDPC_REG_JUMP (0x10) 162 #define XSDFEC_REG_WIDTH_JUMP (4) 163 164 /* The maximum number of pinned pages */ 165 #define MAX_NUM_PAGES ((XSDFEC_QC_TABLE_DEPTH / PAGE_SIZE) + 1) 166 167 /** 168 * struct xsdfec_clks - For managing SD-FEC clocks 169 * @core_clk: Main processing clock for core 170 * @axi_clk: AXI4-Lite memory-mapped clock 171 * @din_words_clk: DIN Words AXI4-Stream Slave clock 172 * @din_clk: DIN AXI4-Stream Slave clock 173 * @dout_clk: DOUT Words AXI4-Stream Slave clock 174 * @dout_words_clk: DOUT AXI4-Stream Slave clock 175 * @ctrl_clk: Control AXI4-Stream Slave clock 176 * @status_clk: Status AXI4-Stream Slave clock 177 */ 178 struct xsdfec_clks { 179 struct clk *core_clk; 180 struct clk *axi_clk; 181 struct clk *din_words_clk; 182 struct clk *din_clk; 183 struct clk *dout_clk; 184 struct clk *dout_words_clk; 185 struct clk *ctrl_clk; 186 struct clk *status_clk; 187 }; 188 189 /** 190 * struct xsdfec_dev - Driver data for SDFEC 191 * @miscdev: Misc device handle 192 * @clks: Clocks managed by the SDFEC driver 193 * @waitq: Driver wait queue 194 * @config: Configuration of the SDFEC device 195 * @dev_name: Device name 196 * @flags: spinlock flags 197 * @regs: device physical base address 198 * @dev: pointer to device struct 199 * @state: State of the SDFEC device 200 * @error_data_lock: Error counter and states spinlock 201 * @dev_id: Device ID 202 * @isr_err_count: Count of ISR errors 203 * @cecc_count: Count of Correctable ECC errors (SBE) 204 * @uecc_count: Count of Uncorrectable ECC errors (MBE) 205 * @irq: IRQ number 206 * @state_updated: indicates State updated by interrupt handler 207 * @stats_updated: indicates Stats updated by interrupt handler 208 * @intr_enabled: indicates IRQ enabled 209 * 210 * This structure contains necessary state for SDFEC driver to operate 211 */ 212 struct xsdfec_dev { 213 struct miscdevice miscdev; 214 struct xsdfec_clks clks; 215 wait_queue_head_t waitq; 216 struct xsdfec_config config; 217 char dev_name[DEV_NAME_LEN]; 218 unsigned long flags; 219 void __iomem *regs; 220 struct device *dev; 221 enum xsdfec_state state; 222 /* Spinlock to protect state_updated and stats_updated */ 223 spinlock_t error_data_lock; 224 int dev_id; 225 u32 isr_err_count; 226 u32 cecc_count; 227 u32 uecc_count; 228 int irq; 229 bool state_updated; 230 bool stats_updated; 231 bool intr_enabled; 232 }; 233 234 static inline void xsdfec_regwrite(struct xsdfec_dev *xsdfec, u32 addr, 235 u32 value) 236 { 237 dev_dbg(xsdfec->dev, "Writing 0x%x to offset 0x%x", value, addr); 238 iowrite32(value, xsdfec->regs + addr); 239 } 240 241 static inline u32 xsdfec_regread(struct xsdfec_dev *xsdfec, u32 addr) 242 { 243 u32 rval; 244 245 rval = ioread32(xsdfec->regs + addr); 246 dev_dbg(xsdfec->dev, "Read value = 0x%x from offset 0x%x", rval, addr); 247 return rval; 248 } 249 250 static void update_bool_config_from_reg(struct xsdfec_dev *xsdfec, 251 u32 reg_offset, u32 bit_num, 252 char *config_value) 253 { 254 u32 reg_val; 255 u32 bit_mask = 1 << bit_num; 256 257 reg_val = xsdfec_regread(xsdfec, reg_offset); 258 *config_value = (reg_val & bit_mask) > 0; 259 } 260 261 static void update_config_from_hw(struct xsdfec_dev *xsdfec) 262 { 263 u32 reg_value; 264 bool sdfec_started; 265 266 /* Update the Order */ 267 reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR); 268 xsdfec->config.order = reg_value; 269 270 update_bool_config_from_reg(xsdfec, XSDFEC_BYPASS_ADDR, 271 0, /* Bit Number, maybe change to mask */ 272 &xsdfec->config.bypass); 273 274 update_bool_config_from_reg(xsdfec, XSDFEC_CODE_WR_PROTECT_ADDR, 275 0, /* Bit Number */ 276 &xsdfec->config.code_wr_protect); 277 278 reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); 279 xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0; 280 281 reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); 282 xsdfec->config.irq.enable_ecc_isr = 283 (reg_value & XSDFEC_ECC_ISR_MASK) > 0; 284 285 reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR); 286 sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0; 287 if (sdfec_started) 288 xsdfec->state = XSDFEC_STARTED; 289 else 290 xsdfec->state = XSDFEC_STOPPED; 291 } 292 293 static int xsdfec_get_status(struct xsdfec_dev *xsdfec, void __user *arg) 294 { 295 struct xsdfec_status status; 296 int err; 297 298 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 299 status.state = xsdfec->state; 300 xsdfec->state_updated = false; 301 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 302 status.activity = (xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR) & 303 XSDFEC_IS_ACTIVITY_SET); 304 305 err = copy_to_user(arg, &status, sizeof(status)); 306 if (err) 307 err = -EFAULT; 308 309 return err; 310 } 311 312 static int xsdfec_get_config(struct xsdfec_dev *xsdfec, void __user *arg) 313 { 314 int err; 315 316 err = copy_to_user(arg, &xsdfec->config, sizeof(xsdfec->config)); 317 if (err) 318 err = -EFAULT; 319 320 return err; 321 } 322 323 static int xsdfec_isr_enable(struct xsdfec_dev *xsdfec, bool enable) 324 { 325 u32 mask_read; 326 327 if (enable) { 328 /* Enable */ 329 xsdfec_regwrite(xsdfec, XSDFEC_IER_ADDR, XSDFEC_ISR_MASK); 330 mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); 331 if (mask_read & XSDFEC_ISR_MASK) { 332 dev_dbg(xsdfec->dev, 333 "SDFEC enabling irq with IER failed"); 334 return -EIO; 335 } 336 } else { 337 /* Disable */ 338 xsdfec_regwrite(xsdfec, XSDFEC_IDR_ADDR, XSDFEC_ISR_MASK); 339 mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); 340 if ((mask_read & XSDFEC_ISR_MASK) != XSDFEC_ISR_MASK) { 341 dev_dbg(xsdfec->dev, 342 "SDFEC disabling irq with IDR failed"); 343 return -EIO; 344 } 345 } 346 return 0; 347 } 348 349 static int xsdfec_ecc_isr_enable(struct xsdfec_dev *xsdfec, bool enable) 350 { 351 u32 mask_read; 352 353 if (enable) { 354 /* Enable */ 355 xsdfec_regwrite(xsdfec, XSDFEC_ECC_IER_ADDR, 356 XSDFEC_ALL_ECC_ISR_MASK); 357 mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); 358 if (mask_read & XSDFEC_ALL_ECC_ISR_MASK) { 359 dev_dbg(xsdfec->dev, 360 "SDFEC enabling ECC irq with ECC IER failed"); 361 return -EIO; 362 } 363 } else { 364 /* Disable */ 365 xsdfec_regwrite(xsdfec, XSDFEC_ECC_IDR_ADDR, 366 XSDFEC_ALL_ECC_ISR_MASK); 367 mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); 368 if (!(((mask_read & XSDFEC_ALL_ECC_ISR_MASK) == 369 XSDFEC_ECC_ISR_MASK) || 370 ((mask_read & XSDFEC_ALL_ECC_ISR_MASK) == 371 XSDFEC_PL_INIT_ECC_ISR_MASK))) { 372 dev_dbg(xsdfec->dev, 373 "SDFEC disable ECC irq with ECC IDR failed"); 374 return -EIO; 375 } 376 } 377 return 0; 378 } 379 380 static int xsdfec_set_irq(struct xsdfec_dev *xsdfec, void __user *arg) 381 { 382 struct xsdfec_irq irq; 383 int err; 384 int isr_err; 385 int ecc_err; 386 387 err = copy_from_user(&irq, arg, sizeof(irq)); 388 if (err) 389 return -EFAULT; 390 391 /* Setup tlast related IRQ */ 392 isr_err = xsdfec_isr_enable(xsdfec, irq.enable_isr); 393 if (!isr_err) 394 xsdfec->config.irq.enable_isr = irq.enable_isr; 395 396 /* Setup ECC related IRQ */ 397 ecc_err = xsdfec_ecc_isr_enable(xsdfec, irq.enable_ecc_isr); 398 if (!ecc_err) 399 xsdfec->config.irq.enable_ecc_isr = irq.enable_ecc_isr; 400 401 if (isr_err < 0 || ecc_err < 0) 402 err = -EIO; 403 404 return err; 405 } 406 407 static int xsdfec_set_turbo(struct xsdfec_dev *xsdfec, void __user *arg) 408 { 409 struct xsdfec_turbo turbo; 410 int err; 411 u32 turbo_write; 412 413 err = copy_from_user(&turbo, arg, sizeof(turbo)); 414 if (err) 415 return -EFAULT; 416 417 if (turbo.alg >= XSDFEC_TURBO_ALG_MAX) 418 return -EINVAL; 419 420 if (turbo.scale > XSDFEC_TURBO_SCALE_MAX) 421 return -EINVAL; 422 423 /* Check to see what device tree says about the FEC codes */ 424 if (xsdfec->config.code == XSDFEC_LDPC_CODE) 425 return -EIO; 426 427 turbo_write = ((turbo.scale & XSDFEC_TURBO_SCALE_MASK) 428 << XSDFEC_TURBO_SCALE_BIT_POS) | 429 turbo.alg; 430 xsdfec_regwrite(xsdfec, XSDFEC_TURBO_ADDR, turbo_write); 431 return err; 432 } 433 434 static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg) 435 { 436 u32 reg_value; 437 struct xsdfec_turbo turbo_params; 438 int err; 439 440 if (xsdfec->config.code == XSDFEC_LDPC_CODE) 441 return -EIO; 442 443 reg_value = xsdfec_regread(xsdfec, XSDFEC_TURBO_ADDR); 444 445 turbo_params.scale = (reg_value & XSDFEC_TURBO_SCALE_MASK) >> 446 XSDFEC_TURBO_SCALE_BIT_POS; 447 turbo_params.alg = reg_value & 0x1; 448 449 err = copy_to_user(arg, &turbo_params, sizeof(turbo_params)); 450 if (err) 451 err = -EFAULT; 452 453 return err; 454 } 455 456 static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize, 457 u32 offset) 458 { 459 u32 wdata; 460 461 if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX || 462 (n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) { 463 dev_dbg(xsdfec->dev, "N value is not in range"); 464 return -EINVAL; 465 } 466 n <<= XSDFEC_REG0_N_LSB; 467 468 if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX || 469 (k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) { 470 dev_dbg(xsdfec->dev, "K value is not in range"); 471 return -EINVAL; 472 } 473 k = k << XSDFEC_REG0_K_LSB; 474 wdata = k | n; 475 476 if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 477 XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) { 478 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg0 space 0x%x", 479 XSDFEC_LDPC_CODE_REG0_ADDR_BASE + 480 (offset * XSDFEC_LDPC_REG_JUMP)); 481 return -EINVAL; 482 } 483 xsdfec_regwrite(xsdfec, 484 XSDFEC_LDPC_CODE_REG0_ADDR_BASE + 485 (offset * XSDFEC_LDPC_REG_JUMP), 486 wdata); 487 return 0; 488 } 489 490 static int xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize, 491 u32 no_packing, u32 nm, u32 offset) 492 { 493 u32 wdata; 494 495 if (psize < XSDFEC_REG1_PSIZE_MIN || psize > XSDFEC_REG1_PSIZE_MAX) { 496 dev_dbg(xsdfec->dev, "Psize is not in range"); 497 return -EINVAL; 498 } 499 500 if (no_packing != 0 && no_packing != 1) 501 dev_dbg(xsdfec->dev, "No-packing bit register invalid"); 502 no_packing = ((no_packing << XSDFEC_REG1_NO_PACKING_LSB) & 503 XSDFEC_REG1_NO_PACKING_MASK); 504 505 if (nm & ~(XSDFEC_REG1_NM_MASK >> XSDFEC_REG1_NM_LSB)) 506 dev_dbg(xsdfec->dev, "NM is beyond 10 bits"); 507 nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK; 508 509 wdata = nm | no_packing | psize; 510 if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 511 XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) { 512 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg1 space 0x%x", 513 XSDFEC_LDPC_CODE_REG1_ADDR_BASE + 514 (offset * XSDFEC_LDPC_REG_JUMP)); 515 return -EINVAL; 516 } 517 xsdfec_regwrite(xsdfec, 518 XSDFEC_LDPC_CODE_REG1_ADDR_BASE + 519 (offset * XSDFEC_LDPC_REG_JUMP), 520 wdata); 521 return 0; 522 } 523 524 static int xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc, 525 u32 norm_type, u32 special_qc, u32 no_final_parity, 526 u32 max_schedule, u32 offset) 527 { 528 u32 wdata; 529 530 if (nlayers < XSDFEC_REG2_NLAYERS_MIN || 531 nlayers > XSDFEC_REG2_NLAYERS_MAX) { 532 dev_dbg(xsdfec->dev, "Nlayers is not in range"); 533 return -EINVAL; 534 } 535 536 if (nmqc & ~(XSDFEC_REG2_NNMQC_MASK >> XSDFEC_REG2_NMQC_LSB)) 537 dev_dbg(xsdfec->dev, "NMQC exceeds 11 bits"); 538 nmqc = (nmqc << XSDFEC_REG2_NMQC_LSB) & XSDFEC_REG2_NNMQC_MASK; 539 540 if (norm_type > 1) 541 dev_dbg(xsdfec->dev, "Norm type is invalid"); 542 norm_type = ((norm_type << XSDFEC_REG2_NORM_TYPE_LSB) & 543 XSDFEC_REG2_NORM_TYPE_MASK); 544 if (special_qc > 1) 545 dev_dbg(xsdfec->dev, "Special QC in invalid"); 546 special_qc = ((special_qc << XSDFEC_REG2_SPEICAL_QC_LSB) & 547 XSDFEC_REG2_SPECIAL_QC_MASK); 548 549 if (no_final_parity > 1) 550 dev_dbg(xsdfec->dev, "No final parity check invalid"); 551 no_final_parity = 552 ((no_final_parity << XSDFEC_REG2_NO_FINAL_PARITY_LSB) & 553 XSDFEC_REG2_NO_FINAL_PARITY_MASK); 554 if (max_schedule & 555 ~(XSDFEC_REG2_MAX_SCHEDULE_MASK >> XSDFEC_REG2_MAX_SCHEDULE_LSB)) 556 dev_dbg(xsdfec->dev, "Max Schdule exceeds 2 bits"); 557 max_schedule = ((max_schedule << XSDFEC_REG2_MAX_SCHEDULE_LSB) & 558 XSDFEC_REG2_MAX_SCHEDULE_MASK); 559 560 wdata = (max_schedule | no_final_parity | special_qc | norm_type | 561 nmqc | nlayers); 562 563 if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 564 XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) { 565 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg2 space 0x%x", 566 XSDFEC_LDPC_CODE_REG2_ADDR_BASE + 567 (offset * XSDFEC_LDPC_REG_JUMP)); 568 return -EINVAL; 569 } 570 xsdfec_regwrite(xsdfec, 571 XSDFEC_LDPC_CODE_REG2_ADDR_BASE + 572 (offset * XSDFEC_LDPC_REG_JUMP), 573 wdata); 574 return 0; 575 } 576 577 static int xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off, u8 la_off, 578 u16 qc_off, u32 offset) 579 { 580 u32 wdata; 581 582 wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) | 583 (la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off); 584 if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 585 XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) { 586 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg3 space 0x%x", 587 XSDFEC_LDPC_CODE_REG3_ADDR_BASE + 588 (offset * XSDFEC_LDPC_REG_JUMP)); 589 return -EINVAL; 590 } 591 xsdfec_regwrite(xsdfec, 592 XSDFEC_LDPC_CODE_REG3_ADDR_BASE + 593 (offset * XSDFEC_LDPC_REG_JUMP), 594 wdata); 595 return 0; 596 } 597 598 static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, 599 u32 *src_ptr, u32 len, const u32 base_addr, 600 const u32 depth) 601 { 602 u32 reg = 0; 603 u32 res; 604 u32 n, i; 605 u32 *addr = NULL; 606 struct page *page[MAX_NUM_PAGES]; 607 608 /* 609 * Writes that go beyond the length of 610 * Shared Scale(SC) table should fail 611 */ 612 if ((XSDFEC_REG_WIDTH_JUMP * (offset + len)) > depth) { 613 dev_dbg(xsdfec->dev, "Write exceeds SC table length"); 614 return -EINVAL; 615 } 616 617 n = (len * XSDFEC_REG_WIDTH_JUMP) / PAGE_SIZE; 618 if ((len * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE) 619 n += 1; 620 621 res = get_user_pages_fast((unsigned long)src_ptr, n, 0, page); 622 if (res < n) { 623 for (i = 0; i < res; i++) 624 put_page(page[i]); 625 return -EINVAL; 626 } 627 628 for (i = 0; i < n; i++) { 629 addr = kmap(page[i]); 630 do { 631 xsdfec_regwrite(xsdfec, 632 base_addr + ((offset + reg) * 633 XSDFEC_REG_WIDTH_JUMP), 634 addr[reg]); 635 reg++; 636 } while ((reg < len) && 637 ((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)); 638 put_page(page[i]); 639 } 640 return reg; 641 } 642 643 static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) 644 { 645 struct xsdfec_ldpc_params *ldpc; 646 int ret, n; 647 648 ldpc = kzalloc(sizeof(*ldpc), GFP_KERNEL); 649 if (!ldpc) 650 return -ENOMEM; 651 652 ret = copy_from_user(ldpc, arg, sizeof(*ldpc)); 653 if (ret) 654 goto err_out; 655 656 if (xsdfec->config.code == XSDFEC_TURBO_CODE) { 657 ret = -EIO; 658 goto err_out; 659 } 660 661 /* Verify Device has not started */ 662 if (xsdfec->state == XSDFEC_STARTED) { 663 ret = -EIO; 664 goto err_out; 665 } 666 667 if (xsdfec->config.code_wr_protect) { 668 ret = -EIO; 669 goto err_out; 670 } 671 672 /* Write Reg 0 */ 673 ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize, 674 ldpc->code_id); 675 if (ret) 676 goto err_out; 677 678 /* Write Reg 1 */ 679 ret = xsdfec_reg1_write(xsdfec, ldpc->psize, ldpc->no_packing, ldpc->nm, 680 ldpc->code_id); 681 if (ret) 682 goto err_out; 683 684 /* Write Reg 2 */ 685 ret = xsdfec_reg2_write(xsdfec, ldpc->nlayers, ldpc->nmqc, 686 ldpc->norm_type, ldpc->special_qc, 687 ldpc->no_final_parity, ldpc->max_schedule, 688 ldpc->code_id); 689 if (ret) 690 goto err_out; 691 692 /* Write Reg 3 */ 693 ret = xsdfec_reg3_write(xsdfec, ldpc->sc_off, ldpc->la_off, 694 ldpc->qc_off, ldpc->code_id); 695 if (ret) 696 goto err_out; 697 698 /* Write Shared Codes */ 699 n = ldpc->nlayers / 4; 700 if (ldpc->nlayers % 4) 701 n++; 702 703 ret = xsdfec_table_write(xsdfec, ldpc->sc_off, ldpc->sc_table, n, 704 XSDFEC_LDPC_SC_TABLE_ADDR_BASE, 705 XSDFEC_SC_TABLE_DEPTH); 706 if (ret < 0) 707 goto err_out; 708 709 ret = xsdfec_table_write(xsdfec, 4 * ldpc->la_off, ldpc->la_table, 710 ldpc->nlayers, XSDFEC_LDPC_LA_TABLE_ADDR_BASE, 711 XSDFEC_LA_TABLE_DEPTH); 712 if (ret < 0) 713 goto err_out; 714 715 ret = xsdfec_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table, 716 ldpc->nqc, XSDFEC_LDPC_QC_TABLE_ADDR_BASE, 717 XSDFEC_QC_TABLE_DEPTH); 718 if (ret > 0) 719 ret = 0; 720 err_out: 721 kfree(ldpc); 722 return ret; 723 } 724 725 static int xsdfec_set_order(struct xsdfec_dev *xsdfec, void __user *arg) 726 { 727 bool order_invalid; 728 enum xsdfec_order order; 729 int err; 730 731 err = get_user(order, (enum xsdfec_order *)arg); 732 if (err) 733 return -EFAULT; 734 735 order_invalid = (order != XSDFEC_MAINTAIN_ORDER) && 736 (order != XSDFEC_OUT_OF_ORDER); 737 if (order_invalid) 738 return -EINVAL; 739 740 /* Verify Device has not started */ 741 if (xsdfec->state == XSDFEC_STARTED) 742 return -EIO; 743 744 xsdfec_regwrite(xsdfec, XSDFEC_ORDER_ADDR, order); 745 746 xsdfec->config.order = order; 747 748 return 0; 749 } 750 751 static int xsdfec_set_bypass(struct xsdfec_dev *xsdfec, bool __user *arg) 752 { 753 bool bypass; 754 int err; 755 756 err = get_user(bypass, arg); 757 if (err) 758 return -EFAULT; 759 760 /* Verify Device has not started */ 761 if (xsdfec->state == XSDFEC_STARTED) 762 return -EIO; 763 764 if (bypass) 765 xsdfec_regwrite(xsdfec, XSDFEC_BYPASS_ADDR, 1); 766 else 767 xsdfec_regwrite(xsdfec, XSDFEC_BYPASS_ADDR, 0); 768 769 xsdfec->config.bypass = bypass; 770 771 return 0; 772 } 773 774 static int xsdfec_is_active(struct xsdfec_dev *xsdfec, bool __user *arg) 775 { 776 u32 reg_value; 777 bool is_active; 778 int err; 779 780 reg_value = xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR); 781 /* using a double ! operator instead of casting */ 782 is_active = !!(reg_value & XSDFEC_IS_ACTIVITY_SET); 783 err = put_user(is_active, arg); 784 if (err) 785 return -EFAULT; 786 787 return err; 788 } 789 790 static u32 791 xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg) 792 { 793 u32 axis_width_field = 0; 794 795 switch (axis_width_cfg) { 796 case XSDFEC_1x128b: 797 axis_width_field = 0; 798 break; 799 case XSDFEC_2x128b: 800 axis_width_field = 1; 801 break; 802 case XSDFEC_4x128b: 803 axis_width_field = 2; 804 break; 805 } 806 807 return axis_width_field; 808 } 809 810 static u32 xsdfec_translate_axis_words_cfg_val(enum xsdfec_axis_word_include 811 axis_word_inc_cfg) 812 { 813 u32 axis_words_field = 0; 814 815 if (axis_word_inc_cfg == XSDFEC_FIXED_VALUE || 816 axis_word_inc_cfg == XSDFEC_IN_BLOCK) 817 axis_words_field = 0; 818 else if (axis_word_inc_cfg == XSDFEC_PER_AXI_TRANSACTION) 819 axis_words_field = 1; 820 821 return axis_words_field; 822 } 823 824 static int xsdfec_cfg_axi_streams(struct xsdfec_dev *xsdfec) 825 { 826 u32 reg_value; 827 u32 dout_words_field; 828 u32 dout_width_field; 829 u32 din_words_field; 830 u32 din_width_field; 831 struct xsdfec_config *config = &xsdfec->config; 832 833 /* translate config info to register values */ 834 dout_words_field = 835 xsdfec_translate_axis_words_cfg_val(config->dout_word_include); 836 dout_width_field = 837 xsdfec_translate_axis_width_cfg_val(config->dout_width); 838 din_words_field = 839 xsdfec_translate_axis_words_cfg_val(config->din_word_include); 840 din_width_field = 841 xsdfec_translate_axis_width_cfg_val(config->din_width); 842 843 reg_value = dout_words_field << XSDFEC_AXIS_DOUT_WORDS_LSB; 844 reg_value |= dout_width_field << XSDFEC_AXIS_DOUT_WIDTH_LSB; 845 reg_value |= din_words_field << XSDFEC_AXIS_DIN_WORDS_LSB; 846 reg_value |= din_width_field << XSDFEC_AXIS_DIN_WIDTH_LSB; 847 848 xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, reg_value); 849 850 return 0; 851 } 852 853 static int xsdfec_dev_open(struct inode *iptr, struct file *fptr) 854 { 855 return 0; 856 } 857 858 static int xsdfec_dev_release(struct inode *iptr, struct file *fptr) 859 { 860 return 0; 861 } 862 863 static int xsdfec_start(struct xsdfec_dev *xsdfec) 864 { 865 u32 regread; 866 867 regread = xsdfec_regread(xsdfec, XSDFEC_FEC_CODE_ADDR); 868 regread &= 0x1; 869 if (regread != xsdfec->config.code) { 870 dev_dbg(xsdfec->dev, 871 "%s SDFEC HW code does not match driver code, reg %d, code %d", 872 __func__, regread, xsdfec->config.code); 873 return -EINVAL; 874 } 875 876 /* Set AXIS enable */ 877 xsdfec_regwrite(xsdfec, XSDFEC_AXIS_ENABLE_ADDR, 878 XSDFEC_AXIS_ENABLE_MASK); 879 /* Done */ 880 xsdfec->state = XSDFEC_STARTED; 881 return 0; 882 } 883 884 static int xsdfec_stop(struct xsdfec_dev *xsdfec) 885 { 886 u32 regread; 887 888 if (xsdfec->state != XSDFEC_STARTED) 889 dev_dbg(xsdfec->dev, "Device not started correctly"); 890 /* Disable AXIS_ENABLE Input interfaces only */ 891 regread = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR); 892 regread &= (~XSDFEC_AXIS_IN_ENABLE_MASK); 893 xsdfec_regwrite(xsdfec, XSDFEC_AXIS_ENABLE_ADDR, regread); 894 /* Stop */ 895 xsdfec->state = XSDFEC_STOPPED; 896 return 0; 897 } 898 899 static int xsdfec_clear_stats(struct xsdfec_dev *xsdfec) 900 { 901 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 902 xsdfec->isr_err_count = 0; 903 xsdfec->uecc_count = 0; 904 xsdfec->cecc_count = 0; 905 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 906 907 return 0; 908 } 909 910 static int xsdfec_get_stats(struct xsdfec_dev *xsdfec, void __user *arg) 911 { 912 int err; 913 struct xsdfec_stats user_stats; 914 915 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 916 user_stats.isr_err_count = xsdfec->isr_err_count; 917 user_stats.cecc_count = xsdfec->cecc_count; 918 user_stats.uecc_count = xsdfec->uecc_count; 919 xsdfec->stats_updated = false; 920 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 921 922 err = copy_to_user(arg, &user_stats, sizeof(user_stats)); 923 if (err) 924 err = -EFAULT; 925 926 return err; 927 } 928 929 static int xsdfec_set_default_config(struct xsdfec_dev *xsdfec) 930 { 931 /* Ensure registers are aligned with core configuration */ 932 xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, xsdfec->config.code); 933 xsdfec_cfg_axi_streams(xsdfec); 934 update_config_from_hw(xsdfec); 935 936 return 0; 937 } 938 939 static long xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd, 940 unsigned long data) 941 { 942 struct xsdfec_dev *xsdfec; 943 void __user *arg = NULL; 944 int rval = -EINVAL; 945 946 xsdfec = container_of(fptr->private_data, struct xsdfec_dev, miscdev); 947 948 /* In failed state allow only reset and get status IOCTLs */ 949 if (xsdfec->state == XSDFEC_NEEDS_RESET && 950 (cmd != XSDFEC_SET_DEFAULT_CONFIG && cmd != XSDFEC_GET_STATUS && 951 cmd != XSDFEC_GET_STATS && cmd != XSDFEC_CLEAR_STATS)) { 952 return -EPERM; 953 } 954 955 if (_IOC_TYPE(cmd) != XSDFEC_MAGIC) 956 return -ENOTTY; 957 958 /* check if ioctl argument is present and valid */ 959 if (_IOC_DIR(cmd) != _IOC_NONE) { 960 arg = (void __user *)data; 961 if (!arg) 962 return rval; 963 } 964 965 switch (cmd) { 966 case XSDFEC_START_DEV: 967 rval = xsdfec_start(xsdfec); 968 break; 969 case XSDFEC_STOP_DEV: 970 rval = xsdfec_stop(xsdfec); 971 break; 972 case XSDFEC_CLEAR_STATS: 973 rval = xsdfec_clear_stats(xsdfec); 974 break; 975 case XSDFEC_GET_STATS: 976 rval = xsdfec_get_stats(xsdfec, arg); 977 break; 978 case XSDFEC_GET_STATUS: 979 rval = xsdfec_get_status(xsdfec, arg); 980 break; 981 case XSDFEC_GET_CONFIG: 982 rval = xsdfec_get_config(xsdfec, arg); 983 break; 984 case XSDFEC_SET_DEFAULT_CONFIG: 985 rval = xsdfec_set_default_config(xsdfec); 986 break; 987 case XSDFEC_SET_IRQ: 988 rval = xsdfec_set_irq(xsdfec, arg); 989 break; 990 case XSDFEC_SET_TURBO: 991 rval = xsdfec_set_turbo(xsdfec, arg); 992 break; 993 case XSDFEC_GET_TURBO: 994 rval = xsdfec_get_turbo(xsdfec, arg); 995 break; 996 case XSDFEC_ADD_LDPC_CODE_PARAMS: 997 rval = xsdfec_add_ldpc(xsdfec, arg); 998 break; 999 case XSDFEC_SET_ORDER: 1000 rval = xsdfec_set_order(xsdfec, arg); 1001 break; 1002 case XSDFEC_SET_BYPASS: 1003 rval = xsdfec_set_bypass(xsdfec, arg); 1004 break; 1005 case XSDFEC_IS_ACTIVE: 1006 rval = xsdfec_is_active(xsdfec, (bool __user *)arg); 1007 break; 1008 default: 1009 /* Should not get here */ 1010 break; 1011 } 1012 return rval; 1013 } 1014 1015 #ifdef CONFIG_COMPAT 1016 static long xsdfec_dev_compat_ioctl(struct file *file, unsigned int cmd, 1017 unsigned long data) 1018 { 1019 return xsdfec_dev_ioctl(file, cmd, (unsigned long)compat_ptr(data)); 1020 } 1021 #endif 1022 1023 static unsigned int xsdfec_poll(struct file *file, poll_table *wait) 1024 { 1025 unsigned int mask = 0; 1026 struct xsdfec_dev *xsdfec; 1027 1028 xsdfec = container_of(file->private_data, struct xsdfec_dev, miscdev); 1029 1030 if (!xsdfec) 1031 return POLLNVAL | POLLHUP; 1032 1033 poll_wait(file, &xsdfec->waitq, wait); 1034 1035 /* XSDFEC ISR detected an error */ 1036 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 1037 if (xsdfec->state_updated) 1038 mask |= POLLIN | POLLPRI; 1039 1040 if (xsdfec->stats_updated) 1041 mask |= POLLIN | POLLRDNORM; 1042 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 1043 1044 return mask; 1045 } 1046 1047 static const struct file_operations xsdfec_fops = { 1048 .owner = THIS_MODULE, 1049 .open = xsdfec_dev_open, 1050 .release = xsdfec_dev_release, 1051 .unlocked_ioctl = xsdfec_dev_ioctl, 1052 .poll = xsdfec_poll, 1053 #ifdef CONFIG_COMPAT 1054 .compat_ioctl = xsdfec_dev_compat_ioctl, 1055 #endif 1056 }; 1057 1058 static int xsdfec_parse_of(struct xsdfec_dev *xsdfec) 1059 { 1060 struct device *dev = xsdfec->dev; 1061 struct device_node *node = dev->of_node; 1062 int rval; 1063 const char *fec_code; 1064 u32 din_width; 1065 u32 din_word_include; 1066 u32 dout_width; 1067 u32 dout_word_include; 1068 1069 rval = of_property_read_string(node, "xlnx,sdfec-code", &fec_code); 1070 if (rval < 0) 1071 return rval; 1072 1073 if (!strcasecmp(fec_code, "ldpc")) 1074 xsdfec->config.code = XSDFEC_LDPC_CODE; 1075 else if (!strcasecmp(fec_code, "turbo")) 1076 xsdfec->config.code = XSDFEC_TURBO_CODE; 1077 else 1078 return -EINVAL; 1079 1080 rval = of_property_read_u32(node, "xlnx,sdfec-din-words", 1081 &din_word_include); 1082 if (rval < 0) 1083 return rval; 1084 1085 if (din_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX) 1086 xsdfec->config.din_word_include = din_word_include; 1087 else 1088 return -EINVAL; 1089 1090 rval = of_property_read_u32(node, "xlnx,sdfec-din-width", &din_width); 1091 if (rval < 0) 1092 return rval; 1093 1094 switch (din_width) { 1095 /* Fall through and set for valid values */ 1096 case XSDFEC_1x128b: 1097 case XSDFEC_2x128b: 1098 case XSDFEC_4x128b: 1099 xsdfec->config.din_width = din_width; 1100 break; 1101 default: 1102 return -EINVAL; 1103 } 1104 1105 rval = of_property_read_u32(node, "xlnx,sdfec-dout-words", 1106 &dout_word_include); 1107 if (rval < 0) 1108 return rval; 1109 1110 if (dout_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX) 1111 xsdfec->config.dout_word_include = dout_word_include; 1112 else 1113 return -EINVAL; 1114 1115 rval = of_property_read_u32(node, "xlnx,sdfec-dout-width", &dout_width); 1116 if (rval < 0) 1117 return rval; 1118 1119 switch (dout_width) { 1120 /* Fall through and set for valid values */ 1121 case XSDFEC_1x128b: 1122 case XSDFEC_2x128b: 1123 case XSDFEC_4x128b: 1124 xsdfec->config.dout_width = dout_width; 1125 break; 1126 default: 1127 return -EINVAL; 1128 } 1129 1130 /* Write LDPC to CODE Register */ 1131 xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, xsdfec->config.code); 1132 1133 xsdfec_cfg_axi_streams(xsdfec); 1134 1135 return 0; 1136 } 1137 1138 static irqreturn_t xsdfec_irq_thread(int irq, void *dev_id) 1139 { 1140 struct xsdfec_dev *xsdfec = dev_id; 1141 irqreturn_t ret = IRQ_HANDLED; 1142 u32 ecc_err; 1143 u32 isr_err; 1144 u32 uecc_count; 1145 u32 cecc_count; 1146 u32 isr_err_count; 1147 u32 aecc_count; 1148 u32 tmp; 1149 1150 WARN_ON(xsdfec->irq != irq); 1151 1152 /* Mask Interrupts */ 1153 xsdfec_isr_enable(xsdfec, false); 1154 xsdfec_ecc_isr_enable(xsdfec, false); 1155 /* Read ISR */ 1156 ecc_err = xsdfec_regread(xsdfec, XSDFEC_ECC_ISR_ADDR); 1157 isr_err = xsdfec_regread(xsdfec, XSDFEC_ISR_ADDR); 1158 /* Clear the interrupts */ 1159 xsdfec_regwrite(xsdfec, XSDFEC_ECC_ISR_ADDR, ecc_err); 1160 xsdfec_regwrite(xsdfec, XSDFEC_ISR_ADDR, isr_err); 1161 1162 tmp = ecc_err & XSDFEC_ALL_ECC_ISR_MBE_MASK; 1163 /* Count uncorrectable 2-bit errors */ 1164 uecc_count = hweight32(tmp); 1165 /* Count all ECC errors */ 1166 aecc_count = hweight32(ecc_err); 1167 /* Number of correctable 1-bit ECC error */ 1168 cecc_count = aecc_count - 2 * uecc_count; 1169 /* Count ISR errors */ 1170 isr_err_count = hweight32(isr_err); 1171 dev_dbg(xsdfec->dev, "tmp=%x, uecc=%x, aecc=%x, cecc=%x, isr=%x", tmp, 1172 uecc_count, aecc_count, cecc_count, isr_err_count); 1173 dev_dbg(xsdfec->dev, "uecc=%x, cecc=%x, isr=%x", xsdfec->uecc_count, 1174 xsdfec->cecc_count, xsdfec->isr_err_count); 1175 1176 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 1177 /* Add new errors to a 2-bits counter */ 1178 if (uecc_count) 1179 xsdfec->uecc_count += uecc_count; 1180 /* Add new errors to a 1-bits counter */ 1181 if (cecc_count) 1182 xsdfec->cecc_count += cecc_count; 1183 /* Add new errors to a ISR counter */ 1184 if (isr_err_count) 1185 xsdfec->isr_err_count += isr_err_count; 1186 1187 /* Update state/stats flag */ 1188 if (uecc_count) { 1189 if (ecc_err & XSDFEC_ECC_ISR_MBE_MASK) 1190 xsdfec->state = XSDFEC_NEEDS_RESET; 1191 else if (ecc_err & XSDFEC_PL_INIT_ECC_ISR_MBE_MASK) 1192 xsdfec->state = XSDFEC_PL_RECONFIGURE; 1193 xsdfec->stats_updated = true; 1194 xsdfec->state_updated = true; 1195 } 1196 1197 if (cecc_count) 1198 xsdfec->stats_updated = true; 1199 1200 if (isr_err_count) { 1201 xsdfec->state = XSDFEC_NEEDS_RESET; 1202 xsdfec->stats_updated = true; 1203 xsdfec->state_updated = true; 1204 } 1205 1206 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 1207 dev_dbg(xsdfec->dev, "state=%x, stats=%x", xsdfec->state_updated, 1208 xsdfec->stats_updated); 1209 1210 /* Enable another polling */ 1211 if (xsdfec->state_updated || xsdfec->stats_updated) 1212 wake_up_interruptible(&xsdfec->waitq); 1213 else 1214 ret = IRQ_NONE; 1215 1216 /* Unmask Interrupts */ 1217 xsdfec_isr_enable(xsdfec, true); 1218 xsdfec_ecc_isr_enable(xsdfec, true); 1219 1220 return ret; 1221 } 1222 1223 static int xsdfec_clk_init(struct platform_device *pdev, 1224 struct xsdfec_clks *clks) 1225 { 1226 int err; 1227 1228 clks->core_clk = devm_clk_get(&pdev->dev, "core_clk"); 1229 if (IS_ERR(clks->core_clk)) { 1230 dev_err(&pdev->dev, "failed to get core_clk"); 1231 return PTR_ERR(clks->core_clk); 1232 } 1233 1234 clks->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 1235 if (IS_ERR(clks->axi_clk)) { 1236 dev_err(&pdev->dev, "failed to get axi_clk"); 1237 return PTR_ERR(clks->axi_clk); 1238 } 1239 1240 clks->din_words_clk = devm_clk_get(&pdev->dev, "s_axis_din_words_aclk"); 1241 if (IS_ERR(clks->din_words_clk)) { 1242 if (PTR_ERR(clks->din_words_clk) != -ENOENT) { 1243 err = PTR_ERR(clks->din_words_clk); 1244 return err; 1245 } 1246 clks->din_words_clk = NULL; 1247 } 1248 1249 clks->din_clk = devm_clk_get(&pdev->dev, "s_axis_din_aclk"); 1250 if (IS_ERR(clks->din_clk)) { 1251 if (PTR_ERR(clks->din_clk) != -ENOENT) { 1252 err = PTR_ERR(clks->din_clk); 1253 return err; 1254 } 1255 clks->din_clk = NULL; 1256 } 1257 1258 clks->dout_clk = devm_clk_get(&pdev->dev, "m_axis_dout_aclk"); 1259 if (IS_ERR(clks->dout_clk)) { 1260 if (PTR_ERR(clks->dout_clk) != -ENOENT) { 1261 err = PTR_ERR(clks->dout_clk); 1262 return err; 1263 } 1264 clks->dout_clk = NULL; 1265 } 1266 1267 clks->dout_words_clk = 1268 devm_clk_get(&pdev->dev, "s_axis_dout_words_aclk"); 1269 if (IS_ERR(clks->dout_words_clk)) { 1270 if (PTR_ERR(clks->dout_words_clk) != -ENOENT) { 1271 err = PTR_ERR(clks->dout_words_clk); 1272 return err; 1273 } 1274 clks->dout_words_clk = NULL; 1275 } 1276 1277 clks->ctrl_clk = devm_clk_get(&pdev->dev, "s_axis_ctrl_aclk"); 1278 if (IS_ERR(clks->ctrl_clk)) { 1279 if (PTR_ERR(clks->ctrl_clk) != -ENOENT) { 1280 err = PTR_ERR(clks->ctrl_clk); 1281 return err; 1282 } 1283 clks->ctrl_clk = NULL; 1284 } 1285 1286 clks->status_clk = devm_clk_get(&pdev->dev, "m_axis_status_aclk"); 1287 if (IS_ERR(clks->status_clk)) { 1288 if (PTR_ERR(clks->status_clk) != -ENOENT) { 1289 err = PTR_ERR(clks->status_clk); 1290 return err; 1291 } 1292 clks->status_clk = NULL; 1293 } 1294 1295 err = clk_prepare_enable(clks->core_clk); 1296 if (err) { 1297 dev_err(&pdev->dev, "failed to enable core_clk (%d)", err); 1298 return err; 1299 } 1300 1301 err = clk_prepare_enable(clks->axi_clk); 1302 if (err) { 1303 dev_err(&pdev->dev, "failed to enable axi_clk (%d)", err); 1304 goto err_disable_core_clk; 1305 } 1306 1307 err = clk_prepare_enable(clks->din_clk); 1308 if (err) { 1309 dev_err(&pdev->dev, "failed to enable din_clk (%d)", err); 1310 goto err_disable_axi_clk; 1311 } 1312 1313 err = clk_prepare_enable(clks->din_words_clk); 1314 if (err) { 1315 dev_err(&pdev->dev, "failed to enable din_words_clk (%d)", err); 1316 goto err_disable_din_clk; 1317 } 1318 1319 err = clk_prepare_enable(clks->dout_clk); 1320 if (err) { 1321 dev_err(&pdev->dev, "failed to enable dout_clk (%d)", err); 1322 goto err_disable_din_words_clk; 1323 } 1324 1325 err = clk_prepare_enable(clks->dout_words_clk); 1326 if (err) { 1327 dev_err(&pdev->dev, "failed to enable dout_words_clk (%d)", 1328 err); 1329 goto err_disable_dout_clk; 1330 } 1331 1332 err = clk_prepare_enable(clks->ctrl_clk); 1333 if (err) { 1334 dev_err(&pdev->dev, "failed to enable ctrl_clk (%d)", err); 1335 goto err_disable_dout_words_clk; 1336 } 1337 1338 err = clk_prepare_enable(clks->status_clk); 1339 if (err) { 1340 dev_err(&pdev->dev, "failed to enable status_clk (%d)\n", err); 1341 goto err_disable_ctrl_clk; 1342 } 1343 1344 return err; 1345 1346 err_disable_ctrl_clk: 1347 clk_disable_unprepare(clks->ctrl_clk); 1348 err_disable_dout_words_clk: 1349 clk_disable_unprepare(clks->dout_words_clk); 1350 err_disable_dout_clk: 1351 clk_disable_unprepare(clks->dout_clk); 1352 err_disable_din_words_clk: 1353 clk_disable_unprepare(clks->din_words_clk); 1354 err_disable_din_clk: 1355 clk_disable_unprepare(clks->din_clk); 1356 err_disable_axi_clk: 1357 clk_disable_unprepare(clks->axi_clk); 1358 err_disable_core_clk: 1359 clk_disable_unprepare(clks->core_clk); 1360 1361 return err; 1362 } 1363 1364 static void xsdfec_disable_all_clks(struct xsdfec_clks *clks) 1365 { 1366 clk_disable_unprepare(clks->status_clk); 1367 clk_disable_unprepare(clks->ctrl_clk); 1368 clk_disable_unprepare(clks->dout_words_clk); 1369 clk_disable_unprepare(clks->dout_clk); 1370 clk_disable_unprepare(clks->din_words_clk); 1371 clk_disable_unprepare(clks->din_clk); 1372 clk_disable_unprepare(clks->core_clk); 1373 clk_disable_unprepare(clks->axi_clk); 1374 } 1375 1376 static int xsdfec_probe(struct platform_device *pdev) 1377 { 1378 struct xsdfec_dev *xsdfec; 1379 struct device *dev; 1380 struct resource *res; 1381 int err; 1382 bool irq_enabled = true; 1383 1384 xsdfec = devm_kzalloc(&pdev->dev, sizeof(*xsdfec), GFP_KERNEL); 1385 if (!xsdfec) 1386 return -ENOMEM; 1387 1388 xsdfec->dev = &pdev->dev; 1389 spin_lock_init(&xsdfec->error_data_lock); 1390 1391 err = xsdfec_clk_init(pdev, &xsdfec->clks); 1392 if (err) 1393 return err; 1394 1395 dev = xsdfec->dev; 1396 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1397 xsdfec->regs = devm_ioremap_resource(dev, res); 1398 if (IS_ERR(xsdfec->regs)) { 1399 err = PTR_ERR(xsdfec->regs); 1400 goto err_xsdfec_dev; 1401 } 1402 1403 xsdfec->irq = platform_get_irq(pdev, 0); 1404 if (xsdfec->irq < 0) { 1405 dev_dbg(dev, "platform_get_irq failed"); 1406 irq_enabled = false; 1407 } 1408 1409 err = xsdfec_parse_of(xsdfec); 1410 if (err < 0) 1411 goto err_xsdfec_dev; 1412 1413 update_config_from_hw(xsdfec); 1414 1415 /* Save driver private data */ 1416 platform_set_drvdata(pdev, xsdfec); 1417 1418 if (irq_enabled) { 1419 init_waitqueue_head(&xsdfec->waitq); 1420 /* Register IRQ thread */ 1421 err = devm_request_threaded_irq(dev, xsdfec->irq, NULL, 1422 xsdfec_irq_thread, IRQF_ONESHOT, 1423 "xilinx-sdfec16", xsdfec); 1424 if (err < 0) { 1425 dev_err(dev, "unable to request IRQ%d", xsdfec->irq); 1426 goto err_xsdfec_dev; 1427 } 1428 } 1429 1430 err = ida_alloc(&dev_nrs, GFP_KERNEL); 1431 if (err < 0) 1432 goto err_xsdfec_dev; 1433 xsdfec->dev_id = err; 1434 1435 snprintf(xsdfec->dev_name, DEV_NAME_LEN, "xsdfec%d", xsdfec->dev_id); 1436 xsdfec->miscdev.minor = MISC_DYNAMIC_MINOR; 1437 xsdfec->miscdev.name = xsdfec->dev_name; 1438 xsdfec->miscdev.fops = &xsdfec_fops; 1439 xsdfec->miscdev.parent = dev; 1440 err = misc_register(&xsdfec->miscdev); 1441 if (err) { 1442 dev_err(dev, "error:%d. Unable to register device", err); 1443 goto err_xsdfec_ida; 1444 } 1445 return 0; 1446 1447 err_xsdfec_ida: 1448 ida_free(&dev_nrs, xsdfec->dev_id); 1449 err_xsdfec_dev: 1450 xsdfec_disable_all_clks(&xsdfec->clks); 1451 return err; 1452 } 1453 1454 static int xsdfec_remove(struct platform_device *pdev) 1455 { 1456 struct xsdfec_dev *xsdfec; 1457 1458 xsdfec = platform_get_drvdata(pdev); 1459 misc_deregister(&xsdfec->miscdev); 1460 ida_free(&dev_nrs, xsdfec->dev_id); 1461 xsdfec_disable_all_clks(&xsdfec->clks); 1462 return 0; 1463 } 1464 1465 static const struct of_device_id xsdfec_of_match[] = { 1466 { 1467 .compatible = "xlnx,sd-fec-1.1", 1468 }, 1469 { /* end of table */ } 1470 }; 1471 MODULE_DEVICE_TABLE(of, xsdfec_of_match); 1472 1473 static struct platform_driver xsdfec_driver = { 1474 .driver = { 1475 .name = "xilinx-sdfec", 1476 .of_match_table = xsdfec_of_match, 1477 }, 1478 .probe = xsdfec_probe, 1479 .remove = xsdfec_remove, 1480 }; 1481 1482 static int __init xsdfec_init(void) 1483 { 1484 int err; 1485 1486 err = platform_driver_register(&xsdfec_driver); 1487 if (err < 0) { 1488 pr_err("%s Unabled to register SDFEC driver", __func__); 1489 return err; 1490 } 1491 return 0; 1492 } 1493 1494 static void __exit xsdfec_exit(void) 1495 { 1496 platform_driver_unregister(&xsdfec_driver); 1497 } 1498 1499 module_init(xsdfec_init); 1500 module_exit(xsdfec_exit); 1501 1502 MODULE_AUTHOR("Xilinx, Inc"); 1503 MODULE_DESCRIPTION("Xilinx SD-FEC16 Driver"); 1504 MODULE_LICENSE("GPL"); 1505