1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx SDFEC 4 * 5 * Copyright (C) 2019 Xilinx, Inc. 6 * 7 * Description: 8 * This driver is developed for SDFEC16 (Soft Decision FEC 16nm) 9 * IP. It exposes a char device which supports file operations 10 * like open(), close() and ioctl(). 11 */ 12 13 #include <linux/miscdevice.h> 14 #include <linux/io.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of_platform.h> 19 #include <linux/poll.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/compat.h> 23 #include <linux/highmem.h> 24 25 #include <uapi/misc/xilinx_sdfec.h> 26 27 #define DEV_NAME_LEN 12 28 29 static DEFINE_IDA(dev_nrs); 30 31 /* Xilinx SDFEC Register Map */ 32 /* CODE_WRI_PROTECT Register */ 33 #define XSDFEC_CODE_WR_PROTECT_ADDR (0x4) 34 35 /* ACTIVE Register */ 36 #define XSDFEC_ACTIVE_ADDR (0x8) 37 #define XSDFEC_IS_ACTIVITY_SET (0x1) 38 39 /* AXIS_WIDTH Register */ 40 #define XSDFEC_AXIS_WIDTH_ADDR (0xC) 41 #define XSDFEC_AXIS_DOUT_WORDS_LSB (5) 42 #define XSDFEC_AXIS_DOUT_WIDTH_LSB (3) 43 #define XSDFEC_AXIS_DIN_WORDS_LSB (2) 44 #define XSDFEC_AXIS_DIN_WIDTH_LSB (0) 45 46 /* AXIS_ENABLE Register */ 47 #define XSDFEC_AXIS_ENABLE_ADDR (0x10) 48 #define XSDFEC_AXIS_OUT_ENABLE_MASK (0x38) 49 #define XSDFEC_AXIS_IN_ENABLE_MASK (0x7) 50 #define XSDFEC_AXIS_ENABLE_MASK \ 51 (XSDFEC_AXIS_OUT_ENABLE_MASK | XSDFEC_AXIS_IN_ENABLE_MASK) 52 53 /* FEC_CODE Register */ 54 #define XSDFEC_FEC_CODE_ADDR (0x14) 55 56 /* ORDER Register Map */ 57 #define XSDFEC_ORDER_ADDR (0x18) 58 59 /* Interrupt Status Register */ 60 #define XSDFEC_ISR_ADDR (0x1C) 61 /* Interrupt Status Register Bit Mask */ 62 #define XSDFEC_ISR_MASK (0x3F) 63 64 /* Write Only - Interrupt Enable Register */ 65 #define XSDFEC_IER_ADDR (0x20) 66 /* Write Only - Interrupt Disable Register */ 67 #define XSDFEC_IDR_ADDR (0x24) 68 /* Read Only - Interrupt Mask Register */ 69 #define XSDFEC_IMR_ADDR (0x28) 70 71 /* ECC Interrupt Status Register */ 72 #define XSDFEC_ECC_ISR_ADDR (0x2C) 73 /* Single Bit Errors */ 74 #define XSDFEC_ECC_ISR_SBE_MASK (0x7FF) 75 /* PL Initialize Single Bit Errors */ 76 #define XSDFEC_PL_INIT_ECC_ISR_SBE_MASK (0x3C00000) 77 /* Multi Bit Errors */ 78 #define XSDFEC_ECC_ISR_MBE_MASK (0x3FF800) 79 /* PL Initialize Multi Bit Errors */ 80 #define XSDFEC_PL_INIT_ECC_ISR_MBE_MASK (0x3C000000) 81 /* Multi Bit Error to Event Shift */ 82 #define XSDFEC_ECC_ISR_MBE_TO_EVENT_SHIFT (11) 83 /* PL Initialize Multi Bit Error to Event Shift */ 84 #define XSDFEC_PL_INIT_ECC_ISR_MBE_TO_EVENT_SHIFT (4) 85 /* ECC Interrupt Status Bit Mask */ 86 #define XSDFEC_ECC_ISR_MASK (XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_ECC_ISR_MBE_MASK) 87 /* ECC Interrupt Status PL Initialize Bit Mask */ 88 #define XSDFEC_PL_INIT_ECC_ISR_MASK \ 89 (XSDFEC_PL_INIT_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK) 90 /* ECC Interrupt Status All Bit Mask */ 91 #define XSDFEC_ALL_ECC_ISR_MASK \ 92 (XSDFEC_ECC_ISR_MASK | XSDFEC_PL_INIT_ECC_ISR_MASK) 93 /* ECC Interrupt Status Single Bit Errors Mask */ 94 #define XSDFEC_ALL_ECC_ISR_SBE_MASK \ 95 (XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_SBE_MASK) 96 /* ECC Interrupt Status Multi Bit Errors Mask */ 97 #define XSDFEC_ALL_ECC_ISR_MBE_MASK \ 98 (XSDFEC_ECC_ISR_MBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK) 99 100 /* Write Only - ECC Interrupt Enable Register */ 101 #define XSDFEC_ECC_IER_ADDR (0x30) 102 /* Write Only - ECC Interrupt Disable Register */ 103 #define XSDFEC_ECC_IDR_ADDR (0x34) 104 /* Read Only - ECC Interrupt Mask Register */ 105 #define XSDFEC_ECC_IMR_ADDR (0x38) 106 107 /* BYPASS Register */ 108 #define XSDFEC_BYPASS_ADDR (0x3C) 109 110 /* Turbo Code Register */ 111 #define XSDFEC_TURBO_ADDR (0x100) 112 #define XSDFEC_TURBO_SCALE_MASK (0xFFF) 113 #define XSDFEC_TURBO_SCALE_BIT_POS (8) 114 #define XSDFEC_TURBO_SCALE_MAX (15) 115 116 /* REG0 Register */ 117 #define XSDFEC_LDPC_CODE_REG0_ADDR_BASE (0x2000) 118 #define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH (0x27F0) 119 #define XSDFEC_REG0_N_MIN (4) 120 #define XSDFEC_REG0_N_MAX (32768) 121 #define XSDFEC_REG0_N_MUL_P (256) 122 #define XSDFEC_REG0_N_LSB (0) 123 #define XSDFEC_REG0_K_MIN (2) 124 #define XSDFEC_REG0_K_MAX (32766) 125 #define XSDFEC_REG0_K_MUL_P (256) 126 #define XSDFEC_REG0_K_LSB (16) 127 128 /* REG1 Register */ 129 #define XSDFEC_LDPC_CODE_REG1_ADDR_BASE (0x2004) 130 #define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH (0x27f4) 131 #define XSDFEC_REG1_PSIZE_MIN (2) 132 #define XSDFEC_REG1_PSIZE_MAX (512) 133 #define XSDFEC_REG1_NO_PACKING_MASK (0x400) 134 #define XSDFEC_REG1_NO_PACKING_LSB (10) 135 #define XSDFEC_REG1_NM_MASK (0xFF800) 136 #define XSDFEC_REG1_NM_LSB (11) 137 #define XSDFEC_REG1_BYPASS_MASK (0x100000) 138 139 /* REG2 Register */ 140 #define XSDFEC_LDPC_CODE_REG2_ADDR_BASE (0x2008) 141 #define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH (0x27f8) 142 #define XSDFEC_REG2_NLAYERS_MIN (1) 143 #define XSDFEC_REG2_NLAYERS_MAX (256) 144 #define XSDFEC_REG2_NNMQC_MASK (0xFFE00) 145 #define XSDFEC_REG2_NMQC_LSB (9) 146 #define XSDFEC_REG2_NORM_TYPE_MASK (0x100000) 147 #define XSDFEC_REG2_NORM_TYPE_LSB (20) 148 #define XSDFEC_REG2_SPECIAL_QC_MASK (0x200000) 149 #define XSDFEC_REG2_SPEICAL_QC_LSB (21) 150 #define XSDFEC_REG2_NO_FINAL_PARITY_MASK (0x400000) 151 #define XSDFEC_REG2_NO_FINAL_PARITY_LSB (22) 152 #define XSDFEC_REG2_MAX_SCHEDULE_MASK (0x1800000) 153 #define XSDFEC_REG2_MAX_SCHEDULE_LSB (23) 154 155 /* REG3 Register */ 156 #define XSDFEC_LDPC_CODE_REG3_ADDR_BASE (0x200C) 157 #define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH (0x27FC) 158 #define XSDFEC_REG3_LA_OFF_LSB (8) 159 #define XSDFEC_REG3_QC_OFF_LSB (16) 160 161 #define XSDFEC_LDPC_REG_JUMP (0x10) 162 #define XSDFEC_REG_WIDTH_JUMP (4) 163 164 /* The maximum number of pinned pages */ 165 #define MAX_NUM_PAGES ((XSDFEC_QC_TABLE_DEPTH / PAGE_SIZE) + 1) 166 167 /** 168 * struct xsdfec_clks - For managing SD-FEC clocks 169 * @core_clk: Main processing clock for core 170 * @axi_clk: AXI4-Lite memory-mapped clock 171 * @din_words_clk: DIN Words AXI4-Stream Slave clock 172 * @din_clk: DIN AXI4-Stream Slave clock 173 * @dout_clk: DOUT Words AXI4-Stream Slave clock 174 * @dout_words_clk: DOUT AXI4-Stream Slave clock 175 * @ctrl_clk: Control AXI4-Stream Slave clock 176 * @status_clk: Status AXI4-Stream Slave clock 177 */ 178 struct xsdfec_clks { 179 struct clk *core_clk; 180 struct clk *axi_clk; 181 struct clk *din_words_clk; 182 struct clk *din_clk; 183 struct clk *dout_clk; 184 struct clk *dout_words_clk; 185 struct clk *ctrl_clk; 186 struct clk *status_clk; 187 }; 188 189 /** 190 * struct xsdfec_dev - Driver data for SDFEC 191 * @miscdev: Misc device handle 192 * @clks: Clocks managed by the SDFEC driver 193 * @waitq: Driver wait queue 194 * @config: Configuration of the SDFEC device 195 * @dev_name: Device name 196 * @flags: spinlock flags 197 * @regs: device physical base address 198 * @dev: pointer to device struct 199 * @state: State of the SDFEC device 200 * @error_data_lock: Error counter and states spinlock 201 * @dev_id: Device ID 202 * @isr_err_count: Count of ISR errors 203 * @cecc_count: Count of Correctable ECC errors (SBE) 204 * @uecc_count: Count of Uncorrectable ECC errors (MBE) 205 * @irq: IRQ number 206 * @state_updated: indicates State updated by interrupt handler 207 * @stats_updated: indicates Stats updated by interrupt handler 208 * @intr_enabled: indicates IRQ enabled 209 * 210 * This structure contains necessary state for SDFEC driver to operate 211 */ 212 struct xsdfec_dev { 213 struct miscdevice miscdev; 214 struct xsdfec_clks clks; 215 wait_queue_head_t waitq; 216 struct xsdfec_config config; 217 char dev_name[DEV_NAME_LEN]; 218 unsigned long flags; 219 void __iomem *regs; 220 struct device *dev; 221 enum xsdfec_state state; 222 /* Spinlock to protect state_updated and stats_updated */ 223 spinlock_t error_data_lock; 224 int dev_id; 225 u32 isr_err_count; 226 u32 cecc_count; 227 u32 uecc_count; 228 int irq; 229 bool state_updated; 230 bool stats_updated; 231 bool intr_enabled; 232 }; 233 234 static inline void xsdfec_regwrite(struct xsdfec_dev *xsdfec, u32 addr, 235 u32 value) 236 { 237 dev_dbg(xsdfec->dev, "Writing 0x%x to offset 0x%x", value, addr); 238 iowrite32(value, xsdfec->regs + addr); 239 } 240 241 static inline u32 xsdfec_regread(struct xsdfec_dev *xsdfec, u32 addr) 242 { 243 u32 rval; 244 245 rval = ioread32(xsdfec->regs + addr); 246 dev_dbg(xsdfec->dev, "Read value = 0x%x from offset 0x%x", rval, addr); 247 return rval; 248 } 249 250 static void update_bool_config_from_reg(struct xsdfec_dev *xsdfec, 251 u32 reg_offset, u32 bit_num, 252 char *config_value) 253 { 254 u32 reg_val; 255 u32 bit_mask = 1 << bit_num; 256 257 reg_val = xsdfec_regread(xsdfec, reg_offset); 258 *config_value = (reg_val & bit_mask) > 0; 259 } 260 261 static void update_config_from_hw(struct xsdfec_dev *xsdfec) 262 { 263 u32 reg_value; 264 bool sdfec_started; 265 266 /* Update the Order */ 267 reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR); 268 xsdfec->config.order = reg_value; 269 270 update_bool_config_from_reg(xsdfec, XSDFEC_BYPASS_ADDR, 271 0, /* Bit Number, maybe change to mask */ 272 &xsdfec->config.bypass); 273 274 update_bool_config_from_reg(xsdfec, XSDFEC_CODE_WR_PROTECT_ADDR, 275 0, /* Bit Number */ 276 &xsdfec->config.code_wr_protect); 277 278 reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); 279 xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0; 280 281 reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); 282 xsdfec->config.irq.enable_ecc_isr = 283 (reg_value & XSDFEC_ECC_ISR_MASK) > 0; 284 285 reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR); 286 sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0; 287 if (sdfec_started) 288 xsdfec->state = XSDFEC_STARTED; 289 else 290 xsdfec->state = XSDFEC_STOPPED; 291 } 292 293 static int xsdfec_get_status(struct xsdfec_dev *xsdfec, void __user *arg) 294 { 295 struct xsdfec_status status; 296 int err; 297 298 memset(&status, 0, sizeof(status)); 299 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 300 status.state = xsdfec->state; 301 xsdfec->state_updated = false; 302 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 303 status.activity = (xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR) & 304 XSDFEC_IS_ACTIVITY_SET); 305 306 err = copy_to_user(arg, &status, sizeof(status)); 307 if (err) 308 err = -EFAULT; 309 310 return err; 311 } 312 313 static int xsdfec_get_config(struct xsdfec_dev *xsdfec, void __user *arg) 314 { 315 int err; 316 317 err = copy_to_user(arg, &xsdfec->config, sizeof(xsdfec->config)); 318 if (err) 319 err = -EFAULT; 320 321 return err; 322 } 323 324 static int xsdfec_isr_enable(struct xsdfec_dev *xsdfec, bool enable) 325 { 326 u32 mask_read; 327 328 if (enable) { 329 /* Enable */ 330 xsdfec_regwrite(xsdfec, XSDFEC_IER_ADDR, XSDFEC_ISR_MASK); 331 mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); 332 if (mask_read & XSDFEC_ISR_MASK) { 333 dev_dbg(xsdfec->dev, 334 "SDFEC enabling irq with IER failed"); 335 return -EIO; 336 } 337 } else { 338 /* Disable */ 339 xsdfec_regwrite(xsdfec, XSDFEC_IDR_ADDR, XSDFEC_ISR_MASK); 340 mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); 341 if ((mask_read & XSDFEC_ISR_MASK) != XSDFEC_ISR_MASK) { 342 dev_dbg(xsdfec->dev, 343 "SDFEC disabling irq with IDR failed"); 344 return -EIO; 345 } 346 } 347 return 0; 348 } 349 350 static int xsdfec_ecc_isr_enable(struct xsdfec_dev *xsdfec, bool enable) 351 { 352 u32 mask_read; 353 354 if (enable) { 355 /* Enable */ 356 xsdfec_regwrite(xsdfec, XSDFEC_ECC_IER_ADDR, 357 XSDFEC_ALL_ECC_ISR_MASK); 358 mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); 359 if (mask_read & XSDFEC_ALL_ECC_ISR_MASK) { 360 dev_dbg(xsdfec->dev, 361 "SDFEC enabling ECC irq with ECC IER failed"); 362 return -EIO; 363 } 364 } else { 365 /* Disable */ 366 xsdfec_regwrite(xsdfec, XSDFEC_ECC_IDR_ADDR, 367 XSDFEC_ALL_ECC_ISR_MASK); 368 mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); 369 if (!(((mask_read & XSDFEC_ALL_ECC_ISR_MASK) == 370 XSDFEC_ECC_ISR_MASK) || 371 ((mask_read & XSDFEC_ALL_ECC_ISR_MASK) == 372 XSDFEC_PL_INIT_ECC_ISR_MASK))) { 373 dev_dbg(xsdfec->dev, 374 "SDFEC disable ECC irq with ECC IDR failed"); 375 return -EIO; 376 } 377 } 378 return 0; 379 } 380 381 static int xsdfec_set_irq(struct xsdfec_dev *xsdfec, void __user *arg) 382 { 383 struct xsdfec_irq irq; 384 int err; 385 int isr_err; 386 int ecc_err; 387 388 err = copy_from_user(&irq, arg, sizeof(irq)); 389 if (err) 390 return -EFAULT; 391 392 /* Setup tlast related IRQ */ 393 isr_err = xsdfec_isr_enable(xsdfec, irq.enable_isr); 394 if (!isr_err) 395 xsdfec->config.irq.enable_isr = irq.enable_isr; 396 397 /* Setup ECC related IRQ */ 398 ecc_err = xsdfec_ecc_isr_enable(xsdfec, irq.enable_ecc_isr); 399 if (!ecc_err) 400 xsdfec->config.irq.enable_ecc_isr = irq.enable_ecc_isr; 401 402 if (isr_err < 0 || ecc_err < 0) 403 err = -EIO; 404 405 return err; 406 } 407 408 static int xsdfec_set_turbo(struct xsdfec_dev *xsdfec, void __user *arg) 409 { 410 struct xsdfec_turbo turbo; 411 int err; 412 u32 turbo_write; 413 414 err = copy_from_user(&turbo, arg, sizeof(turbo)); 415 if (err) 416 return -EFAULT; 417 418 if (turbo.alg >= XSDFEC_TURBO_ALG_MAX) 419 return -EINVAL; 420 421 if (turbo.scale > XSDFEC_TURBO_SCALE_MAX) 422 return -EINVAL; 423 424 /* Check to see what device tree says about the FEC codes */ 425 if (xsdfec->config.code == XSDFEC_LDPC_CODE) 426 return -EIO; 427 428 turbo_write = ((turbo.scale & XSDFEC_TURBO_SCALE_MASK) 429 << XSDFEC_TURBO_SCALE_BIT_POS) | 430 turbo.alg; 431 xsdfec_regwrite(xsdfec, XSDFEC_TURBO_ADDR, turbo_write); 432 return err; 433 } 434 435 static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg) 436 { 437 u32 reg_value; 438 struct xsdfec_turbo turbo_params; 439 int err; 440 441 if (xsdfec->config.code == XSDFEC_LDPC_CODE) 442 return -EIO; 443 444 memset(&turbo_params, 0, sizeof(turbo_params)); 445 reg_value = xsdfec_regread(xsdfec, XSDFEC_TURBO_ADDR); 446 447 turbo_params.scale = (reg_value & XSDFEC_TURBO_SCALE_MASK) >> 448 XSDFEC_TURBO_SCALE_BIT_POS; 449 turbo_params.alg = reg_value & 0x1; 450 451 err = copy_to_user(arg, &turbo_params, sizeof(turbo_params)); 452 if (err) 453 err = -EFAULT; 454 455 return err; 456 } 457 458 static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize, 459 u32 offset) 460 { 461 u32 wdata; 462 463 if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX || psize == 0 || 464 (n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) { 465 dev_dbg(xsdfec->dev, "N value is not in range"); 466 return -EINVAL; 467 } 468 n <<= XSDFEC_REG0_N_LSB; 469 470 if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX || 471 (k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) { 472 dev_dbg(xsdfec->dev, "K value is not in range"); 473 return -EINVAL; 474 } 475 k = k << XSDFEC_REG0_K_LSB; 476 wdata = k | n; 477 478 if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 479 XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) { 480 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg0 space 0x%x", 481 XSDFEC_LDPC_CODE_REG0_ADDR_BASE + 482 (offset * XSDFEC_LDPC_REG_JUMP)); 483 return -EINVAL; 484 } 485 xsdfec_regwrite(xsdfec, 486 XSDFEC_LDPC_CODE_REG0_ADDR_BASE + 487 (offset * XSDFEC_LDPC_REG_JUMP), 488 wdata); 489 return 0; 490 } 491 492 static int xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize, 493 u32 no_packing, u32 nm, u32 offset) 494 { 495 u32 wdata; 496 497 if (psize < XSDFEC_REG1_PSIZE_MIN || psize > XSDFEC_REG1_PSIZE_MAX) { 498 dev_dbg(xsdfec->dev, "Psize is not in range"); 499 return -EINVAL; 500 } 501 502 if (no_packing != 0 && no_packing != 1) 503 dev_dbg(xsdfec->dev, "No-packing bit register invalid"); 504 no_packing = ((no_packing << XSDFEC_REG1_NO_PACKING_LSB) & 505 XSDFEC_REG1_NO_PACKING_MASK); 506 507 if (nm & ~(XSDFEC_REG1_NM_MASK >> XSDFEC_REG1_NM_LSB)) 508 dev_dbg(xsdfec->dev, "NM is beyond 10 bits"); 509 nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK; 510 511 wdata = nm | no_packing | psize; 512 if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 513 XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) { 514 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg1 space 0x%x", 515 XSDFEC_LDPC_CODE_REG1_ADDR_BASE + 516 (offset * XSDFEC_LDPC_REG_JUMP)); 517 return -EINVAL; 518 } 519 xsdfec_regwrite(xsdfec, 520 XSDFEC_LDPC_CODE_REG1_ADDR_BASE + 521 (offset * XSDFEC_LDPC_REG_JUMP), 522 wdata); 523 return 0; 524 } 525 526 static int xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc, 527 u32 norm_type, u32 special_qc, u32 no_final_parity, 528 u32 max_schedule, u32 offset) 529 { 530 u32 wdata; 531 532 if (nlayers < XSDFEC_REG2_NLAYERS_MIN || 533 nlayers > XSDFEC_REG2_NLAYERS_MAX) { 534 dev_dbg(xsdfec->dev, "Nlayers is not in range"); 535 return -EINVAL; 536 } 537 538 if (nmqc & ~(XSDFEC_REG2_NNMQC_MASK >> XSDFEC_REG2_NMQC_LSB)) 539 dev_dbg(xsdfec->dev, "NMQC exceeds 11 bits"); 540 nmqc = (nmqc << XSDFEC_REG2_NMQC_LSB) & XSDFEC_REG2_NNMQC_MASK; 541 542 if (norm_type > 1) 543 dev_dbg(xsdfec->dev, "Norm type is invalid"); 544 norm_type = ((norm_type << XSDFEC_REG2_NORM_TYPE_LSB) & 545 XSDFEC_REG2_NORM_TYPE_MASK); 546 if (special_qc > 1) 547 dev_dbg(xsdfec->dev, "Special QC in invalid"); 548 special_qc = ((special_qc << XSDFEC_REG2_SPEICAL_QC_LSB) & 549 XSDFEC_REG2_SPECIAL_QC_MASK); 550 551 if (no_final_parity > 1) 552 dev_dbg(xsdfec->dev, "No final parity check invalid"); 553 no_final_parity = 554 ((no_final_parity << XSDFEC_REG2_NO_FINAL_PARITY_LSB) & 555 XSDFEC_REG2_NO_FINAL_PARITY_MASK); 556 if (max_schedule & 557 ~(XSDFEC_REG2_MAX_SCHEDULE_MASK >> XSDFEC_REG2_MAX_SCHEDULE_LSB)) 558 dev_dbg(xsdfec->dev, "Max Schedule exceeds 2 bits"); 559 max_schedule = ((max_schedule << XSDFEC_REG2_MAX_SCHEDULE_LSB) & 560 XSDFEC_REG2_MAX_SCHEDULE_MASK); 561 562 wdata = (max_schedule | no_final_parity | special_qc | norm_type | 563 nmqc | nlayers); 564 565 if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 566 XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) { 567 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg2 space 0x%x", 568 XSDFEC_LDPC_CODE_REG2_ADDR_BASE + 569 (offset * XSDFEC_LDPC_REG_JUMP)); 570 return -EINVAL; 571 } 572 xsdfec_regwrite(xsdfec, 573 XSDFEC_LDPC_CODE_REG2_ADDR_BASE + 574 (offset * XSDFEC_LDPC_REG_JUMP), 575 wdata); 576 return 0; 577 } 578 579 static int xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off, u8 la_off, 580 u16 qc_off, u32 offset) 581 { 582 u32 wdata; 583 584 wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) | 585 (la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off); 586 if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) > 587 XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) { 588 dev_dbg(xsdfec->dev, "Writing outside of LDPC reg3 space 0x%x", 589 XSDFEC_LDPC_CODE_REG3_ADDR_BASE + 590 (offset * XSDFEC_LDPC_REG_JUMP)); 591 return -EINVAL; 592 } 593 xsdfec_regwrite(xsdfec, 594 XSDFEC_LDPC_CODE_REG3_ADDR_BASE + 595 (offset * XSDFEC_LDPC_REG_JUMP), 596 wdata); 597 return 0; 598 } 599 600 static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, 601 u32 *src_ptr, u32 len, const u32 base_addr, 602 const u32 depth) 603 { 604 u32 reg = 0; 605 int res, i, nr_pages; 606 u32 n; 607 u32 *addr = NULL; 608 struct page *pages[MAX_NUM_PAGES]; 609 610 /* 611 * Writes that go beyond the length of 612 * Shared Scale(SC) table should fail 613 */ 614 if (offset > depth / XSDFEC_REG_WIDTH_JUMP || 615 len > depth / XSDFEC_REG_WIDTH_JUMP || 616 offset + len > depth / XSDFEC_REG_WIDTH_JUMP) { 617 dev_dbg(xsdfec->dev, "Write exceeds SC table length"); 618 return -EINVAL; 619 } 620 621 n = (len * XSDFEC_REG_WIDTH_JUMP) / PAGE_SIZE; 622 if ((len * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE) 623 n += 1; 624 625 if (WARN_ON_ONCE(n > INT_MAX)) 626 return -EINVAL; 627 628 nr_pages = n; 629 630 res = get_user_pages_fast((unsigned long)src_ptr, nr_pages, 0, pages); 631 if (res < nr_pages) { 632 if (res > 0) { 633 for (i = 0; i < res; i++) 634 put_page(pages[i]); 635 } 636 return -EINVAL; 637 } 638 639 for (i = 0; i < nr_pages; i++) { 640 addr = kmap(pages[i]); 641 do { 642 xsdfec_regwrite(xsdfec, 643 base_addr + ((offset + reg) * 644 XSDFEC_REG_WIDTH_JUMP), 645 addr[reg]); 646 reg++; 647 } while ((reg < len) && 648 ((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)); 649 put_page(pages[i]); 650 } 651 return reg; 652 } 653 654 static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) 655 { 656 struct xsdfec_ldpc_params *ldpc; 657 int ret, n; 658 659 ldpc = memdup_user(arg, sizeof(*ldpc)); 660 if (IS_ERR(ldpc)) 661 return PTR_ERR(ldpc); 662 663 if (xsdfec->config.code == XSDFEC_TURBO_CODE) { 664 ret = -EIO; 665 goto err_out; 666 } 667 668 /* Verify Device has not started */ 669 if (xsdfec->state == XSDFEC_STARTED) { 670 ret = -EIO; 671 goto err_out; 672 } 673 674 if (xsdfec->config.code_wr_protect) { 675 ret = -EIO; 676 goto err_out; 677 } 678 679 /* Write Reg 0 */ 680 ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize, 681 ldpc->code_id); 682 if (ret) 683 goto err_out; 684 685 /* Write Reg 1 */ 686 ret = xsdfec_reg1_write(xsdfec, ldpc->psize, ldpc->no_packing, ldpc->nm, 687 ldpc->code_id); 688 if (ret) 689 goto err_out; 690 691 /* Write Reg 2 */ 692 ret = xsdfec_reg2_write(xsdfec, ldpc->nlayers, ldpc->nmqc, 693 ldpc->norm_type, ldpc->special_qc, 694 ldpc->no_final_parity, ldpc->max_schedule, 695 ldpc->code_id); 696 if (ret) 697 goto err_out; 698 699 /* Write Reg 3 */ 700 ret = xsdfec_reg3_write(xsdfec, ldpc->sc_off, ldpc->la_off, 701 ldpc->qc_off, ldpc->code_id); 702 if (ret) 703 goto err_out; 704 705 /* Write Shared Codes */ 706 n = ldpc->nlayers / 4; 707 if (ldpc->nlayers % 4) 708 n++; 709 710 ret = xsdfec_table_write(xsdfec, ldpc->sc_off, ldpc->sc_table, n, 711 XSDFEC_LDPC_SC_TABLE_ADDR_BASE, 712 XSDFEC_SC_TABLE_DEPTH); 713 if (ret < 0) 714 goto err_out; 715 716 ret = xsdfec_table_write(xsdfec, 4 * ldpc->la_off, ldpc->la_table, 717 ldpc->nlayers, XSDFEC_LDPC_LA_TABLE_ADDR_BASE, 718 XSDFEC_LA_TABLE_DEPTH); 719 if (ret < 0) 720 goto err_out; 721 722 ret = xsdfec_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table, 723 ldpc->nqc, XSDFEC_LDPC_QC_TABLE_ADDR_BASE, 724 XSDFEC_QC_TABLE_DEPTH); 725 if (ret > 0) 726 ret = 0; 727 err_out: 728 kfree(ldpc); 729 return ret; 730 } 731 732 static int xsdfec_set_order(struct xsdfec_dev *xsdfec, void __user *arg) 733 { 734 bool order_invalid; 735 enum xsdfec_order order; 736 int err; 737 738 err = get_user(order, (enum xsdfec_order __user *)arg); 739 if (err) 740 return -EFAULT; 741 742 order_invalid = (order != XSDFEC_MAINTAIN_ORDER) && 743 (order != XSDFEC_OUT_OF_ORDER); 744 if (order_invalid) 745 return -EINVAL; 746 747 /* Verify Device has not started */ 748 if (xsdfec->state == XSDFEC_STARTED) 749 return -EIO; 750 751 xsdfec_regwrite(xsdfec, XSDFEC_ORDER_ADDR, order); 752 753 xsdfec->config.order = order; 754 755 return 0; 756 } 757 758 static int xsdfec_set_bypass(struct xsdfec_dev *xsdfec, bool __user *arg) 759 { 760 bool bypass; 761 int err; 762 763 err = get_user(bypass, arg); 764 if (err) 765 return -EFAULT; 766 767 /* Verify Device has not started */ 768 if (xsdfec->state == XSDFEC_STARTED) 769 return -EIO; 770 771 if (bypass) 772 xsdfec_regwrite(xsdfec, XSDFEC_BYPASS_ADDR, 1); 773 else 774 xsdfec_regwrite(xsdfec, XSDFEC_BYPASS_ADDR, 0); 775 776 xsdfec->config.bypass = bypass; 777 778 return 0; 779 } 780 781 static int xsdfec_is_active(struct xsdfec_dev *xsdfec, bool __user *arg) 782 { 783 u32 reg_value; 784 bool is_active; 785 int err; 786 787 reg_value = xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR); 788 /* using a double ! operator instead of casting */ 789 is_active = !!(reg_value & XSDFEC_IS_ACTIVITY_SET); 790 err = put_user(is_active, arg); 791 if (err) 792 return -EFAULT; 793 794 return err; 795 } 796 797 static u32 798 xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg) 799 { 800 u32 axis_width_field = 0; 801 802 switch (axis_width_cfg) { 803 case XSDFEC_1x128b: 804 axis_width_field = 0; 805 break; 806 case XSDFEC_2x128b: 807 axis_width_field = 1; 808 break; 809 case XSDFEC_4x128b: 810 axis_width_field = 2; 811 break; 812 } 813 814 return axis_width_field; 815 } 816 817 static u32 xsdfec_translate_axis_words_cfg_val(enum xsdfec_axis_word_include 818 axis_word_inc_cfg) 819 { 820 u32 axis_words_field = 0; 821 822 if (axis_word_inc_cfg == XSDFEC_FIXED_VALUE || 823 axis_word_inc_cfg == XSDFEC_IN_BLOCK) 824 axis_words_field = 0; 825 else if (axis_word_inc_cfg == XSDFEC_PER_AXI_TRANSACTION) 826 axis_words_field = 1; 827 828 return axis_words_field; 829 } 830 831 static int xsdfec_cfg_axi_streams(struct xsdfec_dev *xsdfec) 832 { 833 u32 reg_value; 834 u32 dout_words_field; 835 u32 dout_width_field; 836 u32 din_words_field; 837 u32 din_width_field; 838 struct xsdfec_config *config = &xsdfec->config; 839 840 /* translate config info to register values */ 841 dout_words_field = 842 xsdfec_translate_axis_words_cfg_val(config->dout_word_include); 843 dout_width_field = 844 xsdfec_translate_axis_width_cfg_val(config->dout_width); 845 din_words_field = 846 xsdfec_translate_axis_words_cfg_val(config->din_word_include); 847 din_width_field = 848 xsdfec_translate_axis_width_cfg_val(config->din_width); 849 850 reg_value = dout_words_field << XSDFEC_AXIS_DOUT_WORDS_LSB; 851 reg_value |= dout_width_field << XSDFEC_AXIS_DOUT_WIDTH_LSB; 852 reg_value |= din_words_field << XSDFEC_AXIS_DIN_WORDS_LSB; 853 reg_value |= din_width_field << XSDFEC_AXIS_DIN_WIDTH_LSB; 854 855 xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, reg_value); 856 857 return 0; 858 } 859 860 static int xsdfec_dev_open(struct inode *iptr, struct file *fptr) 861 { 862 return 0; 863 } 864 865 static int xsdfec_dev_release(struct inode *iptr, struct file *fptr) 866 { 867 return 0; 868 } 869 870 static int xsdfec_start(struct xsdfec_dev *xsdfec) 871 { 872 u32 regread; 873 874 regread = xsdfec_regread(xsdfec, XSDFEC_FEC_CODE_ADDR); 875 regread &= 0x1; 876 if (regread != xsdfec->config.code) { 877 dev_dbg(xsdfec->dev, 878 "%s SDFEC HW code does not match driver code, reg %d, code %d", 879 __func__, regread, xsdfec->config.code); 880 return -EINVAL; 881 } 882 883 /* Set AXIS enable */ 884 xsdfec_regwrite(xsdfec, XSDFEC_AXIS_ENABLE_ADDR, 885 XSDFEC_AXIS_ENABLE_MASK); 886 /* Done */ 887 xsdfec->state = XSDFEC_STARTED; 888 return 0; 889 } 890 891 static int xsdfec_stop(struct xsdfec_dev *xsdfec) 892 { 893 u32 regread; 894 895 if (xsdfec->state != XSDFEC_STARTED) 896 dev_dbg(xsdfec->dev, "Device not started correctly"); 897 /* Disable AXIS_ENABLE Input interfaces only */ 898 regread = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR); 899 regread &= (~XSDFEC_AXIS_IN_ENABLE_MASK); 900 xsdfec_regwrite(xsdfec, XSDFEC_AXIS_ENABLE_ADDR, regread); 901 /* Stop */ 902 xsdfec->state = XSDFEC_STOPPED; 903 return 0; 904 } 905 906 static int xsdfec_clear_stats(struct xsdfec_dev *xsdfec) 907 { 908 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 909 xsdfec->isr_err_count = 0; 910 xsdfec->uecc_count = 0; 911 xsdfec->cecc_count = 0; 912 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 913 914 return 0; 915 } 916 917 static int xsdfec_get_stats(struct xsdfec_dev *xsdfec, void __user *arg) 918 { 919 int err; 920 struct xsdfec_stats user_stats; 921 922 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 923 user_stats.isr_err_count = xsdfec->isr_err_count; 924 user_stats.cecc_count = xsdfec->cecc_count; 925 user_stats.uecc_count = xsdfec->uecc_count; 926 xsdfec->stats_updated = false; 927 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 928 929 err = copy_to_user(arg, &user_stats, sizeof(user_stats)); 930 if (err) 931 err = -EFAULT; 932 933 return err; 934 } 935 936 static int xsdfec_set_default_config(struct xsdfec_dev *xsdfec) 937 { 938 /* Ensure registers are aligned with core configuration */ 939 xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, xsdfec->config.code); 940 xsdfec_cfg_axi_streams(xsdfec); 941 update_config_from_hw(xsdfec); 942 943 return 0; 944 } 945 946 static long xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd, 947 unsigned long data) 948 { 949 struct xsdfec_dev *xsdfec; 950 void __user *arg = NULL; 951 int rval = -EINVAL; 952 953 xsdfec = container_of(fptr->private_data, struct xsdfec_dev, miscdev); 954 955 /* In failed state allow only reset and get status IOCTLs */ 956 if (xsdfec->state == XSDFEC_NEEDS_RESET && 957 (cmd != XSDFEC_SET_DEFAULT_CONFIG && cmd != XSDFEC_GET_STATUS && 958 cmd != XSDFEC_GET_STATS && cmd != XSDFEC_CLEAR_STATS)) { 959 return -EPERM; 960 } 961 962 if (_IOC_TYPE(cmd) != XSDFEC_MAGIC) 963 return -ENOTTY; 964 965 /* check if ioctl argument is present and valid */ 966 if (_IOC_DIR(cmd) != _IOC_NONE) { 967 arg = (void __user *)data; 968 if (!arg) 969 return rval; 970 } 971 972 switch (cmd) { 973 case XSDFEC_START_DEV: 974 rval = xsdfec_start(xsdfec); 975 break; 976 case XSDFEC_STOP_DEV: 977 rval = xsdfec_stop(xsdfec); 978 break; 979 case XSDFEC_CLEAR_STATS: 980 rval = xsdfec_clear_stats(xsdfec); 981 break; 982 case XSDFEC_GET_STATS: 983 rval = xsdfec_get_stats(xsdfec, arg); 984 break; 985 case XSDFEC_GET_STATUS: 986 rval = xsdfec_get_status(xsdfec, arg); 987 break; 988 case XSDFEC_GET_CONFIG: 989 rval = xsdfec_get_config(xsdfec, arg); 990 break; 991 case XSDFEC_SET_DEFAULT_CONFIG: 992 rval = xsdfec_set_default_config(xsdfec); 993 break; 994 case XSDFEC_SET_IRQ: 995 rval = xsdfec_set_irq(xsdfec, arg); 996 break; 997 case XSDFEC_SET_TURBO: 998 rval = xsdfec_set_turbo(xsdfec, arg); 999 break; 1000 case XSDFEC_GET_TURBO: 1001 rval = xsdfec_get_turbo(xsdfec, arg); 1002 break; 1003 case XSDFEC_ADD_LDPC_CODE_PARAMS: 1004 rval = xsdfec_add_ldpc(xsdfec, arg); 1005 break; 1006 case XSDFEC_SET_ORDER: 1007 rval = xsdfec_set_order(xsdfec, arg); 1008 break; 1009 case XSDFEC_SET_BYPASS: 1010 rval = xsdfec_set_bypass(xsdfec, arg); 1011 break; 1012 case XSDFEC_IS_ACTIVE: 1013 rval = xsdfec_is_active(xsdfec, (bool __user *)arg); 1014 break; 1015 default: 1016 /* Should not get here */ 1017 break; 1018 } 1019 return rval; 1020 } 1021 1022 #ifdef CONFIG_COMPAT 1023 static long xsdfec_dev_compat_ioctl(struct file *file, unsigned int cmd, 1024 unsigned long data) 1025 { 1026 return xsdfec_dev_ioctl(file, cmd, (unsigned long)compat_ptr(data)); 1027 } 1028 #endif 1029 1030 static __poll_t xsdfec_poll(struct file *file, poll_table *wait) 1031 { 1032 __poll_t mask = 0; 1033 struct xsdfec_dev *xsdfec; 1034 1035 xsdfec = container_of(file->private_data, struct xsdfec_dev, miscdev); 1036 1037 if (!xsdfec) 1038 return EPOLLNVAL | EPOLLHUP; 1039 1040 poll_wait(file, &xsdfec->waitq, wait); 1041 1042 /* XSDFEC ISR detected an error */ 1043 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 1044 if (xsdfec->state_updated) 1045 mask |= EPOLLIN | EPOLLPRI; 1046 1047 if (xsdfec->stats_updated) 1048 mask |= EPOLLIN | EPOLLRDNORM; 1049 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 1050 1051 return mask; 1052 } 1053 1054 static const struct file_operations xsdfec_fops = { 1055 .owner = THIS_MODULE, 1056 .open = xsdfec_dev_open, 1057 .release = xsdfec_dev_release, 1058 .unlocked_ioctl = xsdfec_dev_ioctl, 1059 .poll = xsdfec_poll, 1060 #ifdef CONFIG_COMPAT 1061 .compat_ioctl = xsdfec_dev_compat_ioctl, 1062 #endif 1063 }; 1064 1065 static int xsdfec_parse_of(struct xsdfec_dev *xsdfec) 1066 { 1067 struct device *dev = xsdfec->dev; 1068 struct device_node *node = dev->of_node; 1069 int rval; 1070 const char *fec_code; 1071 u32 din_width; 1072 u32 din_word_include; 1073 u32 dout_width; 1074 u32 dout_word_include; 1075 1076 rval = of_property_read_string(node, "xlnx,sdfec-code", &fec_code); 1077 if (rval < 0) 1078 return rval; 1079 1080 if (!strcasecmp(fec_code, "ldpc")) 1081 xsdfec->config.code = XSDFEC_LDPC_CODE; 1082 else if (!strcasecmp(fec_code, "turbo")) 1083 xsdfec->config.code = XSDFEC_TURBO_CODE; 1084 else 1085 return -EINVAL; 1086 1087 rval = of_property_read_u32(node, "xlnx,sdfec-din-words", 1088 &din_word_include); 1089 if (rval < 0) 1090 return rval; 1091 1092 if (din_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX) 1093 xsdfec->config.din_word_include = din_word_include; 1094 else 1095 return -EINVAL; 1096 1097 rval = of_property_read_u32(node, "xlnx,sdfec-din-width", &din_width); 1098 if (rval < 0) 1099 return rval; 1100 1101 switch (din_width) { 1102 /* Fall through and set for valid values */ 1103 case XSDFEC_1x128b: 1104 case XSDFEC_2x128b: 1105 case XSDFEC_4x128b: 1106 xsdfec->config.din_width = din_width; 1107 break; 1108 default: 1109 return -EINVAL; 1110 } 1111 1112 rval = of_property_read_u32(node, "xlnx,sdfec-dout-words", 1113 &dout_word_include); 1114 if (rval < 0) 1115 return rval; 1116 1117 if (dout_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX) 1118 xsdfec->config.dout_word_include = dout_word_include; 1119 else 1120 return -EINVAL; 1121 1122 rval = of_property_read_u32(node, "xlnx,sdfec-dout-width", &dout_width); 1123 if (rval < 0) 1124 return rval; 1125 1126 switch (dout_width) { 1127 /* Fall through and set for valid values */ 1128 case XSDFEC_1x128b: 1129 case XSDFEC_2x128b: 1130 case XSDFEC_4x128b: 1131 xsdfec->config.dout_width = dout_width; 1132 break; 1133 default: 1134 return -EINVAL; 1135 } 1136 1137 /* Write LDPC to CODE Register */ 1138 xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, xsdfec->config.code); 1139 1140 xsdfec_cfg_axi_streams(xsdfec); 1141 1142 return 0; 1143 } 1144 1145 static irqreturn_t xsdfec_irq_thread(int irq, void *dev_id) 1146 { 1147 struct xsdfec_dev *xsdfec = dev_id; 1148 irqreturn_t ret = IRQ_HANDLED; 1149 u32 ecc_err; 1150 u32 isr_err; 1151 u32 uecc_count; 1152 u32 cecc_count; 1153 u32 isr_err_count; 1154 u32 aecc_count; 1155 u32 tmp; 1156 1157 WARN_ON(xsdfec->irq != irq); 1158 1159 /* Mask Interrupts */ 1160 xsdfec_isr_enable(xsdfec, false); 1161 xsdfec_ecc_isr_enable(xsdfec, false); 1162 /* Read ISR */ 1163 ecc_err = xsdfec_regread(xsdfec, XSDFEC_ECC_ISR_ADDR); 1164 isr_err = xsdfec_regread(xsdfec, XSDFEC_ISR_ADDR); 1165 /* Clear the interrupts */ 1166 xsdfec_regwrite(xsdfec, XSDFEC_ECC_ISR_ADDR, ecc_err); 1167 xsdfec_regwrite(xsdfec, XSDFEC_ISR_ADDR, isr_err); 1168 1169 tmp = ecc_err & XSDFEC_ALL_ECC_ISR_MBE_MASK; 1170 /* Count uncorrectable 2-bit errors */ 1171 uecc_count = hweight32(tmp); 1172 /* Count all ECC errors */ 1173 aecc_count = hweight32(ecc_err); 1174 /* Number of correctable 1-bit ECC error */ 1175 cecc_count = aecc_count - 2 * uecc_count; 1176 /* Count ISR errors */ 1177 isr_err_count = hweight32(isr_err); 1178 dev_dbg(xsdfec->dev, "tmp=%x, uecc=%x, aecc=%x, cecc=%x, isr=%x", tmp, 1179 uecc_count, aecc_count, cecc_count, isr_err_count); 1180 dev_dbg(xsdfec->dev, "uecc=%x, cecc=%x, isr=%x", xsdfec->uecc_count, 1181 xsdfec->cecc_count, xsdfec->isr_err_count); 1182 1183 spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags); 1184 /* Add new errors to a 2-bits counter */ 1185 if (uecc_count) 1186 xsdfec->uecc_count += uecc_count; 1187 /* Add new errors to a 1-bits counter */ 1188 if (cecc_count) 1189 xsdfec->cecc_count += cecc_count; 1190 /* Add new errors to a ISR counter */ 1191 if (isr_err_count) 1192 xsdfec->isr_err_count += isr_err_count; 1193 1194 /* Update state/stats flag */ 1195 if (uecc_count) { 1196 if (ecc_err & XSDFEC_ECC_ISR_MBE_MASK) 1197 xsdfec->state = XSDFEC_NEEDS_RESET; 1198 else if (ecc_err & XSDFEC_PL_INIT_ECC_ISR_MBE_MASK) 1199 xsdfec->state = XSDFEC_PL_RECONFIGURE; 1200 xsdfec->stats_updated = true; 1201 xsdfec->state_updated = true; 1202 } 1203 1204 if (cecc_count) 1205 xsdfec->stats_updated = true; 1206 1207 if (isr_err_count) { 1208 xsdfec->state = XSDFEC_NEEDS_RESET; 1209 xsdfec->stats_updated = true; 1210 xsdfec->state_updated = true; 1211 } 1212 1213 spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags); 1214 dev_dbg(xsdfec->dev, "state=%x, stats=%x", xsdfec->state_updated, 1215 xsdfec->stats_updated); 1216 1217 /* Enable another polling */ 1218 if (xsdfec->state_updated || xsdfec->stats_updated) 1219 wake_up_interruptible(&xsdfec->waitq); 1220 else 1221 ret = IRQ_NONE; 1222 1223 /* Unmask Interrupts */ 1224 xsdfec_isr_enable(xsdfec, true); 1225 xsdfec_ecc_isr_enable(xsdfec, true); 1226 1227 return ret; 1228 } 1229 1230 static int xsdfec_clk_init(struct platform_device *pdev, 1231 struct xsdfec_clks *clks) 1232 { 1233 int err; 1234 1235 clks->core_clk = devm_clk_get(&pdev->dev, "core_clk"); 1236 if (IS_ERR(clks->core_clk)) { 1237 dev_err(&pdev->dev, "failed to get core_clk"); 1238 return PTR_ERR(clks->core_clk); 1239 } 1240 1241 clks->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 1242 if (IS_ERR(clks->axi_clk)) { 1243 dev_err(&pdev->dev, "failed to get axi_clk"); 1244 return PTR_ERR(clks->axi_clk); 1245 } 1246 1247 clks->din_words_clk = devm_clk_get(&pdev->dev, "s_axis_din_words_aclk"); 1248 if (IS_ERR(clks->din_words_clk)) { 1249 if (PTR_ERR(clks->din_words_clk) != -ENOENT) { 1250 err = PTR_ERR(clks->din_words_clk); 1251 return err; 1252 } 1253 clks->din_words_clk = NULL; 1254 } 1255 1256 clks->din_clk = devm_clk_get(&pdev->dev, "s_axis_din_aclk"); 1257 if (IS_ERR(clks->din_clk)) { 1258 if (PTR_ERR(clks->din_clk) != -ENOENT) { 1259 err = PTR_ERR(clks->din_clk); 1260 return err; 1261 } 1262 clks->din_clk = NULL; 1263 } 1264 1265 clks->dout_clk = devm_clk_get(&pdev->dev, "m_axis_dout_aclk"); 1266 if (IS_ERR(clks->dout_clk)) { 1267 if (PTR_ERR(clks->dout_clk) != -ENOENT) { 1268 err = PTR_ERR(clks->dout_clk); 1269 return err; 1270 } 1271 clks->dout_clk = NULL; 1272 } 1273 1274 clks->dout_words_clk = 1275 devm_clk_get(&pdev->dev, "s_axis_dout_words_aclk"); 1276 if (IS_ERR(clks->dout_words_clk)) { 1277 if (PTR_ERR(clks->dout_words_clk) != -ENOENT) { 1278 err = PTR_ERR(clks->dout_words_clk); 1279 return err; 1280 } 1281 clks->dout_words_clk = NULL; 1282 } 1283 1284 clks->ctrl_clk = devm_clk_get(&pdev->dev, "s_axis_ctrl_aclk"); 1285 if (IS_ERR(clks->ctrl_clk)) { 1286 if (PTR_ERR(clks->ctrl_clk) != -ENOENT) { 1287 err = PTR_ERR(clks->ctrl_clk); 1288 return err; 1289 } 1290 clks->ctrl_clk = NULL; 1291 } 1292 1293 clks->status_clk = devm_clk_get(&pdev->dev, "m_axis_status_aclk"); 1294 if (IS_ERR(clks->status_clk)) { 1295 if (PTR_ERR(clks->status_clk) != -ENOENT) { 1296 err = PTR_ERR(clks->status_clk); 1297 return err; 1298 } 1299 clks->status_clk = NULL; 1300 } 1301 1302 err = clk_prepare_enable(clks->core_clk); 1303 if (err) { 1304 dev_err(&pdev->dev, "failed to enable core_clk (%d)", err); 1305 return err; 1306 } 1307 1308 err = clk_prepare_enable(clks->axi_clk); 1309 if (err) { 1310 dev_err(&pdev->dev, "failed to enable axi_clk (%d)", err); 1311 goto err_disable_core_clk; 1312 } 1313 1314 err = clk_prepare_enable(clks->din_clk); 1315 if (err) { 1316 dev_err(&pdev->dev, "failed to enable din_clk (%d)", err); 1317 goto err_disable_axi_clk; 1318 } 1319 1320 err = clk_prepare_enable(clks->din_words_clk); 1321 if (err) { 1322 dev_err(&pdev->dev, "failed to enable din_words_clk (%d)", err); 1323 goto err_disable_din_clk; 1324 } 1325 1326 err = clk_prepare_enable(clks->dout_clk); 1327 if (err) { 1328 dev_err(&pdev->dev, "failed to enable dout_clk (%d)", err); 1329 goto err_disable_din_words_clk; 1330 } 1331 1332 err = clk_prepare_enable(clks->dout_words_clk); 1333 if (err) { 1334 dev_err(&pdev->dev, "failed to enable dout_words_clk (%d)", 1335 err); 1336 goto err_disable_dout_clk; 1337 } 1338 1339 err = clk_prepare_enable(clks->ctrl_clk); 1340 if (err) { 1341 dev_err(&pdev->dev, "failed to enable ctrl_clk (%d)", err); 1342 goto err_disable_dout_words_clk; 1343 } 1344 1345 err = clk_prepare_enable(clks->status_clk); 1346 if (err) { 1347 dev_err(&pdev->dev, "failed to enable status_clk (%d)\n", err); 1348 goto err_disable_ctrl_clk; 1349 } 1350 1351 return err; 1352 1353 err_disable_ctrl_clk: 1354 clk_disable_unprepare(clks->ctrl_clk); 1355 err_disable_dout_words_clk: 1356 clk_disable_unprepare(clks->dout_words_clk); 1357 err_disable_dout_clk: 1358 clk_disable_unprepare(clks->dout_clk); 1359 err_disable_din_words_clk: 1360 clk_disable_unprepare(clks->din_words_clk); 1361 err_disable_din_clk: 1362 clk_disable_unprepare(clks->din_clk); 1363 err_disable_axi_clk: 1364 clk_disable_unprepare(clks->axi_clk); 1365 err_disable_core_clk: 1366 clk_disable_unprepare(clks->core_clk); 1367 1368 return err; 1369 } 1370 1371 static void xsdfec_disable_all_clks(struct xsdfec_clks *clks) 1372 { 1373 clk_disable_unprepare(clks->status_clk); 1374 clk_disable_unprepare(clks->ctrl_clk); 1375 clk_disable_unprepare(clks->dout_words_clk); 1376 clk_disable_unprepare(clks->dout_clk); 1377 clk_disable_unprepare(clks->din_words_clk); 1378 clk_disable_unprepare(clks->din_clk); 1379 clk_disable_unprepare(clks->core_clk); 1380 clk_disable_unprepare(clks->axi_clk); 1381 } 1382 1383 static int xsdfec_probe(struct platform_device *pdev) 1384 { 1385 struct xsdfec_dev *xsdfec; 1386 struct device *dev; 1387 struct resource *res; 1388 int err; 1389 bool irq_enabled = true; 1390 1391 xsdfec = devm_kzalloc(&pdev->dev, sizeof(*xsdfec), GFP_KERNEL); 1392 if (!xsdfec) 1393 return -ENOMEM; 1394 1395 xsdfec->dev = &pdev->dev; 1396 spin_lock_init(&xsdfec->error_data_lock); 1397 1398 err = xsdfec_clk_init(pdev, &xsdfec->clks); 1399 if (err) 1400 return err; 1401 1402 dev = xsdfec->dev; 1403 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1404 xsdfec->regs = devm_ioremap_resource(dev, res); 1405 if (IS_ERR(xsdfec->regs)) { 1406 err = PTR_ERR(xsdfec->regs); 1407 goto err_xsdfec_dev; 1408 } 1409 1410 xsdfec->irq = platform_get_irq(pdev, 0); 1411 if (xsdfec->irq < 0) { 1412 dev_dbg(dev, "platform_get_irq failed"); 1413 irq_enabled = false; 1414 } 1415 1416 err = xsdfec_parse_of(xsdfec); 1417 if (err < 0) 1418 goto err_xsdfec_dev; 1419 1420 update_config_from_hw(xsdfec); 1421 1422 /* Save driver private data */ 1423 platform_set_drvdata(pdev, xsdfec); 1424 1425 if (irq_enabled) { 1426 init_waitqueue_head(&xsdfec->waitq); 1427 /* Register IRQ thread */ 1428 err = devm_request_threaded_irq(dev, xsdfec->irq, NULL, 1429 xsdfec_irq_thread, IRQF_ONESHOT, 1430 "xilinx-sdfec16", xsdfec); 1431 if (err < 0) { 1432 dev_err(dev, "unable to request IRQ%d", xsdfec->irq); 1433 goto err_xsdfec_dev; 1434 } 1435 } 1436 1437 err = ida_alloc(&dev_nrs, GFP_KERNEL); 1438 if (err < 0) 1439 goto err_xsdfec_dev; 1440 xsdfec->dev_id = err; 1441 1442 snprintf(xsdfec->dev_name, DEV_NAME_LEN, "xsdfec%d", xsdfec->dev_id); 1443 xsdfec->miscdev.minor = MISC_DYNAMIC_MINOR; 1444 xsdfec->miscdev.name = xsdfec->dev_name; 1445 xsdfec->miscdev.fops = &xsdfec_fops; 1446 xsdfec->miscdev.parent = dev; 1447 err = misc_register(&xsdfec->miscdev); 1448 if (err) { 1449 dev_err(dev, "error:%d. Unable to register device", err); 1450 goto err_xsdfec_ida; 1451 } 1452 return 0; 1453 1454 err_xsdfec_ida: 1455 ida_free(&dev_nrs, xsdfec->dev_id); 1456 err_xsdfec_dev: 1457 xsdfec_disable_all_clks(&xsdfec->clks); 1458 return err; 1459 } 1460 1461 static int xsdfec_remove(struct platform_device *pdev) 1462 { 1463 struct xsdfec_dev *xsdfec; 1464 1465 xsdfec = platform_get_drvdata(pdev); 1466 misc_deregister(&xsdfec->miscdev); 1467 ida_free(&dev_nrs, xsdfec->dev_id); 1468 xsdfec_disable_all_clks(&xsdfec->clks); 1469 return 0; 1470 } 1471 1472 static const struct of_device_id xsdfec_of_match[] = { 1473 { 1474 .compatible = "xlnx,sd-fec-1.1", 1475 }, 1476 { /* end of table */ } 1477 }; 1478 MODULE_DEVICE_TABLE(of, xsdfec_of_match); 1479 1480 static struct platform_driver xsdfec_driver = { 1481 .driver = { 1482 .name = "xilinx-sdfec", 1483 .of_match_table = xsdfec_of_match, 1484 }, 1485 .probe = xsdfec_probe, 1486 .remove = xsdfec_remove, 1487 }; 1488 1489 module_platform_driver(xsdfec_driver); 1490 1491 MODULE_AUTHOR("Xilinx, Inc"); 1492 MODULE_DESCRIPTION("Xilinx SD-FEC16 Driver"); 1493 MODULE_LICENSE("GPL"); 1494