1 /* 2 * linux/drivers/message/fusion/mptbase.c 3 * This is the Fusion MPT base driver which supports multiple 4 * (SCSI + LAN) specialized protocol drivers. 5 * For use with LSI PCI chip/adapter(s) 6 * running LSI Fusion MPT (Message Passing Technology) firmware. 7 * 8 * Copyright (c) 1999-2008 LSI Corporation 9 * (mailto:[email protected]) 10 * 11 */ 12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 13 /* 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; version 2 of the License. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 NO WARRANTY 24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 28 solely responsible for determining the appropriateness of using and 29 distributing the Program and assumes all risks associated with its 30 exercise of rights under this Agreement, including but not limited to 31 the risks and costs of program errors, damage to or loss of data, 32 programs or equipment, and unavailability or interruption of operations. 33 34 DISCLAIMER OF LIABILITY 35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 42 43 You should have received a copy of the GNU General Public License 44 along with this program; if not, write to the Free Software 45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 46 */ 47 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 48 49 #include <linux/kernel.h> 50 #include <linux/module.h> 51 #include <linux/errno.h> 52 #include <linux/init.h> 53 #include <linux/seq_file.h> 54 #include <linux/slab.h> 55 #include <linux/types.h> 56 #include <linux/pci.h> 57 #include <linux/kdev_t.h> 58 #include <linux/blkdev.h> 59 #include <linux/delay.h> 60 #include <linux/interrupt.h> 61 #include <linux/dma-mapping.h> 62 #include <linux/kthread.h> 63 #include <scsi/scsi_host.h> 64 65 #include "mptbase.h" 66 #include "lsi/mpi_log_fc.h" 67 68 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 69 #define my_NAME "Fusion MPT base driver" 70 #define my_VERSION MPT_LINUX_VERSION_COMMON 71 #define MYNAM "mptbase" 72 73 MODULE_AUTHOR(MODULEAUTHOR); 74 MODULE_DESCRIPTION(my_NAME); 75 MODULE_LICENSE("GPL"); 76 MODULE_VERSION(my_VERSION); 77 78 /* 79 * cmd line parameters 80 */ 81 82 static int mpt_msi_enable_spi; 83 module_param(mpt_msi_enable_spi, int, 0); 84 MODULE_PARM_DESC(mpt_msi_enable_spi, 85 " Enable MSI Support for SPI controllers (default=0)"); 86 87 static int mpt_msi_enable_fc; 88 module_param(mpt_msi_enable_fc, int, 0); 89 MODULE_PARM_DESC(mpt_msi_enable_fc, 90 " Enable MSI Support for FC controllers (default=0)"); 91 92 static int mpt_msi_enable_sas; 93 module_param(mpt_msi_enable_sas, int, 0); 94 MODULE_PARM_DESC(mpt_msi_enable_sas, 95 " Enable MSI Support for SAS controllers (default=0)"); 96 97 static int mpt_channel_mapping; 98 module_param(mpt_channel_mapping, int, 0); 99 MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)"); 100 101 static int mpt_debug_level; 102 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp); 103 module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int, 104 &mpt_debug_level, 0600); 105 MODULE_PARM_DESC(mpt_debug_level, 106 " debug level - refer to mptdebug.h - (default=0)"); 107 108 int mpt_fwfault_debug; 109 EXPORT_SYMBOL(mpt_fwfault_debug); 110 module_param(mpt_fwfault_debug, int, 0600); 111 MODULE_PARM_DESC(mpt_fwfault_debug, 112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)"); 113 114 static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS] 115 [MPT_MAX_CALLBACKNAME_LEN+1]; 116 117 #ifdef MFCNT 118 static int mfcounter = 0; 119 #define PRINT_MF_COUNT 20000 120 #endif 121 122 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 123 /* 124 * Public data... 125 */ 126 127 #define WHOINIT_UNKNOWN 0xAA 128 129 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 130 /* 131 * Private data... 132 */ 133 /* Adapter link list */ 134 LIST_HEAD(ioc_list); 135 /* Callback lookup table */ 136 static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS]; 137 /* Protocol driver class lookup table */ 138 static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS]; 139 /* Event handler lookup table */ 140 static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 141 /* Reset handler lookup table */ 142 static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 143 static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 144 145 #ifdef CONFIG_PROC_FS 146 static struct proc_dir_entry *mpt_proc_root_dir; 147 #endif 148 149 /* 150 * Driver Callback Index's 151 */ 152 static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS; 153 static u8 last_drv_idx; 154 155 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 156 /* 157 * Forward protos... 158 */ 159 static irqreturn_t mpt_interrupt(int irq, void *bus_id); 160 static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, 161 MPT_FRAME_HDR *reply); 162 static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, 163 u32 *req, int replyBytes, u16 *u16reply, int maxwait, 164 int sleepFlag); 165 static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag); 166 static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev); 167 static void mpt_adapter_disable(MPT_ADAPTER *ioc); 168 static void mpt_adapter_dispose(MPT_ADAPTER *ioc); 169 170 static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc); 171 static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag); 172 static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason); 173 static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 174 static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag); 175 static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 176 static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag); 177 static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag); 178 static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 179 static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 180 static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag); 181 static int PrimeIocFifos(MPT_ADAPTER *ioc); 182 static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 183 static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 184 static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 185 static int GetLanConfigPages(MPT_ADAPTER *ioc); 186 static int GetIoUnitPage2(MPT_ADAPTER *ioc); 187 int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode); 188 static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum); 189 static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum); 190 static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc); 191 static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc); 192 static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc); 193 static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, 194 int sleepFlag); 195 static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp); 196 static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag); 197 static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init); 198 199 #ifdef CONFIG_PROC_FS 200 static int mpt_summary_proc_show(struct seq_file *m, void *v); 201 static int mpt_version_proc_show(struct seq_file *m, void *v); 202 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v); 203 #endif 204 static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc); 205 206 static int ProcessEventNotification(MPT_ADAPTER *ioc, 207 EventNotificationReply_t *evReply, int *evHandlers); 208 static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf); 209 static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info); 210 static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info); 211 static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx); 212 static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc); 213 static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc); 214 215 /* module entry point */ 216 static int __init fusion_init (void); 217 static void __exit fusion_exit (void); 218 219 #define CHIPREG_READ32(addr) readl_relaxed(addr) 220 #define CHIPREG_READ32_dmasync(addr) readl(addr) 221 #define CHIPREG_WRITE32(addr,val) writel(val, addr) 222 #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr) 223 #define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr) 224 225 static void 226 pci_disable_io_access(struct pci_dev *pdev) 227 { 228 u16 command_reg; 229 230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 231 command_reg &= ~1; 232 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 233 } 234 235 static void 236 pci_enable_io_access(struct pci_dev *pdev) 237 { 238 u16 command_reg; 239 240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 241 command_reg |= 1; 242 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 243 } 244 245 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp) 246 { 247 int ret = param_set_int(val, kp); 248 MPT_ADAPTER *ioc; 249 250 if (ret) 251 return ret; 252 253 list_for_each_entry(ioc, &ioc_list, list) 254 ioc->debug_level = mpt_debug_level; 255 return 0; 256 } 257 258 /** 259 * mpt_get_cb_idx - obtain cb_idx for registered driver 260 * @dclass: class driver enum 261 * 262 * Returns cb_idx, or zero means it wasn't found 263 **/ 264 static u8 265 mpt_get_cb_idx(MPT_DRIVER_CLASS dclass) 266 { 267 u8 cb_idx; 268 269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) 270 if (MptDriverClass[cb_idx] == dclass) 271 return cb_idx; 272 return 0; 273 } 274 275 /** 276 * mpt_is_discovery_complete - determine if discovery has completed 277 * @ioc: per adatper instance 278 * 279 * Returns 1 when discovery completed, else zero. 280 */ 281 static int 282 mpt_is_discovery_complete(MPT_ADAPTER *ioc) 283 { 284 ConfigExtendedPageHeader_t hdr; 285 CONFIGPARMS cfg; 286 SasIOUnitPage0_t *buffer; 287 dma_addr_t dma_handle; 288 int rc = 0; 289 290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t)); 291 memset(&cfg, 0, sizeof(CONFIGPARMS)); 292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION; 293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; 295 cfg.cfghdr.ehdr = &hdr; 296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 297 298 if ((mpt_config(ioc, &cfg))) 299 goto out; 300 if (!hdr.ExtPageLength) 301 goto out; 302 303 buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 304 &dma_handle); 305 if (!buffer) 306 goto out; 307 308 cfg.physAddr = dma_handle; 309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 310 311 if ((mpt_config(ioc, &cfg))) 312 goto out_free_consistent; 313 314 if (!(buffer->PhyData[0].PortFlags & 315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS)) 316 rc = 1; 317 318 out_free_consistent: 319 dma_free_coherent(&ioc->pcidev->dev, hdr.ExtPageLength * 4, buffer, 320 dma_handle); 321 out: 322 return rc; 323 } 324 325 326 /** 327 * mpt_remove_dead_ioc_func - kthread context to remove dead ioc 328 * @arg: input argument, used to derive ioc 329 * 330 * Return 0 if controller is removed from pci subsystem. 331 * Return -1 for other case. 332 */ 333 static int mpt_remove_dead_ioc_func(void *arg) 334 { 335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; 336 struct pci_dev *pdev; 337 338 if (!ioc) 339 return -1; 340 341 pdev = ioc->pcidev; 342 if (!pdev) 343 return -1; 344 345 pci_stop_and_remove_bus_device_locked(pdev); 346 return 0; 347 } 348 349 350 351 /** 352 * mpt_fault_reset_work - work performed on workq after ioc fault 353 * @work: input argument, used to derive ioc 354 * 355 **/ 356 static void 357 mpt_fault_reset_work(struct work_struct *work) 358 { 359 MPT_ADAPTER *ioc = 360 container_of(work, MPT_ADAPTER, fault_reset_work.work); 361 u32 ioc_raw_state; 362 int rc; 363 unsigned long flags; 364 MPT_SCSI_HOST *hd; 365 struct task_struct *p; 366 367 if (ioc->ioc_reset_in_progress || !ioc->active) 368 goto out; 369 370 371 ioc_raw_state = mpt_GetIocState(ioc, 0); 372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) { 373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n", 374 ioc->name, __func__); 375 376 /* 377 * Call mptscsih_flush_pending_cmds callback so that we 378 * flush all pending commands back to OS. 379 * This call is required to aovid deadlock at block layer. 380 * Dead IOC will fail to do diag reset,and this call is safe 381 * since dead ioc will never return any command back from HW. 382 */ 383 hd = shost_priv(ioc->sh); 384 ioc->schedule_dead_ioc_flush_running_cmds(hd); 385 386 /*Remove the Dead Host */ 387 p = kthread_run(mpt_remove_dead_ioc_func, ioc, 388 "mpt_dead_ioc_%d", ioc->id); 389 if (IS_ERR(p)) { 390 printk(MYIOC_s_ERR_FMT 391 "%s: Running mpt_dead_ioc thread failed !\n", 392 ioc->name, __func__); 393 } else { 394 printk(MYIOC_s_WARN_FMT 395 "%s: Running mpt_dead_ioc thread success !\n", 396 ioc->name, __func__); 397 } 398 return; /* don't rearm timer */ 399 } 400 401 if ((ioc_raw_state & MPI_IOC_STATE_MASK) 402 == MPI_IOC_STATE_FAULT) { 403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n", 404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n", 406 ioc->name, __func__); 407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP); 408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name, 409 __func__, (rc == 0) ? "success" : "failed"); 410 ioc_raw_state = mpt_GetIocState(ioc, 0); 411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) 412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after " 413 "reset (%04xh)\n", ioc->name, ioc_raw_state & 414 MPI_DOORBELL_DATA_MASK); 415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) { 416 if ((mpt_is_discovery_complete(ioc))) { 417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing " 418 "discovery_quiesce_io flag\n", ioc->name)); 419 ioc->sas_discovery_quiesce_io = 0; 420 } 421 } 422 423 out: 424 /* 425 * Take turns polling alternate controller 426 */ 427 if (ioc->alt_ioc) 428 ioc = ioc->alt_ioc; 429 430 /* rearm the timer */ 431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 432 if (ioc->reset_work_q) 433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 434 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 436 } 437 438 439 /* 440 * Process turbo (context) reply... 441 */ 442 static void 443 mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa) 444 { 445 MPT_FRAME_HDR *mf = NULL; 446 MPT_FRAME_HDR *mr = NULL; 447 u16 req_idx = 0; 448 u8 cb_idx; 449 450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n", 451 ioc->name, pa)); 452 453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) { 454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT: 455 req_idx = pa & 0x0000FFFF; 456 cb_idx = (pa & 0x00FF0000) >> 16; 457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 458 break; 459 case MPI_CONTEXT_REPLY_TYPE_LAN: 460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER); 461 /* 462 * Blind set of mf to NULL here was fatal 463 * after lan_reply says "freeme" 464 * Fix sort of combined with an optimization here; 465 * added explicit check for case where lan_reply 466 * was just returning 1 and doing nothing else. 467 * For this case skip the callback, but set up 468 * proper mf value first here:-) 469 */ 470 if ((pa & 0x58000000) == 0x58000000) { 471 req_idx = pa & 0x0000FFFF; 472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 473 mpt_free_msg_frame(ioc, mf); 474 mb(); 475 return; 476 } 477 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 478 break; 479 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET: 480 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER); 481 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 482 break; 483 default: 484 cb_idx = 0; 485 BUG(); 486 } 487 488 /* Check for (valid) IO callback! */ 489 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 490 MptCallbacks[cb_idx] == NULL) { 491 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 492 __func__, ioc->name, cb_idx); 493 goto out; 494 } 495 496 if (MptCallbacks[cb_idx](ioc, mf, mr)) 497 mpt_free_msg_frame(ioc, mf); 498 out: 499 mb(); 500 } 501 502 static void 503 mpt_reply(MPT_ADAPTER *ioc, u32 pa) 504 { 505 MPT_FRAME_HDR *mf; 506 MPT_FRAME_HDR *mr; 507 u16 req_idx; 508 u8 cb_idx; 509 int freeme; 510 511 u32 reply_dma_low; 512 u16 ioc_stat; 513 514 /* non-TURBO reply! Hmmm, something may be up... 515 * Newest turbo reply mechanism; get address 516 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)! 517 */ 518 519 /* Map DMA address of reply header to cpu address. 520 * pa is 32 bits - but the dma address may be 32 or 64 bits 521 * get offset based only only the low addresses 522 */ 523 524 reply_dma_low = (pa <<= 1); 525 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames + 526 (reply_dma_low - ioc->reply_frames_low_dma)); 527 528 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx); 529 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx; 530 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 531 532 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n", 533 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function)); 534 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr); 535 536 /* Check/log IOC log info 537 */ 538 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus); 539 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 540 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo); 541 if (ioc->bus_type == FC) 542 mpt_fc_log_info(ioc, log_info); 543 else if (ioc->bus_type == SPI) 544 mpt_spi_log_info(ioc, log_info); 545 else if (ioc->bus_type == SAS) 546 mpt_sas_log_info(ioc, log_info, cb_idx); 547 } 548 549 if (ioc_stat & MPI_IOCSTATUS_MASK) 550 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf); 551 552 /* Check for (valid) IO callback! */ 553 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 554 MptCallbacks[cb_idx] == NULL) { 555 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 556 __func__, ioc->name, cb_idx); 557 freeme = 0; 558 goto out; 559 } 560 561 freeme = MptCallbacks[cb_idx](ioc, mf, mr); 562 563 out: 564 /* Flush (non-TURBO) reply with a WRITE! */ 565 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa); 566 567 if (freeme) 568 mpt_free_msg_frame(ioc, mf); 569 mb(); 570 } 571 572 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 573 /** 574 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler. 575 * @irq: irq number (not used) 576 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 577 * 578 * This routine is registered via the request_irq() kernel API call, 579 * and handles all interrupts generated from a specific MPT adapter 580 * (also referred to as a IO Controller or IOC). 581 * This routine must clear the interrupt from the adapter and does 582 * so by reading the reply FIFO. Multiple replies may be processed 583 * per single call to this routine. 584 * 585 * This routine handles register-level access of the adapter but 586 * dispatches (calls) a protocol-specific callback routine to handle 587 * the protocol-specific details of the MPT request completion. 588 */ 589 static irqreturn_t 590 mpt_interrupt(int irq, void *bus_id) 591 { 592 MPT_ADAPTER *ioc = bus_id; 593 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 594 595 if (pa == 0xFFFFFFFF) 596 return IRQ_NONE; 597 598 /* 599 * Drain the reply FIFO! 600 */ 601 do { 602 if (pa & MPI_ADDRESS_REPLY_A_BIT) 603 mpt_reply(ioc, pa); 604 else 605 mpt_turbo_reply(ioc, pa); 606 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 607 } while (pa != 0xFFFFFFFF); 608 609 return IRQ_HANDLED; 610 } 611 612 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 613 /** 614 * mptbase_reply - MPT base driver's callback routine 615 * @ioc: Pointer to MPT_ADAPTER structure 616 * @req: Pointer to original MPT request frame 617 * @reply: Pointer to MPT reply frame (NULL if TurboReply) 618 * 619 * MPT base driver's callback routine; all base driver 620 * "internal" request/reply processing is routed here. 621 * Currently used for EventNotification and EventAck handling. 622 * 623 * Returns 1 indicating original alloc'd request frame ptr 624 * should be freed, or 0 if it shouldn't. 625 */ 626 static int 627 mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply) 628 { 629 EventNotificationReply_t *pEventReply; 630 u8 event; 631 int evHandlers; 632 int freereq = 1; 633 634 switch (reply->u.hdr.Function) { 635 case MPI_FUNCTION_EVENT_NOTIFICATION: 636 pEventReply = (EventNotificationReply_t *)reply; 637 evHandlers = 0; 638 ProcessEventNotification(ioc, pEventReply, &evHandlers); 639 event = le32_to_cpu(pEventReply->Event) & 0xFF; 640 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) 641 freereq = 0; 642 if (event != MPI_EVENT_EVENT_CHANGE) 643 break; 644 fallthrough; 645 case MPI_FUNCTION_CONFIG: 646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL: 647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; 648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID; 649 memcpy(ioc->mptbase_cmds.reply, reply, 650 min(MPT_DEFAULT_FRAME_SIZE, 651 4 * reply->u.reply.MsgLength)); 652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING; 654 complete(&ioc->mptbase_cmds.done); 655 } else 656 freereq = 0; 657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF) 658 freereq = 1; 659 break; 660 case MPI_FUNCTION_EVENT_ACK: 661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 662 "EventAck reply received\n", ioc->name)); 663 break; 664 default: 665 printk(MYIOC_s_ERR_FMT 666 "Unexpected msg function (=%02Xh) reply received!\n", 667 ioc->name, reply->u.hdr.Function); 668 break; 669 } 670 671 /* 672 * Conditionally tell caller to free the original 673 * EventNotification/EventAck/unexpected request frame! 674 */ 675 return freereq; 676 } 677 678 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 679 /** 680 * mpt_register - Register protocol-specific main callback handler. 681 * @cbfunc: callback function pointer 682 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value) 683 * @func_name: call function's name 684 * 685 * This routine is called by a protocol-specific driver (SCSI host, 686 * LAN, SCSI target) to register its reply callback routine. Each 687 * protocol-specific driver must do this before it will be able to 688 * use any IOC resources, such as obtaining request frames. 689 * 690 * NOTES: The SCSI protocol driver currently calls this routine thrice 691 * in order to register separate callbacks; one for "normal" SCSI IO; 692 * one for MptScsiTaskMgmt requests; one for Scan/DV requests. 693 * 694 * Returns u8 valued "handle" in the range (and S.O.D. order) 695 * {N,...,7,6,5,...,1} if successful. 696 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be 697 * considered an error by the caller. 698 */ 699 u8 700 mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name) 701 { 702 u8 cb_idx; 703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS; 704 705 /* 706 * Search for empty callback slot in this order: {N,...,7,6,5,...,1} 707 * (slot/handle 0 is reserved!) 708 */ 709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 710 if (MptCallbacks[cb_idx] == NULL) { 711 MptCallbacks[cb_idx] = cbfunc; 712 MptDriverClass[cb_idx] = dclass; 713 MptEvHandlers[cb_idx] = NULL; 714 last_drv_idx = cb_idx; 715 strlcpy(MptCallbacksName[cb_idx], func_name, 716 MPT_MAX_CALLBACKNAME_LEN+1); 717 break; 718 } 719 } 720 721 return last_drv_idx; 722 } 723 724 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 725 /** 726 * mpt_deregister - Deregister a protocol drivers resources. 727 * @cb_idx: previously registered callback handle 728 * 729 * Each protocol-specific driver should call this routine when its 730 * module is unloaded. 731 */ 732 void 733 mpt_deregister(u8 cb_idx) 734 { 735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) { 736 MptCallbacks[cb_idx] = NULL; 737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 738 MptEvHandlers[cb_idx] = NULL; 739 740 last_drv_idx++; 741 } 742 } 743 744 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 745 /** 746 * mpt_event_register - Register protocol-specific event callback handler. 747 * @cb_idx: previously registered (via mpt_register) callback handle 748 * @ev_cbfunc: callback function 749 * 750 * This routine can be called by one or more protocol-specific drivers 751 * if/when they choose to be notified of MPT events. 752 * 753 * Returns 0 for success. 754 */ 755 int 756 mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc) 757 { 758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 759 return -1; 760 761 MptEvHandlers[cb_idx] = ev_cbfunc; 762 return 0; 763 } 764 765 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 766 /** 767 * mpt_event_deregister - Deregister protocol-specific event callback handler 768 * @cb_idx: previously registered callback handle 769 * 770 * Each protocol-specific driver should call this routine 771 * when it does not (or can no longer) handle events, 772 * or when its module is unloaded. 773 */ 774 void 775 mpt_event_deregister(u8 cb_idx) 776 { 777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 778 return; 779 780 MptEvHandlers[cb_idx] = NULL; 781 } 782 783 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 784 /** 785 * mpt_reset_register - Register protocol-specific IOC reset handler. 786 * @cb_idx: previously registered (via mpt_register) callback handle 787 * @reset_func: reset function 788 * 789 * This routine can be called by one or more protocol-specific drivers 790 * if/when they choose to be notified of IOC resets. 791 * 792 * Returns 0 for success. 793 */ 794 int 795 mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func) 796 { 797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 798 return -1; 799 800 MptResetHandlers[cb_idx] = reset_func; 801 return 0; 802 } 803 804 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 805 /** 806 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler. 807 * @cb_idx: previously registered callback handle 808 * 809 * Each protocol-specific driver should call this routine 810 * when it does not (or can no longer) handle IOC reset handling, 811 * or when its module is unloaded. 812 */ 813 void 814 mpt_reset_deregister(u8 cb_idx) 815 { 816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 817 return; 818 819 MptResetHandlers[cb_idx] = NULL; 820 } 821 822 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 823 /** 824 * mpt_device_driver_register - Register device driver hooks 825 * @dd_cbfunc: driver callbacks struct 826 * @cb_idx: MPT protocol driver index 827 */ 828 int 829 mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx) 830 { 831 MPT_ADAPTER *ioc; 832 833 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 834 return -EINVAL; 835 836 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc; 837 838 /* call per pci device probe entry point */ 839 list_for_each_entry(ioc, &ioc_list, list) { 840 if (dd_cbfunc->probe) 841 dd_cbfunc->probe(ioc->pcidev); 842 } 843 844 return 0; 845 } 846 847 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 848 /** 849 * mpt_device_driver_deregister - DeRegister device driver hooks 850 * @cb_idx: MPT protocol driver index 851 */ 852 void 853 mpt_device_driver_deregister(u8 cb_idx) 854 { 855 struct mpt_pci_driver *dd_cbfunc; 856 MPT_ADAPTER *ioc; 857 858 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 859 return; 860 861 dd_cbfunc = MptDeviceDriverHandlers[cb_idx]; 862 863 list_for_each_entry(ioc, &ioc_list, list) { 864 if (dd_cbfunc->remove) 865 dd_cbfunc->remove(ioc->pcidev); 866 } 867 868 MptDeviceDriverHandlers[cb_idx] = NULL; 869 } 870 871 872 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 873 /** 874 * mpt_get_msg_frame - Obtain an MPT request frame from the pool 875 * @cb_idx: Handle of registered MPT protocol driver 876 * @ioc: Pointer to MPT adapter structure 877 * 878 * Obtain an MPT request frame from the pool (of 1024) that are 879 * allocated per MPT adapter. 880 * 881 * Returns pointer to a MPT request frame or %NULL if none are available 882 * or IOC is not active. 883 */ 884 MPT_FRAME_HDR* 885 mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc) 886 { 887 MPT_FRAME_HDR *mf; 888 unsigned long flags; 889 u16 req_idx; /* Request index */ 890 891 /* validate handle and ioc identifier */ 892 893 #ifdef MFCNT 894 if (!ioc->active) 895 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame " 896 "returning NULL!\n", ioc->name); 897 #endif 898 899 /* If interrupts are not attached, do not return a request frame */ 900 if (!ioc->active) 901 return NULL; 902 903 spin_lock_irqsave(&ioc->FreeQlock, flags); 904 if (!list_empty(&ioc->FreeQ)) { 905 int req_offset; 906 907 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR, 908 u.frame.linkage.list); 909 list_del(&mf->u.frame.linkage.list); 910 mf->u.frame.linkage.arg1 = 0; 911 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 912 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 913 /* u16! */ 914 req_idx = req_offset / ioc->req_sz; 915 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 916 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 917 /* Default, will be changed if necessary in SG generation */ 918 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame; 919 #ifdef MFCNT 920 ioc->mfcnt++; 921 #endif 922 } 923 else 924 mf = NULL; 925 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 926 927 #ifdef MFCNT 928 if (mf == NULL) 929 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! " 930 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt, 931 ioc->req_depth); 932 mfcounter++; 933 if (mfcounter == PRINT_MF_COUNT) 934 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name, 935 ioc->mfcnt, ioc->req_depth); 936 #endif 937 938 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n", 939 ioc->name, cb_idx, ioc->id, mf)); 940 return mf; 941 } 942 943 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 944 /** 945 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC 946 * @cb_idx: Handle of registered MPT protocol driver 947 * @ioc: Pointer to MPT adapter structure 948 * @mf: Pointer to MPT request frame 949 * 950 * This routine posts an MPT request frame to the request post FIFO of a 951 * specific MPT adapter. 952 */ 953 void 954 mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 955 { 956 u32 mf_dma_addr; 957 int req_offset; 958 u16 req_idx; /* Request index */ 959 960 /* ensure values are reset properly! */ 961 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 962 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 963 /* u16! */ 964 req_idx = req_offset / ioc->req_sz; 965 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 966 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 967 968 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 969 970 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx]; 971 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d " 972 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx, 973 ioc->RequestNB[req_idx])); 974 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr); 975 } 976 977 /** 978 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame 979 * @cb_idx: Handle of registered MPT protocol driver 980 * @ioc: Pointer to MPT adapter structure 981 * @mf: Pointer to MPT request frame 982 * 983 * Send a protocol-specific MPT request frame to an IOC using 984 * hi-priority request queue. 985 * 986 * This routine posts an MPT request frame to the request post FIFO of a 987 * specific MPT adapter. 988 **/ 989 void 990 mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 991 { 992 u32 mf_dma_addr; 993 int req_offset; 994 u16 req_idx; /* Request index */ 995 996 /* ensure values are reset properly! */ 997 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 998 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 999 req_idx = req_offset / ioc->req_sz; 1000 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 1001 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 1002 1003 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 1004 1005 mf_dma_addr = (ioc->req_frames_low_dma + req_offset); 1006 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n", 1007 ioc->name, mf_dma_addr, req_idx)); 1008 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr); 1009 } 1010 1011 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1012 /** 1013 * mpt_free_msg_frame - Place MPT request frame back on FreeQ. 1014 * @ioc: Pointer to MPT adapter structure 1015 * @mf: Pointer to MPT request frame 1016 * 1017 * This routine places a MPT request frame back on the MPT adapter's 1018 * FreeQ. 1019 */ 1020 void 1021 mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 1022 { 1023 unsigned long flags; 1024 1025 /* Put Request back on FreeQ! */ 1026 spin_lock_irqsave(&ioc->FreeQlock, flags); 1027 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf) 1028 goto out; 1029 /* signature to know if this mf is freed */ 1030 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf); 1031 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ); 1032 #ifdef MFCNT 1033 ioc->mfcnt--; 1034 #endif 1035 out: 1036 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 1037 } 1038 1039 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1040 /** 1041 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr. 1042 * @pAddr: virtual address for SGE 1043 * @flagslength: SGE flags and data transfer length 1044 * @dma_addr: Physical address 1045 * 1046 * This routine places a MPT request frame back on the MPT adapter's 1047 * FreeQ. 1048 */ 1049 static void 1050 mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1051 { 1052 SGESimple32_t *pSge = (SGESimple32_t *) pAddr; 1053 pSge->FlagsLength = cpu_to_le32(flagslength); 1054 pSge->Address = cpu_to_le32(dma_addr); 1055 } 1056 1057 /** 1058 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr. 1059 * @pAddr: virtual address for SGE 1060 * @flagslength: SGE flags and data transfer length 1061 * @dma_addr: Physical address 1062 * 1063 * This routine places a MPT request frame back on the MPT adapter's 1064 * FreeQ. 1065 **/ 1066 static void 1067 mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1068 { 1069 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1070 pSge->Address.Low = cpu_to_le32 1071 (lower_32_bits(dma_addr)); 1072 pSge->Address.High = cpu_to_le32 1073 (upper_32_bits(dma_addr)); 1074 pSge->FlagsLength = cpu_to_le32 1075 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1076 } 1077 1078 /** 1079 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround). 1080 * @pAddr: virtual address for SGE 1081 * @flagslength: SGE flags and data transfer length 1082 * @dma_addr: Physical address 1083 * 1084 * This routine places a MPT request frame back on the MPT adapter's 1085 * FreeQ. 1086 **/ 1087 static void 1088 mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1089 { 1090 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1091 u32 tmp; 1092 1093 pSge->Address.Low = cpu_to_le32 1094 (lower_32_bits(dma_addr)); 1095 tmp = (u32)(upper_32_bits(dma_addr)); 1096 1097 /* 1098 * 1078 errata workaround for the 36GB limitation 1099 */ 1100 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) { 1101 flagslength |= 1102 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS); 1103 tmp |= (1<<31); 1104 if (mpt_debug_level & MPT_DEBUG_36GB_MEM) 1105 printk(KERN_DEBUG "1078 P0M2 addressing for " 1106 "addr = 0x%llx len = %d\n", 1107 (unsigned long long)dma_addr, 1108 MPI_SGE_LENGTH(flagslength)); 1109 } 1110 1111 pSge->Address.High = cpu_to_le32(tmp); 1112 pSge->FlagsLength = cpu_to_le32( 1113 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1114 } 1115 1116 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1117 /** 1118 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr. 1119 * @pAddr: virtual address for SGE 1120 * @next: nextChainOffset value (u32's) 1121 * @length: length of next SGL segment 1122 * @dma_addr: Physical address 1123 * 1124 */ 1125 static void 1126 mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1127 { 1128 SGEChain32_t *pChain = (SGEChain32_t *) pAddr; 1129 1130 pChain->Length = cpu_to_le16(length); 1131 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT; 1132 pChain->NextChainOffset = next; 1133 pChain->Address = cpu_to_le32(dma_addr); 1134 } 1135 1136 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1137 /** 1138 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr. 1139 * @pAddr: virtual address for SGE 1140 * @next: nextChainOffset value (u32's) 1141 * @length: length of next SGL segment 1142 * @dma_addr: Physical address 1143 * 1144 */ 1145 static void 1146 mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1147 { 1148 SGEChain64_t *pChain = (SGEChain64_t *) pAddr; 1149 u32 tmp = dma_addr & 0xFFFFFFFF; 1150 1151 pChain->Length = cpu_to_le16(length); 1152 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT | 1153 MPI_SGE_FLAGS_64_BIT_ADDRESSING); 1154 1155 pChain->NextChainOffset = next; 1156 1157 pChain->Address.Low = cpu_to_le32(tmp); 1158 tmp = (u32)(upper_32_bits(dma_addr)); 1159 pChain->Address.High = cpu_to_le32(tmp); 1160 } 1161 1162 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1163 /** 1164 * mpt_send_handshake_request - Send MPT request via doorbell handshake method. 1165 * @cb_idx: Handle of registered MPT protocol driver 1166 * @ioc: Pointer to MPT adapter structure 1167 * @reqBytes: Size of the request in bytes 1168 * @req: Pointer to MPT request frame 1169 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 1170 * 1171 * This routine is used exclusively to send MptScsiTaskMgmt 1172 * requests since they are required to be sent via doorbell handshake. 1173 * 1174 * NOTE: It is the callers responsibility to byte-swap fields in the 1175 * request which are greater than 1 byte in size. 1176 * 1177 * Returns 0 for success, non-zero for failure. 1178 */ 1179 int 1180 mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag) 1181 { 1182 int r = 0; 1183 u8 *req_as_bytes; 1184 int ii; 1185 1186 /* State is known to be good upon entering 1187 * this function so issue the bus reset 1188 * request. 1189 */ 1190 1191 /* 1192 * Emulate what mpt_put_msg_frame() does /wrt to sanity 1193 * setting cb_idx/req_idx. But ONLY if this request 1194 * is in proper (pre-alloc'd) request buffer range... 1195 */ 1196 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req); 1197 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) { 1198 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req; 1199 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii); 1200 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 1201 } 1202 1203 /* Make sure there are no doorbells */ 1204 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1205 1206 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1207 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 1208 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 1209 1210 /* Wait for IOC doorbell int */ 1211 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) { 1212 return ii; 1213 } 1214 1215 /* Read doorbell and check for active bit */ 1216 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 1217 return -5; 1218 1219 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n", 1220 ioc->name, ii)); 1221 1222 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1223 1224 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1225 return -2; 1226 } 1227 1228 /* Send request via doorbell handshake */ 1229 req_as_bytes = (u8 *) req; 1230 for (ii = 0; ii < reqBytes/4; ii++) { 1231 u32 word; 1232 1233 word = ((req_as_bytes[(ii*4) + 0] << 0) | 1234 (req_as_bytes[(ii*4) + 1] << 8) | 1235 (req_as_bytes[(ii*4) + 2] << 16) | 1236 (req_as_bytes[(ii*4) + 3] << 24)); 1237 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 1238 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1239 r = -3; 1240 break; 1241 } 1242 } 1243 1244 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0) 1245 r = 0; 1246 else 1247 r = -4; 1248 1249 /* Make sure there are no doorbells */ 1250 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1251 1252 return r; 1253 } 1254 1255 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1256 /** 1257 * mpt_host_page_access_control - control the IOC's Host Page Buffer access 1258 * @ioc: Pointer to MPT adapter structure 1259 * @access_control_value: define bits below 1260 * @sleepFlag: Specifies whether the process can sleep 1261 * 1262 * Provides mechanism for the host driver to control the IOC's 1263 * Host Page Buffer access. 1264 * 1265 * Access Control Value - bits[15:12] 1266 * 0h Reserved 1267 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS } 1268 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS } 1269 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER } 1270 * 1271 * Returns 0 for success, non-zero for failure. 1272 */ 1273 1274 static int 1275 mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag) 1276 { 1277 /* return if in use */ 1278 if (CHIPREG_READ32(&ioc->chip->Doorbell) 1279 & MPI_DOORBELL_ACTIVE) 1280 return -1; 1281 1282 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1283 1284 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1285 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL 1286 <<MPI_DOORBELL_FUNCTION_SHIFT) | 1287 (access_control_value<<12))); 1288 1289 /* Wait for IOC to clear Doorbell Status bit */ 1290 if (WaitForDoorbellAck(ioc, 5, sleepFlag) < 0) 1291 return -2; 1292 else 1293 return 0; 1294 } 1295 1296 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1297 /** 1298 * mpt_host_page_alloc - allocate system memory for the fw 1299 * @ioc: Pointer to pointer to IOC adapter 1300 * @ioc_init: Pointer to ioc init config page 1301 * 1302 * If we already allocated memory in past, then resend the same pointer. 1303 * Returns 0 for success, non-zero for failure. 1304 */ 1305 static int 1306 mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init) 1307 { 1308 char *psge; 1309 int flags_length; 1310 u32 host_page_buffer_sz=0; 1311 1312 if(!ioc->HostPageBuffer) { 1313 1314 host_page_buffer_sz = 1315 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF; 1316 1317 if(!host_page_buffer_sz) 1318 return 0; /* fw doesn't need any host buffers */ 1319 1320 /* spin till we get enough memory */ 1321 while (host_page_buffer_sz > 0) { 1322 ioc->HostPageBuffer = 1323 dma_alloc_coherent(&ioc->pcidev->dev, 1324 host_page_buffer_sz, 1325 &ioc->HostPageBuffer_dma, 1326 GFP_KERNEL); 1327 if (ioc->HostPageBuffer) { 1328 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 1329 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n", 1330 ioc->name, ioc->HostPageBuffer, 1331 (u32)ioc->HostPageBuffer_dma, 1332 host_page_buffer_sz)); 1333 ioc->alloc_total += host_page_buffer_sz; 1334 ioc->HostPageBuffer_sz = host_page_buffer_sz; 1335 break; 1336 } 1337 1338 host_page_buffer_sz -= (4*1024); 1339 } 1340 } 1341 1342 if(!ioc->HostPageBuffer) { 1343 printk(MYIOC_s_ERR_FMT 1344 "Failed to alloc memory for host_page_buffer!\n", 1345 ioc->name); 1346 return -999; 1347 } 1348 1349 psge = (char *)&ioc_init->HostPageBufferSGE; 1350 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT | 1351 MPI_SGE_FLAGS_SYSTEM_ADDRESS | 1352 MPI_SGE_FLAGS_HOST_TO_IOC | 1353 MPI_SGE_FLAGS_END_OF_BUFFER; 1354 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT; 1355 flags_length |= ioc->HostPageBuffer_sz; 1356 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma); 1357 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE; 1358 1359 return 0; 1360 } 1361 1362 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1363 /** 1364 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure. 1365 * @iocid: IOC unique identifier (integer) 1366 * @iocpp: Pointer to pointer to IOC adapter 1367 * 1368 * Given a unique IOC identifier, set pointer to the associated MPT 1369 * adapter structure. 1370 * 1371 * Returns iocid and sets iocpp if iocid is found. 1372 * Returns -1 if iocid is not found. 1373 */ 1374 int 1375 mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp) 1376 { 1377 MPT_ADAPTER *ioc; 1378 1379 list_for_each_entry(ioc,&ioc_list,list) { 1380 if (ioc->id == iocid) { 1381 *iocpp =ioc; 1382 return iocid; 1383 } 1384 } 1385 1386 *iocpp = NULL; 1387 return -1; 1388 } 1389 1390 /** 1391 * mpt_get_product_name - returns product string 1392 * @vendor: pci vendor id 1393 * @device: pci device id 1394 * @revision: pci revision id 1395 * 1396 * Returns product string displayed when driver loads, 1397 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product 1398 * 1399 **/ 1400 static const char* 1401 mpt_get_product_name(u16 vendor, u16 device, u8 revision) 1402 { 1403 char *product_str = NULL; 1404 1405 if (vendor == PCI_VENDOR_ID_BROCADE) { 1406 switch (device) 1407 { 1408 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1409 switch (revision) 1410 { 1411 case 0x00: 1412 product_str = "BRE040 A0"; 1413 break; 1414 case 0x01: 1415 product_str = "BRE040 A1"; 1416 break; 1417 default: 1418 product_str = "BRE040"; 1419 break; 1420 } 1421 break; 1422 } 1423 goto out; 1424 } 1425 1426 switch (device) 1427 { 1428 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1429 product_str = "LSIFC909 B1"; 1430 break; 1431 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1432 product_str = "LSIFC919 B0"; 1433 break; 1434 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1435 product_str = "LSIFC929 B0"; 1436 break; 1437 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1438 if (revision < 0x80) 1439 product_str = "LSIFC919X A0"; 1440 else 1441 product_str = "LSIFC919XL A1"; 1442 break; 1443 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1444 if (revision < 0x80) 1445 product_str = "LSIFC929X A0"; 1446 else 1447 product_str = "LSIFC929XL A1"; 1448 break; 1449 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1450 product_str = "LSIFC939X A1"; 1451 break; 1452 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1453 product_str = "LSIFC949X A1"; 1454 break; 1455 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1456 switch (revision) 1457 { 1458 case 0x00: 1459 product_str = "LSIFC949E A0"; 1460 break; 1461 case 0x01: 1462 product_str = "LSIFC949E A1"; 1463 break; 1464 default: 1465 product_str = "LSIFC949E"; 1466 break; 1467 } 1468 break; 1469 case MPI_MANUFACTPAGE_DEVID_53C1030: 1470 switch (revision) 1471 { 1472 case 0x00: 1473 product_str = "LSI53C1030 A0"; 1474 break; 1475 case 0x01: 1476 product_str = "LSI53C1030 B0"; 1477 break; 1478 case 0x03: 1479 product_str = "LSI53C1030 B1"; 1480 break; 1481 case 0x07: 1482 product_str = "LSI53C1030 B2"; 1483 break; 1484 case 0x08: 1485 product_str = "LSI53C1030 C0"; 1486 break; 1487 case 0x80: 1488 product_str = "LSI53C1030T A0"; 1489 break; 1490 case 0x83: 1491 product_str = "LSI53C1030T A2"; 1492 break; 1493 case 0x87: 1494 product_str = "LSI53C1030T A3"; 1495 break; 1496 case 0xc1: 1497 product_str = "LSI53C1020A A1"; 1498 break; 1499 default: 1500 product_str = "LSI53C1030"; 1501 break; 1502 } 1503 break; 1504 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1505 switch (revision) 1506 { 1507 case 0x03: 1508 product_str = "LSI53C1035 A2"; 1509 break; 1510 case 0x04: 1511 product_str = "LSI53C1035 B0"; 1512 break; 1513 default: 1514 product_str = "LSI53C1035"; 1515 break; 1516 } 1517 break; 1518 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1519 switch (revision) 1520 { 1521 case 0x00: 1522 product_str = "LSISAS1064 A1"; 1523 break; 1524 case 0x01: 1525 product_str = "LSISAS1064 A2"; 1526 break; 1527 case 0x02: 1528 product_str = "LSISAS1064 A3"; 1529 break; 1530 case 0x03: 1531 product_str = "LSISAS1064 A4"; 1532 break; 1533 default: 1534 product_str = "LSISAS1064"; 1535 break; 1536 } 1537 break; 1538 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1539 switch (revision) 1540 { 1541 case 0x00: 1542 product_str = "LSISAS1064E A0"; 1543 break; 1544 case 0x01: 1545 product_str = "LSISAS1064E B0"; 1546 break; 1547 case 0x02: 1548 product_str = "LSISAS1064E B1"; 1549 break; 1550 case 0x04: 1551 product_str = "LSISAS1064E B2"; 1552 break; 1553 case 0x08: 1554 product_str = "LSISAS1064E B3"; 1555 break; 1556 default: 1557 product_str = "LSISAS1064E"; 1558 break; 1559 } 1560 break; 1561 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1562 switch (revision) 1563 { 1564 case 0x00: 1565 product_str = "LSISAS1068 A0"; 1566 break; 1567 case 0x01: 1568 product_str = "LSISAS1068 B0"; 1569 break; 1570 case 0x02: 1571 product_str = "LSISAS1068 B1"; 1572 break; 1573 default: 1574 product_str = "LSISAS1068"; 1575 break; 1576 } 1577 break; 1578 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1579 switch (revision) 1580 { 1581 case 0x00: 1582 product_str = "LSISAS1068E A0"; 1583 break; 1584 case 0x01: 1585 product_str = "LSISAS1068E B0"; 1586 break; 1587 case 0x02: 1588 product_str = "LSISAS1068E B1"; 1589 break; 1590 case 0x04: 1591 product_str = "LSISAS1068E B2"; 1592 break; 1593 case 0x08: 1594 product_str = "LSISAS1068E B3"; 1595 break; 1596 default: 1597 product_str = "LSISAS1068E"; 1598 break; 1599 } 1600 break; 1601 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1602 switch (revision) 1603 { 1604 case 0x00: 1605 product_str = "LSISAS1078 A0"; 1606 break; 1607 case 0x01: 1608 product_str = "LSISAS1078 B0"; 1609 break; 1610 case 0x02: 1611 product_str = "LSISAS1078 C0"; 1612 break; 1613 case 0x03: 1614 product_str = "LSISAS1078 C1"; 1615 break; 1616 case 0x04: 1617 product_str = "LSISAS1078 C2"; 1618 break; 1619 default: 1620 product_str = "LSISAS1078"; 1621 break; 1622 } 1623 break; 1624 } 1625 1626 out: 1627 return product_str; 1628 } 1629 1630 /** 1631 * mpt_mapresources - map in memory mapped io 1632 * @ioc: Pointer to pointer to IOC adapter 1633 * 1634 **/ 1635 static int 1636 mpt_mapresources(MPT_ADAPTER *ioc) 1637 { 1638 u8 __iomem *mem; 1639 int ii; 1640 resource_size_t mem_phys; 1641 unsigned long port; 1642 u32 msize; 1643 u32 psize; 1644 int r = -ENODEV; 1645 struct pci_dev *pdev; 1646 1647 pdev = ioc->pcidev; 1648 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 1649 if (pci_enable_device_mem(pdev)) { 1650 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() " 1651 "failed\n", ioc->name); 1652 return r; 1653 } 1654 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) { 1655 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with " 1656 "MEM failed\n", ioc->name); 1657 goto out_pci_disable_device; 1658 } 1659 1660 if (sizeof(dma_addr_t) > 4) { 1661 const uint64_t required_mask = dma_get_required_mask 1662 (&pdev->dev); 1663 if (required_mask > DMA_BIT_MASK(32) 1664 && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) 1665 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 1666 ioc->dma_mask = DMA_BIT_MASK(64); 1667 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1668 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1669 ioc->name)); 1670 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) 1671 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1672 ioc->dma_mask = DMA_BIT_MASK(32); 1673 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1674 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1675 ioc->name)); 1676 } else { 1677 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1678 ioc->name, pci_name(pdev)); 1679 goto out_pci_release_region; 1680 } 1681 } else { 1682 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) 1683 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1684 ioc->dma_mask = DMA_BIT_MASK(32); 1685 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1686 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1687 ioc->name)); 1688 } else { 1689 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1690 ioc->name, pci_name(pdev)); 1691 goto out_pci_release_region; 1692 } 1693 } 1694 1695 mem_phys = msize = 0; 1696 port = psize = 0; 1697 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) { 1698 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) { 1699 if (psize) 1700 continue; 1701 /* Get I/O space! */ 1702 port = pci_resource_start(pdev, ii); 1703 psize = pci_resource_len(pdev, ii); 1704 } else { 1705 if (msize) 1706 continue; 1707 /* Get memmap */ 1708 mem_phys = pci_resource_start(pdev, ii); 1709 msize = pci_resource_len(pdev, ii); 1710 } 1711 } 1712 ioc->mem_size = msize; 1713 1714 mem = NULL; 1715 /* Get logical ptr for PciMem0 space */ 1716 /*mem = ioremap(mem_phys, msize);*/ 1717 mem = ioremap(mem_phys, msize); 1718 if (mem == NULL) { 1719 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter" 1720 " memory!\n", ioc->name); 1721 r = -EINVAL; 1722 goto out_pci_release_region; 1723 } 1724 ioc->memmap = mem; 1725 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n", 1726 ioc->name, mem, (unsigned long long)mem_phys)); 1727 1728 ioc->mem_phys = mem_phys; 1729 ioc->chip = (SYSIF_REGS __iomem *)mem; 1730 1731 /* Save Port IO values in case we need to do downloadboot */ 1732 ioc->pio_mem_phys = port; 1733 ioc->pio_chip = (SYSIF_REGS __iomem *)port; 1734 1735 return 0; 1736 1737 out_pci_release_region: 1738 pci_release_selected_regions(pdev, ioc->bars); 1739 out_pci_disable_device: 1740 pci_disable_device(pdev); 1741 return r; 1742 } 1743 1744 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1745 /** 1746 * mpt_attach - Install a PCI intelligent MPT adapter. 1747 * @pdev: Pointer to pci_dev structure 1748 * @id: PCI device ID information 1749 * 1750 * This routine performs all the steps necessary to bring the IOC of 1751 * a MPT adapter to a OPERATIONAL state. This includes registering 1752 * memory regions, registering the interrupt, and allocating request 1753 * and reply memory pools. 1754 * 1755 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 1756 * MPT adapter. 1757 * 1758 * Returns 0 for success, non-zero for failure. 1759 * 1760 * TODO: Add support for polled controllers 1761 */ 1762 int 1763 mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id) 1764 { 1765 MPT_ADAPTER *ioc; 1766 u8 cb_idx; 1767 int r = -ENODEV; 1768 u8 pcixcmd; 1769 static int mpt_ids = 0; 1770 #ifdef CONFIG_PROC_FS 1771 struct proc_dir_entry *dent; 1772 #endif 1773 1774 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL); 1775 if (ioc == NULL) { 1776 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n"); 1777 return -ENOMEM; 1778 } 1779 1780 ioc->id = mpt_ids++; 1781 sprintf(ioc->name, "ioc%d", ioc->id); 1782 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n")); 1783 1784 /* 1785 * set initial debug level 1786 * (refer to mptdebug.h) 1787 * 1788 */ 1789 ioc->debug_level = mpt_debug_level; 1790 if (mpt_debug_level) 1791 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level); 1792 1793 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name)); 1794 1795 ioc->pcidev = pdev; 1796 if (mpt_mapresources(ioc)) { 1797 goto out_free_ioc; 1798 } 1799 1800 /* 1801 * Setting up proper handlers for scatter gather handling 1802 */ 1803 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 1804 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 1805 ioc->add_sge = &mpt_add_sge_64bit_1078; 1806 else 1807 ioc->add_sge = &mpt_add_sge_64bit; 1808 ioc->add_chain = &mpt_add_chain_64bit; 1809 ioc->sg_addr_size = 8; 1810 } else { 1811 ioc->add_sge = &mpt_add_sge; 1812 ioc->add_chain = &mpt_add_chain; 1813 ioc->sg_addr_size = 4; 1814 } 1815 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 1816 1817 ioc->alloc_total = sizeof(MPT_ADAPTER); 1818 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */ 1819 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 1820 1821 1822 spin_lock_init(&ioc->taskmgmt_lock); 1823 mutex_init(&ioc->internal_cmds.mutex); 1824 init_completion(&ioc->internal_cmds.done); 1825 mutex_init(&ioc->mptbase_cmds.mutex); 1826 init_completion(&ioc->mptbase_cmds.done); 1827 mutex_init(&ioc->taskmgmt_cmds.mutex); 1828 init_completion(&ioc->taskmgmt_cmds.done); 1829 1830 /* Initialize the event logging. 1831 */ 1832 ioc->eventTypes = 0; /* None */ 1833 ioc->eventContext = 0; 1834 ioc->eventLogSize = 0; 1835 ioc->events = NULL; 1836 1837 #ifdef MFCNT 1838 ioc->mfcnt = 0; 1839 #endif 1840 1841 ioc->sh = NULL; 1842 ioc->cached_fw = NULL; 1843 1844 /* Initialize SCSI Config Data structure 1845 */ 1846 memset(&ioc->spi_data, 0, sizeof(SpiCfgData)); 1847 1848 /* Initialize the fc rport list head. 1849 */ 1850 INIT_LIST_HEAD(&ioc->fc_rports); 1851 1852 /* Find lookup slot. */ 1853 INIT_LIST_HEAD(&ioc->list); 1854 1855 1856 /* Initialize workqueue */ 1857 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work); 1858 1859 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN, 1860 "mpt_poll_%d", ioc->id); 1861 ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name, 1862 WQ_MEM_RECLAIM, 0); 1863 if (!ioc->reset_work_q) { 1864 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 1865 ioc->name); 1866 r = -ENOMEM; 1867 goto out_unmap_resources; 1868 } 1869 1870 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n", 1871 ioc->name, &ioc->facts, &ioc->pfacts[0])); 1872 1873 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device, 1874 pdev->revision); 1875 1876 switch (pdev->device) 1877 { 1878 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1879 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1880 ioc->errata_flag_1064 = 1; 1881 fallthrough; 1882 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1883 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1884 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1885 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1886 ioc->bus_type = FC; 1887 break; 1888 1889 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1890 if (pdev->revision < XL_929) { 1891 /* 929X Chip Fix. Set Split transactions level 1892 * for PCIX. Set MOST bits to zero. 1893 */ 1894 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1895 pcixcmd &= 0x8F; 1896 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1897 } else { 1898 /* 929XL Chip Fix. Set MMRBC to 0x08. 1899 */ 1900 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1901 pcixcmd |= 0x08; 1902 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1903 } 1904 ioc->bus_type = FC; 1905 break; 1906 1907 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1908 /* 919X Chip Fix. Set Split transactions level 1909 * for PCIX. Set MOST bits to zero. 1910 */ 1911 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1912 pcixcmd &= 0x8F; 1913 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1914 ioc->bus_type = FC; 1915 break; 1916 1917 case MPI_MANUFACTPAGE_DEVID_53C1030: 1918 /* 1030 Chip Fix. Disable Split transactions 1919 * for PCIX. Set MOST bits to zero if Rev < C0( = 8). 1920 */ 1921 if (pdev->revision < C0_1030) { 1922 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1923 pcixcmd &= 0x8F; 1924 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1925 } 1926 fallthrough; 1927 1928 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1929 ioc->bus_type = SPI; 1930 break; 1931 1932 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1933 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1934 ioc->errata_flag_1064 = 1; 1935 ioc->bus_type = SAS; 1936 break; 1937 1938 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1939 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1940 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1941 ioc->bus_type = SAS; 1942 break; 1943 } 1944 1945 1946 switch (ioc->bus_type) { 1947 1948 case SAS: 1949 ioc->msi_enable = mpt_msi_enable_sas; 1950 break; 1951 1952 case SPI: 1953 ioc->msi_enable = mpt_msi_enable_spi; 1954 break; 1955 1956 case FC: 1957 ioc->msi_enable = mpt_msi_enable_fc; 1958 break; 1959 1960 default: 1961 ioc->msi_enable = 0; 1962 break; 1963 } 1964 1965 ioc->fw_events_off = 1; 1966 1967 if (ioc->errata_flag_1064) 1968 pci_disable_io_access(pdev); 1969 1970 spin_lock_init(&ioc->FreeQlock); 1971 1972 /* Disable all! */ 1973 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 1974 ioc->active = 0; 1975 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1976 1977 /* Set IOC ptr in the pcidev's driver data. */ 1978 pci_set_drvdata(ioc->pcidev, ioc); 1979 1980 /* Set lookup ptr. */ 1981 list_add_tail(&ioc->list, &ioc_list); 1982 1983 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets. 1984 */ 1985 mpt_detect_bound_ports(ioc, pdev); 1986 1987 INIT_LIST_HEAD(&ioc->fw_event_list); 1988 spin_lock_init(&ioc->fw_event_lock); 1989 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id); 1990 ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name, 1991 WQ_MEM_RECLAIM, 0); 1992 if (!ioc->fw_event_q) { 1993 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 1994 ioc->name); 1995 r = -ENOMEM; 1996 goto out_remove_ioc; 1997 } 1998 1999 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2000 CAN_SLEEP)) != 0){ 2001 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n", 2002 ioc->name, r); 2003 2004 destroy_workqueue(ioc->fw_event_q); 2005 ioc->fw_event_q = NULL; 2006 2007 list_del(&ioc->list); 2008 if (ioc->alt_ioc) 2009 ioc->alt_ioc->alt_ioc = NULL; 2010 iounmap(ioc->memmap); 2011 if (pci_is_enabled(pdev)) 2012 pci_disable_device(pdev); 2013 if (r != -5) 2014 pci_release_selected_regions(pdev, ioc->bars); 2015 2016 destroy_workqueue(ioc->reset_work_q); 2017 ioc->reset_work_q = NULL; 2018 2019 kfree(ioc); 2020 return r; 2021 } 2022 2023 /* call per device driver probe entry point */ 2024 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2025 if(MptDeviceDriverHandlers[cb_idx] && 2026 MptDeviceDriverHandlers[cb_idx]->probe) { 2027 MptDeviceDriverHandlers[cb_idx]->probe(pdev); 2028 } 2029 } 2030 2031 #ifdef CONFIG_PROC_FS 2032 /* 2033 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter. 2034 */ 2035 dent = proc_mkdir(ioc->name, mpt_proc_root_dir); 2036 if (dent) { 2037 proc_create_single_data("info", S_IRUGO, dent, 2038 mpt_iocinfo_proc_show, ioc); 2039 proc_create_single_data("summary", S_IRUGO, dent, 2040 mpt_summary_proc_show, ioc); 2041 } 2042 #endif 2043 2044 if (!ioc->alt_ioc) 2045 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 2046 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 2047 2048 return 0; 2049 2050 out_remove_ioc: 2051 list_del(&ioc->list); 2052 if (ioc->alt_ioc) 2053 ioc->alt_ioc->alt_ioc = NULL; 2054 2055 destroy_workqueue(ioc->reset_work_q); 2056 ioc->reset_work_q = NULL; 2057 2058 out_unmap_resources: 2059 iounmap(ioc->memmap); 2060 pci_disable_device(pdev); 2061 pci_release_selected_regions(pdev, ioc->bars); 2062 2063 out_free_ioc: 2064 kfree(ioc); 2065 2066 return r; 2067 } 2068 2069 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2070 /** 2071 * mpt_detach - Remove a PCI intelligent MPT adapter. 2072 * @pdev: Pointer to pci_dev structure 2073 */ 2074 2075 void 2076 mpt_detach(struct pci_dev *pdev) 2077 { 2078 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2079 char pname[64]; 2080 u8 cb_idx; 2081 unsigned long flags; 2082 struct workqueue_struct *wq; 2083 2084 /* 2085 * Stop polling ioc for fault condition 2086 */ 2087 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 2088 wq = ioc->reset_work_q; 2089 ioc->reset_work_q = NULL; 2090 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 2091 cancel_delayed_work(&ioc->fault_reset_work); 2092 destroy_workqueue(wq); 2093 2094 spin_lock_irqsave(&ioc->fw_event_lock, flags); 2095 wq = ioc->fw_event_q; 2096 ioc->fw_event_q = NULL; 2097 spin_unlock_irqrestore(&ioc->fw_event_lock, flags); 2098 destroy_workqueue(wq); 2099 2100 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name); 2101 remove_proc_entry(pname, NULL); 2102 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name); 2103 remove_proc_entry(pname, NULL); 2104 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name); 2105 remove_proc_entry(pname, NULL); 2106 2107 /* call per device driver remove entry point */ 2108 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2109 if(MptDeviceDriverHandlers[cb_idx] && 2110 MptDeviceDriverHandlers[cb_idx]->remove) { 2111 MptDeviceDriverHandlers[cb_idx]->remove(pdev); 2112 } 2113 } 2114 2115 /* Disable interrupts! */ 2116 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2117 2118 ioc->active = 0; 2119 synchronize_irq(pdev->irq); 2120 2121 /* Clear any lingering interrupt */ 2122 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2123 2124 CHIPREG_READ32(&ioc->chip->IntStatus); 2125 2126 mpt_adapter_dispose(ioc); 2127 2128 } 2129 2130 /************************************************************************** 2131 * Power Management 2132 */ 2133 #ifdef CONFIG_PM 2134 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2135 /** 2136 * mpt_suspend - Fusion MPT base driver suspend routine. 2137 * @pdev: Pointer to pci_dev structure 2138 * @state: new state to enter 2139 */ 2140 int 2141 mpt_suspend(struct pci_dev *pdev, pm_message_t state) 2142 { 2143 u32 device_state; 2144 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2145 2146 device_state = pci_choose_state(pdev, state); 2147 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering " 2148 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2149 device_state); 2150 2151 /* put ioc into READY_STATE */ 2152 if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) { 2153 printk(MYIOC_s_ERR_FMT 2154 "pci-suspend: IOC msg unit reset failed!\n", ioc->name); 2155 } 2156 2157 /* disable interrupts */ 2158 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2159 ioc->active = 0; 2160 2161 /* Clear any lingering interrupt */ 2162 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2163 2164 free_irq(ioc->pci_irq, ioc); 2165 if (ioc->msi_enable) 2166 pci_disable_msi(ioc->pcidev); 2167 ioc->pci_irq = -1; 2168 pci_save_state(pdev); 2169 pci_disable_device(pdev); 2170 pci_release_selected_regions(pdev, ioc->bars); 2171 pci_set_power_state(pdev, device_state); 2172 return 0; 2173 } 2174 2175 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2176 /** 2177 * mpt_resume - Fusion MPT base driver resume routine. 2178 * @pdev: Pointer to pci_dev structure 2179 */ 2180 int 2181 mpt_resume(struct pci_dev *pdev) 2182 { 2183 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2184 u32 device_state = pdev->current_state; 2185 int recovery_state; 2186 int err; 2187 2188 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous " 2189 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2190 device_state); 2191 2192 pci_set_power_state(pdev, PCI_D0); 2193 pci_enable_wake(pdev, PCI_D0, 0); 2194 pci_restore_state(pdev); 2195 ioc->pcidev = pdev; 2196 err = mpt_mapresources(ioc); 2197 if (err) 2198 return err; 2199 2200 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 2201 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 2202 ioc->add_sge = &mpt_add_sge_64bit_1078; 2203 else 2204 ioc->add_sge = &mpt_add_sge_64bit; 2205 ioc->add_chain = &mpt_add_chain_64bit; 2206 ioc->sg_addr_size = 8; 2207 } else { 2208 2209 ioc->add_sge = &mpt_add_sge; 2210 ioc->add_chain = &mpt_add_chain; 2211 ioc->sg_addr_size = 4; 2212 } 2213 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 2214 2215 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n", 2216 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT), 2217 CHIPREG_READ32(&ioc->chip->Doorbell)); 2218 2219 /* 2220 * Errata workaround for SAS pci express: 2221 * Upon returning to the D0 state, the contents of the doorbell will be 2222 * stale data, and this will incorrectly signal to the host driver that 2223 * the firmware is ready to process mpt commands. The workaround is 2224 * to issue a diagnostic reset. 2225 */ 2226 if (ioc->bus_type == SAS && (pdev->device == 2227 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device == 2228 MPI_MANUFACTPAGE_DEVID_SAS1064E)) { 2229 if (KickStart(ioc, 1, CAN_SLEEP) < 0) { 2230 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n", 2231 ioc->name); 2232 goto out; 2233 } 2234 } 2235 2236 /* bring ioc to operational state */ 2237 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name); 2238 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2239 CAN_SLEEP); 2240 if (recovery_state != 0) 2241 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, " 2242 "error:[%x]\n", ioc->name, recovery_state); 2243 else 2244 printk(MYIOC_s_INFO_FMT 2245 "pci-resume: success\n", ioc->name); 2246 out: 2247 return 0; 2248 2249 } 2250 #endif 2251 2252 static int 2253 mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase) 2254 { 2255 if ((MptDriverClass[index] == MPTSPI_DRIVER && 2256 ioc->bus_type != SPI) || 2257 (MptDriverClass[index] == MPTFC_DRIVER && 2258 ioc->bus_type != FC) || 2259 (MptDriverClass[index] == MPTSAS_DRIVER && 2260 ioc->bus_type != SAS)) 2261 /* make sure we only call the relevant reset handler 2262 * for the bus */ 2263 return 0; 2264 return (MptResetHandlers[index])(ioc, reset_phase); 2265 } 2266 2267 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2268 /** 2269 * mpt_do_ioc_recovery - Initialize or recover MPT adapter. 2270 * @ioc: Pointer to MPT adapter structure 2271 * @reason: Event word / reason 2272 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 2273 * 2274 * This routine performs all the steps necessary to bring the IOC 2275 * to a OPERATIONAL state. 2276 * 2277 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 2278 * MPT adapter. 2279 * 2280 * Returns: 2281 * 0 for success 2282 * -1 if failed to get board READY 2283 * -2 if READY but IOCFacts Failed 2284 * -3 if READY but PrimeIOCFifos Failed 2285 * -4 if READY but IOCInit Failed 2286 * -5 if failed to enable_device and/or request_selected_regions 2287 * -6 if failed to upload firmware 2288 */ 2289 static int 2290 mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag) 2291 { 2292 int hard_reset_done = 0; 2293 int alt_ioc_ready = 0; 2294 int hard; 2295 int rc=0; 2296 int ii; 2297 int ret = 0; 2298 int reset_alt_ioc_active = 0; 2299 int irq_allocated = 0; 2300 u8 *a; 2301 2302 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name, 2303 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery"); 2304 2305 /* Disable reply interrupts (also blocks FreeQ) */ 2306 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2307 ioc->active = 0; 2308 2309 if (ioc->alt_ioc) { 2310 if (ioc->alt_ioc->active || 2311 reason == MPT_HOSTEVENT_IOC_RECOVER) { 2312 reset_alt_ioc_active = 1; 2313 /* Disable alt-IOC's reply interrupts 2314 * (and FreeQ) for a bit 2315 **/ 2316 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2317 0xFFFFFFFF); 2318 ioc->alt_ioc->active = 0; 2319 } 2320 } 2321 2322 hard = 1; 2323 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) 2324 hard = 0; 2325 2326 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) { 2327 if (hard_reset_done == -4) { 2328 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n", 2329 ioc->name); 2330 2331 if (reset_alt_ioc_active && ioc->alt_ioc) { 2332 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */ 2333 dprintk(ioc, printk(MYIOC_s_INFO_FMT 2334 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name)); 2335 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM); 2336 ioc->alt_ioc->active = 1; 2337 } 2338 2339 } else { 2340 printk(MYIOC_s_WARN_FMT 2341 "NOT READY WARNING!\n", ioc->name); 2342 } 2343 ret = -1; 2344 goto out; 2345 } 2346 2347 /* hard_reset_done = 0 if a soft reset was performed 2348 * and 1 if a hard reset was performed. 2349 */ 2350 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) { 2351 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0) 2352 alt_ioc_ready = 1; 2353 else 2354 printk(MYIOC_s_WARN_FMT 2355 ": alt-ioc Not ready WARNING!\n", 2356 ioc->alt_ioc->name); 2357 } 2358 2359 for (ii=0; ii<5; ii++) { 2360 /* Get IOC facts! Allow 5 retries */ 2361 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0) 2362 break; 2363 } 2364 2365 2366 if (ii == 5) { 2367 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2368 "Retry IocFacts failed rc=%x\n", ioc->name, rc)); 2369 ret = -2; 2370 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2371 MptDisplayIocCapabilities(ioc); 2372 } 2373 2374 if (alt_ioc_ready) { 2375 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) { 2376 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2377 "Initial Alt IocFacts failed rc=%x\n", 2378 ioc->name, rc)); 2379 /* Retry - alt IOC was initialized once 2380 */ 2381 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason); 2382 } 2383 if (rc) { 2384 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2385 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc)); 2386 alt_ioc_ready = 0; 2387 reset_alt_ioc_active = 0; 2388 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2389 MptDisplayIocCapabilities(ioc->alt_ioc); 2390 } 2391 } 2392 2393 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) && 2394 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) { 2395 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2396 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM | 2397 IORESOURCE_IO); 2398 if (pci_enable_device(ioc->pcidev)) 2399 return -5; 2400 if (pci_request_selected_regions(ioc->pcidev, ioc->bars, 2401 "mpt")) 2402 return -5; 2403 } 2404 2405 /* 2406 * Device is reset now. It must have de-asserted the interrupt line 2407 * (if it was asserted) and it should be safe to register for the 2408 * interrupt now. 2409 */ 2410 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2411 ioc->pci_irq = -1; 2412 if (ioc->pcidev->irq) { 2413 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev)) 2414 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n", 2415 ioc->name); 2416 else 2417 ioc->msi_enable = 0; 2418 rc = request_irq(ioc->pcidev->irq, mpt_interrupt, 2419 IRQF_SHARED, ioc->name, ioc); 2420 if (rc < 0) { 2421 printk(MYIOC_s_ERR_FMT "Unable to allocate " 2422 "interrupt %d!\n", 2423 ioc->name, ioc->pcidev->irq); 2424 if (ioc->msi_enable) 2425 pci_disable_msi(ioc->pcidev); 2426 ret = -EBUSY; 2427 goto out; 2428 } 2429 irq_allocated = 1; 2430 ioc->pci_irq = ioc->pcidev->irq; 2431 pci_set_master(ioc->pcidev); /* ?? */ 2432 pci_set_drvdata(ioc->pcidev, ioc); 2433 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2434 "installed at interrupt %d\n", ioc->name, 2435 ioc->pcidev->irq)); 2436 } 2437 } 2438 2439 /* Prime reply & request queues! 2440 * (mucho alloc's) Must be done prior to 2441 * init as upper addresses are needed for init. 2442 * If fails, continue with alt-ioc processing 2443 */ 2444 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n", 2445 ioc->name)); 2446 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0)) 2447 ret = -3; 2448 2449 /* May need to check/upload firmware & data here! 2450 * If fails, continue with alt-ioc processing 2451 */ 2452 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n", 2453 ioc->name)); 2454 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0)) 2455 ret = -4; 2456 // NEW! 2457 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) { 2458 printk(MYIOC_s_WARN_FMT 2459 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n", 2460 ioc->alt_ioc->name, rc); 2461 alt_ioc_ready = 0; 2462 reset_alt_ioc_active = 0; 2463 } 2464 2465 if (alt_ioc_ready) { 2466 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) { 2467 alt_ioc_ready = 0; 2468 reset_alt_ioc_active = 0; 2469 printk(MYIOC_s_WARN_FMT 2470 ": alt-ioc: (%d) init failure WARNING!\n", 2471 ioc->alt_ioc->name, rc); 2472 } 2473 } 2474 2475 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){ 2476 if (ioc->upload_fw) { 2477 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2478 "firmware upload required!\n", ioc->name)); 2479 2480 /* Controller is not operational, cannot do upload 2481 */ 2482 if (ret == 0) { 2483 rc = mpt_do_upload(ioc, sleepFlag); 2484 if (rc == 0) { 2485 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 2486 /* 2487 * Maintain only one pointer to FW memory 2488 * so there will not be two attempt to 2489 * downloadboot onboard dual function 2490 * chips (mpt_adapter_disable, 2491 * mpt_diag_reset) 2492 */ 2493 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2494 "mpt_upload: alt_%s has cached_fw=%p \n", 2495 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw)); 2496 ioc->cached_fw = NULL; 2497 } 2498 } else { 2499 printk(MYIOC_s_WARN_FMT 2500 "firmware upload failure!\n", ioc->name); 2501 ret = -6; 2502 } 2503 } 2504 } 2505 } 2506 2507 /* Enable MPT base driver management of EventNotification 2508 * and EventAck handling. 2509 */ 2510 if ((ret == 0) && (!ioc->facts.EventState)) { 2511 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2512 "SendEventNotification\n", 2513 ioc->name)); 2514 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */ 2515 } 2516 2517 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState) 2518 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag); 2519 2520 if (ret == 0) { 2521 /* Enable! (reply interrupt) */ 2522 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 2523 ioc->active = 1; 2524 } 2525 if (rc == 0) { /* alt ioc */ 2526 if (reset_alt_ioc_active && ioc->alt_ioc) { 2527 /* (re)Enable alt-IOC! (reply interrupt) */ 2528 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc" 2529 "reply irq re-enabled\n", 2530 ioc->alt_ioc->name)); 2531 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2532 MPI_HIM_DIM); 2533 ioc->alt_ioc->active = 1; 2534 } 2535 } 2536 2537 2538 /* Add additional "reason" check before call to GetLanConfigPages 2539 * (combined with GetIoUnitPage2 call). This prevents a somewhat 2540 * recursive scenario; GetLanConfigPages times out, timer expired 2541 * routine calls HardResetHandler, which calls into here again, 2542 * and we try GetLanConfigPages again... 2543 */ 2544 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2545 2546 /* 2547 * Initialize link list for inactive raid volumes. 2548 */ 2549 mutex_init(&ioc->raid_data.inactive_list_mutex); 2550 INIT_LIST_HEAD(&ioc->raid_data.inactive_list); 2551 2552 switch (ioc->bus_type) { 2553 2554 case SAS: 2555 /* clear persistency table */ 2556 if(ioc->facts.IOCExceptions & 2557 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) { 2558 ret = mptbase_sas_persist_operation(ioc, 2559 MPI_SAS_OP_CLEAR_NOT_PRESENT); 2560 if(ret != 0) 2561 goto out; 2562 } 2563 2564 /* Find IM volumes 2565 */ 2566 mpt_findImVolumes(ioc); 2567 2568 /* Check, and possibly reset, the coalescing value 2569 */ 2570 mpt_read_ioc_pg_1(ioc); 2571 2572 break; 2573 2574 case FC: 2575 if ((ioc->pfacts[0].ProtocolFlags & 2576 MPI_PORTFACTS_PROTOCOL_LAN) && 2577 (ioc->lan_cnfg_page0.Header.PageLength == 0)) { 2578 /* 2579 * Pre-fetch the ports LAN MAC address! 2580 * (LANPage1_t stuff) 2581 */ 2582 (void) GetLanConfigPages(ioc); 2583 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 2584 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2585 "LanAddr = %pMR\n", ioc->name, a)); 2586 } 2587 break; 2588 2589 case SPI: 2590 /* Get NVRAM and adapter maximums from SPP 0 and 2 2591 */ 2592 mpt_GetScsiPortSettings(ioc, 0); 2593 2594 /* Get version and length of SDP 1 2595 */ 2596 mpt_readScsiDevicePageHeaders(ioc, 0); 2597 2598 /* Find IM volumes 2599 */ 2600 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02) 2601 mpt_findImVolumes(ioc); 2602 2603 /* Check, and possibly reset, the coalescing value 2604 */ 2605 mpt_read_ioc_pg_1(ioc); 2606 2607 mpt_read_ioc_pg_4(ioc); 2608 2609 break; 2610 } 2611 2612 GetIoUnitPage2(ioc); 2613 mpt_get_manufacturing_pg_0(ioc); 2614 } 2615 2616 out: 2617 if ((ret != 0) && irq_allocated) { 2618 free_irq(ioc->pci_irq, ioc); 2619 if (ioc->msi_enable) 2620 pci_disable_msi(ioc->pcidev); 2621 } 2622 return ret; 2623 } 2624 2625 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2626 /** 2627 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function 2628 * @ioc: Pointer to MPT adapter structure 2629 * @pdev: Pointer to (struct pci_dev) structure 2630 * 2631 * Search for PCI bus/dev_function which matches 2632 * PCI bus/dev_function (+/-1) for newly discovered 929, 2633 * 929X, 1030 or 1035. 2634 * 2635 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters 2636 * using alt_ioc pointer fields in their %MPT_ADAPTER structures. 2637 */ 2638 static void 2639 mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev) 2640 { 2641 struct pci_dev *peer=NULL; 2642 unsigned int slot = PCI_SLOT(pdev->devfn); 2643 unsigned int func = PCI_FUNC(pdev->devfn); 2644 MPT_ADAPTER *ioc_srch; 2645 2646 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x," 2647 " searching for devfn match on %x or %x\n", 2648 ioc->name, pci_name(pdev), pdev->bus->number, 2649 pdev->devfn, func-1, func+1)); 2650 2651 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1)); 2652 if (!peer) { 2653 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1)); 2654 if (!peer) 2655 return; 2656 } 2657 2658 list_for_each_entry(ioc_srch, &ioc_list, list) { 2659 struct pci_dev *_pcidev = ioc_srch->pcidev; 2660 if (_pcidev == peer) { 2661 /* Paranoia checks */ 2662 if (ioc->alt_ioc != NULL) { 2663 printk(MYIOC_s_WARN_FMT 2664 "Oops, already bound (%s <==> %s)!\n", 2665 ioc->name, ioc->name, ioc->alt_ioc->name); 2666 break; 2667 } else if (ioc_srch->alt_ioc != NULL) { 2668 printk(MYIOC_s_WARN_FMT 2669 "Oops, already bound (%s <==> %s)!\n", 2670 ioc_srch->name, ioc_srch->name, 2671 ioc_srch->alt_ioc->name); 2672 break; 2673 } 2674 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2675 "FOUND! binding %s <==> %s\n", 2676 ioc->name, ioc->name, ioc_srch->name)); 2677 ioc_srch->alt_ioc = ioc; 2678 ioc->alt_ioc = ioc_srch; 2679 } 2680 } 2681 pci_dev_put(peer); 2682 } 2683 2684 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2685 /** 2686 * mpt_adapter_disable - Disable misbehaving MPT adapter. 2687 * @ioc: Pointer to MPT adapter structure 2688 */ 2689 static void 2690 mpt_adapter_disable(MPT_ADAPTER *ioc) 2691 { 2692 int sz; 2693 int ret; 2694 2695 if (ioc->cached_fw != NULL) { 2696 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2697 "%s: Pushing FW onto adapter\n", __func__, ioc->name)); 2698 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *) 2699 ioc->cached_fw, CAN_SLEEP)) < 0) { 2700 printk(MYIOC_s_WARN_FMT 2701 ": firmware downloadboot failure (%d)!\n", 2702 ioc->name, ret); 2703 } 2704 } 2705 2706 /* 2707 * Put the controller into ready state (if its not already) 2708 */ 2709 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) { 2710 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, 2711 CAN_SLEEP)) { 2712 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) 2713 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit " 2714 "reset failed to put ioc in ready state!\n", 2715 ioc->name, __func__); 2716 } else 2717 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset " 2718 "failed!\n", ioc->name, __func__); 2719 } 2720 2721 2722 /* Disable adapter interrupts! */ 2723 synchronize_irq(ioc->pcidev->irq); 2724 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2725 ioc->active = 0; 2726 2727 /* Clear any lingering interrupt */ 2728 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2729 CHIPREG_READ32(&ioc->chip->IntStatus); 2730 2731 if (ioc->alloc != NULL) { 2732 sz = ioc->alloc_sz; 2733 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n", 2734 ioc->name, ioc->alloc, ioc->alloc_sz)); 2735 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 2736 ioc->alloc_dma); 2737 ioc->reply_frames = NULL; 2738 ioc->req_frames = NULL; 2739 ioc->alloc = NULL; 2740 ioc->alloc_total -= sz; 2741 } 2742 2743 if (ioc->sense_buf_pool != NULL) { 2744 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 2745 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 2746 ioc->sense_buf_pool_dma); 2747 ioc->sense_buf_pool = NULL; 2748 ioc->alloc_total -= sz; 2749 } 2750 2751 if (ioc->events != NULL){ 2752 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS); 2753 kfree(ioc->events); 2754 ioc->events = NULL; 2755 ioc->alloc_total -= sz; 2756 } 2757 2758 mpt_free_fw_memory(ioc); 2759 2760 kfree(ioc->spi_data.nvram); 2761 mpt_inactive_raid_list_free(ioc); 2762 kfree(ioc->raid_data.pIocPg2); 2763 kfree(ioc->raid_data.pIocPg3); 2764 ioc->spi_data.nvram = NULL; 2765 ioc->raid_data.pIocPg3 = NULL; 2766 2767 if (ioc->spi_data.pIocPg4 != NULL) { 2768 sz = ioc->spi_data.IocPg4Sz; 2769 dma_free_coherent(&ioc->pcidev->dev, sz, 2770 ioc->spi_data.pIocPg4, 2771 ioc->spi_data.IocPg4_dma); 2772 ioc->spi_data.pIocPg4 = NULL; 2773 ioc->alloc_total -= sz; 2774 } 2775 2776 if (ioc->ReqToChain != NULL) { 2777 kfree(ioc->ReqToChain); 2778 kfree(ioc->RequestNB); 2779 ioc->ReqToChain = NULL; 2780 } 2781 2782 kfree(ioc->ChainToChain); 2783 ioc->ChainToChain = NULL; 2784 2785 if (ioc->HostPageBuffer != NULL) { 2786 if((ret = mpt_host_page_access_control(ioc, 2787 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) { 2788 printk(MYIOC_s_ERR_FMT 2789 ": %s: host page buffers free failed (%d)!\n", 2790 ioc->name, __func__, ret); 2791 } 2792 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2793 "HostPageBuffer free @ %p, sz=%d bytes\n", 2794 ioc->name, ioc->HostPageBuffer, 2795 ioc->HostPageBuffer_sz)); 2796 dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz, 2797 ioc->HostPageBuffer, ioc->HostPageBuffer_dma); 2798 ioc->HostPageBuffer = NULL; 2799 ioc->HostPageBuffer_sz = 0; 2800 ioc->alloc_total -= ioc->HostPageBuffer_sz; 2801 } 2802 2803 pci_set_drvdata(ioc->pcidev, NULL); 2804 } 2805 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2806 /** 2807 * mpt_adapter_dispose - Free all resources associated with an MPT adapter 2808 * @ioc: Pointer to MPT adapter structure 2809 * 2810 * This routine unregisters h/w resources and frees all alloc'd memory 2811 * associated with a MPT adapter structure. 2812 */ 2813 static void 2814 mpt_adapter_dispose(MPT_ADAPTER *ioc) 2815 { 2816 int sz_first, sz_last; 2817 2818 if (ioc == NULL) 2819 return; 2820 2821 sz_first = ioc->alloc_total; 2822 2823 mpt_adapter_disable(ioc); 2824 2825 if (ioc->pci_irq != -1) { 2826 free_irq(ioc->pci_irq, ioc); 2827 if (ioc->msi_enable) 2828 pci_disable_msi(ioc->pcidev); 2829 ioc->pci_irq = -1; 2830 } 2831 2832 if (ioc->memmap != NULL) { 2833 iounmap(ioc->memmap); 2834 ioc->memmap = NULL; 2835 } 2836 2837 pci_disable_device(ioc->pcidev); 2838 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2839 2840 /* Zap the adapter lookup ptr! */ 2841 list_del(&ioc->list); 2842 2843 sz_last = ioc->alloc_total; 2844 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n", 2845 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first)); 2846 2847 if (ioc->alt_ioc) 2848 ioc->alt_ioc->alt_ioc = NULL; 2849 2850 kfree(ioc); 2851 } 2852 2853 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2854 /** 2855 * MptDisplayIocCapabilities - Disply IOC's capabilities. 2856 * @ioc: Pointer to MPT adapter structure 2857 */ 2858 static void 2859 MptDisplayIocCapabilities(MPT_ADAPTER *ioc) 2860 { 2861 int i = 0; 2862 2863 printk(KERN_INFO "%s: ", ioc->name); 2864 if (ioc->prod_name) 2865 pr_cont("%s: ", ioc->prod_name); 2866 pr_cont("Capabilities={"); 2867 2868 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { 2869 pr_cont("Initiator"); 2870 i++; 2871 } 2872 2873 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2874 pr_cont("%sTarget", i ? "," : ""); 2875 i++; 2876 } 2877 2878 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 2879 pr_cont("%sLAN", i ? "," : ""); 2880 i++; 2881 } 2882 2883 #if 0 2884 /* 2885 * This would probably evoke more questions than it's worth 2886 */ 2887 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2888 pr_cont("%sLogBusAddr", i ? "," : ""); 2889 i++; 2890 } 2891 #endif 2892 2893 pr_cont("}\n"); 2894 } 2895 2896 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2897 /** 2898 * MakeIocReady - Get IOC to a READY state, using KickStart if needed. 2899 * @ioc: Pointer to MPT_ADAPTER structure 2900 * @force: Force hard KickStart of IOC 2901 * @sleepFlag: Specifies whether the process can sleep 2902 * 2903 * Returns: 2904 * 1 - DIAG reset and READY 2905 * 0 - READY initially OR soft reset and READY 2906 * -1 - Any failure on KickStart 2907 * -2 - Msg Unit Reset Failed 2908 * -3 - IO Unit Reset Failed 2909 * -4 - IOC owned by a PEER 2910 */ 2911 static int 2912 MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag) 2913 { 2914 u32 ioc_state; 2915 int statefault = 0; 2916 int cntdn; 2917 int hard_reset_done = 0; 2918 int r; 2919 int ii; 2920 int whoinit; 2921 2922 /* Get current [raw] IOC state */ 2923 ioc_state = mpt_GetIocState(ioc, 0); 2924 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state)); 2925 2926 /* 2927 * Check to see if IOC got left/stuck in doorbell handshake 2928 * grip of death. If so, hard reset the IOC. 2929 */ 2930 if (ioc_state & MPI_DOORBELL_ACTIVE) { 2931 statefault = 1; 2932 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n", 2933 ioc->name); 2934 } 2935 2936 /* Is it already READY? */ 2937 if (!statefault && 2938 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) { 2939 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2940 "IOC is in READY state\n", ioc->name)); 2941 return 0; 2942 } 2943 2944 /* 2945 * Check to see if IOC is in FAULT state. 2946 */ 2947 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 2948 statefault = 2; 2949 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n", 2950 ioc->name); 2951 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n", 2952 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK); 2953 } 2954 2955 /* 2956 * Hmmm... Did it get left operational? 2957 */ 2958 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) { 2959 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n", 2960 ioc->name)); 2961 2962 /* Check WhoInit. 2963 * If PCI Peer, exit. 2964 * Else, if no fault conditions are present, issue a MessageUnitReset 2965 * Else, fall through to KickStart case 2966 */ 2967 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT; 2968 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2969 "whoinit 0x%x statefault %d force %d\n", 2970 ioc->name, whoinit, statefault, force)); 2971 if (whoinit == MPI_WHOINIT_PCI_PEER) 2972 return -4; 2973 else { 2974 if ((statefault == 0 ) && (force == 0)) { 2975 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0) 2976 return 0; 2977 } 2978 statefault = 3; 2979 } 2980 } 2981 2982 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag); 2983 if (hard_reset_done < 0) 2984 return -1; 2985 2986 /* 2987 * Loop here waiting for IOC to come READY. 2988 */ 2989 ii = 0; 2990 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */ 2991 2992 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 2993 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) { 2994 /* 2995 * BIOS or previous driver load left IOC in OP state. 2996 * Reset messaging FIFOs. 2997 */ 2998 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) { 2999 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name); 3000 return -2; 3001 } 3002 } else if (ioc_state == MPI_IOC_STATE_RESET) { 3003 /* 3004 * Something is wrong. Try to get IOC back 3005 * to a known state. 3006 */ 3007 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) { 3008 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name); 3009 return -3; 3010 } 3011 } 3012 3013 ii++; cntdn--; 3014 if (!cntdn) { 3015 printk(MYIOC_s_ERR_FMT 3016 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 3017 ioc->name, ioc_state, (int)((ii+5)/HZ)); 3018 return -ETIME; 3019 } 3020 3021 if (sleepFlag == CAN_SLEEP) { 3022 msleep(1); 3023 } else { 3024 mdelay (1); /* 1 msec delay */ 3025 } 3026 3027 } 3028 3029 if (statefault < 3) { 3030 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name, 3031 statefault == 1 ? "stuck handshake" : "IOC FAULT"); 3032 } 3033 3034 return hard_reset_done; 3035 } 3036 3037 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3038 /** 3039 * mpt_GetIocState - Get the current state of a MPT adapter. 3040 * @ioc: Pointer to MPT_ADAPTER structure 3041 * @cooked: Request raw or cooked IOC state 3042 * 3043 * Returns all IOC Doorbell register bits if cooked==0, else just the 3044 * Doorbell bits in MPI_IOC_STATE_MASK. 3045 */ 3046 u32 3047 mpt_GetIocState(MPT_ADAPTER *ioc, int cooked) 3048 { 3049 u32 s, sc; 3050 3051 /* Get! */ 3052 s = CHIPREG_READ32(&ioc->chip->Doorbell); 3053 sc = s & MPI_IOC_STATE_MASK; 3054 3055 /* Save! */ 3056 ioc->last_state = sc; 3057 3058 return cooked ? sc : s; 3059 } 3060 3061 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3062 /** 3063 * GetIocFacts - Send IOCFacts request to MPT adapter. 3064 * @ioc: Pointer to MPT_ADAPTER structure 3065 * @sleepFlag: Specifies whether the process can sleep 3066 * @reason: If recovery, only update facts. 3067 * 3068 * Returns 0 for success, non-zero for failure. 3069 */ 3070 static int 3071 GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason) 3072 { 3073 IOCFacts_t get_facts; 3074 IOCFactsReply_t *facts; 3075 int r; 3076 int req_sz; 3077 int reply_sz; 3078 int sz; 3079 u32 vv; 3080 u8 shiftFactor=1; 3081 3082 /* IOC *must* NOT be in RESET state! */ 3083 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3084 printk(KERN_ERR MYNAM 3085 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n", 3086 ioc->name, ioc->last_state); 3087 return -44; 3088 } 3089 3090 facts = &ioc->facts; 3091 3092 /* Destination (reply area)... */ 3093 reply_sz = sizeof(*facts); 3094 memset(facts, 0, reply_sz); 3095 3096 /* Request area (get_facts on the stack right now!) */ 3097 req_sz = sizeof(get_facts); 3098 memset(&get_facts, 0, req_sz); 3099 3100 get_facts.Function = MPI_FUNCTION_IOC_FACTS; 3101 /* Assert: All other get_facts fields are zero! */ 3102 3103 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3104 "Sending get IocFacts request req_sz=%d reply_sz=%d\n", 3105 ioc->name, req_sz, reply_sz)); 3106 3107 /* No non-zero fields in the get_facts request are greater than 3108 * 1 byte in size, so we can just fire it off as is. 3109 */ 3110 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts, 3111 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag); 3112 if (r != 0) 3113 return r; 3114 3115 /* 3116 * Now byte swap (GRRR) the necessary fields before any further 3117 * inspection of reply contents. 3118 * 3119 * But need to do some sanity checks on MsgLength (byte) field 3120 * to make sure we don't zero IOC's req_sz! 3121 */ 3122 /* Did we get a valid reply? */ 3123 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) { 3124 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3125 /* 3126 * If not been here, done that, save off first WhoInit value 3127 */ 3128 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN) 3129 ioc->FirstWhoInit = facts->WhoInit; 3130 } 3131 3132 facts->MsgVersion = le16_to_cpu(facts->MsgVersion); 3133 facts->MsgContext = le32_to_cpu(facts->MsgContext); 3134 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions); 3135 facts->IOCStatus = le16_to_cpu(facts->IOCStatus); 3136 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo); 3137 /* CHECKME! IOCStatus, IOCLogInfo */ 3138 3139 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth); 3140 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize); 3141 3142 /* 3143 * FC f/w version changed between 1.1 and 1.2 3144 * Old: u16{Major(4),Minor(4),SubMinor(8)} 3145 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)} 3146 */ 3147 if (facts->MsgVersion < MPI_VERSION_01_02) { 3148 /* 3149 * Handle old FC f/w style, convert to new... 3150 */ 3151 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion); 3152 facts->FWVersion.Word = 3153 ((oldv<<12) & 0xFF000000) | 3154 ((oldv<<8) & 0x000FFF00); 3155 } else 3156 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word); 3157 3158 facts->ProductID = le16_to_cpu(facts->ProductID); 3159 3160 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK) 3161 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI) 3162 ioc->ir_firmware = 1; 3163 3164 facts->CurrentHostMfaHighAddr = 3165 le32_to_cpu(facts->CurrentHostMfaHighAddr); 3166 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits); 3167 facts->CurrentSenseBufferHighAddr = 3168 le32_to_cpu(facts->CurrentSenseBufferHighAddr); 3169 facts->CurReplyFrameSize = 3170 le16_to_cpu(facts->CurReplyFrameSize); 3171 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities); 3172 3173 /* 3174 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx 3175 * Older MPI-1.00.xx struct had 13 dwords, and enlarged 3176 * to 14 in MPI-1.01.0x. 3177 */ 3178 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 && 3179 facts->MsgVersion > MPI_VERSION_01_00) { 3180 facts->FWImageSize = le32_to_cpu(facts->FWImageSize); 3181 } 3182 3183 facts->FWImageSize = ALIGN(facts->FWImageSize, 4); 3184 3185 if (!facts->RequestFrameSize) { 3186 /* Something is wrong! */ 3187 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n", 3188 ioc->name); 3189 return -55; 3190 } 3191 3192 r = sz = facts->BlockSize; 3193 vv = ((63 / (sz * 4)) + 1) & 0x03; 3194 ioc->NB_for_64_byte_frame = vv; 3195 while ( sz ) 3196 { 3197 shiftFactor++; 3198 sz = sz >> 1; 3199 } 3200 ioc->NBShiftFactor = shiftFactor; 3201 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3202 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n", 3203 ioc->name, vv, shiftFactor, r)); 3204 3205 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3206 /* 3207 * Set values for this IOC's request & reply frame sizes, 3208 * and request & reply queue depths... 3209 */ 3210 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4); 3211 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits); 3212 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 3213 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth); 3214 3215 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n", 3216 ioc->name, ioc->reply_sz, ioc->reply_depth)); 3217 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n", 3218 ioc->name, ioc->req_sz, ioc->req_depth)); 3219 3220 /* Get port facts! */ 3221 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 ) 3222 return r; 3223 } 3224 } else { 3225 printk(MYIOC_s_ERR_FMT 3226 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n", 3227 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t, 3228 RequestFrameSize)/sizeof(u32))); 3229 return -66; 3230 } 3231 3232 return 0; 3233 } 3234 3235 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3236 /** 3237 * GetPortFacts - Send PortFacts request to MPT adapter. 3238 * @ioc: Pointer to MPT_ADAPTER structure 3239 * @portnum: Port number 3240 * @sleepFlag: Specifies whether the process can sleep 3241 * 3242 * Returns 0 for success, non-zero for failure. 3243 */ 3244 static int 3245 GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3246 { 3247 PortFacts_t get_pfacts; 3248 PortFactsReply_t *pfacts; 3249 int ii; 3250 int req_sz; 3251 int reply_sz; 3252 int max_id; 3253 3254 /* IOC *must* NOT be in RESET state! */ 3255 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3256 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n", 3257 ioc->name, ioc->last_state ); 3258 return -4; 3259 } 3260 3261 pfacts = &ioc->pfacts[portnum]; 3262 3263 /* Destination (reply area)... */ 3264 reply_sz = sizeof(*pfacts); 3265 memset(pfacts, 0, reply_sz); 3266 3267 /* Request area (get_pfacts on the stack right now!) */ 3268 req_sz = sizeof(get_pfacts); 3269 memset(&get_pfacts, 0, req_sz); 3270 3271 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS; 3272 get_pfacts.PortNumber = portnum; 3273 /* Assert: All other get_pfacts fields are zero! */ 3274 3275 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n", 3276 ioc->name, portnum)); 3277 3278 /* No non-zero fields in the get_pfacts request are greater than 3279 * 1 byte in size, so we can just fire it off as is. 3280 */ 3281 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts, 3282 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag); 3283 if (ii != 0) 3284 return ii; 3285 3286 /* Did we get a valid reply? */ 3287 3288 /* Now byte swap the necessary fields in the response. */ 3289 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext); 3290 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus); 3291 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo); 3292 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices); 3293 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID); 3294 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags); 3295 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers); 3296 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs); 3297 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets); 3298 3299 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID : 3300 pfacts->MaxDevices; 3301 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id; 3302 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256; 3303 3304 /* 3305 * Place all the devices on channels 3306 * 3307 * (for debuging) 3308 */ 3309 if (mpt_channel_mapping) { 3310 ioc->devices_per_bus = 1; 3311 ioc->number_of_buses = (max_id > 255) ? 255 : max_id; 3312 } 3313 3314 return 0; 3315 } 3316 3317 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3318 /** 3319 * SendIocInit - Send IOCInit request to MPT adapter. 3320 * @ioc: Pointer to MPT_ADAPTER structure 3321 * @sleepFlag: Specifies whether the process can sleep 3322 * 3323 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state. 3324 * 3325 * Returns 0 for success, non-zero for failure. 3326 */ 3327 static int 3328 SendIocInit(MPT_ADAPTER *ioc, int sleepFlag) 3329 { 3330 IOCInit_t ioc_init; 3331 MPIDefaultReply_t init_reply; 3332 u32 state; 3333 int r; 3334 int count; 3335 int cntdn; 3336 3337 memset(&ioc_init, 0, sizeof(ioc_init)); 3338 memset(&init_reply, 0, sizeof(init_reply)); 3339 3340 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER; 3341 ioc_init.Function = MPI_FUNCTION_IOC_INIT; 3342 3343 /* If we are in a recovery mode and we uploaded the FW image, 3344 * then this pointer is not NULL. Skip the upload a second time. 3345 * Set this flag if cached_fw set for either IOC. 3346 */ 3347 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 3348 ioc->upload_fw = 1; 3349 else 3350 ioc->upload_fw = 0; 3351 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n", 3352 ioc->name, ioc->upload_fw, ioc->facts.Flags)); 3353 3354 ioc_init.MaxDevices = (U8)ioc->devices_per_bus; 3355 ioc_init.MaxBuses = (U8)ioc->number_of_buses; 3356 3357 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n", 3358 ioc->name, ioc->facts.MsgVersion)); 3359 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) { 3360 // set MsgVersion and HeaderVersion host driver was built with 3361 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION); 3362 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION); 3363 3364 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) { 3365 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE; 3366 } else if(mpt_host_page_alloc(ioc, &ioc_init)) 3367 return -99; 3368 } 3369 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */ 3370 3371 if (ioc->sg_addr_size == sizeof(u64)) { 3372 /* Save the upper 32-bits of the request 3373 * (reply) and sense buffers. 3374 */ 3375 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32)); 3376 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32)); 3377 } else { 3378 /* Force 32-bit addressing */ 3379 ioc_init.HostMfaHighAddr = cpu_to_le32(0); 3380 ioc_init.SenseBufferHighAddr = cpu_to_le32(0); 3381 } 3382 3383 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr; 3384 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr; 3385 ioc->facts.MaxDevices = ioc_init.MaxDevices; 3386 ioc->facts.MaxBuses = ioc_init.MaxBuses; 3387 3388 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n", 3389 ioc->name, &ioc_init)); 3390 3391 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init, 3392 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag); 3393 if (r != 0) { 3394 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r); 3395 return r; 3396 } 3397 3398 /* No need to byte swap the multibyte fields in the reply 3399 * since we don't even look at its contents. 3400 */ 3401 3402 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n", 3403 ioc->name, &ioc_init)); 3404 3405 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) { 3406 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r); 3407 return r; 3408 } 3409 3410 /* YIKES! SUPER IMPORTANT!!! 3411 * Poll IocState until _OPERATIONAL while IOC is doing 3412 * LoopInit and TargetDiscovery! 3413 */ 3414 count = 0; 3415 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */ 3416 state = mpt_GetIocState(ioc, 1); 3417 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) { 3418 if (sleepFlag == CAN_SLEEP) { 3419 msleep(1); 3420 } else { 3421 mdelay(1); 3422 } 3423 3424 if (!cntdn) { 3425 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n", 3426 ioc->name, (int)((count+5)/HZ)); 3427 return -9; 3428 } 3429 3430 state = mpt_GetIocState(ioc, 1); 3431 count++; 3432 } 3433 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n", 3434 ioc->name, count)); 3435 3436 ioc->aen_event_read_flag=0; 3437 return r; 3438 } 3439 3440 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3441 /** 3442 * SendPortEnable - Send PortEnable request to MPT adapter port. 3443 * @ioc: Pointer to MPT_ADAPTER structure 3444 * @portnum: Port number to enable 3445 * @sleepFlag: Specifies whether the process can sleep 3446 * 3447 * Send PortEnable to bring IOC to OPERATIONAL state. 3448 * 3449 * Returns 0 for success, non-zero for failure. 3450 */ 3451 static int 3452 SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3453 { 3454 PortEnable_t port_enable; 3455 MPIDefaultReply_t reply_buf; 3456 int rc; 3457 int req_sz; 3458 int reply_sz; 3459 3460 /* Destination... */ 3461 reply_sz = sizeof(MPIDefaultReply_t); 3462 memset(&reply_buf, 0, reply_sz); 3463 3464 req_sz = sizeof(PortEnable_t); 3465 memset(&port_enable, 0, req_sz); 3466 3467 port_enable.Function = MPI_FUNCTION_PORT_ENABLE; 3468 port_enable.PortNumber = portnum; 3469 /* port_enable.ChainOffset = 0; */ 3470 /* port_enable.MsgFlags = 0; */ 3471 /* port_enable.MsgContext = 0; */ 3472 3473 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n", 3474 ioc->name, portnum, &port_enable)); 3475 3476 /* RAID FW may take a long time to enable 3477 */ 3478 if (ioc->ir_firmware || ioc->bus_type == SAS) { 3479 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3480 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3481 300 /*seconds*/, sleepFlag); 3482 } else { 3483 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3484 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3485 30 /*seconds*/, sleepFlag); 3486 } 3487 return rc; 3488 } 3489 3490 /** 3491 * mpt_alloc_fw_memory - allocate firmware memory 3492 * @ioc: Pointer to MPT_ADAPTER structure 3493 * @size: total FW bytes 3494 * 3495 * If memory has already been allocated, the same (cached) value 3496 * is returned. 3497 * 3498 * Return 0 if successful, or non-zero for failure 3499 **/ 3500 int 3501 mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size) 3502 { 3503 int rc; 3504 3505 if (ioc->cached_fw) { 3506 rc = 0; /* use already allocated memory */ 3507 goto out; 3508 } 3509 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 3510 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */ 3511 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma; 3512 rc = 0; 3513 goto out; 3514 } 3515 ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma); 3516 if (!ioc->cached_fw) { 3517 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n", 3518 ioc->name); 3519 rc = -1; 3520 } else { 3521 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n", 3522 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size)); 3523 ioc->alloc_total += size; 3524 rc = 0; 3525 } 3526 out: 3527 return rc; 3528 } 3529 3530 /** 3531 * mpt_free_fw_memory - free firmware memory 3532 * @ioc: Pointer to MPT_ADAPTER structure 3533 * 3534 * If alt_img is NULL, delete from ioc structure. 3535 * Else, delete a secondary image in same format. 3536 **/ 3537 void 3538 mpt_free_fw_memory(MPT_ADAPTER *ioc) 3539 { 3540 int sz; 3541 3542 if (!ioc->cached_fw) 3543 return; 3544 3545 sz = ioc->facts.FWImageSize; 3546 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n", 3547 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3548 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->cached_fw, 3549 ioc->cached_fw_dma); 3550 ioc->alloc_total -= sz; 3551 ioc->cached_fw = NULL; 3552 } 3553 3554 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3555 /** 3556 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port. 3557 * @ioc: Pointer to MPT_ADAPTER structure 3558 * @sleepFlag: Specifies whether the process can sleep 3559 * 3560 * Returns 0 for success, >0 for handshake failure 3561 * <0 for fw upload failure. 3562 * 3563 * Remark: If bound IOC and a successful FWUpload was performed 3564 * on the bound IOC, the second image is discarded 3565 * and memory is free'd. Both channels must upload to prevent 3566 * IOC from running in degraded mode. 3567 */ 3568 static int 3569 mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag) 3570 { 3571 u8 reply[sizeof(FWUploadReply_t)]; 3572 FWUpload_t *prequest; 3573 FWUploadReply_t *preply; 3574 FWUploadTCSGE_t *ptcsge; 3575 u32 flagsLength; 3576 int ii, sz, reply_sz; 3577 int cmdStatus; 3578 int request_size; 3579 /* If the image size is 0, we are done. 3580 */ 3581 if ((sz = ioc->facts.FWImageSize) == 0) 3582 return 0; 3583 3584 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0) 3585 return -ENOMEM; 3586 3587 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n", 3588 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3589 3590 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) : 3591 kzalloc(ioc->req_sz, GFP_KERNEL); 3592 if (!prequest) { 3593 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed " 3594 "while allocating memory \n", ioc->name)); 3595 mpt_free_fw_memory(ioc); 3596 return -ENOMEM; 3597 } 3598 3599 preply = (FWUploadReply_t *)&reply; 3600 3601 reply_sz = sizeof(reply); 3602 memset(preply, 0, reply_sz); 3603 3604 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; 3605 prequest->Function = MPI_FUNCTION_FW_UPLOAD; 3606 3607 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL; 3608 ptcsge->DetailsLength = 12; 3609 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; 3610 ptcsge->ImageSize = cpu_to_le32(sz); 3611 ptcsge++; 3612 3613 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz; 3614 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma); 3615 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) + 3616 ioc->SGE_size; 3617 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload " 3618 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest, 3619 ioc->facts.FWImageSize, request_size)); 3620 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest); 3621 3622 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest, 3623 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag); 3624 3625 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed " 3626 "rc=%x \n", ioc->name, ii)); 3627 3628 cmdStatus = -EFAULT; 3629 if (ii == 0) { 3630 /* Handshake transfer was complete and successful. 3631 * Check the Reply Frame. 3632 */ 3633 int status; 3634 status = le16_to_cpu(preply->IOCStatus) & 3635 MPI_IOCSTATUS_MASK; 3636 if (status == MPI_IOCSTATUS_SUCCESS && 3637 ioc->facts.FWImageSize == 3638 le32_to_cpu(preply->ActualImageSize)) 3639 cmdStatus = 0; 3640 } 3641 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n", 3642 ioc->name, cmdStatus)); 3643 3644 3645 if (cmdStatus) { 3646 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, " 3647 "freeing image \n", ioc->name)); 3648 mpt_free_fw_memory(ioc); 3649 } 3650 kfree(prequest); 3651 3652 return cmdStatus; 3653 } 3654 3655 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3656 /** 3657 * mpt_downloadboot - DownloadBoot code 3658 * @ioc: Pointer to MPT_ADAPTER structure 3659 * @pFwHeader: Pointer to firmware header info 3660 * @sleepFlag: Specifies whether the process can sleep 3661 * 3662 * FwDownloadBoot requires Programmed IO access. 3663 * 3664 * Returns 0 for success 3665 * -1 FW Image size is 0 3666 * -2 No valid cached_fw Pointer 3667 * <0 for fw upload failure. 3668 */ 3669 static int 3670 mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag) 3671 { 3672 MpiExtImageHeader_t *pExtImage; 3673 u32 fwSize; 3674 u32 diag0val; 3675 int count; 3676 u32 *ptrFw; 3677 u32 diagRwData; 3678 u32 nextImage; 3679 u32 load_addr; 3680 u32 ioc_state=0; 3681 3682 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n", 3683 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader)); 3684 3685 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3686 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3687 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3688 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3689 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3690 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3691 3692 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM)); 3693 3694 /* wait 1 msec */ 3695 if (sleepFlag == CAN_SLEEP) { 3696 msleep(1); 3697 } else { 3698 mdelay (1); 3699 } 3700 3701 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3702 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 3703 3704 for (count = 0; count < 30; count ++) { 3705 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3706 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 3707 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n", 3708 ioc->name, count)); 3709 break; 3710 } 3711 /* wait .1 sec */ 3712 if (sleepFlag == CAN_SLEEP) { 3713 msleep (100); 3714 } else { 3715 mdelay (100); 3716 } 3717 } 3718 3719 if ( count == 30 ) { 3720 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! " 3721 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n", 3722 ioc->name, diag0val)); 3723 return -3; 3724 } 3725 3726 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3727 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3728 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3729 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3730 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3731 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3732 3733 /* Set the DiagRwEn and Disable ARM bits */ 3734 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM)); 3735 3736 fwSize = (pFwHeader->ImageSize + 3)/4; 3737 ptrFw = (u32 *) pFwHeader; 3738 3739 /* Write the LoadStartAddress to the DiagRw Address Register 3740 * using Programmed IO 3741 */ 3742 if (ioc->errata_flag_1064) 3743 pci_enable_io_access(ioc->pcidev); 3744 3745 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress); 3746 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n", 3747 ioc->name, pFwHeader->LoadStartAddress)); 3748 3749 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n", 3750 ioc->name, fwSize*4, ptrFw)); 3751 while (fwSize--) { 3752 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3753 } 3754 3755 nextImage = pFwHeader->NextImageHeaderOffset; 3756 while (nextImage) { 3757 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage); 3758 3759 load_addr = pExtImage->LoadStartAddress; 3760 3761 fwSize = (pExtImage->ImageSize + 3) >> 2; 3762 ptrFw = (u32 *)pExtImage; 3763 3764 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n", 3765 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr)); 3766 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr); 3767 3768 while (fwSize--) { 3769 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3770 } 3771 nextImage = pExtImage->NextImageHeaderOffset; 3772 } 3773 3774 /* Write the IopResetVectorRegAddr */ 3775 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr)); 3776 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr); 3777 3778 /* Write the IopResetVectorValue */ 3779 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue)); 3780 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue); 3781 3782 /* Clear the internal flash bad bit - autoincrementing register, 3783 * so must do two writes. 3784 */ 3785 if (ioc->bus_type == SPI) { 3786 /* 3787 * 1030 and 1035 H/W errata, workaround to access 3788 * the ClearFlashBadSignatureBit 3789 */ 3790 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3791 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData); 3792 diagRwData |= 0x40000000; 3793 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3794 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData); 3795 3796 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ { 3797 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3798 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | 3799 MPI_DIAG_CLEAR_FLASH_BAD_SIG); 3800 3801 /* wait 1 msec */ 3802 if (sleepFlag == CAN_SLEEP) { 3803 msleep (1); 3804 } else { 3805 mdelay (1); 3806 } 3807 } 3808 3809 if (ioc->errata_flag_1064) 3810 pci_disable_io_access(ioc->pcidev); 3811 3812 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3813 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, " 3814 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n", 3815 ioc->name, diag0val)); 3816 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE); 3817 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n", 3818 ioc->name, diag0val)); 3819 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 3820 3821 /* Write 0xFF to reset the sequencer */ 3822 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3823 3824 if (ioc->bus_type == SAS) { 3825 ioc_state = mpt_GetIocState(ioc, 0); 3826 if ( (GetIocFacts(ioc, sleepFlag, 3827 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) { 3828 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n", 3829 ioc->name, ioc_state)); 3830 return -EFAULT; 3831 } 3832 } 3833 3834 for (count=0; count<HZ*20; count++) { 3835 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) { 3836 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3837 "downloadboot successful! (count=%d) IocState=%x\n", 3838 ioc->name, count, ioc_state)); 3839 if (ioc->bus_type == SAS) { 3840 return 0; 3841 } 3842 if ((SendIocInit(ioc, sleepFlag)) != 0) { 3843 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3844 "downloadboot: SendIocInit failed\n", 3845 ioc->name)); 3846 return -EFAULT; 3847 } 3848 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3849 "downloadboot: SendIocInit successful\n", 3850 ioc->name)); 3851 return 0; 3852 } 3853 if (sleepFlag == CAN_SLEEP) { 3854 msleep (10); 3855 } else { 3856 mdelay (10); 3857 } 3858 } 3859 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3860 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state)); 3861 return -EFAULT; 3862 } 3863 3864 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3865 /** 3866 * KickStart - Perform hard reset of MPT adapter. 3867 * @ioc: Pointer to MPT_ADAPTER structure 3868 * @force: Force hard reset 3869 * @sleepFlag: Specifies whether the process can sleep 3870 * 3871 * This routine places MPT adapter in diagnostic mode via the 3872 * WriteSequence register, and then performs a hard reset of adapter 3873 * via the Diagnostic register. 3874 * 3875 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread) 3876 * or NO_SLEEP (interrupt thread, use mdelay) 3877 * force - 1 if doorbell active, board fault state 3878 * board operational, IOC_RECOVERY or 3879 * IOC_BRINGUP and there is an alt_ioc. 3880 * 0 else 3881 * 3882 * Returns: 3883 * 1 - hard reset, READY 3884 * 0 - no reset due to History bit, READY 3885 * -1 - no reset due to History bit but not READY 3886 * OR reset but failed to come READY 3887 * -2 - no reset, could not enter DIAG mode 3888 * -3 - reset but bad FW bit 3889 */ 3890 static int 3891 KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag) 3892 { 3893 int hard_reset_done = 0; 3894 u32 ioc_state=0; 3895 int cnt,cntdn; 3896 3897 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name)); 3898 if (ioc->bus_type == SPI) { 3899 /* Always issue a Msg Unit Reset first. This will clear some 3900 * SCSI bus hang conditions. 3901 */ 3902 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 3903 3904 if (sleepFlag == CAN_SLEEP) { 3905 msleep (1000); 3906 } else { 3907 mdelay (1000); 3908 } 3909 } 3910 3911 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag); 3912 if (hard_reset_done < 0) 3913 return hard_reset_done; 3914 3915 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n", 3916 ioc->name)); 3917 3918 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */ 3919 for (cnt=0; cnt<cntdn; cnt++) { 3920 ioc_state = mpt_GetIocState(ioc, 1); 3921 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) { 3922 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n", 3923 ioc->name, cnt)); 3924 return hard_reset_done; 3925 } 3926 if (sleepFlag == CAN_SLEEP) { 3927 msleep (10); 3928 } else { 3929 mdelay (10); 3930 } 3931 } 3932 3933 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n", 3934 ioc->name, mpt_GetIocState(ioc, 0))); 3935 return -1; 3936 } 3937 3938 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3939 /** 3940 * mpt_diag_reset - Perform hard reset of the adapter. 3941 * @ioc: Pointer to MPT_ADAPTER structure 3942 * @ignore: Set if to honor and clear to ignore 3943 * the reset history bit 3944 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread, 3945 * else set to NO_SLEEP (use mdelay instead) 3946 * 3947 * This routine places the adapter in diagnostic mode via the 3948 * WriteSequence register and then performs a hard reset of adapter 3949 * via the Diagnostic register. Adapter should be in ready state 3950 * upon successful completion. 3951 * 3952 * Returns: 1 hard reset successful 3953 * 0 no reset performed because reset history bit set 3954 * -2 enabling diagnostic mode failed 3955 * -3 diagnostic reset failed 3956 */ 3957 static int 3958 mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag) 3959 { 3960 u32 diag0val; 3961 u32 doorbell; 3962 int hard_reset_done = 0; 3963 int count = 0; 3964 u32 diag1val = 0; 3965 MpiFwHeader_t *cached_fw; /* Pointer to FW */ 3966 u8 cb_idx; 3967 3968 /* Clear any existing interrupts */ 3969 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 3970 3971 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) { 3972 3973 if (!ignore) 3974 return 0; 3975 3976 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset " 3977 "address=%p\n", ioc->name, __func__, 3978 &ioc->chip->Doorbell, &ioc->chip->Reset_1078)); 3979 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07); 3980 if (sleepFlag == CAN_SLEEP) 3981 msleep(1); 3982 else 3983 mdelay(1); 3984 3985 /* 3986 * Call each currently registered protocol IOC reset handler 3987 * with pre-reset indication. 3988 * NOTE: If we're doing _IOC_BRINGUP, there can be no 3989 * MptResetHandlers[] registered yet. 3990 */ 3991 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 3992 if (MptResetHandlers[cb_idx]) 3993 (*(MptResetHandlers[cb_idx]))(ioc, 3994 MPT_IOC_PRE_RESET); 3995 } 3996 3997 for (count = 0; count < 60; count ++) { 3998 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 3999 doorbell &= MPI_IOC_STATE_MASK; 4000 4001 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4002 "looking for READY STATE: doorbell=%x" 4003 " count=%d\n", 4004 ioc->name, doorbell, count)); 4005 4006 if (doorbell == MPI_IOC_STATE_READY) { 4007 return 1; 4008 } 4009 4010 /* wait 1 sec */ 4011 if (sleepFlag == CAN_SLEEP) 4012 msleep(1000); 4013 else 4014 mdelay(1000); 4015 } 4016 return -1; 4017 } 4018 4019 /* Use "Diagnostic reset" method! (only thing available!) */ 4020 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4021 4022 if (ioc->debug_level & MPT_DEBUG) { 4023 if (ioc->alt_ioc) 4024 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4025 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n", 4026 ioc->name, diag0val, diag1val)); 4027 } 4028 4029 /* Do the reset if we are told to ignore the reset history 4030 * or if the reset history is 0 4031 */ 4032 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) { 4033 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4034 /* Write magic sequence to WriteSequence register 4035 * Loop until in diagnostic mode 4036 */ 4037 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4038 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4039 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4040 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4041 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4042 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4043 4044 /* wait 100 msec */ 4045 if (sleepFlag == CAN_SLEEP) { 4046 msleep (100); 4047 } else { 4048 mdelay (100); 4049 } 4050 4051 count++; 4052 if (count > 20) { 4053 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4054 ioc->name, diag0val); 4055 return -2; 4056 4057 } 4058 4059 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4060 4061 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n", 4062 ioc->name, diag0val)); 4063 } 4064 4065 if (ioc->debug_level & MPT_DEBUG) { 4066 if (ioc->alt_ioc) 4067 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4068 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n", 4069 ioc->name, diag0val, diag1val)); 4070 } 4071 /* 4072 * Disable the ARM (Bug fix) 4073 * 4074 */ 4075 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM); 4076 mdelay(1); 4077 4078 /* 4079 * Now hit the reset bit in the Diagnostic register 4080 * (THE BIG HAMMER!) (Clears DRWE bit). 4081 */ 4082 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 4083 hard_reset_done = 1; 4084 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n", 4085 ioc->name)); 4086 4087 /* 4088 * Call each currently registered protocol IOC reset handler 4089 * with pre-reset indication. 4090 * NOTE: If we're doing _IOC_BRINGUP, there can be no 4091 * MptResetHandlers[] registered yet. 4092 */ 4093 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 4094 if (MptResetHandlers[cb_idx]) { 4095 mpt_signal_reset(cb_idx, 4096 ioc, MPT_IOC_PRE_RESET); 4097 if (ioc->alt_ioc) { 4098 mpt_signal_reset(cb_idx, 4099 ioc->alt_ioc, MPT_IOC_PRE_RESET); 4100 } 4101 } 4102 } 4103 4104 if (ioc->cached_fw) 4105 cached_fw = (MpiFwHeader_t *)ioc->cached_fw; 4106 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) 4107 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw; 4108 else 4109 cached_fw = NULL; 4110 if (cached_fw) { 4111 /* If the DownloadBoot operation fails, the 4112 * IOC will be left unusable. This is a fatal error 4113 * case. _diag_reset will return < 0 4114 */ 4115 for (count = 0; count < 30; count ++) { 4116 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4117 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 4118 break; 4119 } 4120 4121 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n", 4122 ioc->name, diag0val, count)); 4123 /* wait 1 sec */ 4124 if (sleepFlag == CAN_SLEEP) { 4125 msleep (1000); 4126 } else { 4127 mdelay (1000); 4128 } 4129 } 4130 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) { 4131 printk(MYIOC_s_WARN_FMT 4132 "firmware downloadboot failure (%d)!\n", ioc->name, count); 4133 } 4134 4135 } else { 4136 /* Wait for FW to reload and for board 4137 * to go to the READY state. 4138 * Maximum wait is 60 seconds. 4139 * If fail, no error will check again 4140 * with calling program. 4141 */ 4142 for (count = 0; count < 60; count ++) { 4143 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 4144 doorbell &= MPI_IOC_STATE_MASK; 4145 4146 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4147 "looking for READY STATE: doorbell=%x" 4148 " count=%d\n", ioc->name, doorbell, count)); 4149 4150 if (doorbell == MPI_IOC_STATE_READY) { 4151 break; 4152 } 4153 4154 /* wait 1 sec */ 4155 if (sleepFlag == CAN_SLEEP) { 4156 msleep (1000); 4157 } else { 4158 mdelay (1000); 4159 } 4160 } 4161 4162 if (doorbell != MPI_IOC_STATE_READY) 4163 printk(MYIOC_s_ERR_FMT "Failed to come READY " 4164 "after reset! IocState=%x", ioc->name, 4165 doorbell); 4166 } 4167 } 4168 4169 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4170 if (ioc->debug_level & MPT_DEBUG) { 4171 if (ioc->alt_ioc) 4172 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4173 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n", 4174 ioc->name, diag0val, diag1val)); 4175 } 4176 4177 /* Clear RESET_HISTORY bit! Place board in the 4178 * diagnostic mode to update the diag register. 4179 */ 4180 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4181 count = 0; 4182 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4183 /* Write magic sequence to WriteSequence register 4184 * Loop until in diagnostic mode 4185 */ 4186 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4187 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4188 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4189 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4190 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4191 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4192 4193 /* wait 100 msec */ 4194 if (sleepFlag == CAN_SLEEP) { 4195 msleep (100); 4196 } else { 4197 mdelay (100); 4198 } 4199 4200 count++; 4201 if (count > 20) { 4202 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4203 ioc->name, diag0val); 4204 break; 4205 } 4206 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4207 } 4208 diag0val &= ~MPI_DIAG_RESET_HISTORY; 4209 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 4210 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4211 if (diag0val & MPI_DIAG_RESET_HISTORY) { 4212 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n", 4213 ioc->name); 4214 } 4215 4216 /* Disable Diagnostic Mode 4217 */ 4218 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF); 4219 4220 /* Check FW reload status flags. 4221 */ 4222 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4223 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) { 4224 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n", 4225 ioc->name, diag0val); 4226 return -3; 4227 } 4228 4229 if (ioc->debug_level & MPT_DEBUG) { 4230 if (ioc->alt_ioc) 4231 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4232 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n", 4233 ioc->name, diag0val, diag1val)); 4234 } 4235 4236 /* 4237 * Reset flag that says we've enabled event notification 4238 */ 4239 ioc->facts.EventState = 0; 4240 4241 if (ioc->alt_ioc) 4242 ioc->alt_ioc->facts.EventState = 0; 4243 4244 return hard_reset_done; 4245 } 4246 4247 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4248 /** 4249 * SendIocReset - Send IOCReset request to MPT adapter. 4250 * @ioc: Pointer to MPT_ADAPTER structure 4251 * @reset_type: reset type, expected values are 4252 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET 4253 * @sleepFlag: Specifies whether the process can sleep 4254 * 4255 * Send IOCReset request to the MPT adapter. 4256 * 4257 * Returns 0 for success, non-zero for failure. 4258 */ 4259 static int 4260 SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag) 4261 { 4262 int r; 4263 u32 state; 4264 int cntdn, count; 4265 4266 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n", 4267 ioc->name, reset_type)); 4268 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT); 4269 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4270 return r; 4271 4272 /* FW ACK'd request, wait for READY state 4273 */ 4274 count = 0; 4275 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */ 4276 4277 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 4278 cntdn--; 4279 count++; 4280 if (!cntdn) { 4281 if (sleepFlag != CAN_SLEEP) 4282 count *= 10; 4283 4284 printk(MYIOC_s_ERR_FMT 4285 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 4286 ioc->name, state, (int)((count+5)/HZ)); 4287 return -ETIME; 4288 } 4289 4290 if (sleepFlag == CAN_SLEEP) { 4291 msleep(1); 4292 } else { 4293 mdelay (1); /* 1 msec delay */ 4294 } 4295 } 4296 4297 /* TODO! 4298 * Cleanup all event stuff for this IOC; re-issue EventNotification 4299 * request if needed. 4300 */ 4301 if (ioc->facts.Function) 4302 ioc->facts.EventState = 0; 4303 4304 return 0; 4305 } 4306 4307 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4308 /** 4309 * initChainBuffers - Allocate memory for and initialize chain buffers 4310 * @ioc: Pointer to MPT_ADAPTER structure 4311 * 4312 * Allocates memory for and initializes chain buffers, 4313 * chain buffer control arrays and spinlock. 4314 */ 4315 static int 4316 initChainBuffers(MPT_ADAPTER *ioc) 4317 { 4318 u8 *mem; 4319 int sz, ii, num_chain; 4320 int scale, num_sge, numSGE; 4321 4322 /* ReqToChain size must equal the req_depth 4323 * index = req_idx 4324 */ 4325 if (ioc->ReqToChain == NULL) { 4326 sz = ioc->req_depth * sizeof(int); 4327 mem = kmalloc(sz, GFP_ATOMIC); 4328 if (mem == NULL) 4329 return -1; 4330 4331 ioc->ReqToChain = (int *) mem; 4332 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n", 4333 ioc->name, mem, sz)); 4334 mem = kmalloc(sz, GFP_ATOMIC); 4335 if (mem == NULL) 4336 return -1; 4337 4338 ioc->RequestNB = (int *) mem; 4339 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n", 4340 ioc->name, mem, sz)); 4341 } 4342 for (ii = 0; ii < ioc->req_depth; ii++) { 4343 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN; 4344 } 4345 4346 /* ChainToChain size must equal the total number 4347 * of chain buffers to be allocated. 4348 * index = chain_idx 4349 * 4350 * Calculate the number of chain buffers needed(plus 1) per I/O 4351 * then multiply the maximum number of simultaneous cmds 4352 * 4353 * num_sge = num sge in request frame + last chain buffer 4354 * scale = num sge per chain buffer if no chain element 4355 */ 4356 scale = ioc->req_sz / ioc->SGE_size; 4357 if (ioc->sg_addr_size == sizeof(u64)) 4358 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size; 4359 else 4360 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size; 4361 4362 if (ioc->sg_addr_size == sizeof(u64)) { 4363 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale + 4364 (ioc->req_sz - 60) / ioc->SGE_size; 4365 } else { 4366 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) + 4367 scale + (ioc->req_sz - 64) / ioc->SGE_size; 4368 } 4369 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n", 4370 ioc->name, num_sge, numSGE)); 4371 4372 if (ioc->bus_type == FC) { 4373 if (numSGE > MPT_SCSI_FC_SG_DEPTH) 4374 numSGE = MPT_SCSI_FC_SG_DEPTH; 4375 } else { 4376 if (numSGE > MPT_SCSI_SG_DEPTH) 4377 numSGE = MPT_SCSI_SG_DEPTH; 4378 } 4379 4380 num_chain = 1; 4381 while (numSGE - num_sge > 0) { 4382 num_chain++; 4383 num_sge += (scale - 1); 4384 } 4385 num_chain++; 4386 4387 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n", 4388 ioc->name, numSGE, num_sge, num_chain)); 4389 4390 if (ioc->bus_type == SPI) 4391 num_chain *= MPT_SCSI_CAN_QUEUE; 4392 else if (ioc->bus_type == SAS) 4393 num_chain *= MPT_SAS_CAN_QUEUE; 4394 else 4395 num_chain *= MPT_FC_CAN_QUEUE; 4396 4397 ioc->num_chain = num_chain; 4398 4399 sz = num_chain * sizeof(int); 4400 if (ioc->ChainToChain == NULL) { 4401 mem = kmalloc(sz, GFP_ATOMIC); 4402 if (mem == NULL) 4403 return -1; 4404 4405 ioc->ChainToChain = (int *) mem; 4406 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n", 4407 ioc->name, mem, sz)); 4408 } else { 4409 mem = (u8 *) ioc->ChainToChain; 4410 } 4411 memset(mem, 0xFF, sz); 4412 return num_chain; 4413 } 4414 4415 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4416 /** 4417 * PrimeIocFifos - Initialize IOC request and reply FIFOs. 4418 * @ioc: Pointer to MPT_ADAPTER structure 4419 * 4420 * This routine allocates memory for the MPT reply and request frame 4421 * pools (if necessary), and primes the IOC reply FIFO with 4422 * reply frames. 4423 * 4424 * Returns 0 for success, non-zero for failure. 4425 */ 4426 static int 4427 PrimeIocFifos(MPT_ADAPTER *ioc) 4428 { 4429 MPT_FRAME_HDR *mf; 4430 unsigned long flags; 4431 dma_addr_t alloc_dma; 4432 u8 *mem; 4433 int i, reply_sz, sz, total_size, num_chain; 4434 u64 dma_mask; 4435 4436 dma_mask = 0; 4437 4438 /* Prime reply FIFO... */ 4439 4440 if (ioc->reply_frames == NULL) { 4441 if ( (num_chain = initChainBuffers(ioc)) < 0) 4442 return -1; 4443 /* 4444 * 1078 errata workaround for the 36GB limitation 4445 */ 4446 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 && 4447 ioc->dma_mask > DMA_BIT_MASK(35)) { 4448 if (!dma_set_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32)) 4449 && !dma_set_coherent_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32))) { 4450 dma_mask = DMA_BIT_MASK(35); 4451 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4452 "setting 35 bit addressing for " 4453 "Request/Reply/Chain and Sense Buffers\n", 4454 ioc->name)); 4455 } else { 4456 /*Reseting DMA mask to 64 bit*/ 4457 dma_set_mask(&ioc->pcidev->dev, 4458 DMA_BIT_MASK(64)); 4459 dma_set_coherent_mask(&ioc->pcidev->dev, 4460 DMA_BIT_MASK(64)); 4461 4462 printk(MYIOC_s_ERR_FMT 4463 "failed setting 35 bit addressing for " 4464 "Request/Reply/Chain and Sense Buffers\n", 4465 ioc->name); 4466 return -1; 4467 } 4468 } 4469 4470 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth); 4471 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n", 4472 ioc->name, ioc->reply_sz, ioc->reply_depth)); 4473 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n", 4474 ioc->name, reply_sz, reply_sz)); 4475 4476 sz = (ioc->req_sz * ioc->req_depth); 4477 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n", 4478 ioc->name, ioc->req_sz, ioc->req_depth)); 4479 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n", 4480 ioc->name, sz, sz)); 4481 total_size += sz; 4482 4483 sz = num_chain * ioc->req_sz; /* chain buffer pool size */ 4484 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n", 4485 ioc->name, ioc->req_sz, num_chain)); 4486 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n", 4487 ioc->name, sz, sz, num_chain)); 4488 4489 total_size += sz; 4490 mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size, 4491 &alloc_dma, GFP_KERNEL); 4492 if (mem == NULL) { 4493 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n", 4494 ioc->name); 4495 goto out_fail; 4496 } 4497 4498 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n", 4499 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size)); 4500 4501 memset(mem, 0, total_size); 4502 ioc->alloc_total += total_size; 4503 ioc->alloc = mem; 4504 ioc->alloc_dma = alloc_dma; 4505 ioc->alloc_sz = total_size; 4506 ioc->reply_frames = (MPT_FRAME_HDR *) mem; 4507 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4508 4509 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4510 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4511 4512 alloc_dma += reply_sz; 4513 mem += reply_sz; 4514 4515 /* Request FIFO - WE manage this! */ 4516 4517 ioc->req_frames = (MPT_FRAME_HDR *) mem; 4518 ioc->req_frames_dma = alloc_dma; 4519 4520 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n", 4521 ioc->name, mem, (void *)(ulong)alloc_dma)); 4522 4523 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4524 4525 for (i = 0; i < ioc->req_depth; i++) { 4526 alloc_dma += ioc->req_sz; 4527 mem += ioc->req_sz; 4528 } 4529 4530 ioc->ChainBuffer = mem; 4531 ioc->ChainBufferDMA = alloc_dma; 4532 4533 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n", 4534 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA)); 4535 4536 /* Initialize the free chain Q. 4537 */ 4538 4539 INIT_LIST_HEAD(&ioc->FreeChainQ); 4540 4541 /* Post the chain buffers to the FreeChainQ. 4542 */ 4543 mem = (u8 *)ioc->ChainBuffer; 4544 for (i=0; i < num_chain; i++) { 4545 mf = (MPT_FRAME_HDR *) mem; 4546 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ); 4547 mem += ioc->req_sz; 4548 } 4549 4550 /* Initialize Request frames linked list 4551 */ 4552 alloc_dma = ioc->req_frames_dma; 4553 mem = (u8 *) ioc->req_frames; 4554 4555 spin_lock_irqsave(&ioc->FreeQlock, flags); 4556 INIT_LIST_HEAD(&ioc->FreeQ); 4557 for (i = 0; i < ioc->req_depth; i++) { 4558 mf = (MPT_FRAME_HDR *) mem; 4559 4560 /* Queue REQUESTs *internally*! */ 4561 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ); 4562 4563 mem += ioc->req_sz; 4564 } 4565 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 4566 4567 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4568 ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz, 4569 &ioc->sense_buf_pool_dma, GFP_KERNEL); 4570 if (ioc->sense_buf_pool == NULL) { 4571 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n", 4572 ioc->name); 4573 goto out_fail; 4574 } 4575 4576 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF); 4577 ioc->alloc_total += sz; 4578 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n", 4579 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma)); 4580 4581 } 4582 4583 /* Post Reply frames to FIFO 4584 */ 4585 alloc_dma = ioc->alloc_dma; 4586 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4587 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4588 4589 for (i = 0; i < ioc->reply_depth; i++) { 4590 /* Write each address to the IOC! */ 4591 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma); 4592 alloc_dma += ioc->reply_sz; 4593 } 4594 4595 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev, 4596 ioc->dma_mask) && !dma_set_coherent_mask(&ioc->pcidev->dev, 4597 ioc->dma_mask)) 4598 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4599 "restoring 64 bit addressing\n", ioc->name)); 4600 4601 return 0; 4602 4603 out_fail: 4604 4605 if (ioc->alloc != NULL) { 4606 sz = ioc->alloc_sz; 4607 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 4608 ioc->alloc_dma); 4609 ioc->reply_frames = NULL; 4610 ioc->req_frames = NULL; 4611 ioc->alloc_total -= sz; 4612 } 4613 if (ioc->sense_buf_pool != NULL) { 4614 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4615 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 4616 ioc->sense_buf_pool_dma); 4617 ioc->sense_buf_pool = NULL; 4618 } 4619 4620 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev, 4621 DMA_BIT_MASK(64)) && !dma_set_coherent_mask(&ioc->pcidev->dev, 4622 DMA_BIT_MASK(64))) 4623 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4624 "restoring 64 bit addressing\n", ioc->name)); 4625 4626 return -1; 4627 } 4628 4629 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4630 /** 4631 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply 4632 * from IOC via doorbell handshake method. 4633 * @ioc: Pointer to MPT_ADAPTER structure 4634 * @reqBytes: Size of the request in bytes 4635 * @req: Pointer to MPT request frame 4636 * @replyBytes: Expected size of the reply in bytes 4637 * @u16reply: Pointer to area where reply should be written 4638 * @maxwait: Max wait time for a reply (in seconds) 4639 * @sleepFlag: Specifies whether the process can sleep 4640 * 4641 * NOTES: It is the callers responsibility to byte-swap fields in the 4642 * request which are greater than 1 byte in size. It is also the 4643 * callers responsibility to byte-swap response fields which are 4644 * greater than 1 byte in size. 4645 * 4646 * Returns 0 for success, non-zero for failure. 4647 */ 4648 static int 4649 mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req, 4650 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag) 4651 { 4652 MPIDefaultReply_t *mptReply; 4653 int failcnt = 0; 4654 int t; 4655 4656 /* 4657 * Get ready to cache a handshake reply 4658 */ 4659 ioc->hs_reply_idx = 0; 4660 mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4661 mptReply->MsgLength = 0; 4662 4663 /* 4664 * Make sure there are no doorbells (WRITE 0 to IntStatus reg), 4665 * then tell IOC that we want to handshake a request of N words. 4666 * (WRITE u32val to Doorbell reg). 4667 */ 4668 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4669 CHIPREG_WRITE32(&ioc->chip->Doorbell, 4670 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 4671 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 4672 4673 /* 4674 * Wait for IOC's doorbell handshake int 4675 */ 4676 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4677 failcnt++; 4678 4679 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n", 4680 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4681 4682 /* Read doorbell and check for active bit */ 4683 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 4684 return -1; 4685 4686 /* 4687 * Clear doorbell int (WRITE 0 to IntStatus reg), 4688 * then wait for IOC to ACKnowledge that it's ready for 4689 * our handshake request. 4690 */ 4691 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4692 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4693 failcnt++; 4694 4695 if (!failcnt) { 4696 int ii; 4697 u8 *req_as_bytes = (u8 *) req; 4698 4699 /* 4700 * Stuff request words via doorbell handshake, 4701 * with ACK from IOC for each. 4702 */ 4703 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) { 4704 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) | 4705 (req_as_bytes[(ii*4) + 1] << 8) | 4706 (req_as_bytes[(ii*4) + 2] << 16) | 4707 (req_as_bytes[(ii*4) + 3] << 24)); 4708 4709 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 4710 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4711 failcnt++; 4712 } 4713 4714 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req)); 4715 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req); 4716 4717 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n", 4718 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : "")); 4719 4720 /* 4721 * Wait for completion of doorbell handshake reply from the IOC 4722 */ 4723 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0) 4724 failcnt++; 4725 4726 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n", 4727 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : "")); 4728 4729 /* 4730 * Copy out the cached reply... 4731 */ 4732 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++) 4733 u16reply[ii] = ioc->hs_reply[ii]; 4734 } else { 4735 return -99; 4736 } 4737 4738 return -failcnt; 4739 } 4740 4741 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4742 /** 4743 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge 4744 * @ioc: Pointer to MPT_ADAPTER structure 4745 * @howlong: How long to wait (in seconds) 4746 * @sleepFlag: Specifies whether the process can sleep 4747 * 4748 * This routine waits (up to ~2 seconds max) for IOC doorbell 4749 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS 4750 * bit in its IntStatus register being clear. 4751 * 4752 * Returns a negative value on failure, else wait loop count. 4753 */ 4754 static int 4755 WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4756 { 4757 int cntdn; 4758 int count = 0; 4759 u32 intstat=0; 4760 4761 cntdn = 1000 * howlong; 4762 4763 if (sleepFlag == CAN_SLEEP) { 4764 while (--cntdn) { 4765 msleep (1); 4766 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4767 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4768 break; 4769 count++; 4770 } 4771 } else { 4772 while (--cntdn) { 4773 udelay (1000); 4774 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4775 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4776 break; 4777 count++; 4778 } 4779 } 4780 4781 if (cntdn) { 4782 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n", 4783 ioc->name, count)); 4784 return count; 4785 } 4786 4787 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n", 4788 ioc->name, count, intstat); 4789 return -1; 4790 } 4791 4792 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4793 /** 4794 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit 4795 * @ioc: Pointer to MPT_ADAPTER structure 4796 * @howlong: How long to wait (in seconds) 4797 * @sleepFlag: Specifies whether the process can sleep 4798 * 4799 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt 4800 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register. 4801 * 4802 * Returns a negative value on failure, else wait loop count. 4803 */ 4804 static int 4805 WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4806 { 4807 int cntdn; 4808 int count = 0; 4809 u32 intstat=0; 4810 4811 cntdn = 1000 * howlong; 4812 if (sleepFlag == CAN_SLEEP) { 4813 while (--cntdn) { 4814 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4815 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4816 break; 4817 msleep(1); 4818 count++; 4819 } 4820 } else { 4821 while (--cntdn) { 4822 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4823 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4824 break; 4825 udelay (1000); 4826 count++; 4827 } 4828 } 4829 4830 if (cntdn) { 4831 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n", 4832 ioc->name, count, howlong)); 4833 return count; 4834 } 4835 4836 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n", 4837 ioc->name, count, intstat); 4838 return -1; 4839 } 4840 4841 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4842 /** 4843 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply. 4844 * @ioc: Pointer to MPT_ADAPTER structure 4845 * @howlong: How long to wait (in seconds) 4846 * @sleepFlag: Specifies whether the process can sleep 4847 * 4848 * This routine polls the IOC for a handshake reply, 16 bits at a time. 4849 * Reply is cached to IOC private area large enough to hold a maximum 4850 * of 128 bytes of reply data. 4851 * 4852 * Returns a negative value on failure, else size of reply in WORDS. 4853 */ 4854 static int 4855 WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4856 { 4857 int u16cnt = 0; 4858 int failcnt = 0; 4859 int t; 4860 u16 *hs_reply = ioc->hs_reply; 4861 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4862 u16 hword; 4863 4864 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0; 4865 4866 /* 4867 * Get first two u16's so we can look at IOC's intended reply MsgLength 4868 */ 4869 u16cnt=0; 4870 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) { 4871 failcnt++; 4872 } else { 4873 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4874 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4875 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4876 failcnt++; 4877 else { 4878 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4879 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4880 } 4881 } 4882 4883 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n", 4884 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply), 4885 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4886 4887 /* 4888 * If no error (and IOC said MsgLength is > 0), piece together 4889 * reply 16 bits at a time. 4890 */ 4891 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) { 4892 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4893 failcnt++; 4894 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4895 /* don't overflow our IOC hs_reply[] buffer! */ 4896 if (u16cnt < ARRAY_SIZE(ioc->hs_reply)) 4897 hs_reply[u16cnt] = hword; 4898 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4899 } 4900 4901 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4902 failcnt++; 4903 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4904 4905 if (failcnt) { 4906 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n", 4907 ioc->name); 4908 return -failcnt; 4909 } 4910 #if 0 4911 else if (u16cnt != (2 * mptReply->MsgLength)) { 4912 return -101; 4913 } 4914 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 4915 return -102; 4916 } 4917 #endif 4918 4919 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name)); 4920 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply); 4921 4922 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n", 4923 ioc->name, t, u16cnt/2)); 4924 return u16cnt/2; 4925 } 4926 4927 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4928 /** 4929 * GetLanConfigPages - Fetch LANConfig pages. 4930 * @ioc: Pointer to MPT_ADAPTER structure 4931 * 4932 * Return: 0 for success 4933 * -ENOMEM if no memory available 4934 * -EPERM if not allowed due to ISR context 4935 * -EAGAIN if no msg frames currently available 4936 * -EFAULT for non-successful reply or no reply (timeout) 4937 */ 4938 static int 4939 GetLanConfigPages(MPT_ADAPTER *ioc) 4940 { 4941 ConfigPageHeader_t hdr; 4942 CONFIGPARMS cfg; 4943 LANPage0_t *ppage0_alloc; 4944 dma_addr_t page0_dma; 4945 LANPage1_t *ppage1_alloc; 4946 dma_addr_t page1_dma; 4947 int rc = 0; 4948 int data_sz; 4949 int copy_sz; 4950 4951 /* Get LAN Page 0 header */ 4952 hdr.PageVersion = 0; 4953 hdr.PageLength = 0; 4954 hdr.PageNumber = 0; 4955 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 4956 cfg.cfghdr.hdr = &hdr; 4957 cfg.physAddr = -1; 4958 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 4959 cfg.dir = 0; 4960 cfg.pageAddr = 0; 4961 cfg.timeout = 0; 4962 4963 if ((rc = mpt_config(ioc, &cfg)) != 0) 4964 return rc; 4965 4966 if (hdr.PageLength > 0) { 4967 data_sz = hdr.PageLength * 4; 4968 ppage0_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma); 4969 rc = -ENOMEM; 4970 if (ppage0_alloc) { 4971 memset((u8 *)ppage0_alloc, 0, data_sz); 4972 cfg.physAddr = page0_dma; 4973 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 4974 4975 if ((rc = mpt_config(ioc, &cfg)) == 0) { 4976 /* save the data */ 4977 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz); 4978 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz); 4979 4980 } 4981 4982 dma_free_coherent(&ioc->pcidev->dev, data_sz, 4983 (u8 *)ppage0_alloc, page0_dma); 4984 4985 /* FIXME! 4986 * Normalize endianness of structure data, 4987 * by byte-swapping all > 1 byte fields! 4988 */ 4989 4990 } 4991 4992 if (rc) 4993 return rc; 4994 } 4995 4996 /* Get LAN Page 1 header */ 4997 hdr.PageVersion = 0; 4998 hdr.PageLength = 0; 4999 hdr.PageNumber = 1; 5000 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 5001 cfg.cfghdr.hdr = &hdr; 5002 cfg.physAddr = -1; 5003 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5004 cfg.dir = 0; 5005 cfg.pageAddr = 0; 5006 5007 if ((rc = mpt_config(ioc, &cfg)) != 0) 5008 return rc; 5009 5010 if (hdr.PageLength == 0) 5011 return 0; 5012 5013 data_sz = hdr.PageLength * 4; 5014 rc = -ENOMEM; 5015 ppage1_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma); 5016 if (ppage1_alloc) { 5017 memset((u8 *)ppage1_alloc, 0, data_sz); 5018 cfg.physAddr = page1_dma; 5019 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5020 5021 if ((rc = mpt_config(ioc, &cfg)) == 0) { 5022 /* save the data */ 5023 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz); 5024 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz); 5025 } 5026 5027 dma_free_coherent(&ioc->pcidev->dev, data_sz, 5028 (u8 *)ppage1_alloc, page1_dma); 5029 5030 /* FIXME! 5031 * Normalize endianness of structure data, 5032 * by byte-swapping all > 1 byte fields! 5033 */ 5034 5035 } 5036 5037 return rc; 5038 } 5039 5040 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5041 /** 5042 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table 5043 * @ioc: Pointer to MPT_ADAPTER structure 5044 * @persist_opcode: see below 5045 * 5046 * =============================== ====================================== 5047 * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for 5048 * devices not currently present. 5049 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings 5050 * =============================== ====================================== 5051 * 5052 * NOTE: Don't use not this function during interrupt time. 5053 * 5054 * Returns 0 for success, non-zero error 5055 */ 5056 5057 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5058 int 5059 mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode) 5060 { 5061 SasIoUnitControlRequest_t *sasIoUnitCntrReq; 5062 SasIoUnitControlReply_t *sasIoUnitCntrReply; 5063 MPT_FRAME_HDR *mf = NULL; 5064 MPIHeader_t *mpi_hdr; 5065 int ret = 0; 5066 unsigned long timeleft; 5067 5068 mutex_lock(&ioc->mptbase_cmds.mutex); 5069 5070 /* init the internal cmd struct */ 5071 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 5072 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 5073 5074 /* insure garbage is not sent to fw */ 5075 switch(persist_opcode) { 5076 5077 case MPI_SAS_OP_CLEAR_NOT_PRESENT: 5078 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT: 5079 break; 5080 5081 default: 5082 ret = -1; 5083 goto out; 5084 } 5085 5086 printk(KERN_DEBUG "%s: persist_opcode=%x\n", 5087 __func__, persist_opcode); 5088 5089 /* Get a MF for this command. 5090 */ 5091 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 5092 printk(KERN_DEBUG "%s: no msg frames!\n", __func__); 5093 ret = -1; 5094 goto out; 5095 } 5096 5097 mpi_hdr = (MPIHeader_t *) mf; 5098 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf; 5099 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t)); 5100 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL; 5101 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext; 5102 sasIoUnitCntrReq->Operation = persist_opcode; 5103 5104 mpt_put_msg_frame(mpt_base_index, ioc, mf); 5105 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ); 5106 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 5107 ret = -ETIME; 5108 printk(KERN_DEBUG "%s: failed\n", __func__); 5109 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 5110 goto out; 5111 if (!timeleft) { 5112 printk(MYIOC_s_WARN_FMT 5113 "Issuing Reset from %s!!, doorbell=0x%08x\n", 5114 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 5115 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP); 5116 mpt_free_msg_frame(ioc, mf); 5117 } 5118 goto out; 5119 } 5120 5121 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 5122 ret = -1; 5123 goto out; 5124 } 5125 5126 sasIoUnitCntrReply = 5127 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply; 5128 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) { 5129 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n", 5130 __func__, sasIoUnitCntrReply->IOCStatus, 5131 sasIoUnitCntrReply->IOCLogInfo); 5132 printk(KERN_DEBUG "%s: failed\n", __func__); 5133 ret = -1; 5134 } else 5135 printk(KERN_DEBUG "%s: success\n", __func__); 5136 out: 5137 5138 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 5139 mutex_unlock(&ioc->mptbase_cmds.mutex); 5140 return ret; 5141 } 5142 5143 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5144 5145 static void 5146 mptbase_raid_process_event_data(MPT_ADAPTER *ioc, 5147 MpiEventDataRaid_t * pRaidEventData) 5148 { 5149 int volume; 5150 int reason; 5151 int disk; 5152 int status; 5153 int flags; 5154 int state; 5155 5156 volume = pRaidEventData->VolumeID; 5157 reason = pRaidEventData->ReasonCode; 5158 disk = pRaidEventData->PhysDiskNum; 5159 status = le32_to_cpu(pRaidEventData->SettingsStatus); 5160 flags = (status >> 0) & 0xff; 5161 state = (status >> 8) & 0xff; 5162 5163 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) { 5164 return; 5165 } 5166 5167 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED && 5168 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) || 5169 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) { 5170 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n", 5171 ioc->name, disk, volume); 5172 } else { 5173 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n", 5174 ioc->name, volume); 5175 } 5176 5177 switch(reason) { 5178 case MPI_EVENT_RAID_RC_VOLUME_CREATED: 5179 printk(MYIOC_s_INFO_FMT " volume has been created\n", 5180 ioc->name); 5181 break; 5182 5183 case MPI_EVENT_RAID_RC_VOLUME_DELETED: 5184 5185 printk(MYIOC_s_INFO_FMT " volume has been deleted\n", 5186 ioc->name); 5187 break; 5188 5189 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED: 5190 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n", 5191 ioc->name); 5192 break; 5193 5194 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED: 5195 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n", 5196 ioc->name, 5197 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL 5198 ? "optimal" 5199 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED 5200 ? "degraded" 5201 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED 5202 ? "failed" 5203 : "state unknown", 5204 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED 5205 ? ", enabled" : "", 5206 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED 5207 ? ", quiesced" : "", 5208 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 5209 ? ", resync in progress" : "" ); 5210 break; 5211 5212 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED: 5213 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n", 5214 ioc->name, disk); 5215 break; 5216 5217 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED: 5218 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n", 5219 ioc->name); 5220 break; 5221 5222 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED: 5223 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n", 5224 ioc->name); 5225 break; 5226 5227 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED: 5228 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n", 5229 ioc->name); 5230 break; 5231 5232 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED: 5233 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n", 5234 ioc->name, 5235 state == MPI_PHYSDISK0_STATUS_ONLINE 5236 ? "online" 5237 : state == MPI_PHYSDISK0_STATUS_MISSING 5238 ? "missing" 5239 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE 5240 ? "not compatible" 5241 : state == MPI_PHYSDISK0_STATUS_FAILED 5242 ? "failed" 5243 : state == MPI_PHYSDISK0_STATUS_INITIALIZING 5244 ? "initializing" 5245 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED 5246 ? "offline requested" 5247 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED 5248 ? "failed requested" 5249 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE 5250 ? "offline" 5251 : "state unknown", 5252 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 5253 ? ", out of sync" : "", 5254 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED 5255 ? ", quiesced" : "" ); 5256 break; 5257 5258 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED: 5259 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n", 5260 ioc->name, disk); 5261 break; 5262 5263 case MPI_EVENT_RAID_RC_SMART_DATA: 5264 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n", 5265 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ); 5266 break; 5267 5268 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED: 5269 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n", 5270 ioc->name, disk); 5271 break; 5272 } 5273 } 5274 5275 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5276 /** 5277 * GetIoUnitPage2 - Retrieve BIOS version and boot order information. 5278 * @ioc: Pointer to MPT_ADAPTER structure 5279 * 5280 * Returns: 0 for success 5281 * -ENOMEM if no memory available 5282 * -EPERM if not allowed due to ISR context 5283 * -EAGAIN if no msg frames currently available 5284 * -EFAULT for non-successful reply or no reply (timeout) 5285 */ 5286 static int 5287 GetIoUnitPage2(MPT_ADAPTER *ioc) 5288 { 5289 ConfigPageHeader_t hdr; 5290 CONFIGPARMS cfg; 5291 IOUnitPage2_t *ppage_alloc; 5292 dma_addr_t page_dma; 5293 int data_sz; 5294 int rc; 5295 5296 /* Get the page header */ 5297 hdr.PageVersion = 0; 5298 hdr.PageLength = 0; 5299 hdr.PageNumber = 2; 5300 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT; 5301 cfg.cfghdr.hdr = &hdr; 5302 cfg.physAddr = -1; 5303 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5304 cfg.dir = 0; 5305 cfg.pageAddr = 0; 5306 cfg.timeout = 0; 5307 5308 if ((rc = mpt_config(ioc, &cfg)) != 0) 5309 return rc; 5310 5311 if (hdr.PageLength == 0) 5312 return 0; 5313 5314 /* Read the config page */ 5315 data_sz = hdr.PageLength * 4; 5316 rc = -ENOMEM; 5317 ppage_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma); 5318 if (ppage_alloc) { 5319 memset((u8 *)ppage_alloc, 0, data_sz); 5320 cfg.physAddr = page_dma; 5321 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5322 5323 /* If Good, save data */ 5324 if ((rc = mpt_config(ioc, &cfg)) == 0) 5325 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion); 5326 5327 dma_free_coherent(&ioc->pcidev->dev, data_sz, 5328 (u8 *)ppage_alloc, page_dma); 5329 } 5330 5331 return rc; 5332 } 5333 5334 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5335 /** 5336 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2 5337 * @ioc: Pointer to a Adapter Strucutre 5338 * @portnum: IOC port number 5339 * 5340 * Return: -EFAULT if read of config page header fails 5341 * or if no nvram 5342 * If read of SCSI Port Page 0 fails, 5343 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5344 * Adapter settings: async, narrow 5345 * Return 1 5346 * If read of SCSI Port Page 2 fails, 5347 * Adapter settings valid 5348 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5349 * Return 1 5350 * Else 5351 * Both valid 5352 * Return 0 5353 * CHECK - what type of locking mechanisms should be used???? 5354 */ 5355 static int 5356 mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum) 5357 { 5358 u8 *pbuf; 5359 dma_addr_t buf_dma; 5360 CONFIGPARMS cfg; 5361 ConfigPageHeader_t header; 5362 int ii; 5363 int data, rc = 0; 5364 5365 /* Allocate memory 5366 */ 5367 if (!ioc->spi_data.nvram) { 5368 int sz; 5369 u8 *mem; 5370 sz = MPT_MAX_SCSI_DEVICES * sizeof(int); 5371 mem = kmalloc(sz, GFP_ATOMIC); 5372 if (mem == NULL) 5373 return -EFAULT; 5374 5375 ioc->spi_data.nvram = (int *) mem; 5376 5377 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n", 5378 ioc->name, ioc->spi_data.nvram, sz)); 5379 } 5380 5381 /* Invalidate NVRAM information 5382 */ 5383 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5384 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID; 5385 } 5386 5387 /* Read SPP0 header, allocate memory, then read page. 5388 */ 5389 header.PageVersion = 0; 5390 header.PageLength = 0; 5391 header.PageNumber = 0; 5392 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5393 cfg.cfghdr.hdr = &header; 5394 cfg.physAddr = -1; 5395 cfg.pageAddr = portnum; 5396 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5397 cfg.dir = 0; 5398 cfg.timeout = 0; /* use default */ 5399 if (mpt_config(ioc, &cfg) != 0) 5400 return -EFAULT; 5401 5402 if (header.PageLength > 0) { 5403 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5404 if (pbuf) { 5405 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5406 cfg.physAddr = buf_dma; 5407 if (mpt_config(ioc, &cfg) != 0) { 5408 ioc->spi_data.maxBusWidth = MPT_NARROW; 5409 ioc->spi_data.maxSyncOffset = 0; 5410 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5411 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN; 5412 rc = 1; 5413 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5414 "Unable to read PortPage0 minSyncFactor=%x\n", 5415 ioc->name, ioc->spi_data.minSyncFactor)); 5416 } else { 5417 /* Save the Port Page 0 data 5418 */ 5419 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf; 5420 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities); 5421 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface); 5422 5423 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) { 5424 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS; 5425 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5426 "noQas due to Capabilities=%x\n", 5427 ioc->name, pPP0->Capabilities)); 5428 } 5429 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0; 5430 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK; 5431 if (data) { 5432 ioc->spi_data.maxSyncOffset = (u8) (data >> 16); 5433 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK; 5434 ioc->spi_data.minSyncFactor = (u8) (data >> 8); 5435 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5436 "PortPage0 minSyncFactor=%x\n", 5437 ioc->name, ioc->spi_data.minSyncFactor)); 5438 } else { 5439 ioc->spi_data.maxSyncOffset = 0; 5440 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5441 } 5442 5443 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK; 5444 5445 /* Update the minSyncFactor based on bus type. 5446 */ 5447 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) || 5448 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) { 5449 5450 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) { 5451 ioc->spi_data.minSyncFactor = MPT_ULTRA; 5452 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5453 "HVD or SE detected, minSyncFactor=%x\n", 5454 ioc->name, ioc->spi_data.minSyncFactor)); 5455 } 5456 } 5457 } 5458 if (pbuf) { 5459 dma_free_coherent(&ioc->pcidev->dev, 5460 header.PageLength * 4, pbuf, 5461 buf_dma); 5462 } 5463 } 5464 } 5465 5466 /* SCSI Port Page 2 - Read the header then the page. 5467 */ 5468 header.PageVersion = 0; 5469 header.PageLength = 0; 5470 header.PageNumber = 2; 5471 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5472 cfg.cfghdr.hdr = &header; 5473 cfg.physAddr = -1; 5474 cfg.pageAddr = portnum; 5475 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5476 cfg.dir = 0; 5477 if (mpt_config(ioc, &cfg) != 0) 5478 return -EFAULT; 5479 5480 if (header.PageLength > 0) { 5481 /* Allocate memory and read SCSI Port Page 2 5482 */ 5483 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5484 if (pbuf) { 5485 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM; 5486 cfg.physAddr = buf_dma; 5487 if (mpt_config(ioc, &cfg) != 0) { 5488 /* Nvram data is left with INVALID mark 5489 */ 5490 rc = 1; 5491 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) { 5492 5493 /* This is an ATTO adapter, read Page2 accordingly 5494 */ 5495 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf; 5496 ATTODeviceInfo_t *pdevice = NULL; 5497 u16 ATTOFlags; 5498 5499 /* Save the Port Page 2 data 5500 * (reformat into a 32bit quantity) 5501 */ 5502 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5503 pdevice = &pPP2->DeviceSettings[ii]; 5504 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags); 5505 data = 0; 5506 5507 /* Translate ATTO device flags to LSI format 5508 */ 5509 if (ATTOFlags & ATTOFLAG_DISC) 5510 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE); 5511 if (ATTOFlags & ATTOFLAG_ID_ENB) 5512 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE); 5513 if (ATTOFlags & ATTOFLAG_LUN_ENB) 5514 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE); 5515 if (ATTOFlags & ATTOFLAG_TAGGED) 5516 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE); 5517 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB)) 5518 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE); 5519 5520 data = (data << 16) | (pdevice->Period << 8) | 10; 5521 ioc->spi_data.nvram[ii] = data; 5522 } 5523 } else { 5524 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf; 5525 MpiDeviceInfo_t *pdevice = NULL; 5526 5527 /* 5528 * Save "Set to Avoid SCSI Bus Resets" flag 5529 */ 5530 ioc->spi_data.bus_reset = 5531 (le32_to_cpu(pPP2->PortFlags) & 5532 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ? 5533 0 : 1 ; 5534 5535 /* Save the Port Page 2 data 5536 * (reformat into a 32bit quantity) 5537 */ 5538 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK; 5539 ioc->spi_data.PortFlags = data; 5540 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5541 pdevice = &pPP2->DeviceSettings[ii]; 5542 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) | 5543 (pdevice->SyncFactor << 8) | pdevice->Timeout; 5544 ioc->spi_data.nvram[ii] = data; 5545 } 5546 } 5547 5548 dma_free_coherent(&ioc->pcidev->dev, 5549 header.PageLength * 4, pbuf, 5550 buf_dma); 5551 } 5552 } 5553 5554 /* Update Adapter limits with those from NVRAM 5555 * Comment: Don't need to do this. Target performance 5556 * parameters will never exceed the adapters limits. 5557 */ 5558 5559 return rc; 5560 } 5561 5562 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5563 /** 5564 * mpt_readScsiDevicePageHeaders - save version and length of SDP1 5565 * @ioc: Pointer to a Adapter Strucutre 5566 * @portnum: IOC port number 5567 * 5568 * Return: -EFAULT if read of config page header fails 5569 * or 0 if success. 5570 */ 5571 static int 5572 mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum) 5573 { 5574 CONFIGPARMS cfg; 5575 ConfigPageHeader_t header; 5576 5577 /* Read the SCSI Device Page 1 header 5578 */ 5579 header.PageVersion = 0; 5580 header.PageLength = 0; 5581 header.PageNumber = 1; 5582 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5583 cfg.cfghdr.hdr = &header; 5584 cfg.physAddr = -1; 5585 cfg.pageAddr = portnum; 5586 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5587 cfg.dir = 0; 5588 cfg.timeout = 0; 5589 if (mpt_config(ioc, &cfg) != 0) 5590 return -EFAULT; 5591 5592 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion; 5593 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength; 5594 5595 header.PageVersion = 0; 5596 header.PageLength = 0; 5597 header.PageNumber = 0; 5598 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5599 if (mpt_config(ioc, &cfg) != 0) 5600 return -EFAULT; 5601 5602 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion; 5603 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength; 5604 5605 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n", 5606 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length)); 5607 5608 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n", 5609 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length)); 5610 return 0; 5611 } 5612 5613 /** 5614 * mpt_inactive_raid_list_free - This clears this link list. 5615 * @ioc : pointer to per adapter structure 5616 **/ 5617 static void 5618 mpt_inactive_raid_list_free(MPT_ADAPTER *ioc) 5619 { 5620 struct inactive_raid_component_info *component_info, *pNext; 5621 5622 if (list_empty(&ioc->raid_data.inactive_list)) 5623 return; 5624 5625 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5626 list_for_each_entry_safe(component_info, pNext, 5627 &ioc->raid_data.inactive_list, list) { 5628 list_del(&component_info->list); 5629 kfree(component_info); 5630 } 5631 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5632 } 5633 5634 /** 5635 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume 5636 * 5637 * @ioc : pointer to per adapter structure 5638 * @channel : volume channel 5639 * @id : volume target id 5640 **/ 5641 static void 5642 mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id) 5643 { 5644 CONFIGPARMS cfg; 5645 ConfigPageHeader_t hdr; 5646 dma_addr_t dma_handle; 5647 pRaidVolumePage0_t buffer = NULL; 5648 int i; 5649 RaidPhysDiskPage0_t phys_disk; 5650 struct inactive_raid_component_info *component_info; 5651 int handle_inactive_volumes; 5652 5653 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5654 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5655 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME; 5656 cfg.pageAddr = (channel << 8) + id; 5657 cfg.cfghdr.hdr = &hdr; 5658 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5659 5660 if (mpt_config(ioc, &cfg) != 0) 5661 goto out; 5662 5663 if (!hdr.PageLength) 5664 goto out; 5665 5666 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5667 &dma_handle); 5668 5669 if (!buffer) 5670 goto out; 5671 5672 cfg.physAddr = dma_handle; 5673 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5674 5675 if (mpt_config(ioc, &cfg) != 0) 5676 goto out; 5677 5678 if (!buffer->NumPhysDisks) 5679 goto out; 5680 5681 handle_inactive_volumes = 5682 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE || 5683 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 || 5684 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED || 5685 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0; 5686 5687 if (!handle_inactive_volumes) 5688 goto out; 5689 5690 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5691 for (i = 0; i < buffer->NumPhysDisks; i++) { 5692 if(mpt_raid_phys_disk_pg0(ioc, 5693 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) 5694 continue; 5695 5696 if ((component_info = kmalloc(sizeof (*component_info), 5697 GFP_KERNEL)) == NULL) 5698 continue; 5699 5700 component_info->volumeID = id; 5701 component_info->volumeBus = channel; 5702 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum; 5703 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus; 5704 component_info->d.PhysDiskID = phys_disk.PhysDiskID; 5705 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC; 5706 5707 list_add_tail(&component_info->list, 5708 &ioc->raid_data.inactive_list); 5709 } 5710 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5711 5712 out: 5713 if (buffer) 5714 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5715 buffer, dma_handle); 5716 } 5717 5718 /** 5719 * mpt_raid_phys_disk_pg0 - returns phys disk page zero 5720 * @ioc: Pointer to a Adapter Structure 5721 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5722 * @phys_disk: requested payload data returned 5723 * 5724 * Return: 5725 * 0 on success 5726 * -EFAULT if read of config page header fails or data pointer not NULL 5727 * -ENOMEM if pci_alloc failed 5728 **/ 5729 int 5730 mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, 5731 RaidPhysDiskPage0_t *phys_disk) 5732 { 5733 CONFIGPARMS cfg; 5734 ConfigPageHeader_t hdr; 5735 dma_addr_t dma_handle; 5736 pRaidPhysDiskPage0_t buffer = NULL; 5737 int rc; 5738 5739 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5740 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5741 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t)); 5742 5743 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION; 5744 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5745 cfg.cfghdr.hdr = &hdr; 5746 cfg.physAddr = -1; 5747 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5748 5749 if (mpt_config(ioc, &cfg) != 0) { 5750 rc = -EFAULT; 5751 goto out; 5752 } 5753 5754 if (!hdr.PageLength) { 5755 rc = -EFAULT; 5756 goto out; 5757 } 5758 5759 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5760 &dma_handle); 5761 5762 if (!buffer) { 5763 rc = -ENOMEM; 5764 goto out; 5765 } 5766 5767 cfg.physAddr = dma_handle; 5768 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5769 cfg.pageAddr = phys_disk_num; 5770 5771 if (mpt_config(ioc, &cfg) != 0) { 5772 rc = -EFAULT; 5773 goto out; 5774 } 5775 5776 rc = 0; 5777 memcpy(phys_disk, buffer, sizeof(*buffer)); 5778 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA); 5779 5780 out: 5781 5782 if (buffer) 5783 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5784 buffer, dma_handle); 5785 5786 return rc; 5787 } 5788 5789 /** 5790 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num 5791 * @ioc: Pointer to a Adapter Structure 5792 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5793 * 5794 * Return: 5795 * returns number paths 5796 **/ 5797 int 5798 mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num) 5799 { 5800 CONFIGPARMS cfg; 5801 ConfigPageHeader_t hdr; 5802 dma_addr_t dma_handle; 5803 pRaidPhysDiskPage1_t buffer = NULL; 5804 int rc; 5805 5806 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5807 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5808 5809 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5810 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5811 hdr.PageNumber = 1; 5812 cfg.cfghdr.hdr = &hdr; 5813 cfg.physAddr = -1; 5814 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5815 5816 if (mpt_config(ioc, &cfg) != 0) { 5817 rc = 0; 5818 goto out; 5819 } 5820 5821 if (!hdr.PageLength) { 5822 rc = 0; 5823 goto out; 5824 } 5825 5826 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5827 &dma_handle); 5828 5829 if (!buffer) { 5830 rc = 0; 5831 goto out; 5832 } 5833 5834 cfg.physAddr = dma_handle; 5835 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5836 cfg.pageAddr = phys_disk_num; 5837 5838 if (mpt_config(ioc, &cfg) != 0) { 5839 rc = 0; 5840 goto out; 5841 } 5842 5843 rc = buffer->NumPhysDiskPaths; 5844 out: 5845 5846 if (buffer) 5847 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5848 buffer, dma_handle); 5849 5850 return rc; 5851 } 5852 EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths); 5853 5854 /** 5855 * mpt_raid_phys_disk_pg1 - returns phys disk page 1 5856 * @ioc: Pointer to a Adapter Structure 5857 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5858 * @phys_disk: requested payload data returned 5859 * 5860 * Return: 5861 * 0 on success 5862 * -EFAULT if read of config page header fails or data pointer not NULL 5863 * -ENOMEM if pci_alloc failed 5864 **/ 5865 int 5866 mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, 5867 RaidPhysDiskPage1_t *phys_disk) 5868 { 5869 CONFIGPARMS cfg; 5870 ConfigPageHeader_t hdr; 5871 dma_addr_t dma_handle; 5872 pRaidPhysDiskPage1_t buffer = NULL; 5873 int rc; 5874 int i; 5875 __le64 sas_address; 5876 5877 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5878 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5879 rc = 0; 5880 5881 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5882 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5883 hdr.PageNumber = 1; 5884 cfg.cfghdr.hdr = &hdr; 5885 cfg.physAddr = -1; 5886 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5887 5888 if (mpt_config(ioc, &cfg) != 0) { 5889 rc = -EFAULT; 5890 goto out; 5891 } 5892 5893 if (!hdr.PageLength) { 5894 rc = -EFAULT; 5895 goto out; 5896 } 5897 5898 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5899 &dma_handle); 5900 5901 if (!buffer) { 5902 rc = -ENOMEM; 5903 goto out; 5904 } 5905 5906 cfg.physAddr = dma_handle; 5907 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5908 cfg.pageAddr = phys_disk_num; 5909 5910 if (mpt_config(ioc, &cfg) != 0) { 5911 rc = -EFAULT; 5912 goto out; 5913 } 5914 5915 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths; 5916 phys_disk->PhysDiskNum = phys_disk_num; 5917 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) { 5918 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID; 5919 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus; 5920 phys_disk->Path[i].OwnerIdentifier = 5921 buffer->Path[i].OwnerIdentifier; 5922 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags); 5923 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64)); 5924 sas_address = le64_to_cpu(sas_address); 5925 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64)); 5926 memcpy(&sas_address, 5927 &buffer->Path[i].OwnerWWID, sizeof(__le64)); 5928 sas_address = le64_to_cpu(sas_address); 5929 memcpy(&phys_disk->Path[i].OwnerWWID, 5930 &sas_address, sizeof(__le64)); 5931 } 5932 5933 out: 5934 5935 if (buffer) 5936 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5937 buffer, dma_handle); 5938 5939 return rc; 5940 } 5941 EXPORT_SYMBOL(mpt_raid_phys_disk_pg1); 5942 5943 5944 /** 5945 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes 5946 * @ioc: Pointer to a Adapter Strucutre 5947 * 5948 * Return: 5949 * 0 on success 5950 * -EFAULT if read of config page header fails or data pointer not NULL 5951 * -ENOMEM if pci_alloc failed 5952 **/ 5953 int 5954 mpt_findImVolumes(MPT_ADAPTER *ioc) 5955 { 5956 IOCPage2_t *pIoc2; 5957 u8 *mem; 5958 dma_addr_t ioc2_dma; 5959 CONFIGPARMS cfg; 5960 ConfigPageHeader_t header; 5961 int rc = 0; 5962 int iocpage2sz; 5963 int i; 5964 5965 if (!ioc->ir_firmware) 5966 return 0; 5967 5968 /* Free the old page 5969 */ 5970 kfree(ioc->raid_data.pIocPg2); 5971 ioc->raid_data.pIocPg2 = NULL; 5972 mpt_inactive_raid_list_free(ioc); 5973 5974 /* Read IOCP2 header then the page. 5975 */ 5976 header.PageVersion = 0; 5977 header.PageLength = 0; 5978 header.PageNumber = 2; 5979 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 5980 cfg.cfghdr.hdr = &header; 5981 cfg.physAddr = -1; 5982 cfg.pageAddr = 0; 5983 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5984 cfg.dir = 0; 5985 cfg.timeout = 0; 5986 if (mpt_config(ioc, &cfg) != 0) 5987 return -EFAULT; 5988 5989 if (header.PageLength == 0) 5990 return -EFAULT; 5991 5992 iocpage2sz = header.PageLength * 4; 5993 pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma); 5994 if (!pIoc2) 5995 return -ENOMEM; 5996 5997 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5998 cfg.physAddr = ioc2_dma; 5999 if (mpt_config(ioc, &cfg) != 0) 6000 goto out; 6001 6002 mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL); 6003 if (!mem) { 6004 rc = -ENOMEM; 6005 goto out; 6006 } 6007 6008 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem; 6009 6010 mpt_read_ioc_pg_3(ioc); 6011 6012 for (i = 0; i < pIoc2->NumActiveVolumes ; i++) 6013 mpt_inactive_raid_volumes(ioc, 6014 pIoc2->RaidVolume[i].VolumeBus, 6015 pIoc2->RaidVolume[i].VolumeID); 6016 6017 out: 6018 dma_free_coherent(&ioc->pcidev->dev, iocpage2sz, pIoc2, ioc2_dma); 6019 6020 return rc; 6021 } 6022 6023 static int 6024 mpt_read_ioc_pg_3(MPT_ADAPTER *ioc) 6025 { 6026 IOCPage3_t *pIoc3; 6027 u8 *mem; 6028 CONFIGPARMS cfg; 6029 ConfigPageHeader_t header; 6030 dma_addr_t ioc3_dma; 6031 int iocpage3sz = 0; 6032 6033 /* Free the old page 6034 */ 6035 kfree(ioc->raid_data.pIocPg3); 6036 ioc->raid_data.pIocPg3 = NULL; 6037 6038 /* There is at least one physical disk. 6039 * Read and save IOC Page 3 6040 */ 6041 header.PageVersion = 0; 6042 header.PageLength = 0; 6043 header.PageNumber = 3; 6044 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6045 cfg.cfghdr.hdr = &header; 6046 cfg.physAddr = -1; 6047 cfg.pageAddr = 0; 6048 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6049 cfg.dir = 0; 6050 cfg.timeout = 0; 6051 if (mpt_config(ioc, &cfg) != 0) 6052 return 0; 6053 6054 if (header.PageLength == 0) 6055 return 0; 6056 6057 /* Read Header good, alloc memory 6058 */ 6059 iocpage3sz = header.PageLength * 4; 6060 pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma); 6061 if (!pIoc3) 6062 return 0; 6063 6064 /* Read the Page and save the data 6065 * into malloc'd memory. 6066 */ 6067 cfg.physAddr = ioc3_dma; 6068 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6069 if (mpt_config(ioc, &cfg) == 0) { 6070 mem = kmalloc(iocpage3sz, GFP_KERNEL); 6071 if (mem) { 6072 memcpy(mem, (u8 *)pIoc3, iocpage3sz); 6073 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem; 6074 } 6075 } 6076 6077 dma_free_coherent(&ioc->pcidev->dev, iocpage3sz, pIoc3, ioc3_dma); 6078 6079 return 0; 6080 } 6081 6082 static void 6083 mpt_read_ioc_pg_4(MPT_ADAPTER *ioc) 6084 { 6085 IOCPage4_t *pIoc4; 6086 CONFIGPARMS cfg; 6087 ConfigPageHeader_t header; 6088 dma_addr_t ioc4_dma; 6089 int iocpage4sz; 6090 6091 /* Read and save IOC Page 4 6092 */ 6093 header.PageVersion = 0; 6094 header.PageLength = 0; 6095 header.PageNumber = 4; 6096 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6097 cfg.cfghdr.hdr = &header; 6098 cfg.physAddr = -1; 6099 cfg.pageAddr = 0; 6100 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6101 cfg.dir = 0; 6102 cfg.timeout = 0; 6103 if (mpt_config(ioc, &cfg) != 0) 6104 return; 6105 6106 if (header.PageLength == 0) 6107 return; 6108 6109 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) { 6110 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */ 6111 pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma); 6112 if (!pIoc4) 6113 return; 6114 ioc->alloc_total += iocpage4sz; 6115 } else { 6116 ioc4_dma = ioc->spi_data.IocPg4_dma; 6117 iocpage4sz = ioc->spi_data.IocPg4Sz; 6118 } 6119 6120 /* Read the Page into dma memory. 6121 */ 6122 cfg.physAddr = ioc4_dma; 6123 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6124 if (mpt_config(ioc, &cfg) == 0) { 6125 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4; 6126 ioc->spi_data.IocPg4_dma = ioc4_dma; 6127 ioc->spi_data.IocPg4Sz = iocpage4sz; 6128 } else { 6129 dma_free_coherent(&ioc->pcidev->dev, iocpage4sz, pIoc4, 6130 ioc4_dma); 6131 ioc->spi_data.pIocPg4 = NULL; 6132 ioc->alloc_total -= iocpage4sz; 6133 } 6134 } 6135 6136 static void 6137 mpt_read_ioc_pg_1(MPT_ADAPTER *ioc) 6138 { 6139 IOCPage1_t *pIoc1; 6140 CONFIGPARMS cfg; 6141 ConfigPageHeader_t header; 6142 dma_addr_t ioc1_dma; 6143 int iocpage1sz = 0; 6144 u32 tmp; 6145 6146 /* Check the Coalescing Timeout in IOC Page 1 6147 */ 6148 header.PageVersion = 0; 6149 header.PageLength = 0; 6150 header.PageNumber = 1; 6151 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6152 cfg.cfghdr.hdr = &header; 6153 cfg.physAddr = -1; 6154 cfg.pageAddr = 0; 6155 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6156 cfg.dir = 0; 6157 cfg.timeout = 0; 6158 if (mpt_config(ioc, &cfg) != 0) 6159 return; 6160 6161 if (header.PageLength == 0) 6162 return; 6163 6164 /* Read Header good, alloc memory 6165 */ 6166 iocpage1sz = header.PageLength * 4; 6167 pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma); 6168 if (!pIoc1) 6169 return; 6170 6171 /* Read the Page and check coalescing timeout 6172 */ 6173 cfg.physAddr = ioc1_dma; 6174 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6175 if (mpt_config(ioc, &cfg) == 0) { 6176 6177 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING; 6178 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) { 6179 tmp = le32_to_cpu(pIoc1->CoalescingTimeout); 6180 6181 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n", 6182 ioc->name, tmp)); 6183 6184 if (tmp > MPT_COALESCING_TIMEOUT) { 6185 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT); 6186 6187 /* Write NVRAM and current 6188 */ 6189 cfg.dir = 1; 6190 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT; 6191 if (mpt_config(ioc, &cfg) == 0) { 6192 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n", 6193 ioc->name, MPT_COALESCING_TIMEOUT)); 6194 6195 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM; 6196 if (mpt_config(ioc, &cfg) == 0) { 6197 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6198 "Reset NVRAM Coalescing Timeout to = %d\n", 6199 ioc->name, MPT_COALESCING_TIMEOUT)); 6200 } else { 6201 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6202 "Reset NVRAM Coalescing Timeout Failed\n", 6203 ioc->name)); 6204 } 6205 6206 } else { 6207 dprintk(ioc, printk(MYIOC_s_WARN_FMT 6208 "Reset of Current Coalescing Timeout Failed!\n", 6209 ioc->name)); 6210 } 6211 } 6212 6213 } else { 6214 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name)); 6215 } 6216 } 6217 6218 dma_free_coherent(&ioc->pcidev->dev, iocpage1sz, pIoc1, ioc1_dma); 6219 6220 return; 6221 } 6222 6223 static void 6224 mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc) 6225 { 6226 CONFIGPARMS cfg; 6227 ConfigPageHeader_t hdr; 6228 dma_addr_t buf_dma; 6229 ManufacturingPage0_t *pbuf = NULL; 6230 6231 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 6232 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 6233 6234 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING; 6235 cfg.cfghdr.hdr = &hdr; 6236 cfg.physAddr = -1; 6237 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6238 cfg.timeout = 10; 6239 6240 if (mpt_config(ioc, &cfg) != 0) 6241 goto out; 6242 6243 if (!cfg.cfghdr.hdr->PageLength) 6244 goto out; 6245 6246 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6247 pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma); 6248 if (!pbuf) 6249 goto out; 6250 6251 cfg.physAddr = buf_dma; 6252 6253 if (mpt_config(ioc, &cfg) != 0) 6254 goto out; 6255 6256 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name)); 6257 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly)); 6258 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer)); 6259 6260 out: 6261 6262 if (pbuf) 6263 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, pbuf, 6264 buf_dma); 6265 } 6266 6267 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6268 /** 6269 * SendEventNotification - Send EventNotification (on or off) request to adapter 6270 * @ioc: Pointer to MPT_ADAPTER structure 6271 * @EvSwitch: Event switch flags 6272 * @sleepFlag: Specifies whether the process can sleep 6273 */ 6274 static int 6275 SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag) 6276 { 6277 EventNotification_t evn; 6278 MPIDefaultReply_t reply_buf; 6279 6280 memset(&evn, 0, sizeof(EventNotification_t)); 6281 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t)); 6282 6283 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION; 6284 evn.Switch = EvSwitch; 6285 evn.MsgContext = cpu_to_le32(mpt_base_index << 16); 6286 6287 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6288 "Sending EventNotification (%d) request %p\n", 6289 ioc->name, EvSwitch, &evn)); 6290 6291 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t), 6292 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30, 6293 sleepFlag); 6294 } 6295 6296 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6297 /** 6298 * SendEventAck - Send EventAck request to MPT adapter. 6299 * @ioc: Pointer to MPT_ADAPTER structure 6300 * @evnp: Pointer to original EventNotification request 6301 */ 6302 static int 6303 SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp) 6304 { 6305 EventAck_t *pAck; 6306 6307 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6308 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n", 6309 ioc->name, __func__)); 6310 return -1; 6311 } 6312 6313 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name)); 6314 6315 pAck->Function = MPI_FUNCTION_EVENT_ACK; 6316 pAck->ChainOffset = 0; 6317 pAck->Reserved[0] = pAck->Reserved[1] = 0; 6318 pAck->MsgFlags = 0; 6319 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0; 6320 pAck->Event = evnp->Event; 6321 pAck->EventContext = evnp->EventContext; 6322 6323 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck); 6324 6325 return 0; 6326 } 6327 6328 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6329 /** 6330 * mpt_config - Generic function to issue config message 6331 * @ioc: Pointer to an adapter structure 6332 * @pCfg: Pointer to a configuration structure. Struct contains 6333 * action, page address, direction, physical address 6334 * and pointer to a configuration page header 6335 * Page header is updated. 6336 * 6337 * Returns 0 for success 6338 * -EAGAIN if no msg frames currently available 6339 * -EFAULT for non-successful reply or no reply (timeout) 6340 */ 6341 int 6342 mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg) 6343 { 6344 Config_t *pReq; 6345 ConfigReply_t *pReply; 6346 ConfigExtendedPageHeader_t *pExtHdr = NULL; 6347 MPT_FRAME_HDR *mf; 6348 int ii; 6349 int flagsLength; 6350 long timeout; 6351 int ret; 6352 u8 page_type = 0, extend_page; 6353 unsigned long timeleft; 6354 unsigned long flags; 6355 u8 issue_hard_reset = 0; 6356 u8 retry_count = 0; 6357 6358 might_sleep(); 6359 6360 /* don't send a config page during diag reset */ 6361 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6362 if (ioc->ioc_reset_in_progress) { 6363 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6364 "%s: busy with host reset\n", ioc->name, __func__)); 6365 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6366 return -EBUSY; 6367 } 6368 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6369 6370 /* don't send if no chance of success */ 6371 if (!ioc->active || 6372 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) { 6373 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6374 "%s: ioc not operational, %d, %xh\n", 6375 ioc->name, __func__, ioc->active, 6376 mpt_GetIocState(ioc, 0))); 6377 return -EFAULT; 6378 } 6379 6380 retry_config: 6381 mutex_lock(&ioc->mptbase_cmds.mutex); 6382 /* init the internal cmd struct */ 6383 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 6384 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 6385 6386 /* Get and Populate a free Frame 6387 */ 6388 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6389 dcprintk(ioc, printk(MYIOC_s_WARN_FMT 6390 "mpt_config: no msg frames!\n", ioc->name)); 6391 ret = -EAGAIN; 6392 goto out; 6393 } 6394 6395 pReq = (Config_t *)mf; 6396 pReq->Action = pCfg->action; 6397 pReq->Reserved = 0; 6398 pReq->ChainOffset = 0; 6399 pReq->Function = MPI_FUNCTION_CONFIG; 6400 6401 /* Assume page type is not extended and clear "reserved" fields. */ 6402 pReq->ExtPageLength = 0; 6403 pReq->ExtPageType = 0; 6404 pReq->MsgFlags = 0; 6405 6406 for (ii=0; ii < 8; ii++) 6407 pReq->Reserved2[ii] = 0; 6408 6409 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion; 6410 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength; 6411 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber; 6412 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); 6413 6414 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) { 6415 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr; 6416 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength); 6417 pReq->ExtPageType = pExtHdr->ExtPageType; 6418 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 6419 6420 /* Page Length must be treated as a reserved field for the 6421 * extended header. 6422 */ 6423 pReq->Header.PageLength = 0; 6424 } 6425 6426 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr); 6427 6428 /* Add a SGE to the config request. 6429 */ 6430 if (pCfg->dir) 6431 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE; 6432 else 6433 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ; 6434 6435 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == 6436 MPI_CONFIG_PAGETYPE_EXTENDED) { 6437 flagsLength |= pExtHdr->ExtPageLength * 4; 6438 page_type = pReq->ExtPageType; 6439 extend_page = 1; 6440 } else { 6441 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4; 6442 page_type = pReq->Header.PageType; 6443 extend_page = 0; 6444 } 6445 6446 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6447 "Sending Config request type 0x%x, page 0x%x and action %d\n", 6448 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action)); 6449 6450 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr); 6451 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout; 6452 mpt_put_msg_frame(mpt_base_index, ioc, mf); 6453 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 6454 timeout); 6455 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 6456 ret = -ETIME; 6457 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6458 "Failed Sending Config request type 0x%x, page 0x%x," 6459 " action %d, status %xh, time left %ld\n\n", 6460 ioc->name, page_type, pReq->Header.PageNumber, 6461 pReq->Action, ioc->mptbase_cmds.status, timeleft)); 6462 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 6463 goto out; 6464 if (!timeleft) { 6465 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6466 if (ioc->ioc_reset_in_progress) { 6467 spin_unlock_irqrestore(&ioc->taskmgmt_lock, 6468 flags); 6469 printk(MYIOC_s_INFO_FMT "%s: host reset in" 6470 " progress mpt_config timed out.!!\n", 6471 __func__, ioc->name); 6472 mutex_unlock(&ioc->mptbase_cmds.mutex); 6473 return -EFAULT; 6474 } 6475 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6476 issue_hard_reset = 1; 6477 } 6478 goto out; 6479 } 6480 6481 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 6482 ret = -1; 6483 goto out; 6484 } 6485 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply; 6486 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK; 6487 if (ret == MPI_IOCSTATUS_SUCCESS) { 6488 if (extend_page) { 6489 pCfg->cfghdr.ehdr->ExtPageLength = 6490 le16_to_cpu(pReply->ExtPageLength); 6491 pCfg->cfghdr.ehdr->ExtPageType = 6492 pReply->ExtPageType; 6493 } 6494 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion; 6495 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength; 6496 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber; 6497 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType; 6498 6499 } 6500 6501 if (retry_count) 6502 printk(MYIOC_s_INFO_FMT "Retry completed " 6503 "ret=0x%x timeleft=%ld\n", 6504 ioc->name, ret, timeleft); 6505 6506 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n", 6507 ret, le32_to_cpu(pReply->IOCLogInfo))); 6508 6509 out: 6510 6511 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 6512 mutex_unlock(&ioc->mptbase_cmds.mutex); 6513 if (issue_hard_reset) { 6514 issue_hard_reset = 0; 6515 printk(MYIOC_s_WARN_FMT 6516 "Issuing Reset from %s!!, doorbell=0x%08x\n", 6517 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 6518 if (retry_count == 0) { 6519 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0) 6520 retry_count++; 6521 } else 6522 mpt_HardResetHandler(ioc, CAN_SLEEP); 6523 6524 mpt_free_msg_frame(ioc, mf); 6525 /* attempt one retry for a timed out command */ 6526 if (retry_count < 2) { 6527 printk(MYIOC_s_INFO_FMT 6528 "Attempting Retry Config request" 6529 " type 0x%x, page 0x%x," 6530 " action %d\n", ioc->name, page_type, 6531 pCfg->cfghdr.hdr->PageNumber, pCfg->action); 6532 retry_count++; 6533 goto retry_config; 6534 } 6535 } 6536 return ret; 6537 6538 } 6539 6540 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6541 /** 6542 * mpt_ioc_reset - Base cleanup for hard reset 6543 * @ioc: Pointer to the adapter structure 6544 * @reset_phase: Indicates pre- or post-reset functionality 6545 * 6546 * Remark: Frees resources with internally generated commands. 6547 */ 6548 static int 6549 mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase) 6550 { 6551 switch (reset_phase) { 6552 case MPT_IOC_SETUP_RESET: 6553 ioc->taskmgmt_quiesce_io = 1; 6554 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6555 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); 6556 break; 6557 case MPT_IOC_PRE_RESET: 6558 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6559 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__)); 6560 break; 6561 case MPT_IOC_POST_RESET: 6562 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6563 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); 6564 /* wake up mptbase_cmds */ 6565 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 6566 ioc->mptbase_cmds.status |= 6567 MPT_MGMT_STATUS_DID_IOCRESET; 6568 complete(&ioc->mptbase_cmds.done); 6569 } 6570 /* wake up taskmgmt_cmds */ 6571 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) { 6572 ioc->taskmgmt_cmds.status |= 6573 MPT_MGMT_STATUS_DID_IOCRESET; 6574 complete(&ioc->taskmgmt_cmds.done); 6575 } 6576 break; 6577 default: 6578 break; 6579 } 6580 6581 return 1; /* currently means nothing really */ 6582 } 6583 6584 6585 #ifdef CONFIG_PROC_FS /* { */ 6586 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6587 /* 6588 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff... 6589 */ 6590 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6591 /** 6592 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries. 6593 * 6594 * Returns 0 for success, non-zero for failure. 6595 */ 6596 static int 6597 procmpt_create(void) 6598 { 6599 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL); 6600 if (mpt_proc_root_dir == NULL) 6601 return -ENOTDIR; 6602 6603 proc_create_single("summary", S_IRUGO, mpt_proc_root_dir, 6604 mpt_summary_proc_show); 6605 proc_create_single("version", S_IRUGO, mpt_proc_root_dir, 6606 mpt_version_proc_show); 6607 return 0; 6608 } 6609 6610 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6611 /** 6612 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries. 6613 * 6614 * Returns 0 for success, non-zero for failure. 6615 */ 6616 static void 6617 procmpt_destroy(void) 6618 { 6619 remove_proc_entry("version", mpt_proc_root_dir); 6620 remove_proc_entry("summary", mpt_proc_root_dir); 6621 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL); 6622 } 6623 6624 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6625 /* 6626 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary. 6627 */ 6628 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan); 6629 6630 static int mpt_summary_proc_show(struct seq_file *m, void *v) 6631 { 6632 MPT_ADAPTER *ioc = m->private; 6633 6634 if (ioc) { 6635 seq_mpt_print_ioc_summary(ioc, m, 1); 6636 } else { 6637 list_for_each_entry(ioc, &ioc_list, list) { 6638 seq_mpt_print_ioc_summary(ioc, m, 1); 6639 } 6640 } 6641 6642 return 0; 6643 } 6644 6645 static int mpt_version_proc_show(struct seq_file *m, void *v) 6646 { 6647 u8 cb_idx; 6648 int scsi, fc, sas, lan, ctl, targ, dmp; 6649 char *drvname; 6650 6651 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON); 6652 seq_printf(m, " Fusion MPT base driver\n"); 6653 6654 scsi = fc = sas = lan = ctl = targ = dmp = 0; 6655 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6656 drvname = NULL; 6657 if (MptCallbacks[cb_idx]) { 6658 switch (MptDriverClass[cb_idx]) { 6659 case MPTSPI_DRIVER: 6660 if (!scsi++) drvname = "SPI host"; 6661 break; 6662 case MPTFC_DRIVER: 6663 if (!fc++) drvname = "FC host"; 6664 break; 6665 case MPTSAS_DRIVER: 6666 if (!sas++) drvname = "SAS host"; 6667 break; 6668 case MPTLAN_DRIVER: 6669 if (!lan++) drvname = "LAN"; 6670 break; 6671 case MPTSTM_DRIVER: 6672 if (!targ++) drvname = "SCSI target"; 6673 break; 6674 case MPTCTL_DRIVER: 6675 if (!ctl++) drvname = "ioctl"; 6676 break; 6677 } 6678 6679 if (drvname) 6680 seq_printf(m, " Fusion MPT %s driver\n", drvname); 6681 } 6682 } 6683 6684 return 0; 6685 } 6686 6687 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v) 6688 { 6689 MPT_ADAPTER *ioc = m->private; 6690 char expVer[32]; 6691 int sz; 6692 int p; 6693 6694 mpt_get_fw_exp_ver(expVer, ioc); 6695 6696 seq_printf(m, "%s:", ioc->name); 6697 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 6698 seq_printf(m, " (f/w download boot flag set)"); 6699 // if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL) 6700 // seq_printf(m, " CONFIG_CHECKSUM_FAIL!"); 6701 6702 seq_printf(m, "\n ProductID = 0x%04x (%s)\n", 6703 ioc->facts.ProductID, 6704 ioc->prod_name); 6705 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer); 6706 if (ioc->facts.FWImageSize) 6707 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize); 6708 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion); 6709 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit); 6710 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState); 6711 6712 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n", 6713 ioc->facts.CurrentHostMfaHighAddr); 6714 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n", 6715 ioc->facts.CurrentSenseBufferHighAddr); 6716 6717 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth); 6718 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize); 6719 6720 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n", 6721 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma); 6722 /* 6723 * Rounding UP to nearest 4-kB boundary here... 6724 */ 6725 sz = (ioc->req_sz * ioc->req_depth) + 128; 6726 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000; 6727 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n", 6728 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz); 6729 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n", 6730 4*ioc->facts.RequestFrameSize, 6731 ioc->facts.GlobalCredits); 6732 6733 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n", 6734 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma); 6735 sz = (ioc->reply_sz * ioc->reply_depth) + 128; 6736 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n", 6737 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz); 6738 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n", 6739 ioc->facts.CurReplyFrameSize, 6740 ioc->facts.ReplyQueueDepth); 6741 6742 seq_printf(m, " MaxDevices = %d\n", 6743 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices); 6744 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses); 6745 6746 /* per-port info */ 6747 for (p=0; p < ioc->facts.NumberOfPorts; p++) { 6748 seq_printf(m, " PortNumber = %d (of %d)\n", 6749 p+1, 6750 ioc->facts.NumberOfPorts); 6751 if (ioc->bus_type == FC) { 6752 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 6753 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6754 seq_printf(m, " LanAddr = %pMR\n", a); 6755 } 6756 seq_printf(m, " WWN = %08X%08X:%08X%08X\n", 6757 ioc->fc_port_page0[p].WWNN.High, 6758 ioc->fc_port_page0[p].WWNN.Low, 6759 ioc->fc_port_page0[p].WWPN.High, 6760 ioc->fc_port_page0[p].WWPN.Low); 6761 } 6762 } 6763 6764 return 0; 6765 } 6766 #endif /* CONFIG_PROC_FS } */ 6767 6768 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6769 static void 6770 mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc) 6771 { 6772 buf[0] ='\0'; 6773 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) { 6774 sprintf(buf, " (Exp %02d%02d)", 6775 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */ 6776 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */ 6777 6778 /* insider hack! */ 6779 if ((ioc->facts.FWVersion.Word >> 8) & 0x80) 6780 strcat(buf, " [MDBG]"); 6781 } 6782 } 6783 6784 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6785 /** 6786 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer. 6787 * @ioc: Pointer to MPT_ADAPTER structure 6788 * @buffer: Pointer to buffer where IOC summary info should be written 6789 * @size: Pointer to number of bytes we wrote (set by this routine) 6790 * @len: Offset at which to start writing in buffer 6791 * @showlan: Display LAN stuff? 6792 * 6793 * This routine writes (english readable) ASCII text, which represents 6794 * a summary of IOC information, to a buffer. 6795 */ 6796 void 6797 mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan) 6798 { 6799 char expVer[32]; 6800 int y; 6801 6802 mpt_get_fw_exp_ver(expVer, ioc); 6803 6804 /* 6805 * Shorter summary of attached ioc's... 6806 */ 6807 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6808 ioc->name, 6809 ioc->prod_name, 6810 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6811 ioc->facts.FWVersion.Word, 6812 expVer, 6813 ioc->facts.NumberOfPorts, 6814 ioc->req_depth); 6815 6816 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6817 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6818 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a); 6819 } 6820 6821 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq); 6822 6823 if (!ioc->active) 6824 y += sprintf(buffer+len+y, " (disabled)"); 6825 6826 y += sprintf(buffer+len+y, "\n"); 6827 6828 *size = y; 6829 } 6830 6831 #ifdef CONFIG_PROC_FS 6832 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan) 6833 { 6834 char expVer[32]; 6835 6836 mpt_get_fw_exp_ver(expVer, ioc); 6837 6838 /* 6839 * Shorter summary of attached ioc's... 6840 */ 6841 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6842 ioc->name, 6843 ioc->prod_name, 6844 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6845 ioc->facts.FWVersion.Word, 6846 expVer, 6847 ioc->facts.NumberOfPorts, 6848 ioc->req_depth); 6849 6850 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6851 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6852 seq_printf(m, ", LanAddr=%pMR", a); 6853 } 6854 6855 seq_printf(m, ", IRQ=%d", ioc->pci_irq); 6856 6857 if (!ioc->active) 6858 seq_printf(m, " (disabled)"); 6859 6860 seq_putc(m, '\n'); 6861 } 6862 #endif 6863 6864 /** 6865 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management 6866 * @ioc: Pointer to MPT_ADAPTER structure 6867 * 6868 * Returns 0 for SUCCESS or -1 if FAILED. 6869 * 6870 * If -1 is return, then it was not possible to set the flags 6871 **/ 6872 int 6873 mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6874 { 6875 unsigned long flags; 6876 int retval; 6877 6878 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6879 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress || 6880 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) { 6881 retval = -1; 6882 goto out; 6883 } 6884 retval = 0; 6885 ioc->taskmgmt_in_progress = 1; 6886 ioc->taskmgmt_quiesce_io = 1; 6887 if (ioc->alt_ioc) { 6888 ioc->alt_ioc->taskmgmt_in_progress = 1; 6889 ioc->alt_ioc->taskmgmt_quiesce_io = 1; 6890 } 6891 out: 6892 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6893 return retval; 6894 } 6895 EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag); 6896 6897 /** 6898 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management 6899 * @ioc: Pointer to MPT_ADAPTER structure 6900 * 6901 **/ 6902 void 6903 mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6904 { 6905 unsigned long flags; 6906 6907 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6908 ioc->taskmgmt_in_progress = 0; 6909 ioc->taskmgmt_quiesce_io = 0; 6910 if (ioc->alt_ioc) { 6911 ioc->alt_ioc->taskmgmt_in_progress = 0; 6912 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 6913 } 6914 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6915 } 6916 EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag); 6917 6918 6919 /** 6920 * mpt_halt_firmware - Halts the firmware if it is operational and panic 6921 * the kernel 6922 * @ioc: Pointer to MPT_ADAPTER structure 6923 * 6924 **/ 6925 void 6926 mpt_halt_firmware(MPT_ADAPTER *ioc) 6927 { 6928 u32 ioc_raw_state; 6929 6930 ioc_raw_state = mpt_GetIocState(ioc, 0); 6931 6932 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 6933 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n", 6934 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6935 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name, 6936 ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6937 } else { 6938 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00); 6939 panic("%s: Firmware is halted due to command timeout\n", 6940 ioc->name); 6941 } 6942 } 6943 EXPORT_SYMBOL(mpt_halt_firmware); 6944 6945 /** 6946 * mpt_SoftResetHandler - Issues a less expensive reset 6947 * @ioc: Pointer to MPT_ADAPTER structure 6948 * @sleepFlag: Indicates if sleep or schedule must be called. 6949 * 6950 * Returns 0 for SUCCESS or -1 if FAILED. 6951 * 6952 * Message Unit Reset - instructs the IOC to reset the Reply Post and 6953 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded. 6954 * All posted buffers are freed, and event notification is turned off. 6955 * IOC doesn't reply to any outstanding request. This will transfer IOC 6956 * to READY state. 6957 **/ 6958 static int 6959 mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 6960 { 6961 int rc; 6962 int ii; 6963 u8 cb_idx; 6964 unsigned long flags; 6965 u32 ioc_state; 6966 unsigned long time_count; 6967 6968 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n", 6969 ioc->name)); 6970 6971 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 6972 6973 if (mpt_fwfault_debug) 6974 mpt_halt_firmware(ioc); 6975 6976 if (ioc_state == MPI_IOC_STATE_FAULT || 6977 ioc_state == MPI_IOC_STATE_RESET) { 6978 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6979 "skipping, either in FAULT or RESET state!\n", ioc->name)); 6980 return -1; 6981 } 6982 6983 if (ioc->bus_type == FC) { 6984 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6985 "skipping, because the bus type is FC!\n", ioc->name)); 6986 return -1; 6987 } 6988 6989 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6990 if (ioc->ioc_reset_in_progress) { 6991 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6992 return -1; 6993 } 6994 ioc->ioc_reset_in_progress = 1; 6995 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6996 6997 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6998 if (MptResetHandlers[cb_idx]) 6999 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 7000 } 7001 7002 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7003 if (ioc->taskmgmt_in_progress) { 7004 ioc->ioc_reset_in_progress = 0; 7005 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7006 return -1; 7007 } 7008 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7009 /* Disable reply interrupts (also blocks FreeQ) */ 7010 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 7011 ioc->active = 0; 7012 time_count = jiffies; 7013 7014 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 7015 7016 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7017 if (MptResetHandlers[cb_idx]) 7018 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET); 7019 } 7020 7021 if (rc) 7022 goto out; 7023 7024 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 7025 if (ioc_state != MPI_IOC_STATE_READY) 7026 goto out; 7027 7028 for (ii = 0; ii < 5; ii++) { 7029 /* Get IOC facts! Allow 5 retries */ 7030 rc = GetIocFacts(ioc, sleepFlag, 7031 MPT_HOSTEVENT_IOC_RECOVER); 7032 if (rc == 0) 7033 break; 7034 if (sleepFlag == CAN_SLEEP) 7035 msleep(100); 7036 else 7037 mdelay(100); 7038 } 7039 if (ii == 5) 7040 goto out; 7041 7042 rc = PrimeIocFifos(ioc); 7043 if (rc != 0) 7044 goto out; 7045 7046 rc = SendIocInit(ioc, sleepFlag); 7047 if (rc != 0) 7048 goto out; 7049 7050 rc = SendEventNotification(ioc, 1, sleepFlag); 7051 if (rc != 0) 7052 goto out; 7053 7054 if (ioc->hard_resets < -1) 7055 ioc->hard_resets++; 7056 7057 /* 7058 * At this point, we know soft reset succeeded. 7059 */ 7060 7061 ioc->active = 1; 7062 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 7063 7064 out: 7065 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7066 ioc->ioc_reset_in_progress = 0; 7067 ioc->taskmgmt_quiesce_io = 0; 7068 ioc->taskmgmt_in_progress = 0; 7069 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7070 7071 if (ioc->active) { /* otherwise, hard reset coming */ 7072 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7073 if (MptResetHandlers[cb_idx]) 7074 mpt_signal_reset(cb_idx, ioc, 7075 MPT_IOC_POST_RESET); 7076 } 7077 } 7078 7079 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7080 "SoftResetHandler: completed (%d seconds): %s\n", 7081 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000, 7082 ((rc == 0) ? "SUCCESS" : "FAILED"))); 7083 7084 return rc; 7085 } 7086 7087 /** 7088 * mpt_Soft_Hard_ResetHandler - Try less expensive reset 7089 * @ioc: Pointer to MPT_ADAPTER structure 7090 * @sleepFlag: Indicates if sleep or schedule must be called. 7091 * 7092 * Returns 0 for SUCCESS or -1 if FAILED. 7093 * Try for softreset first, only if it fails go for expensive 7094 * HardReset. 7095 **/ 7096 int 7097 mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) { 7098 int ret = -1; 7099 7100 ret = mpt_SoftResetHandler(ioc, sleepFlag); 7101 if (ret == 0) 7102 return ret; 7103 ret = mpt_HardResetHandler(ioc, sleepFlag); 7104 return ret; 7105 } 7106 EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler); 7107 7108 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7109 /* 7110 * Reset Handling 7111 */ 7112 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7113 /** 7114 * mpt_HardResetHandler - Generic reset handler 7115 * @ioc: Pointer to MPT_ADAPTER structure 7116 * @sleepFlag: Indicates if sleep or schedule must be called. 7117 * 7118 * Issues SCSI Task Management call based on input arg values. 7119 * If TaskMgmt fails, returns associated SCSI request. 7120 * 7121 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer) 7122 * or a non-interrupt thread. In the former, must not call schedule(). 7123 * 7124 * Note: A return of -1 is a FATAL error case, as it means a 7125 * FW reload/initialization failed. 7126 * 7127 * Returns 0 for SUCCESS or -1 if FAILED. 7128 */ 7129 int 7130 mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 7131 { 7132 int rc; 7133 u8 cb_idx; 7134 unsigned long flags; 7135 unsigned long time_count; 7136 7137 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name)); 7138 #ifdef MFCNT 7139 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name); 7140 printk("MF count 0x%x !\n", ioc->mfcnt); 7141 #endif 7142 if (mpt_fwfault_debug) 7143 mpt_halt_firmware(ioc); 7144 7145 /* Reset the adapter. Prevent more than 1 call to 7146 * mpt_do_ioc_recovery at any instant in time. 7147 */ 7148 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7149 if (ioc->ioc_reset_in_progress) { 7150 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7151 ioc->wait_on_reset_completion = 1; 7152 do { 7153 ssleep(1); 7154 } while (ioc->ioc_reset_in_progress == 1); 7155 ioc->wait_on_reset_completion = 0; 7156 return ioc->reset_status; 7157 } 7158 if (ioc->wait_on_reset_completion) { 7159 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7160 rc = 0; 7161 time_count = jiffies; 7162 goto exit; 7163 } 7164 ioc->ioc_reset_in_progress = 1; 7165 if (ioc->alt_ioc) 7166 ioc->alt_ioc->ioc_reset_in_progress = 1; 7167 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7168 7169 7170 /* The SCSI driver needs to adjust timeouts on all current 7171 * commands prior to the diagnostic reset being issued. 7172 * Prevents timeouts occurring during a diagnostic reset...very bad. 7173 * For all other protocol drivers, this is a no-op. 7174 */ 7175 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7176 if (MptResetHandlers[cb_idx]) { 7177 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 7178 if (ioc->alt_ioc) 7179 mpt_signal_reset(cb_idx, ioc->alt_ioc, 7180 MPT_IOC_SETUP_RESET); 7181 } 7182 } 7183 7184 time_count = jiffies; 7185 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag); 7186 if (rc != 0) { 7187 printk(KERN_WARNING MYNAM 7188 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n", 7189 rc, ioc->name, mpt_GetIocState(ioc, 0)); 7190 } else { 7191 if (ioc->hard_resets < -1) 7192 ioc->hard_resets++; 7193 } 7194 7195 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7196 ioc->ioc_reset_in_progress = 0; 7197 ioc->taskmgmt_quiesce_io = 0; 7198 ioc->taskmgmt_in_progress = 0; 7199 ioc->reset_status = rc; 7200 if (ioc->alt_ioc) { 7201 ioc->alt_ioc->ioc_reset_in_progress = 0; 7202 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 7203 ioc->alt_ioc->taskmgmt_in_progress = 0; 7204 } 7205 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7206 7207 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7208 if (MptResetHandlers[cb_idx]) { 7209 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET); 7210 if (ioc->alt_ioc) 7211 mpt_signal_reset(cb_idx, 7212 ioc->alt_ioc, MPT_IOC_POST_RESET); 7213 } 7214 } 7215 exit: 7216 dtmprintk(ioc, 7217 printk(MYIOC_s_DEBUG_FMT 7218 "HardResetHandler: completed (%d seconds): %s\n", ioc->name, 7219 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ? 7220 "SUCCESS" : "FAILED"))); 7221 7222 return rc; 7223 } 7224 7225 #ifdef CONFIG_FUSION_LOGGING 7226 static void 7227 mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply) 7228 { 7229 char *ds = NULL; 7230 u32 evData0; 7231 int ii; 7232 u8 event; 7233 char *evStr = ioc->evStr; 7234 7235 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7236 evData0 = le32_to_cpu(pEventReply->Data[0]); 7237 7238 switch(event) { 7239 case MPI_EVENT_NONE: 7240 ds = "None"; 7241 break; 7242 case MPI_EVENT_LOG_DATA: 7243 ds = "Log Data"; 7244 break; 7245 case MPI_EVENT_STATE_CHANGE: 7246 ds = "State Change"; 7247 break; 7248 case MPI_EVENT_UNIT_ATTENTION: 7249 ds = "Unit Attention"; 7250 break; 7251 case MPI_EVENT_IOC_BUS_RESET: 7252 ds = "IOC Bus Reset"; 7253 break; 7254 case MPI_EVENT_EXT_BUS_RESET: 7255 ds = "External Bus Reset"; 7256 break; 7257 case MPI_EVENT_RESCAN: 7258 ds = "Bus Rescan Event"; 7259 break; 7260 case MPI_EVENT_LINK_STATUS_CHANGE: 7261 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE) 7262 ds = "Link Status(FAILURE) Change"; 7263 else 7264 ds = "Link Status(ACTIVE) Change"; 7265 break; 7266 case MPI_EVENT_LOOP_STATE_CHANGE: 7267 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP) 7268 ds = "Loop State(LIP) Change"; 7269 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE) 7270 ds = "Loop State(LPE) Change"; 7271 else 7272 ds = "Loop State(LPB) Change"; 7273 break; 7274 case MPI_EVENT_LOGOUT: 7275 ds = "Logout"; 7276 break; 7277 case MPI_EVENT_EVENT_CHANGE: 7278 if (evData0) 7279 ds = "Events ON"; 7280 else 7281 ds = "Events OFF"; 7282 break; 7283 case MPI_EVENT_INTEGRATED_RAID: 7284 { 7285 u8 ReasonCode = (u8)(evData0 >> 16); 7286 switch (ReasonCode) { 7287 case MPI_EVENT_RAID_RC_VOLUME_CREATED : 7288 ds = "Integrated Raid: Volume Created"; 7289 break; 7290 case MPI_EVENT_RAID_RC_VOLUME_DELETED : 7291 ds = "Integrated Raid: Volume Deleted"; 7292 break; 7293 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED : 7294 ds = "Integrated Raid: Volume Settings Changed"; 7295 break; 7296 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED : 7297 ds = "Integrated Raid: Volume Status Changed"; 7298 break; 7299 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED : 7300 ds = "Integrated Raid: Volume Physdisk Changed"; 7301 break; 7302 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED : 7303 ds = "Integrated Raid: Physdisk Created"; 7304 break; 7305 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED : 7306 ds = "Integrated Raid: Physdisk Deleted"; 7307 break; 7308 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED : 7309 ds = "Integrated Raid: Physdisk Settings Changed"; 7310 break; 7311 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED : 7312 ds = "Integrated Raid: Physdisk Status Changed"; 7313 break; 7314 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED : 7315 ds = "Integrated Raid: Domain Validation Needed"; 7316 break; 7317 case MPI_EVENT_RAID_RC_SMART_DATA : 7318 ds = "Integrated Raid; Smart Data"; 7319 break; 7320 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED : 7321 ds = "Integrated Raid: Replace Action Started"; 7322 break; 7323 default: 7324 ds = "Integrated Raid"; 7325 break; 7326 } 7327 break; 7328 } 7329 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE: 7330 ds = "SCSI Device Status Change"; 7331 break; 7332 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: 7333 { 7334 u8 id = (u8)(evData0); 7335 u8 channel = (u8)(evData0 >> 8); 7336 u8 ReasonCode = (u8)(evData0 >> 16); 7337 switch (ReasonCode) { 7338 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED: 7339 snprintf(evStr, EVENT_DESCR_STR_SZ, 7340 "SAS Device Status Change: Added: " 7341 "id=%d channel=%d", id, channel); 7342 break; 7343 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING: 7344 snprintf(evStr, EVENT_DESCR_STR_SZ, 7345 "SAS Device Status Change: Deleted: " 7346 "id=%d channel=%d", id, channel); 7347 break; 7348 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7349 snprintf(evStr, EVENT_DESCR_STR_SZ, 7350 "SAS Device Status Change: SMART Data: " 7351 "id=%d channel=%d", id, channel); 7352 break; 7353 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED: 7354 snprintf(evStr, EVENT_DESCR_STR_SZ, 7355 "SAS Device Status Change: No Persistency: " 7356 "id=%d channel=%d", id, channel); 7357 break; 7358 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7359 snprintf(evStr, EVENT_DESCR_STR_SZ, 7360 "SAS Device Status Change: Unsupported Device " 7361 "Discovered : id=%d channel=%d", id, channel); 7362 break; 7363 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7364 snprintf(evStr, EVENT_DESCR_STR_SZ, 7365 "SAS Device Status Change: Internal Device " 7366 "Reset : id=%d channel=%d", id, channel); 7367 break; 7368 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7369 snprintf(evStr, EVENT_DESCR_STR_SZ, 7370 "SAS Device Status Change: Internal Task " 7371 "Abort : id=%d channel=%d", id, channel); 7372 break; 7373 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7374 snprintf(evStr, EVENT_DESCR_STR_SZ, 7375 "SAS Device Status Change: Internal Abort " 7376 "Task Set : id=%d channel=%d", id, channel); 7377 break; 7378 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7379 snprintf(evStr, EVENT_DESCR_STR_SZ, 7380 "SAS Device Status Change: Internal Clear " 7381 "Task Set : id=%d channel=%d", id, channel); 7382 break; 7383 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7384 snprintf(evStr, EVENT_DESCR_STR_SZ, 7385 "SAS Device Status Change: Internal Query " 7386 "Task : id=%d channel=%d", id, channel); 7387 break; 7388 default: 7389 snprintf(evStr, EVENT_DESCR_STR_SZ, 7390 "SAS Device Status Change: Unknown: " 7391 "id=%d channel=%d", id, channel); 7392 break; 7393 } 7394 break; 7395 } 7396 case MPI_EVENT_ON_BUS_TIMER_EXPIRED: 7397 ds = "Bus Timer Expired"; 7398 break; 7399 case MPI_EVENT_QUEUE_FULL: 7400 { 7401 u16 curr_depth = (u16)(evData0 >> 16); 7402 u8 channel = (u8)(evData0 >> 8); 7403 u8 id = (u8)(evData0); 7404 7405 snprintf(evStr, EVENT_DESCR_STR_SZ, 7406 "Queue Full: channel=%d id=%d depth=%d", 7407 channel, id, curr_depth); 7408 break; 7409 } 7410 case MPI_EVENT_SAS_SES: 7411 ds = "SAS SES Event"; 7412 break; 7413 case MPI_EVENT_PERSISTENT_TABLE_FULL: 7414 ds = "Persistent Table Full"; 7415 break; 7416 case MPI_EVENT_SAS_PHY_LINK_STATUS: 7417 { 7418 u8 LinkRates = (u8)(evData0 >> 8); 7419 u8 PhyNumber = (u8)(evData0); 7420 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >> 7421 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT; 7422 switch (LinkRates) { 7423 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN: 7424 snprintf(evStr, EVENT_DESCR_STR_SZ, 7425 "SAS PHY Link Status: Phy=%d:" 7426 " Rate Unknown",PhyNumber); 7427 break; 7428 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED: 7429 snprintf(evStr, EVENT_DESCR_STR_SZ, 7430 "SAS PHY Link Status: Phy=%d:" 7431 " Phy Disabled",PhyNumber); 7432 break; 7433 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION: 7434 snprintf(evStr, EVENT_DESCR_STR_SZ, 7435 "SAS PHY Link Status: Phy=%d:" 7436 " Failed Speed Nego",PhyNumber); 7437 break; 7438 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE: 7439 snprintf(evStr, EVENT_DESCR_STR_SZ, 7440 "SAS PHY Link Status: Phy=%d:" 7441 " Sata OOB Completed",PhyNumber); 7442 break; 7443 case MPI_EVENT_SAS_PLS_LR_RATE_1_5: 7444 snprintf(evStr, EVENT_DESCR_STR_SZ, 7445 "SAS PHY Link Status: Phy=%d:" 7446 " Rate 1.5 Gbps",PhyNumber); 7447 break; 7448 case MPI_EVENT_SAS_PLS_LR_RATE_3_0: 7449 snprintf(evStr, EVENT_DESCR_STR_SZ, 7450 "SAS PHY Link Status: Phy=%d:" 7451 " Rate 3.0 Gbps", PhyNumber); 7452 break; 7453 case MPI_EVENT_SAS_PLS_LR_RATE_6_0: 7454 snprintf(evStr, EVENT_DESCR_STR_SZ, 7455 "SAS PHY Link Status: Phy=%d:" 7456 " Rate 6.0 Gbps", PhyNumber); 7457 break; 7458 default: 7459 snprintf(evStr, EVENT_DESCR_STR_SZ, 7460 "SAS PHY Link Status: Phy=%d", PhyNumber); 7461 break; 7462 } 7463 break; 7464 } 7465 case MPI_EVENT_SAS_DISCOVERY_ERROR: 7466 ds = "SAS Discovery Error"; 7467 break; 7468 case MPI_EVENT_IR_RESYNC_UPDATE: 7469 { 7470 u8 resync_complete = (u8)(evData0 >> 16); 7471 snprintf(evStr, EVENT_DESCR_STR_SZ, 7472 "IR Resync Update: Complete = %d:",resync_complete); 7473 break; 7474 } 7475 case MPI_EVENT_IR2: 7476 { 7477 u8 id = (u8)(evData0); 7478 u8 channel = (u8)(evData0 >> 8); 7479 u8 phys_num = (u8)(evData0 >> 24); 7480 u8 ReasonCode = (u8)(evData0 >> 16); 7481 7482 switch (ReasonCode) { 7483 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED: 7484 snprintf(evStr, EVENT_DESCR_STR_SZ, 7485 "IR2: LD State Changed: " 7486 "id=%d channel=%d phys_num=%d", 7487 id, channel, phys_num); 7488 break; 7489 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED: 7490 snprintf(evStr, EVENT_DESCR_STR_SZ, 7491 "IR2: PD State Changed " 7492 "id=%d channel=%d phys_num=%d", 7493 id, channel, phys_num); 7494 break; 7495 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL: 7496 snprintf(evStr, EVENT_DESCR_STR_SZ, 7497 "IR2: Bad Block Table Full: " 7498 "id=%d channel=%d phys_num=%d", 7499 id, channel, phys_num); 7500 break; 7501 case MPI_EVENT_IR2_RC_PD_INSERTED: 7502 snprintf(evStr, EVENT_DESCR_STR_SZ, 7503 "IR2: PD Inserted: " 7504 "id=%d channel=%d phys_num=%d", 7505 id, channel, phys_num); 7506 break; 7507 case MPI_EVENT_IR2_RC_PD_REMOVED: 7508 snprintf(evStr, EVENT_DESCR_STR_SZ, 7509 "IR2: PD Removed: " 7510 "id=%d channel=%d phys_num=%d", 7511 id, channel, phys_num); 7512 break; 7513 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED: 7514 snprintf(evStr, EVENT_DESCR_STR_SZ, 7515 "IR2: Foreign CFG Detected: " 7516 "id=%d channel=%d phys_num=%d", 7517 id, channel, phys_num); 7518 break; 7519 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR: 7520 snprintf(evStr, EVENT_DESCR_STR_SZ, 7521 "IR2: Rebuild Medium Error: " 7522 "id=%d channel=%d phys_num=%d", 7523 id, channel, phys_num); 7524 break; 7525 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED: 7526 snprintf(evStr, EVENT_DESCR_STR_SZ, 7527 "IR2: Dual Port Added: " 7528 "id=%d channel=%d phys_num=%d", 7529 id, channel, phys_num); 7530 break; 7531 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED: 7532 snprintf(evStr, EVENT_DESCR_STR_SZ, 7533 "IR2: Dual Port Removed: " 7534 "id=%d channel=%d phys_num=%d", 7535 id, channel, phys_num); 7536 break; 7537 default: 7538 ds = "IR2"; 7539 break; 7540 } 7541 break; 7542 } 7543 case MPI_EVENT_SAS_DISCOVERY: 7544 { 7545 if (evData0) 7546 ds = "SAS Discovery: Start"; 7547 else 7548 ds = "SAS Discovery: Stop"; 7549 break; 7550 } 7551 case MPI_EVENT_LOG_ENTRY_ADDED: 7552 ds = "SAS Log Entry Added"; 7553 break; 7554 7555 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE: 7556 { 7557 u8 phy_num = (u8)(evData0); 7558 u8 port_num = (u8)(evData0 >> 8); 7559 u8 port_width = (u8)(evData0 >> 16); 7560 u8 primitive = (u8)(evData0 >> 24); 7561 snprintf(evStr, EVENT_DESCR_STR_SZ, 7562 "SAS Broadcast Primitive: phy=%d port=%d " 7563 "width=%d primitive=0x%02x", 7564 phy_num, port_num, port_width, primitive); 7565 break; 7566 } 7567 7568 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 7569 { 7570 u8 reason = (u8)(evData0); 7571 7572 switch (reason) { 7573 case MPI_EVENT_SAS_INIT_RC_ADDED: 7574 ds = "SAS Initiator Status Change: Added"; 7575 break; 7576 case MPI_EVENT_SAS_INIT_RC_REMOVED: 7577 ds = "SAS Initiator Status Change: Deleted"; 7578 break; 7579 default: 7580 ds = "SAS Initiator Status Change"; 7581 break; 7582 } 7583 break; 7584 } 7585 7586 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW: 7587 { 7588 u8 max_init = (u8)(evData0); 7589 u8 current_init = (u8)(evData0 >> 8); 7590 7591 snprintf(evStr, EVENT_DESCR_STR_SZ, 7592 "SAS Initiator Device Table Overflow: max initiators=%02d " 7593 "current initiators=%02d", 7594 max_init, current_init); 7595 break; 7596 } 7597 case MPI_EVENT_SAS_SMP_ERROR: 7598 { 7599 u8 status = (u8)(evData0); 7600 u8 port_num = (u8)(evData0 >> 8); 7601 u8 result = (u8)(evData0 >> 16); 7602 7603 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID) 7604 snprintf(evStr, EVENT_DESCR_STR_SZ, 7605 "SAS SMP Error: port=%d result=0x%02x", 7606 port_num, result); 7607 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR) 7608 snprintf(evStr, EVENT_DESCR_STR_SZ, 7609 "SAS SMP Error: port=%d : CRC Error", 7610 port_num); 7611 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT) 7612 snprintf(evStr, EVENT_DESCR_STR_SZ, 7613 "SAS SMP Error: port=%d : Timeout", 7614 port_num); 7615 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION) 7616 snprintf(evStr, EVENT_DESCR_STR_SZ, 7617 "SAS SMP Error: port=%d : No Destination", 7618 port_num); 7619 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION) 7620 snprintf(evStr, EVENT_DESCR_STR_SZ, 7621 "SAS SMP Error: port=%d : Bad Destination", 7622 port_num); 7623 else 7624 snprintf(evStr, EVENT_DESCR_STR_SZ, 7625 "SAS SMP Error: port=%d : status=0x%02x", 7626 port_num, status); 7627 break; 7628 } 7629 7630 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE: 7631 { 7632 u8 reason = (u8)(evData0); 7633 7634 switch (reason) { 7635 case MPI_EVENT_SAS_EXP_RC_ADDED: 7636 ds = "Expander Status Change: Added"; 7637 break; 7638 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING: 7639 ds = "Expander Status Change: Deleted"; 7640 break; 7641 default: 7642 ds = "Expander Status Change"; 7643 break; 7644 } 7645 break; 7646 } 7647 7648 /* 7649 * MPT base "custom" events may be added here... 7650 */ 7651 default: 7652 ds = "Unknown"; 7653 break; 7654 } 7655 if (ds) 7656 strlcpy(evStr, ds, EVENT_DESCR_STR_SZ); 7657 7658 7659 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7660 "MPT event:(%02Xh) : %s\n", 7661 ioc->name, event, evStr)); 7662 7663 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM 7664 ": Event data:\n")); 7665 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++) 7666 devtverboseprintk(ioc, printk(" %08x", 7667 le32_to_cpu(pEventReply->Data[ii]))); 7668 devtverboseprintk(ioc, printk(KERN_DEBUG "\n")); 7669 } 7670 #endif 7671 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7672 /** 7673 * ProcessEventNotification - Route EventNotificationReply to all event handlers 7674 * @ioc: Pointer to MPT_ADAPTER structure 7675 * @pEventReply: Pointer to EventNotification reply frame 7676 * @evHandlers: Pointer to integer, number of event handlers 7677 * 7678 * Routes a received EventNotificationReply to all currently registered 7679 * event handlers. 7680 * Returns sum of event handlers return values. 7681 */ 7682 static int 7683 ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers) 7684 { 7685 u16 evDataLen; 7686 u32 evData0 = 0; 7687 int ii; 7688 u8 cb_idx; 7689 int r = 0; 7690 int handlers = 0; 7691 u8 event; 7692 7693 /* 7694 * Do platform normalization of values 7695 */ 7696 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7697 evDataLen = le16_to_cpu(pEventReply->EventDataLength); 7698 if (evDataLen) { 7699 evData0 = le32_to_cpu(pEventReply->Data[0]); 7700 } 7701 7702 #ifdef CONFIG_FUSION_LOGGING 7703 if (evDataLen) 7704 mpt_display_event_info(ioc, pEventReply); 7705 #endif 7706 7707 /* 7708 * Do general / base driver event processing 7709 */ 7710 switch(event) { 7711 case MPI_EVENT_EVENT_CHANGE: /* 0A */ 7712 if (evDataLen) { 7713 u8 evState = evData0 & 0xFF; 7714 7715 /* CHECKME! What if evState unexpectedly says OFF (0)? */ 7716 7717 /* Update EventState field in cached IocFacts */ 7718 if (ioc->facts.Function) { 7719 ioc->facts.EventState = evState; 7720 } 7721 } 7722 break; 7723 case MPI_EVENT_INTEGRATED_RAID: 7724 mptbase_raid_process_event_data(ioc, 7725 (MpiEventDataRaid_t *)pEventReply->Data); 7726 break; 7727 default: 7728 break; 7729 } 7730 7731 /* 7732 * Should this event be logged? Events are written sequentially. 7733 * When buffer is full, start again at the top. 7734 */ 7735 if (ioc->events && (ioc->eventTypes & ( 1 << event))) { 7736 int idx; 7737 7738 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE; 7739 7740 ioc->events[idx].event = event; 7741 ioc->events[idx].eventContext = ioc->eventContext; 7742 7743 for (ii = 0; ii < 2; ii++) { 7744 if (ii < evDataLen) 7745 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]); 7746 else 7747 ioc->events[idx].data[ii] = 0; 7748 } 7749 7750 ioc->eventContext++; 7751 } 7752 7753 7754 /* 7755 * Call each currently registered protocol event handler. 7756 */ 7757 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7758 if (MptEvHandlers[cb_idx]) { 7759 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7760 "Routing Event to event handler #%d\n", 7761 ioc->name, cb_idx)); 7762 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply); 7763 handlers++; 7764 } 7765 } 7766 /* FIXME? Examine results here? */ 7767 7768 /* 7769 * If needed, send (a single) EventAck. 7770 */ 7771 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) { 7772 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7773 "EventAck required\n",ioc->name)); 7774 if ((ii = SendEventAck(ioc, pEventReply)) != 0) { 7775 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n", 7776 ioc->name, ii)); 7777 } 7778 } 7779 7780 *evHandlers = handlers; 7781 return r; 7782 } 7783 7784 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7785 /** 7786 * mpt_fc_log_info - Log information returned from Fibre Channel IOC. 7787 * @ioc: Pointer to MPT_ADAPTER structure 7788 * @log_info: U32 LogInfo reply word from the IOC 7789 * 7790 * Refer to lsi/mpi_log_fc.h. 7791 */ 7792 static void 7793 mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info) 7794 { 7795 char *desc = "unknown"; 7796 7797 switch (log_info & 0xFF000000) { 7798 case MPI_IOCLOGINFO_FC_INIT_BASE: 7799 desc = "FCP Initiator"; 7800 break; 7801 case MPI_IOCLOGINFO_FC_TARGET_BASE: 7802 desc = "FCP Target"; 7803 break; 7804 case MPI_IOCLOGINFO_FC_LAN_BASE: 7805 desc = "LAN"; 7806 break; 7807 case MPI_IOCLOGINFO_FC_MSG_BASE: 7808 desc = "MPI Message Layer"; 7809 break; 7810 case MPI_IOCLOGINFO_FC_LINK_BASE: 7811 desc = "FC Link"; 7812 break; 7813 case MPI_IOCLOGINFO_FC_CTX_BASE: 7814 desc = "Context Manager"; 7815 break; 7816 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET: 7817 desc = "Invalid Field Offset"; 7818 break; 7819 case MPI_IOCLOGINFO_FC_STATE_CHANGE: 7820 desc = "State Change Info"; 7821 break; 7822 } 7823 7824 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n", 7825 ioc->name, log_info, desc, (log_info & 0xFFFFFF)); 7826 } 7827 7828 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7829 /** 7830 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC. 7831 * @ioc: Pointer to MPT_ADAPTER structure 7832 * @log_info: U32 LogInfo word from the IOC 7833 * 7834 * Refer to lsi/sp_log.h. 7835 */ 7836 static void 7837 mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info) 7838 { 7839 u32 info = log_info & 0x00FF0000; 7840 char *desc = "unknown"; 7841 7842 switch (info) { 7843 case 0x00010000: 7844 desc = "bug! MID not found"; 7845 break; 7846 7847 case 0x00020000: 7848 desc = "Parity Error"; 7849 break; 7850 7851 case 0x00030000: 7852 desc = "ASYNC Outbound Overrun"; 7853 break; 7854 7855 case 0x00040000: 7856 desc = "SYNC Offset Error"; 7857 break; 7858 7859 case 0x00050000: 7860 desc = "BM Change"; 7861 break; 7862 7863 case 0x00060000: 7864 desc = "Msg In Overflow"; 7865 break; 7866 7867 case 0x00070000: 7868 desc = "DMA Error"; 7869 break; 7870 7871 case 0x00080000: 7872 desc = "Outbound DMA Overrun"; 7873 break; 7874 7875 case 0x00090000: 7876 desc = "Task Management"; 7877 break; 7878 7879 case 0x000A0000: 7880 desc = "Device Problem"; 7881 break; 7882 7883 case 0x000B0000: 7884 desc = "Invalid Phase Change"; 7885 break; 7886 7887 case 0x000C0000: 7888 desc = "Untagged Table Size"; 7889 break; 7890 7891 } 7892 7893 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc); 7894 } 7895 7896 /* strings for sas loginfo */ 7897 static char *originator_str[] = { 7898 "IOP", /* 00h */ 7899 "PL", /* 01h */ 7900 "IR" /* 02h */ 7901 }; 7902 static char *iop_code_str[] = { 7903 NULL, /* 00h */ 7904 "Invalid SAS Address", /* 01h */ 7905 NULL, /* 02h */ 7906 "Invalid Page", /* 03h */ 7907 "Diag Message Error", /* 04h */ 7908 "Task Terminated", /* 05h */ 7909 "Enclosure Management", /* 06h */ 7910 "Target Mode" /* 07h */ 7911 }; 7912 static char *pl_code_str[] = { 7913 NULL, /* 00h */ 7914 "Open Failure", /* 01h */ 7915 "Invalid Scatter Gather List", /* 02h */ 7916 "Wrong Relative Offset or Frame Length", /* 03h */ 7917 "Frame Transfer Error", /* 04h */ 7918 "Transmit Frame Connected Low", /* 05h */ 7919 "SATA Non-NCQ RW Error Bit Set", /* 06h */ 7920 "SATA Read Log Receive Data Error", /* 07h */ 7921 "SATA NCQ Fail All Commands After Error", /* 08h */ 7922 "SATA Error in Receive Set Device Bit FIS", /* 09h */ 7923 "Receive Frame Invalid Message", /* 0Ah */ 7924 "Receive Context Message Valid Error", /* 0Bh */ 7925 "Receive Frame Current Frame Error", /* 0Ch */ 7926 "SATA Link Down", /* 0Dh */ 7927 "Discovery SATA Init W IOS", /* 0Eh */ 7928 "Config Invalid Page", /* 0Fh */ 7929 "Discovery SATA Init Timeout", /* 10h */ 7930 "Reset", /* 11h */ 7931 "Abort", /* 12h */ 7932 "IO Not Yet Executed", /* 13h */ 7933 "IO Executed", /* 14h */ 7934 "Persistent Reservation Out Not Affiliation " 7935 "Owner", /* 15h */ 7936 "Open Transmit DMA Abort", /* 16h */ 7937 "IO Device Missing Delay Retry", /* 17h */ 7938 "IO Cancelled Due to Receive Error", /* 18h */ 7939 NULL, /* 19h */ 7940 NULL, /* 1Ah */ 7941 NULL, /* 1Bh */ 7942 NULL, /* 1Ch */ 7943 NULL, /* 1Dh */ 7944 NULL, /* 1Eh */ 7945 NULL, /* 1Fh */ 7946 "Enclosure Management" /* 20h */ 7947 }; 7948 static char *ir_code_str[] = { 7949 "Raid Action Error", /* 00h */ 7950 NULL, /* 00h */ 7951 NULL, /* 01h */ 7952 NULL, /* 02h */ 7953 NULL, /* 03h */ 7954 NULL, /* 04h */ 7955 NULL, /* 05h */ 7956 NULL, /* 06h */ 7957 NULL /* 07h */ 7958 }; 7959 static char *raid_sub_code_str[] = { 7960 NULL, /* 00h */ 7961 "Volume Creation Failed: Data Passed too " 7962 "Large", /* 01h */ 7963 "Volume Creation Failed: Duplicate Volumes " 7964 "Attempted", /* 02h */ 7965 "Volume Creation Failed: Max Number " 7966 "Supported Volumes Exceeded", /* 03h */ 7967 "Volume Creation Failed: DMA Error", /* 04h */ 7968 "Volume Creation Failed: Invalid Volume Type", /* 05h */ 7969 "Volume Creation Failed: Error Reading " 7970 "MFG Page 4", /* 06h */ 7971 "Volume Creation Failed: Creating Internal " 7972 "Structures", /* 07h */ 7973 NULL, /* 08h */ 7974 NULL, /* 09h */ 7975 NULL, /* 0Ah */ 7976 NULL, /* 0Bh */ 7977 NULL, /* 0Ch */ 7978 NULL, /* 0Dh */ 7979 NULL, /* 0Eh */ 7980 NULL, /* 0Fh */ 7981 "Activation failed: Already Active Volume", /* 10h */ 7982 "Activation failed: Unsupported Volume Type", /* 11h */ 7983 "Activation failed: Too Many Active Volumes", /* 12h */ 7984 "Activation failed: Volume ID in Use", /* 13h */ 7985 "Activation failed: Reported Failure", /* 14h */ 7986 "Activation failed: Importing a Volume", /* 15h */ 7987 NULL, /* 16h */ 7988 NULL, /* 17h */ 7989 NULL, /* 18h */ 7990 NULL, /* 19h */ 7991 NULL, /* 1Ah */ 7992 NULL, /* 1Bh */ 7993 NULL, /* 1Ch */ 7994 NULL, /* 1Dh */ 7995 NULL, /* 1Eh */ 7996 NULL, /* 1Fh */ 7997 "Phys Disk failed: Too Many Phys Disks", /* 20h */ 7998 "Phys Disk failed: Data Passed too Large", /* 21h */ 7999 "Phys Disk failed: DMA Error", /* 22h */ 8000 "Phys Disk failed: Invalid <channel:id>", /* 23h */ 8001 "Phys Disk failed: Creating Phys Disk Config " 8002 "Page", /* 24h */ 8003 NULL, /* 25h */ 8004 NULL, /* 26h */ 8005 NULL, /* 27h */ 8006 NULL, /* 28h */ 8007 NULL, /* 29h */ 8008 NULL, /* 2Ah */ 8009 NULL, /* 2Bh */ 8010 NULL, /* 2Ch */ 8011 NULL, /* 2Dh */ 8012 NULL, /* 2Eh */ 8013 NULL, /* 2Fh */ 8014 "Compatibility Error: IR Disabled", /* 30h */ 8015 "Compatibility Error: Inquiry Command Failed", /* 31h */ 8016 "Compatibility Error: Device not Direct Access " 8017 "Device ", /* 32h */ 8018 "Compatibility Error: Removable Device Found", /* 33h */ 8019 "Compatibility Error: Device SCSI Version not " 8020 "2 or Higher", /* 34h */ 8021 "Compatibility Error: SATA Device, 48 BIT LBA " 8022 "not Supported", /* 35h */ 8023 "Compatibility Error: Device doesn't have " 8024 "512 Byte Block Sizes", /* 36h */ 8025 "Compatibility Error: Volume Type Check Failed", /* 37h */ 8026 "Compatibility Error: Volume Type is " 8027 "Unsupported by FW", /* 38h */ 8028 "Compatibility Error: Disk Drive too Small for " 8029 "use in Volume", /* 39h */ 8030 "Compatibility Error: Phys Disk for Create " 8031 "Volume not Found", /* 3Ah */ 8032 "Compatibility Error: Too Many or too Few " 8033 "Disks for Volume Type", /* 3Bh */ 8034 "Compatibility Error: Disk stripe Sizes " 8035 "Must be 64KB", /* 3Ch */ 8036 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */ 8037 }; 8038 8039 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8040 /** 8041 * mpt_sas_log_info - Log information returned from SAS IOC. 8042 * @ioc: Pointer to MPT_ADAPTER structure 8043 * @log_info: U32 LogInfo reply word from the IOC 8044 * @cb_idx: callback function's handle 8045 * 8046 * Refer to lsi/mpi_log_sas.h. 8047 **/ 8048 static void 8049 mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx) 8050 { 8051 union loginfo_type { 8052 u32 loginfo; 8053 struct { 8054 u32 subcode:16; 8055 u32 code:8; 8056 u32 originator:4; 8057 u32 bus_type:4; 8058 } dw; 8059 }; 8060 union loginfo_type sas_loginfo; 8061 char *originator_desc = NULL; 8062 char *code_desc = NULL; 8063 char *sub_code_desc = NULL; 8064 8065 sas_loginfo.loginfo = log_info; 8066 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) && 8067 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str))) 8068 return; 8069 8070 originator_desc = originator_str[sas_loginfo.dw.originator]; 8071 8072 switch (sas_loginfo.dw.originator) { 8073 8074 case 0: /* IOP */ 8075 if (sas_loginfo.dw.code < 8076 ARRAY_SIZE(iop_code_str)) 8077 code_desc = iop_code_str[sas_loginfo.dw.code]; 8078 break; 8079 case 1: /* PL */ 8080 if (sas_loginfo.dw.code < 8081 ARRAY_SIZE(pl_code_str)) 8082 code_desc = pl_code_str[sas_loginfo.dw.code]; 8083 break; 8084 case 2: /* IR */ 8085 if (sas_loginfo.dw.code >= 8086 ARRAY_SIZE(ir_code_str)) 8087 break; 8088 code_desc = ir_code_str[sas_loginfo.dw.code]; 8089 if (sas_loginfo.dw.subcode >= 8090 ARRAY_SIZE(raid_sub_code_str)) 8091 break; 8092 if (sas_loginfo.dw.code == 0) 8093 sub_code_desc = 8094 raid_sub_code_str[sas_loginfo.dw.subcode]; 8095 break; 8096 default: 8097 return; 8098 } 8099 8100 if (sub_code_desc != NULL) 8101 printk(MYIOC_s_INFO_FMT 8102 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8103 " SubCode={%s} cb_idx %s\n", 8104 ioc->name, log_info, originator_desc, code_desc, 8105 sub_code_desc, MptCallbacksName[cb_idx]); 8106 else if (code_desc != NULL) 8107 printk(MYIOC_s_INFO_FMT 8108 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8109 " SubCode(0x%04x) cb_idx %s\n", 8110 ioc->name, log_info, originator_desc, code_desc, 8111 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]); 8112 else 8113 printk(MYIOC_s_INFO_FMT 8114 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x)," 8115 " SubCode(0x%04x) cb_idx %s\n", 8116 ioc->name, log_info, originator_desc, 8117 sas_loginfo.dw.code, sas_loginfo.dw.subcode, 8118 MptCallbacksName[cb_idx]); 8119 } 8120 8121 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8122 /** 8123 * mpt_iocstatus_info_config - IOCSTATUS information for config pages 8124 * @ioc: Pointer to MPT_ADAPTER structure 8125 * @ioc_status: U32 IOCStatus word from IOC 8126 * @mf: Pointer to MPT request frame 8127 * 8128 * Refer to lsi/mpi.h. 8129 **/ 8130 static void 8131 mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8132 { 8133 Config_t *pReq = (Config_t *)mf; 8134 char extend_desc[EVENT_DESCR_STR_SZ]; 8135 char *desc = NULL; 8136 u32 form; 8137 u8 page_type; 8138 8139 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED) 8140 page_type = pReq->ExtPageType; 8141 else 8142 page_type = pReq->Header.PageType; 8143 8144 /* 8145 * ignore invalid page messages for GET_NEXT_HANDLE 8146 */ 8147 form = le32_to_cpu(pReq->PageAddress); 8148 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) { 8149 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE || 8150 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER || 8151 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) { 8152 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) == 8153 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE) 8154 return; 8155 } 8156 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE) 8157 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) == 8158 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 8159 return; 8160 } 8161 8162 snprintf(extend_desc, EVENT_DESCR_STR_SZ, 8163 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh", 8164 page_type, pReq->Header.PageNumber, pReq->Action, form); 8165 8166 switch (ioc_status) { 8167 8168 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8169 desc = "Config Page Invalid Action"; 8170 break; 8171 8172 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8173 desc = "Config Page Invalid Type"; 8174 break; 8175 8176 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8177 desc = "Config Page Invalid Page"; 8178 break; 8179 8180 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8181 desc = "Config Page Invalid Data"; 8182 break; 8183 8184 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8185 desc = "Config Page No Defaults"; 8186 break; 8187 8188 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8189 desc = "Config Page Can't Commit"; 8190 break; 8191 } 8192 8193 if (!desc) 8194 return; 8195 8196 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n", 8197 ioc->name, ioc_status, desc, extend_desc)); 8198 } 8199 8200 /** 8201 * mpt_iocstatus_info - IOCSTATUS information returned from IOC. 8202 * @ioc: Pointer to MPT_ADAPTER structure 8203 * @ioc_status: U32 IOCStatus word from IOC 8204 * @mf: Pointer to MPT request frame 8205 * 8206 * Refer to lsi/mpi.h. 8207 **/ 8208 static void 8209 mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8210 { 8211 u32 status = ioc_status & MPI_IOCSTATUS_MASK; 8212 char *desc = NULL; 8213 8214 switch (status) { 8215 8216 /****************************************************************************/ 8217 /* Common IOCStatus values for all replies */ 8218 /****************************************************************************/ 8219 8220 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */ 8221 desc = "Invalid Function"; 8222 break; 8223 8224 case MPI_IOCSTATUS_BUSY: /* 0x0002 */ 8225 desc = "Busy"; 8226 break; 8227 8228 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */ 8229 desc = "Invalid SGL"; 8230 break; 8231 8232 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */ 8233 desc = "Internal Error"; 8234 break; 8235 8236 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */ 8237 desc = "Reserved"; 8238 break; 8239 8240 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */ 8241 desc = "Insufficient Resources"; 8242 break; 8243 8244 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */ 8245 desc = "Invalid Field"; 8246 break; 8247 8248 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */ 8249 desc = "Invalid State"; 8250 break; 8251 8252 /****************************************************************************/ 8253 /* Config IOCStatus values */ 8254 /****************************************************************************/ 8255 8256 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8257 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8258 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8259 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8260 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8261 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8262 mpt_iocstatus_info_config(ioc, status, mf); 8263 break; 8264 8265 /****************************************************************************/ 8266 /* SCSIIO Reply (SPI, FCP, SAS) initiator values */ 8267 /* */ 8268 /* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */ 8269 /* */ 8270 /****************************************************************************/ 8271 8272 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */ 8273 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */ 8274 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */ 8275 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */ 8276 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */ 8277 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */ 8278 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */ 8279 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */ 8280 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */ 8281 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */ 8282 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */ 8283 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */ 8284 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */ 8285 break; 8286 8287 /****************************************************************************/ 8288 /* SCSI Target values */ 8289 /****************************************************************************/ 8290 8291 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */ 8292 desc = "Target: Priority IO"; 8293 break; 8294 8295 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */ 8296 desc = "Target: Invalid Port"; 8297 break; 8298 8299 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */ 8300 desc = "Target Invalid IO Index:"; 8301 break; 8302 8303 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */ 8304 desc = "Target: Aborted"; 8305 break; 8306 8307 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */ 8308 desc = "Target: No Conn Retryable"; 8309 break; 8310 8311 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */ 8312 desc = "Target: No Connection"; 8313 break; 8314 8315 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */ 8316 desc = "Target: Transfer Count Mismatch"; 8317 break; 8318 8319 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */ 8320 desc = "Target: STS Data not Sent"; 8321 break; 8322 8323 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */ 8324 desc = "Target: Data Offset Error"; 8325 break; 8326 8327 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */ 8328 desc = "Target: Too Much Write Data"; 8329 break; 8330 8331 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */ 8332 desc = "Target: IU Too Short"; 8333 break; 8334 8335 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */ 8336 desc = "Target: ACK NAK Timeout"; 8337 break; 8338 8339 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */ 8340 desc = "Target: Nak Received"; 8341 break; 8342 8343 /****************************************************************************/ 8344 /* Fibre Channel Direct Access values */ 8345 /****************************************************************************/ 8346 8347 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */ 8348 desc = "FC: Aborted"; 8349 break; 8350 8351 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */ 8352 desc = "FC: RX ID Invalid"; 8353 break; 8354 8355 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */ 8356 desc = "FC: DID Invalid"; 8357 break; 8358 8359 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */ 8360 desc = "FC: Node Logged Out"; 8361 break; 8362 8363 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */ 8364 desc = "FC: Exchange Canceled"; 8365 break; 8366 8367 /****************************************************************************/ 8368 /* LAN values */ 8369 /****************************************************************************/ 8370 8371 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */ 8372 desc = "LAN: Device not Found"; 8373 break; 8374 8375 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */ 8376 desc = "LAN: Device Failure"; 8377 break; 8378 8379 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */ 8380 desc = "LAN: Transmit Error"; 8381 break; 8382 8383 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */ 8384 desc = "LAN: Transmit Aborted"; 8385 break; 8386 8387 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */ 8388 desc = "LAN: Receive Error"; 8389 break; 8390 8391 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */ 8392 desc = "LAN: Receive Aborted"; 8393 break; 8394 8395 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */ 8396 desc = "LAN: Partial Packet"; 8397 break; 8398 8399 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */ 8400 desc = "LAN: Canceled"; 8401 break; 8402 8403 /****************************************************************************/ 8404 /* Serial Attached SCSI values */ 8405 /****************************************************************************/ 8406 8407 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */ 8408 desc = "SAS: SMP Request Failed"; 8409 break; 8410 8411 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */ 8412 desc = "SAS: SMP Data Overrun"; 8413 break; 8414 8415 default: 8416 desc = "Others"; 8417 break; 8418 } 8419 8420 if (!desc) 8421 return; 8422 8423 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n", 8424 ioc->name, status, desc)); 8425 } 8426 8427 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8428 EXPORT_SYMBOL(mpt_attach); 8429 EXPORT_SYMBOL(mpt_detach); 8430 #ifdef CONFIG_PM 8431 EXPORT_SYMBOL(mpt_resume); 8432 EXPORT_SYMBOL(mpt_suspend); 8433 #endif 8434 EXPORT_SYMBOL(ioc_list); 8435 EXPORT_SYMBOL(mpt_register); 8436 EXPORT_SYMBOL(mpt_deregister); 8437 EXPORT_SYMBOL(mpt_event_register); 8438 EXPORT_SYMBOL(mpt_event_deregister); 8439 EXPORT_SYMBOL(mpt_reset_register); 8440 EXPORT_SYMBOL(mpt_reset_deregister); 8441 EXPORT_SYMBOL(mpt_device_driver_register); 8442 EXPORT_SYMBOL(mpt_device_driver_deregister); 8443 EXPORT_SYMBOL(mpt_get_msg_frame); 8444 EXPORT_SYMBOL(mpt_put_msg_frame); 8445 EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri); 8446 EXPORT_SYMBOL(mpt_free_msg_frame); 8447 EXPORT_SYMBOL(mpt_send_handshake_request); 8448 EXPORT_SYMBOL(mpt_verify_adapter); 8449 EXPORT_SYMBOL(mpt_GetIocState); 8450 EXPORT_SYMBOL(mpt_print_ioc_summary); 8451 EXPORT_SYMBOL(mpt_HardResetHandler); 8452 EXPORT_SYMBOL(mpt_config); 8453 EXPORT_SYMBOL(mpt_findImVolumes); 8454 EXPORT_SYMBOL(mpt_alloc_fw_memory); 8455 EXPORT_SYMBOL(mpt_free_fw_memory); 8456 EXPORT_SYMBOL(mptbase_sas_persist_operation); 8457 EXPORT_SYMBOL(mpt_raid_phys_disk_pg0); 8458 8459 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8460 /** 8461 * fusion_init - Fusion MPT base driver initialization routine. 8462 * 8463 * Returns 0 for success, non-zero for failure. 8464 */ 8465 static int __init 8466 fusion_init(void) 8467 { 8468 u8 cb_idx; 8469 8470 show_mptmod_ver(my_NAME, my_VERSION); 8471 printk(KERN_INFO COPYRIGHT "\n"); 8472 8473 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 8474 MptCallbacks[cb_idx] = NULL; 8475 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 8476 MptEvHandlers[cb_idx] = NULL; 8477 MptResetHandlers[cb_idx] = NULL; 8478 } 8479 8480 /* Register ourselves (mptbase) in order to facilitate 8481 * EventNotification handling. 8482 */ 8483 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER, 8484 "mptbase_reply"); 8485 8486 /* Register for hard reset handling callbacks. 8487 */ 8488 mpt_reset_register(mpt_base_index, mpt_ioc_reset); 8489 8490 #ifdef CONFIG_PROC_FS 8491 (void) procmpt_create(); 8492 #endif 8493 return 0; 8494 } 8495 8496 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8497 /** 8498 * fusion_exit - Perform driver unload cleanup. 8499 * 8500 * This routine frees all resources associated with each MPT adapter 8501 * and removes all %MPT_PROCFS_MPTBASEDIR entries. 8502 */ 8503 static void __exit 8504 fusion_exit(void) 8505 { 8506 8507 mpt_reset_deregister(mpt_base_index); 8508 8509 #ifdef CONFIG_PROC_FS 8510 procmpt_destroy(); 8511 #endif 8512 } 8513 8514 module_init(fusion_init); 8515 module_exit(fusion_exit); 8516