1 /* 2 * linux/drivers/message/fusion/mptbase.c 3 * This is the Fusion MPT base driver which supports multiple 4 * (SCSI + LAN) specialized protocol drivers. 5 * For use with LSI PCI chip/adapter(s) 6 * running LSI Fusion MPT (Message Passing Technology) firmware. 7 * 8 * Copyright (c) 1999-2008 LSI Corporation 9 * (mailto:[email protected]) 10 * 11 */ 12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 13 /* 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; version 2 of the License. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 NO WARRANTY 24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 28 solely responsible for determining the appropriateness of using and 29 distributing the Program and assumes all risks associated with its 30 exercise of rights under this Agreement, including but not limited to 31 the risks and costs of program errors, damage to or loss of data, 32 programs or equipment, and unavailability or interruption of operations. 33 34 DISCLAIMER OF LIABILITY 35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 42 43 You should have received a copy of the GNU General Public License 44 along with this program; if not, write to the Free Software 45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 46 */ 47 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 48 49 #include <linux/kernel.h> 50 #include <linux/module.h> 51 #include <linux/errno.h> 52 #include <linux/init.h> 53 #include <linux/seq_file.h> 54 #include <linux/slab.h> 55 #include <linux/types.h> 56 #include <linux/pci.h> 57 #include <linux/kdev_t.h> 58 #include <linux/blkdev.h> 59 #include <linux/delay.h> 60 #include <linux/interrupt.h> 61 #include <linux/dma-mapping.h> 62 #include <linux/kthread.h> 63 #include <scsi/scsi_host.h> 64 65 #include "mptbase.h" 66 #include "lsi/mpi_log_fc.h" 67 68 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 69 #define my_NAME "Fusion MPT base driver" 70 #define my_VERSION MPT_LINUX_VERSION_COMMON 71 #define MYNAM "mptbase" 72 73 MODULE_AUTHOR(MODULEAUTHOR); 74 MODULE_DESCRIPTION(my_NAME); 75 MODULE_LICENSE("GPL"); 76 MODULE_VERSION(my_VERSION); 77 78 /* 79 * cmd line parameters 80 */ 81 82 static int mpt_msi_enable_spi; 83 module_param(mpt_msi_enable_spi, int, 0); 84 MODULE_PARM_DESC(mpt_msi_enable_spi, 85 " Enable MSI Support for SPI controllers (default=0)"); 86 87 static int mpt_msi_enable_fc; 88 module_param(mpt_msi_enable_fc, int, 0); 89 MODULE_PARM_DESC(mpt_msi_enable_fc, 90 " Enable MSI Support for FC controllers (default=0)"); 91 92 static int mpt_msi_enable_sas; 93 module_param(mpt_msi_enable_sas, int, 0); 94 MODULE_PARM_DESC(mpt_msi_enable_sas, 95 " Enable MSI Support for SAS controllers (default=0)"); 96 97 static int mpt_channel_mapping; 98 module_param(mpt_channel_mapping, int, 0); 99 MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)"); 100 101 static int mpt_debug_level; 102 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp); 103 module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int, 104 &mpt_debug_level, 0600); 105 MODULE_PARM_DESC(mpt_debug_level, 106 " debug level - refer to mptdebug.h - (default=0)"); 107 108 int mpt_fwfault_debug; 109 EXPORT_SYMBOL(mpt_fwfault_debug); 110 module_param(mpt_fwfault_debug, int, 0600); 111 MODULE_PARM_DESC(mpt_fwfault_debug, 112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)"); 113 114 static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS] 115 [MPT_MAX_CALLBACKNAME_LEN+1]; 116 117 #ifdef MFCNT 118 static int mfcounter = 0; 119 #define PRINT_MF_COUNT 20000 120 #endif 121 122 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 123 /* 124 * Public data... 125 */ 126 127 #define WHOINIT_UNKNOWN 0xAA 128 129 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 130 /* 131 * Private data... 132 */ 133 /* Adapter link list */ 134 LIST_HEAD(ioc_list); 135 /* Callback lookup table */ 136 static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS]; 137 /* Protocol driver class lookup table */ 138 static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS]; 139 /* Event handler lookup table */ 140 static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 141 /* Reset handler lookup table */ 142 static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 143 static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 144 145 #ifdef CONFIG_PROC_FS 146 static struct proc_dir_entry *mpt_proc_root_dir; 147 #endif 148 149 /* 150 * Driver Callback Index's 151 */ 152 static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS; 153 static u8 last_drv_idx; 154 155 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 156 /* 157 * Forward protos... 158 */ 159 static irqreturn_t mpt_interrupt(int irq, void *bus_id); 160 static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, 161 MPT_FRAME_HDR *reply); 162 static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, 163 u32 *req, int replyBytes, u16 *u16reply, int maxwait, 164 int sleepFlag); 165 static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag); 166 static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev); 167 static void mpt_adapter_disable(MPT_ADAPTER *ioc); 168 static void mpt_adapter_dispose(MPT_ADAPTER *ioc); 169 170 static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc); 171 static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag); 172 static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason); 173 static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 174 static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag); 175 static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 176 static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag); 177 static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag); 178 static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 179 static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 180 static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag); 181 static int PrimeIocFifos(MPT_ADAPTER *ioc); 182 static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 183 static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 184 static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 185 static int GetLanConfigPages(MPT_ADAPTER *ioc); 186 static int GetIoUnitPage2(MPT_ADAPTER *ioc); 187 int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode); 188 static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum); 189 static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum); 190 static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc); 191 static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc); 192 static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc); 193 static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, 194 int sleepFlag); 195 static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp); 196 static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag); 197 static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init); 198 199 #ifdef CONFIG_PROC_FS 200 static int mpt_summary_proc_show(struct seq_file *m, void *v); 201 static int mpt_version_proc_show(struct seq_file *m, void *v); 202 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v); 203 #endif 204 static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc); 205 206 static int ProcessEventNotification(MPT_ADAPTER *ioc, 207 EventNotificationReply_t *evReply, int *evHandlers); 208 static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf); 209 static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info); 210 static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info); 211 static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx); 212 static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc); 213 static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc); 214 215 /* module entry point */ 216 static int __init fusion_init (void); 217 static void __exit fusion_exit (void); 218 219 #define CHIPREG_READ32(addr) readl_relaxed(addr) 220 #define CHIPREG_READ32_dmasync(addr) readl(addr) 221 #define CHIPREG_WRITE32(addr,val) writel(val, addr) 222 #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr) 223 #define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr) 224 225 static void 226 pci_disable_io_access(struct pci_dev *pdev) 227 { 228 u16 command_reg; 229 230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 231 command_reg &= ~1; 232 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 233 } 234 235 static void 236 pci_enable_io_access(struct pci_dev *pdev) 237 { 238 u16 command_reg; 239 240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 241 command_reg |= 1; 242 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 243 } 244 245 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp) 246 { 247 int ret = param_set_int(val, kp); 248 MPT_ADAPTER *ioc; 249 250 if (ret) 251 return ret; 252 253 list_for_each_entry(ioc, &ioc_list, list) 254 ioc->debug_level = mpt_debug_level; 255 return 0; 256 } 257 258 /** 259 * mpt_get_cb_idx - obtain cb_idx for registered driver 260 * @dclass: class driver enum 261 * 262 * Returns cb_idx, or zero means it wasn't found 263 **/ 264 static u8 265 mpt_get_cb_idx(MPT_DRIVER_CLASS dclass) 266 { 267 u8 cb_idx; 268 269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) 270 if (MptDriverClass[cb_idx] == dclass) 271 return cb_idx; 272 return 0; 273 } 274 275 /** 276 * mpt_is_discovery_complete - determine if discovery has completed 277 * @ioc: per adatper instance 278 * 279 * Returns 1 when discovery completed, else zero. 280 */ 281 static int 282 mpt_is_discovery_complete(MPT_ADAPTER *ioc) 283 { 284 ConfigExtendedPageHeader_t hdr; 285 CONFIGPARMS cfg; 286 SasIOUnitPage0_t *buffer; 287 dma_addr_t dma_handle; 288 int rc = 0; 289 290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t)); 291 memset(&cfg, 0, sizeof(CONFIGPARMS)); 292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION; 293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; 295 cfg.cfghdr.ehdr = &hdr; 296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 297 298 if ((mpt_config(ioc, &cfg))) 299 goto out; 300 if (!hdr.ExtPageLength) 301 goto out; 302 303 buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 304 &dma_handle); 305 if (!buffer) 306 goto out; 307 308 cfg.physAddr = dma_handle; 309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 310 311 if ((mpt_config(ioc, &cfg))) 312 goto out_free_consistent; 313 314 if (!(buffer->PhyData[0].PortFlags & 315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS)) 316 rc = 1; 317 318 out_free_consistent: 319 dma_free_coherent(&ioc->pcidev->dev, hdr.ExtPageLength * 4, buffer, 320 dma_handle); 321 out: 322 return rc; 323 } 324 325 326 /** 327 * mpt_remove_dead_ioc_func - kthread context to remove dead ioc 328 * @arg: input argument, used to derive ioc 329 * 330 * Return 0 if controller is removed from pci subsystem. 331 * Return -1 for other case. 332 */ 333 static int mpt_remove_dead_ioc_func(void *arg) 334 { 335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; 336 struct pci_dev *pdev; 337 338 if (!ioc) 339 return -1; 340 341 pdev = ioc->pcidev; 342 if (!pdev) 343 return -1; 344 345 pci_stop_and_remove_bus_device_locked(pdev); 346 return 0; 347 } 348 349 350 351 /** 352 * mpt_fault_reset_work - work performed on workq after ioc fault 353 * @work: input argument, used to derive ioc 354 * 355 **/ 356 static void 357 mpt_fault_reset_work(struct work_struct *work) 358 { 359 MPT_ADAPTER *ioc = 360 container_of(work, MPT_ADAPTER, fault_reset_work.work); 361 u32 ioc_raw_state; 362 int rc; 363 unsigned long flags; 364 MPT_SCSI_HOST *hd; 365 struct task_struct *p; 366 367 if (ioc->ioc_reset_in_progress || !ioc->active) 368 goto out; 369 370 371 ioc_raw_state = mpt_GetIocState(ioc, 0); 372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) { 373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n", 374 ioc->name, __func__); 375 376 /* 377 * Call mptscsih_flush_pending_cmds callback so that we 378 * flush all pending commands back to OS. 379 * This call is required to aovid deadlock at block layer. 380 * Dead IOC will fail to do diag reset,and this call is safe 381 * since dead ioc will never return any command back from HW. 382 */ 383 hd = shost_priv(ioc->sh); 384 ioc->schedule_dead_ioc_flush_running_cmds(hd); 385 386 /*Remove the Dead Host */ 387 p = kthread_run(mpt_remove_dead_ioc_func, ioc, 388 "mpt_dead_ioc_%d", ioc->id); 389 if (IS_ERR(p)) { 390 printk(MYIOC_s_ERR_FMT 391 "%s: Running mpt_dead_ioc thread failed !\n", 392 ioc->name, __func__); 393 } else { 394 printk(MYIOC_s_WARN_FMT 395 "%s: Running mpt_dead_ioc thread success !\n", 396 ioc->name, __func__); 397 } 398 return; /* don't rearm timer */ 399 } 400 401 if ((ioc_raw_state & MPI_IOC_STATE_MASK) 402 == MPI_IOC_STATE_FAULT) { 403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n", 404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n", 406 ioc->name, __func__); 407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP); 408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name, 409 __func__, (rc == 0) ? "success" : "failed"); 410 ioc_raw_state = mpt_GetIocState(ioc, 0); 411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) 412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after " 413 "reset (%04xh)\n", ioc->name, ioc_raw_state & 414 MPI_DOORBELL_DATA_MASK); 415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) { 416 if ((mpt_is_discovery_complete(ioc))) { 417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing " 418 "discovery_quiesce_io flag\n", ioc->name)); 419 ioc->sas_discovery_quiesce_io = 0; 420 } 421 } 422 423 out: 424 /* 425 * Take turns polling alternate controller 426 */ 427 if (ioc->alt_ioc) 428 ioc = ioc->alt_ioc; 429 430 /* rearm the timer */ 431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 432 if (ioc->reset_work_q) 433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 434 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 436 } 437 438 439 /* 440 * Process turbo (context) reply... 441 */ 442 static void 443 mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa) 444 { 445 MPT_FRAME_HDR *mf = NULL; 446 MPT_FRAME_HDR *mr = NULL; 447 u16 req_idx = 0; 448 u8 cb_idx; 449 450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n", 451 ioc->name, pa)); 452 453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) { 454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT: 455 req_idx = pa & 0x0000FFFF; 456 cb_idx = (pa & 0x00FF0000) >> 16; 457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 458 break; 459 case MPI_CONTEXT_REPLY_TYPE_LAN: 460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER); 461 /* 462 * Blind set of mf to NULL here was fatal 463 * after lan_reply says "freeme" 464 * Fix sort of combined with an optimization here; 465 * added explicit check for case where lan_reply 466 * was just returning 1 and doing nothing else. 467 * For this case skip the callback, but set up 468 * proper mf value first here:-) 469 */ 470 if ((pa & 0x58000000) == 0x58000000) { 471 req_idx = pa & 0x0000FFFF; 472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 473 mpt_free_msg_frame(ioc, mf); 474 mb(); 475 return; 476 } 477 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 478 break; 479 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET: 480 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER); 481 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 482 break; 483 default: 484 cb_idx = 0; 485 BUG(); 486 } 487 488 /* Check for (valid) IO callback! */ 489 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 490 MptCallbacks[cb_idx] == NULL) { 491 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 492 __func__, ioc->name, cb_idx); 493 goto out; 494 } 495 496 if (MptCallbacks[cb_idx](ioc, mf, mr)) 497 mpt_free_msg_frame(ioc, mf); 498 out: 499 mb(); 500 } 501 502 static void 503 mpt_reply(MPT_ADAPTER *ioc, u32 pa) 504 { 505 MPT_FRAME_HDR *mf; 506 MPT_FRAME_HDR *mr; 507 u16 req_idx; 508 u8 cb_idx; 509 int freeme; 510 511 u32 reply_dma_low; 512 u16 ioc_stat; 513 514 /* non-TURBO reply! Hmmm, something may be up... 515 * Newest turbo reply mechanism; get address 516 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)! 517 */ 518 519 /* Map DMA address of reply header to cpu address. 520 * pa is 32 bits - but the dma address may be 32 or 64 bits 521 * get offset based only only the low addresses 522 */ 523 524 reply_dma_low = (pa <<= 1); 525 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames + 526 (reply_dma_low - ioc->reply_frames_low_dma)); 527 528 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx); 529 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx; 530 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 531 532 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n", 533 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function)); 534 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr); 535 536 /* Check/log IOC log info 537 */ 538 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus); 539 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 540 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo); 541 if (ioc->bus_type == FC) 542 mpt_fc_log_info(ioc, log_info); 543 else if (ioc->bus_type == SPI) 544 mpt_spi_log_info(ioc, log_info); 545 else if (ioc->bus_type == SAS) 546 mpt_sas_log_info(ioc, log_info, cb_idx); 547 } 548 549 if (ioc_stat & MPI_IOCSTATUS_MASK) 550 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf); 551 552 /* Check for (valid) IO callback! */ 553 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 554 MptCallbacks[cb_idx] == NULL) { 555 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 556 __func__, ioc->name, cb_idx); 557 freeme = 0; 558 goto out; 559 } 560 561 freeme = MptCallbacks[cb_idx](ioc, mf, mr); 562 563 out: 564 /* Flush (non-TURBO) reply with a WRITE! */ 565 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa); 566 567 if (freeme) 568 mpt_free_msg_frame(ioc, mf); 569 mb(); 570 } 571 572 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 573 /** 574 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler. 575 * @irq: irq number (not used) 576 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 577 * 578 * This routine is registered via the request_irq() kernel API call, 579 * and handles all interrupts generated from a specific MPT adapter 580 * (also referred to as a IO Controller or IOC). 581 * This routine must clear the interrupt from the adapter and does 582 * so by reading the reply FIFO. Multiple replies may be processed 583 * per single call to this routine. 584 * 585 * This routine handles register-level access of the adapter but 586 * dispatches (calls) a protocol-specific callback routine to handle 587 * the protocol-specific details of the MPT request completion. 588 */ 589 static irqreturn_t 590 mpt_interrupt(int irq, void *bus_id) 591 { 592 MPT_ADAPTER *ioc = bus_id; 593 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 594 595 if (pa == 0xFFFFFFFF) 596 return IRQ_NONE; 597 598 /* 599 * Drain the reply FIFO! 600 */ 601 do { 602 if (pa & MPI_ADDRESS_REPLY_A_BIT) 603 mpt_reply(ioc, pa); 604 else 605 mpt_turbo_reply(ioc, pa); 606 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 607 } while (pa != 0xFFFFFFFF); 608 609 return IRQ_HANDLED; 610 } 611 612 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 613 /** 614 * mptbase_reply - MPT base driver's callback routine 615 * @ioc: Pointer to MPT_ADAPTER structure 616 * @req: Pointer to original MPT request frame 617 * @reply: Pointer to MPT reply frame (NULL if TurboReply) 618 * 619 * MPT base driver's callback routine; all base driver 620 * "internal" request/reply processing is routed here. 621 * Currently used for EventNotification and EventAck handling. 622 * 623 * Returns 1 indicating original alloc'd request frame ptr 624 * should be freed, or 0 if it shouldn't. 625 */ 626 static int 627 mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply) 628 { 629 EventNotificationReply_t *pEventReply; 630 u8 event; 631 int evHandlers; 632 int freereq = 1; 633 634 switch (reply->u.hdr.Function) { 635 case MPI_FUNCTION_EVENT_NOTIFICATION: 636 pEventReply = (EventNotificationReply_t *)reply; 637 evHandlers = 0; 638 ProcessEventNotification(ioc, pEventReply, &evHandlers); 639 event = le32_to_cpu(pEventReply->Event) & 0xFF; 640 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) 641 freereq = 0; 642 if (event != MPI_EVENT_EVENT_CHANGE) 643 break; 644 fallthrough; 645 case MPI_FUNCTION_CONFIG: 646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL: 647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; 648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID; 649 memcpy(ioc->mptbase_cmds.reply, reply, 650 min(MPT_DEFAULT_FRAME_SIZE, 651 4 * reply->u.reply.MsgLength)); 652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING; 654 complete(&ioc->mptbase_cmds.done); 655 } else 656 freereq = 0; 657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF) 658 freereq = 1; 659 break; 660 case MPI_FUNCTION_EVENT_ACK: 661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 662 "EventAck reply received\n", ioc->name)); 663 break; 664 default: 665 printk(MYIOC_s_ERR_FMT 666 "Unexpected msg function (=%02Xh) reply received!\n", 667 ioc->name, reply->u.hdr.Function); 668 break; 669 } 670 671 /* 672 * Conditionally tell caller to free the original 673 * EventNotification/EventAck/unexpected request frame! 674 */ 675 return freereq; 676 } 677 678 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 679 /** 680 * mpt_register - Register protocol-specific main callback handler. 681 * @cbfunc: callback function pointer 682 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value) 683 * @func_name: call function's name 684 * 685 * This routine is called by a protocol-specific driver (SCSI host, 686 * LAN, SCSI target) to register its reply callback routine. Each 687 * protocol-specific driver must do this before it will be able to 688 * use any IOC resources, such as obtaining request frames. 689 * 690 * NOTES: The SCSI protocol driver currently calls this routine thrice 691 * in order to register separate callbacks; one for "normal" SCSI IO; 692 * one for MptScsiTaskMgmt requests; one for Scan/DV requests. 693 * 694 * Returns u8 valued "handle" in the range (and S.O.D. order) 695 * {N,...,7,6,5,...,1} if successful. 696 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be 697 * considered an error by the caller. 698 */ 699 u8 700 mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name) 701 { 702 u8 cb_idx; 703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS; 704 705 /* 706 * Search for empty callback slot in this order: {N,...,7,6,5,...,1} 707 * (slot/handle 0 is reserved!) 708 */ 709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 710 if (MptCallbacks[cb_idx] == NULL) { 711 MptCallbacks[cb_idx] = cbfunc; 712 MptDriverClass[cb_idx] = dclass; 713 MptEvHandlers[cb_idx] = NULL; 714 last_drv_idx = cb_idx; 715 strlcpy(MptCallbacksName[cb_idx], func_name, 716 MPT_MAX_CALLBACKNAME_LEN+1); 717 break; 718 } 719 } 720 721 return last_drv_idx; 722 } 723 724 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 725 /** 726 * mpt_deregister - Deregister a protocol drivers resources. 727 * @cb_idx: previously registered callback handle 728 * 729 * Each protocol-specific driver should call this routine when its 730 * module is unloaded. 731 */ 732 void 733 mpt_deregister(u8 cb_idx) 734 { 735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) { 736 MptCallbacks[cb_idx] = NULL; 737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 738 MptEvHandlers[cb_idx] = NULL; 739 740 last_drv_idx++; 741 } 742 } 743 744 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 745 /** 746 * mpt_event_register - Register protocol-specific event callback handler. 747 * @cb_idx: previously registered (via mpt_register) callback handle 748 * @ev_cbfunc: callback function 749 * 750 * This routine can be called by one or more protocol-specific drivers 751 * if/when they choose to be notified of MPT events. 752 * 753 * Returns 0 for success. 754 */ 755 int 756 mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc) 757 { 758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 759 return -1; 760 761 MptEvHandlers[cb_idx] = ev_cbfunc; 762 return 0; 763 } 764 765 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 766 /** 767 * mpt_event_deregister - Deregister protocol-specific event callback handler 768 * @cb_idx: previously registered callback handle 769 * 770 * Each protocol-specific driver should call this routine 771 * when it does not (or can no longer) handle events, 772 * or when its module is unloaded. 773 */ 774 void 775 mpt_event_deregister(u8 cb_idx) 776 { 777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 778 return; 779 780 MptEvHandlers[cb_idx] = NULL; 781 } 782 783 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 784 /** 785 * mpt_reset_register - Register protocol-specific IOC reset handler. 786 * @cb_idx: previously registered (via mpt_register) callback handle 787 * @reset_func: reset function 788 * 789 * This routine can be called by one or more protocol-specific drivers 790 * if/when they choose to be notified of IOC resets. 791 * 792 * Returns 0 for success. 793 */ 794 int 795 mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func) 796 { 797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 798 return -1; 799 800 MptResetHandlers[cb_idx] = reset_func; 801 return 0; 802 } 803 804 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 805 /** 806 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler. 807 * @cb_idx: previously registered callback handle 808 * 809 * Each protocol-specific driver should call this routine 810 * when it does not (or can no longer) handle IOC reset handling, 811 * or when its module is unloaded. 812 */ 813 void 814 mpt_reset_deregister(u8 cb_idx) 815 { 816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 817 return; 818 819 MptResetHandlers[cb_idx] = NULL; 820 } 821 822 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 823 /** 824 * mpt_device_driver_register - Register device driver hooks 825 * @dd_cbfunc: driver callbacks struct 826 * @cb_idx: MPT protocol driver index 827 */ 828 int 829 mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx) 830 { 831 MPT_ADAPTER *ioc; 832 833 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 834 return -EINVAL; 835 836 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc; 837 838 /* call per pci device probe entry point */ 839 list_for_each_entry(ioc, &ioc_list, list) { 840 if (dd_cbfunc->probe) 841 dd_cbfunc->probe(ioc->pcidev); 842 } 843 844 return 0; 845 } 846 847 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 848 /** 849 * mpt_device_driver_deregister - DeRegister device driver hooks 850 * @cb_idx: MPT protocol driver index 851 */ 852 void 853 mpt_device_driver_deregister(u8 cb_idx) 854 { 855 struct mpt_pci_driver *dd_cbfunc; 856 MPT_ADAPTER *ioc; 857 858 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 859 return; 860 861 dd_cbfunc = MptDeviceDriverHandlers[cb_idx]; 862 863 list_for_each_entry(ioc, &ioc_list, list) { 864 if (dd_cbfunc->remove) 865 dd_cbfunc->remove(ioc->pcidev); 866 } 867 868 MptDeviceDriverHandlers[cb_idx] = NULL; 869 } 870 871 872 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 873 /** 874 * mpt_get_msg_frame - Obtain an MPT request frame from the pool 875 * @cb_idx: Handle of registered MPT protocol driver 876 * @ioc: Pointer to MPT adapter structure 877 * 878 * Obtain an MPT request frame from the pool (of 1024) that are 879 * allocated per MPT adapter. 880 * 881 * Returns pointer to a MPT request frame or %NULL if none are available 882 * or IOC is not active. 883 */ 884 MPT_FRAME_HDR* 885 mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc) 886 { 887 MPT_FRAME_HDR *mf; 888 unsigned long flags; 889 u16 req_idx; /* Request index */ 890 891 /* validate handle and ioc identifier */ 892 893 #ifdef MFCNT 894 if (!ioc->active) 895 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame " 896 "returning NULL!\n", ioc->name); 897 #endif 898 899 /* If interrupts are not attached, do not return a request frame */ 900 if (!ioc->active) 901 return NULL; 902 903 spin_lock_irqsave(&ioc->FreeQlock, flags); 904 if (!list_empty(&ioc->FreeQ)) { 905 int req_offset; 906 907 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR, 908 u.frame.linkage.list); 909 list_del(&mf->u.frame.linkage.list); 910 mf->u.frame.linkage.arg1 = 0; 911 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 912 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 913 /* u16! */ 914 req_idx = req_offset / ioc->req_sz; 915 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 916 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 917 /* Default, will be changed if necessary in SG generation */ 918 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame; 919 #ifdef MFCNT 920 ioc->mfcnt++; 921 #endif 922 } 923 else 924 mf = NULL; 925 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 926 927 #ifdef MFCNT 928 if (mf == NULL) 929 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! " 930 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt, 931 ioc->req_depth); 932 mfcounter++; 933 if (mfcounter == PRINT_MF_COUNT) 934 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name, 935 ioc->mfcnt, ioc->req_depth); 936 #endif 937 938 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n", 939 ioc->name, cb_idx, ioc->id, mf)); 940 return mf; 941 } 942 943 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 944 /** 945 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC 946 * @cb_idx: Handle of registered MPT protocol driver 947 * @ioc: Pointer to MPT adapter structure 948 * @mf: Pointer to MPT request frame 949 * 950 * This routine posts an MPT request frame to the request post FIFO of a 951 * specific MPT adapter. 952 */ 953 void 954 mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 955 { 956 u32 mf_dma_addr; 957 int req_offset; 958 u16 req_idx; /* Request index */ 959 960 /* ensure values are reset properly! */ 961 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 962 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 963 /* u16! */ 964 req_idx = req_offset / ioc->req_sz; 965 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 966 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 967 968 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 969 970 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx]; 971 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d " 972 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx, 973 ioc->RequestNB[req_idx])); 974 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr); 975 } 976 977 /** 978 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame 979 * @cb_idx: Handle of registered MPT protocol driver 980 * @ioc: Pointer to MPT adapter structure 981 * @mf: Pointer to MPT request frame 982 * 983 * Send a protocol-specific MPT request frame to an IOC using 984 * hi-priority request queue. 985 * 986 * This routine posts an MPT request frame to the request post FIFO of a 987 * specific MPT adapter. 988 **/ 989 void 990 mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 991 { 992 u32 mf_dma_addr; 993 int req_offset; 994 u16 req_idx; /* Request index */ 995 996 /* ensure values are reset properly! */ 997 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 998 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 999 req_idx = req_offset / ioc->req_sz; 1000 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 1001 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 1002 1003 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 1004 1005 mf_dma_addr = (ioc->req_frames_low_dma + req_offset); 1006 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n", 1007 ioc->name, mf_dma_addr, req_idx)); 1008 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr); 1009 } 1010 1011 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1012 /** 1013 * mpt_free_msg_frame - Place MPT request frame back on FreeQ. 1014 * @ioc: Pointer to MPT adapter structure 1015 * @mf: Pointer to MPT request frame 1016 * 1017 * This routine places a MPT request frame back on the MPT adapter's 1018 * FreeQ. 1019 */ 1020 void 1021 mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 1022 { 1023 unsigned long flags; 1024 1025 /* Put Request back on FreeQ! */ 1026 spin_lock_irqsave(&ioc->FreeQlock, flags); 1027 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf) 1028 goto out; 1029 /* signature to know if this mf is freed */ 1030 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf); 1031 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ); 1032 #ifdef MFCNT 1033 ioc->mfcnt--; 1034 #endif 1035 out: 1036 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 1037 } 1038 1039 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1040 /** 1041 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr. 1042 * @pAddr: virtual address for SGE 1043 * @flagslength: SGE flags and data transfer length 1044 * @dma_addr: Physical address 1045 * 1046 * This routine places a MPT request frame back on the MPT adapter's 1047 * FreeQ. 1048 */ 1049 static void 1050 mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1051 { 1052 SGESimple32_t *pSge = (SGESimple32_t *) pAddr; 1053 pSge->FlagsLength = cpu_to_le32(flagslength); 1054 pSge->Address = cpu_to_le32(dma_addr); 1055 } 1056 1057 /** 1058 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr. 1059 * @pAddr: virtual address for SGE 1060 * @flagslength: SGE flags and data transfer length 1061 * @dma_addr: Physical address 1062 * 1063 * This routine places a MPT request frame back on the MPT adapter's 1064 * FreeQ. 1065 **/ 1066 static void 1067 mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1068 { 1069 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1070 pSge->Address.Low = cpu_to_le32 1071 (lower_32_bits(dma_addr)); 1072 pSge->Address.High = cpu_to_le32 1073 (upper_32_bits(dma_addr)); 1074 pSge->FlagsLength = cpu_to_le32 1075 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1076 } 1077 1078 /** 1079 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround). 1080 * @pAddr: virtual address for SGE 1081 * @flagslength: SGE flags and data transfer length 1082 * @dma_addr: Physical address 1083 * 1084 * This routine places a MPT request frame back on the MPT adapter's 1085 * FreeQ. 1086 **/ 1087 static void 1088 mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1089 { 1090 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1091 u32 tmp; 1092 1093 pSge->Address.Low = cpu_to_le32 1094 (lower_32_bits(dma_addr)); 1095 tmp = (u32)(upper_32_bits(dma_addr)); 1096 1097 /* 1098 * 1078 errata workaround for the 36GB limitation 1099 */ 1100 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) { 1101 flagslength |= 1102 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS); 1103 tmp |= (1<<31); 1104 if (mpt_debug_level & MPT_DEBUG_36GB_MEM) 1105 printk(KERN_DEBUG "1078 P0M2 addressing for " 1106 "addr = 0x%llx len = %d\n", 1107 (unsigned long long)dma_addr, 1108 MPI_SGE_LENGTH(flagslength)); 1109 } 1110 1111 pSge->Address.High = cpu_to_le32(tmp); 1112 pSge->FlagsLength = cpu_to_le32( 1113 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1114 } 1115 1116 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1117 /** 1118 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr. 1119 * @pAddr: virtual address for SGE 1120 * @next: nextChainOffset value (u32's) 1121 * @length: length of next SGL segment 1122 * @dma_addr: Physical address 1123 * 1124 */ 1125 static void 1126 mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1127 { 1128 SGEChain32_t *pChain = (SGEChain32_t *) pAddr; 1129 1130 pChain->Length = cpu_to_le16(length); 1131 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT; 1132 pChain->NextChainOffset = next; 1133 pChain->Address = cpu_to_le32(dma_addr); 1134 } 1135 1136 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1137 /** 1138 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr. 1139 * @pAddr: virtual address for SGE 1140 * @next: nextChainOffset value (u32's) 1141 * @length: length of next SGL segment 1142 * @dma_addr: Physical address 1143 * 1144 */ 1145 static void 1146 mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1147 { 1148 SGEChain64_t *pChain = (SGEChain64_t *) pAddr; 1149 u32 tmp = dma_addr & 0xFFFFFFFF; 1150 1151 pChain->Length = cpu_to_le16(length); 1152 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT | 1153 MPI_SGE_FLAGS_64_BIT_ADDRESSING); 1154 1155 pChain->NextChainOffset = next; 1156 1157 pChain->Address.Low = cpu_to_le32(tmp); 1158 tmp = (u32)(upper_32_bits(dma_addr)); 1159 pChain->Address.High = cpu_to_le32(tmp); 1160 } 1161 1162 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1163 /** 1164 * mpt_send_handshake_request - Send MPT request via doorbell handshake method. 1165 * @cb_idx: Handle of registered MPT protocol driver 1166 * @ioc: Pointer to MPT adapter structure 1167 * @reqBytes: Size of the request in bytes 1168 * @req: Pointer to MPT request frame 1169 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 1170 * 1171 * This routine is used exclusively to send MptScsiTaskMgmt 1172 * requests since they are required to be sent via doorbell handshake. 1173 * 1174 * NOTE: It is the callers responsibility to byte-swap fields in the 1175 * request which are greater than 1 byte in size. 1176 * 1177 * Returns 0 for success, non-zero for failure. 1178 */ 1179 int 1180 mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag) 1181 { 1182 int r = 0; 1183 u8 *req_as_bytes; 1184 int ii; 1185 1186 /* State is known to be good upon entering 1187 * this function so issue the bus reset 1188 * request. 1189 */ 1190 1191 /* 1192 * Emulate what mpt_put_msg_frame() does /wrt to sanity 1193 * setting cb_idx/req_idx. But ONLY if this request 1194 * is in proper (pre-alloc'd) request buffer range... 1195 */ 1196 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req); 1197 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) { 1198 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req; 1199 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii); 1200 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 1201 } 1202 1203 /* Make sure there are no doorbells */ 1204 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1205 1206 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1207 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 1208 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 1209 1210 /* Wait for IOC doorbell int */ 1211 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) { 1212 return ii; 1213 } 1214 1215 /* Read doorbell and check for active bit */ 1216 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 1217 return -5; 1218 1219 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n", 1220 ioc->name, ii)); 1221 1222 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1223 1224 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1225 return -2; 1226 } 1227 1228 /* Send request via doorbell handshake */ 1229 req_as_bytes = (u8 *) req; 1230 for (ii = 0; ii < reqBytes/4; ii++) { 1231 u32 word; 1232 1233 word = ((req_as_bytes[(ii*4) + 0] << 0) | 1234 (req_as_bytes[(ii*4) + 1] << 8) | 1235 (req_as_bytes[(ii*4) + 2] << 16) | 1236 (req_as_bytes[(ii*4) + 3] << 24)); 1237 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 1238 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1239 r = -3; 1240 break; 1241 } 1242 } 1243 1244 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0) 1245 r = 0; 1246 else 1247 r = -4; 1248 1249 /* Make sure there are no doorbells */ 1250 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1251 1252 return r; 1253 } 1254 1255 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1256 /** 1257 * mpt_host_page_access_control - control the IOC's Host Page Buffer access 1258 * @ioc: Pointer to MPT adapter structure 1259 * @access_control_value: define bits below 1260 * @sleepFlag: Specifies whether the process can sleep 1261 * 1262 * Provides mechanism for the host driver to control the IOC's 1263 * Host Page Buffer access. 1264 * 1265 * Access Control Value - bits[15:12] 1266 * 0h Reserved 1267 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS } 1268 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS } 1269 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER } 1270 * 1271 * Returns 0 for success, non-zero for failure. 1272 */ 1273 1274 static int 1275 mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag) 1276 { 1277 /* return if in use */ 1278 if (CHIPREG_READ32(&ioc->chip->Doorbell) 1279 & MPI_DOORBELL_ACTIVE) 1280 return -1; 1281 1282 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1283 1284 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1285 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL 1286 <<MPI_DOORBELL_FUNCTION_SHIFT) | 1287 (access_control_value<<12))); 1288 1289 /* Wait for IOC to clear Doorbell Status bit */ 1290 if (WaitForDoorbellAck(ioc, 5, sleepFlag) < 0) 1291 return -2; 1292 else 1293 return 0; 1294 } 1295 1296 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1297 /** 1298 * mpt_host_page_alloc - allocate system memory for the fw 1299 * @ioc: Pointer to pointer to IOC adapter 1300 * @ioc_init: Pointer to ioc init config page 1301 * 1302 * If we already allocated memory in past, then resend the same pointer. 1303 * Returns 0 for success, non-zero for failure. 1304 */ 1305 static int 1306 mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init) 1307 { 1308 char *psge; 1309 int flags_length; 1310 u32 host_page_buffer_sz=0; 1311 1312 if(!ioc->HostPageBuffer) { 1313 1314 host_page_buffer_sz = 1315 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF; 1316 1317 if(!host_page_buffer_sz) 1318 return 0; /* fw doesn't need any host buffers */ 1319 1320 /* spin till we get enough memory */ 1321 while (host_page_buffer_sz > 0) { 1322 ioc->HostPageBuffer = 1323 dma_alloc_coherent(&ioc->pcidev->dev, 1324 host_page_buffer_sz, 1325 &ioc->HostPageBuffer_dma, 1326 GFP_KERNEL); 1327 if (ioc->HostPageBuffer) { 1328 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 1329 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n", 1330 ioc->name, ioc->HostPageBuffer, 1331 (u32)ioc->HostPageBuffer_dma, 1332 host_page_buffer_sz)); 1333 ioc->alloc_total += host_page_buffer_sz; 1334 ioc->HostPageBuffer_sz = host_page_buffer_sz; 1335 break; 1336 } 1337 1338 host_page_buffer_sz -= (4*1024); 1339 } 1340 } 1341 1342 if(!ioc->HostPageBuffer) { 1343 printk(MYIOC_s_ERR_FMT 1344 "Failed to alloc memory for host_page_buffer!\n", 1345 ioc->name); 1346 return -999; 1347 } 1348 1349 psge = (char *)&ioc_init->HostPageBufferSGE; 1350 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT | 1351 MPI_SGE_FLAGS_SYSTEM_ADDRESS | 1352 MPI_SGE_FLAGS_HOST_TO_IOC | 1353 MPI_SGE_FLAGS_END_OF_BUFFER; 1354 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT; 1355 flags_length |= ioc->HostPageBuffer_sz; 1356 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma); 1357 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE; 1358 1359 return 0; 1360 } 1361 1362 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1363 /** 1364 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure. 1365 * @iocid: IOC unique identifier (integer) 1366 * @iocpp: Pointer to pointer to IOC adapter 1367 * 1368 * Given a unique IOC identifier, set pointer to the associated MPT 1369 * adapter structure. 1370 * 1371 * Returns iocid and sets iocpp if iocid is found. 1372 * Returns -1 if iocid is not found. 1373 */ 1374 int 1375 mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp) 1376 { 1377 MPT_ADAPTER *ioc; 1378 1379 list_for_each_entry(ioc,&ioc_list,list) { 1380 if (ioc->id == iocid) { 1381 *iocpp =ioc; 1382 return iocid; 1383 } 1384 } 1385 1386 *iocpp = NULL; 1387 return -1; 1388 } 1389 1390 /** 1391 * mpt_get_product_name - returns product string 1392 * @vendor: pci vendor id 1393 * @device: pci device id 1394 * @revision: pci revision id 1395 * 1396 * Returns product string displayed when driver loads, 1397 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product 1398 * 1399 **/ 1400 static const char* 1401 mpt_get_product_name(u16 vendor, u16 device, u8 revision) 1402 { 1403 char *product_str = NULL; 1404 1405 if (vendor == PCI_VENDOR_ID_BROCADE) { 1406 switch (device) 1407 { 1408 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1409 switch (revision) 1410 { 1411 case 0x00: 1412 product_str = "BRE040 A0"; 1413 break; 1414 case 0x01: 1415 product_str = "BRE040 A1"; 1416 break; 1417 default: 1418 product_str = "BRE040"; 1419 break; 1420 } 1421 break; 1422 } 1423 goto out; 1424 } 1425 1426 switch (device) 1427 { 1428 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1429 product_str = "LSIFC909 B1"; 1430 break; 1431 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1432 product_str = "LSIFC919 B0"; 1433 break; 1434 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1435 product_str = "LSIFC929 B0"; 1436 break; 1437 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1438 if (revision < 0x80) 1439 product_str = "LSIFC919X A0"; 1440 else 1441 product_str = "LSIFC919XL A1"; 1442 break; 1443 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1444 if (revision < 0x80) 1445 product_str = "LSIFC929X A0"; 1446 else 1447 product_str = "LSIFC929XL A1"; 1448 break; 1449 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1450 product_str = "LSIFC939X A1"; 1451 break; 1452 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1453 product_str = "LSIFC949X A1"; 1454 break; 1455 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1456 switch (revision) 1457 { 1458 case 0x00: 1459 product_str = "LSIFC949E A0"; 1460 break; 1461 case 0x01: 1462 product_str = "LSIFC949E A1"; 1463 break; 1464 default: 1465 product_str = "LSIFC949E"; 1466 break; 1467 } 1468 break; 1469 case MPI_MANUFACTPAGE_DEVID_53C1030: 1470 switch (revision) 1471 { 1472 case 0x00: 1473 product_str = "LSI53C1030 A0"; 1474 break; 1475 case 0x01: 1476 product_str = "LSI53C1030 B0"; 1477 break; 1478 case 0x03: 1479 product_str = "LSI53C1030 B1"; 1480 break; 1481 case 0x07: 1482 product_str = "LSI53C1030 B2"; 1483 break; 1484 case 0x08: 1485 product_str = "LSI53C1030 C0"; 1486 break; 1487 case 0x80: 1488 product_str = "LSI53C1030T A0"; 1489 break; 1490 case 0x83: 1491 product_str = "LSI53C1030T A2"; 1492 break; 1493 case 0x87: 1494 product_str = "LSI53C1030T A3"; 1495 break; 1496 case 0xc1: 1497 product_str = "LSI53C1020A A1"; 1498 break; 1499 default: 1500 product_str = "LSI53C1030"; 1501 break; 1502 } 1503 break; 1504 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1505 switch (revision) 1506 { 1507 case 0x03: 1508 product_str = "LSI53C1035 A2"; 1509 break; 1510 case 0x04: 1511 product_str = "LSI53C1035 B0"; 1512 break; 1513 default: 1514 product_str = "LSI53C1035"; 1515 break; 1516 } 1517 break; 1518 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1519 switch (revision) 1520 { 1521 case 0x00: 1522 product_str = "LSISAS1064 A1"; 1523 break; 1524 case 0x01: 1525 product_str = "LSISAS1064 A2"; 1526 break; 1527 case 0x02: 1528 product_str = "LSISAS1064 A3"; 1529 break; 1530 case 0x03: 1531 product_str = "LSISAS1064 A4"; 1532 break; 1533 default: 1534 product_str = "LSISAS1064"; 1535 break; 1536 } 1537 break; 1538 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1539 switch (revision) 1540 { 1541 case 0x00: 1542 product_str = "LSISAS1064E A0"; 1543 break; 1544 case 0x01: 1545 product_str = "LSISAS1064E B0"; 1546 break; 1547 case 0x02: 1548 product_str = "LSISAS1064E B1"; 1549 break; 1550 case 0x04: 1551 product_str = "LSISAS1064E B2"; 1552 break; 1553 case 0x08: 1554 product_str = "LSISAS1064E B3"; 1555 break; 1556 default: 1557 product_str = "LSISAS1064E"; 1558 break; 1559 } 1560 break; 1561 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1562 switch (revision) 1563 { 1564 case 0x00: 1565 product_str = "LSISAS1068 A0"; 1566 break; 1567 case 0x01: 1568 product_str = "LSISAS1068 B0"; 1569 break; 1570 case 0x02: 1571 product_str = "LSISAS1068 B1"; 1572 break; 1573 default: 1574 product_str = "LSISAS1068"; 1575 break; 1576 } 1577 break; 1578 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1579 switch (revision) 1580 { 1581 case 0x00: 1582 product_str = "LSISAS1068E A0"; 1583 break; 1584 case 0x01: 1585 product_str = "LSISAS1068E B0"; 1586 break; 1587 case 0x02: 1588 product_str = "LSISAS1068E B1"; 1589 break; 1590 case 0x04: 1591 product_str = "LSISAS1068E B2"; 1592 break; 1593 case 0x08: 1594 product_str = "LSISAS1068E B3"; 1595 break; 1596 default: 1597 product_str = "LSISAS1068E"; 1598 break; 1599 } 1600 break; 1601 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1602 switch (revision) 1603 { 1604 case 0x00: 1605 product_str = "LSISAS1078 A0"; 1606 break; 1607 case 0x01: 1608 product_str = "LSISAS1078 B0"; 1609 break; 1610 case 0x02: 1611 product_str = "LSISAS1078 C0"; 1612 break; 1613 case 0x03: 1614 product_str = "LSISAS1078 C1"; 1615 break; 1616 case 0x04: 1617 product_str = "LSISAS1078 C2"; 1618 break; 1619 default: 1620 product_str = "LSISAS1078"; 1621 break; 1622 } 1623 break; 1624 } 1625 1626 out: 1627 return product_str; 1628 } 1629 1630 /** 1631 * mpt_mapresources - map in memory mapped io 1632 * @ioc: Pointer to pointer to IOC adapter 1633 * 1634 **/ 1635 static int 1636 mpt_mapresources(MPT_ADAPTER *ioc) 1637 { 1638 u8 __iomem *mem; 1639 int ii; 1640 resource_size_t mem_phys; 1641 unsigned long port; 1642 u32 msize; 1643 u32 psize; 1644 int r = -ENODEV; 1645 struct pci_dev *pdev; 1646 1647 pdev = ioc->pcidev; 1648 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 1649 if (pci_enable_device_mem(pdev)) { 1650 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() " 1651 "failed\n", ioc->name); 1652 return r; 1653 } 1654 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) { 1655 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with " 1656 "MEM failed\n", ioc->name); 1657 goto out_pci_disable_device; 1658 } 1659 1660 if (sizeof(dma_addr_t) > 4) { 1661 const uint64_t required_mask = dma_get_required_mask 1662 (&pdev->dev); 1663 if (required_mask > DMA_BIT_MASK(32) 1664 && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) 1665 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 1666 ioc->dma_mask = DMA_BIT_MASK(64); 1667 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1668 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1669 ioc->name)); 1670 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) 1671 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1672 ioc->dma_mask = DMA_BIT_MASK(32); 1673 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1674 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1675 ioc->name)); 1676 } else { 1677 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1678 ioc->name, pci_name(pdev)); 1679 goto out_pci_release_region; 1680 } 1681 } else { 1682 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) 1683 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1684 ioc->dma_mask = DMA_BIT_MASK(32); 1685 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1686 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1687 ioc->name)); 1688 } else { 1689 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1690 ioc->name, pci_name(pdev)); 1691 goto out_pci_release_region; 1692 } 1693 } 1694 1695 mem_phys = msize = 0; 1696 port = psize = 0; 1697 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) { 1698 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) { 1699 if (psize) 1700 continue; 1701 /* Get I/O space! */ 1702 port = pci_resource_start(pdev, ii); 1703 psize = pci_resource_len(pdev, ii); 1704 } else { 1705 if (msize) 1706 continue; 1707 /* Get memmap */ 1708 mem_phys = pci_resource_start(pdev, ii); 1709 msize = pci_resource_len(pdev, ii); 1710 } 1711 } 1712 ioc->mem_size = msize; 1713 1714 mem = NULL; 1715 /* Get logical ptr for PciMem0 space */ 1716 /*mem = ioremap(mem_phys, msize);*/ 1717 mem = ioremap(mem_phys, msize); 1718 if (mem == NULL) { 1719 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter" 1720 " memory!\n", ioc->name); 1721 r = -EINVAL; 1722 goto out_pci_release_region; 1723 } 1724 ioc->memmap = mem; 1725 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n", 1726 ioc->name, mem, (unsigned long long)mem_phys)); 1727 1728 ioc->mem_phys = mem_phys; 1729 ioc->chip = (SYSIF_REGS __iomem *)mem; 1730 1731 /* Save Port IO values in case we need to do downloadboot */ 1732 ioc->pio_mem_phys = port; 1733 ioc->pio_chip = (SYSIF_REGS __iomem *)port; 1734 1735 return 0; 1736 1737 out_pci_release_region: 1738 pci_release_selected_regions(pdev, ioc->bars); 1739 out_pci_disable_device: 1740 pci_disable_device(pdev); 1741 return r; 1742 } 1743 1744 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1745 /** 1746 * mpt_attach - Install a PCI intelligent MPT adapter. 1747 * @pdev: Pointer to pci_dev structure 1748 * @id: PCI device ID information 1749 * 1750 * This routine performs all the steps necessary to bring the IOC of 1751 * a MPT adapter to a OPERATIONAL state. This includes registering 1752 * memory regions, registering the interrupt, and allocating request 1753 * and reply memory pools. 1754 * 1755 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 1756 * MPT adapter. 1757 * 1758 * Returns 0 for success, non-zero for failure. 1759 * 1760 * TODO: Add support for polled controllers 1761 */ 1762 int 1763 mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id) 1764 { 1765 MPT_ADAPTER *ioc; 1766 u8 cb_idx; 1767 int r = -ENODEV; 1768 u8 pcixcmd; 1769 static int mpt_ids = 0; 1770 #ifdef CONFIG_PROC_FS 1771 struct proc_dir_entry *dent; 1772 #endif 1773 1774 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL); 1775 if (ioc == NULL) { 1776 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n"); 1777 return -ENOMEM; 1778 } 1779 1780 ioc->id = mpt_ids++; 1781 sprintf(ioc->name, "ioc%d", ioc->id); 1782 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n")); 1783 1784 /* 1785 * set initial debug level 1786 * (refer to mptdebug.h) 1787 * 1788 */ 1789 ioc->debug_level = mpt_debug_level; 1790 if (mpt_debug_level) 1791 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level); 1792 1793 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name)); 1794 1795 ioc->pcidev = pdev; 1796 if (mpt_mapresources(ioc)) { 1797 goto out_free_ioc; 1798 } 1799 1800 /* 1801 * Setting up proper handlers for scatter gather handling 1802 */ 1803 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 1804 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 1805 ioc->add_sge = &mpt_add_sge_64bit_1078; 1806 else 1807 ioc->add_sge = &mpt_add_sge_64bit; 1808 ioc->add_chain = &mpt_add_chain_64bit; 1809 ioc->sg_addr_size = 8; 1810 } else { 1811 ioc->add_sge = &mpt_add_sge; 1812 ioc->add_chain = &mpt_add_chain; 1813 ioc->sg_addr_size = 4; 1814 } 1815 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 1816 1817 ioc->alloc_total = sizeof(MPT_ADAPTER); 1818 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */ 1819 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 1820 1821 1822 spin_lock_init(&ioc->taskmgmt_lock); 1823 mutex_init(&ioc->internal_cmds.mutex); 1824 init_completion(&ioc->internal_cmds.done); 1825 mutex_init(&ioc->mptbase_cmds.mutex); 1826 init_completion(&ioc->mptbase_cmds.done); 1827 mutex_init(&ioc->taskmgmt_cmds.mutex); 1828 init_completion(&ioc->taskmgmt_cmds.done); 1829 1830 /* Initialize the event logging. 1831 */ 1832 ioc->eventTypes = 0; /* None */ 1833 ioc->eventContext = 0; 1834 ioc->eventLogSize = 0; 1835 ioc->events = NULL; 1836 1837 #ifdef MFCNT 1838 ioc->mfcnt = 0; 1839 #endif 1840 1841 ioc->sh = NULL; 1842 ioc->cached_fw = NULL; 1843 1844 /* Initialize SCSI Config Data structure 1845 */ 1846 memset(&ioc->spi_data, 0, sizeof(SpiCfgData)); 1847 1848 /* Initialize the fc rport list head. 1849 */ 1850 INIT_LIST_HEAD(&ioc->fc_rports); 1851 1852 /* Find lookup slot. */ 1853 INIT_LIST_HEAD(&ioc->list); 1854 1855 1856 /* Initialize workqueue */ 1857 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work); 1858 1859 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN, 1860 "mpt_poll_%d", ioc->id); 1861 ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name, 1862 WQ_MEM_RECLAIM, 0); 1863 if (!ioc->reset_work_q) { 1864 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 1865 ioc->name); 1866 r = -ENOMEM; 1867 goto out_unmap_resources; 1868 } 1869 1870 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n", 1871 ioc->name, &ioc->facts, &ioc->pfacts[0])); 1872 1873 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device, 1874 pdev->revision); 1875 1876 switch (pdev->device) 1877 { 1878 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1879 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1880 ioc->errata_flag_1064 = 1; 1881 fallthrough; 1882 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1883 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1884 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1885 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1886 ioc->bus_type = FC; 1887 break; 1888 1889 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1890 if (pdev->revision < XL_929) { 1891 /* 929X Chip Fix. Set Split transactions level 1892 * for PCIX. Set MOST bits to zero. 1893 */ 1894 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1895 pcixcmd &= 0x8F; 1896 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1897 } else { 1898 /* 929XL Chip Fix. Set MMRBC to 0x08. 1899 */ 1900 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1901 pcixcmd |= 0x08; 1902 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1903 } 1904 ioc->bus_type = FC; 1905 break; 1906 1907 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1908 /* 919X Chip Fix. Set Split transactions level 1909 * for PCIX. Set MOST bits to zero. 1910 */ 1911 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1912 pcixcmd &= 0x8F; 1913 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1914 ioc->bus_type = FC; 1915 break; 1916 1917 case MPI_MANUFACTPAGE_DEVID_53C1030: 1918 /* 1030 Chip Fix. Disable Split transactions 1919 * for PCIX. Set MOST bits to zero if Rev < C0( = 8). 1920 */ 1921 if (pdev->revision < C0_1030) { 1922 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1923 pcixcmd &= 0x8F; 1924 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1925 } 1926 fallthrough; 1927 1928 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1929 ioc->bus_type = SPI; 1930 break; 1931 1932 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1933 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1934 ioc->errata_flag_1064 = 1; 1935 ioc->bus_type = SAS; 1936 break; 1937 1938 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1939 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1940 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1941 ioc->bus_type = SAS; 1942 break; 1943 } 1944 1945 1946 switch (ioc->bus_type) { 1947 1948 case SAS: 1949 ioc->msi_enable = mpt_msi_enable_sas; 1950 break; 1951 1952 case SPI: 1953 ioc->msi_enable = mpt_msi_enable_spi; 1954 break; 1955 1956 case FC: 1957 ioc->msi_enable = mpt_msi_enable_fc; 1958 break; 1959 1960 default: 1961 ioc->msi_enable = 0; 1962 break; 1963 } 1964 1965 ioc->fw_events_off = 1; 1966 1967 if (ioc->errata_flag_1064) 1968 pci_disable_io_access(pdev); 1969 1970 spin_lock_init(&ioc->FreeQlock); 1971 1972 /* Disable all! */ 1973 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 1974 ioc->active = 0; 1975 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1976 1977 /* Set IOC ptr in the pcidev's driver data. */ 1978 pci_set_drvdata(ioc->pcidev, ioc); 1979 1980 /* Set lookup ptr. */ 1981 list_add_tail(&ioc->list, &ioc_list); 1982 1983 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets. 1984 */ 1985 mpt_detect_bound_ports(ioc, pdev); 1986 1987 INIT_LIST_HEAD(&ioc->fw_event_list); 1988 spin_lock_init(&ioc->fw_event_lock); 1989 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id); 1990 ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name, 1991 WQ_MEM_RECLAIM, 0); 1992 if (!ioc->fw_event_q) { 1993 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 1994 ioc->name); 1995 r = -ENOMEM; 1996 goto out_remove_ioc; 1997 } 1998 1999 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2000 CAN_SLEEP)) != 0){ 2001 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n", 2002 ioc->name, r); 2003 2004 destroy_workqueue(ioc->fw_event_q); 2005 ioc->fw_event_q = NULL; 2006 2007 list_del(&ioc->list); 2008 if (ioc->alt_ioc) 2009 ioc->alt_ioc->alt_ioc = NULL; 2010 iounmap(ioc->memmap); 2011 if (pci_is_enabled(pdev)) 2012 pci_disable_device(pdev); 2013 if (r != -5) 2014 pci_release_selected_regions(pdev, ioc->bars); 2015 2016 destroy_workqueue(ioc->reset_work_q); 2017 ioc->reset_work_q = NULL; 2018 2019 kfree(ioc); 2020 return r; 2021 } 2022 2023 /* call per device driver probe entry point */ 2024 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2025 if(MptDeviceDriverHandlers[cb_idx] && 2026 MptDeviceDriverHandlers[cb_idx]->probe) { 2027 MptDeviceDriverHandlers[cb_idx]->probe(pdev); 2028 } 2029 } 2030 2031 #ifdef CONFIG_PROC_FS 2032 /* 2033 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter. 2034 */ 2035 dent = proc_mkdir(ioc->name, mpt_proc_root_dir); 2036 if (dent) { 2037 proc_create_single_data("info", S_IRUGO, dent, 2038 mpt_iocinfo_proc_show, ioc); 2039 proc_create_single_data("summary", S_IRUGO, dent, 2040 mpt_summary_proc_show, ioc); 2041 } 2042 #endif 2043 2044 if (!ioc->alt_ioc) 2045 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 2046 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 2047 2048 return 0; 2049 2050 out_remove_ioc: 2051 list_del(&ioc->list); 2052 if (ioc->alt_ioc) 2053 ioc->alt_ioc->alt_ioc = NULL; 2054 2055 destroy_workqueue(ioc->reset_work_q); 2056 ioc->reset_work_q = NULL; 2057 2058 out_unmap_resources: 2059 iounmap(ioc->memmap); 2060 pci_disable_device(pdev); 2061 pci_release_selected_regions(pdev, ioc->bars); 2062 2063 out_free_ioc: 2064 kfree(ioc); 2065 2066 return r; 2067 } 2068 2069 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2070 /** 2071 * mpt_detach - Remove a PCI intelligent MPT adapter. 2072 * @pdev: Pointer to pci_dev structure 2073 */ 2074 2075 void 2076 mpt_detach(struct pci_dev *pdev) 2077 { 2078 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2079 char pname[64]; 2080 u8 cb_idx; 2081 unsigned long flags; 2082 struct workqueue_struct *wq; 2083 2084 /* 2085 * Stop polling ioc for fault condition 2086 */ 2087 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 2088 wq = ioc->reset_work_q; 2089 ioc->reset_work_q = NULL; 2090 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 2091 cancel_delayed_work(&ioc->fault_reset_work); 2092 destroy_workqueue(wq); 2093 2094 spin_lock_irqsave(&ioc->fw_event_lock, flags); 2095 wq = ioc->fw_event_q; 2096 ioc->fw_event_q = NULL; 2097 spin_unlock_irqrestore(&ioc->fw_event_lock, flags); 2098 destroy_workqueue(wq); 2099 2100 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name); 2101 remove_proc_entry(pname, NULL); 2102 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name); 2103 remove_proc_entry(pname, NULL); 2104 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name); 2105 remove_proc_entry(pname, NULL); 2106 2107 /* call per device driver remove entry point */ 2108 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2109 if(MptDeviceDriverHandlers[cb_idx] && 2110 MptDeviceDriverHandlers[cb_idx]->remove) { 2111 MptDeviceDriverHandlers[cb_idx]->remove(pdev); 2112 } 2113 } 2114 2115 /* Disable interrupts! */ 2116 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2117 2118 ioc->active = 0; 2119 synchronize_irq(pdev->irq); 2120 2121 /* Clear any lingering interrupt */ 2122 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2123 2124 CHIPREG_READ32(&ioc->chip->IntStatus); 2125 2126 mpt_adapter_dispose(ioc); 2127 2128 } 2129 2130 /************************************************************************** 2131 * Power Management 2132 */ 2133 #ifdef CONFIG_PM 2134 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2135 /** 2136 * mpt_suspend - Fusion MPT base driver suspend routine. 2137 * @pdev: Pointer to pci_dev structure 2138 * @state: new state to enter 2139 */ 2140 int 2141 mpt_suspend(struct pci_dev *pdev, pm_message_t state) 2142 { 2143 u32 device_state; 2144 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2145 2146 device_state = pci_choose_state(pdev, state); 2147 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering " 2148 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2149 device_state); 2150 2151 /* put ioc into READY_STATE */ 2152 if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) { 2153 printk(MYIOC_s_ERR_FMT 2154 "pci-suspend: IOC msg unit reset failed!\n", ioc->name); 2155 } 2156 2157 /* disable interrupts */ 2158 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2159 ioc->active = 0; 2160 2161 /* Clear any lingering interrupt */ 2162 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2163 2164 free_irq(ioc->pci_irq, ioc); 2165 if (ioc->msi_enable) 2166 pci_disable_msi(ioc->pcidev); 2167 ioc->pci_irq = -1; 2168 pci_save_state(pdev); 2169 pci_disable_device(pdev); 2170 pci_release_selected_regions(pdev, ioc->bars); 2171 pci_set_power_state(pdev, device_state); 2172 return 0; 2173 } 2174 2175 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2176 /** 2177 * mpt_resume - Fusion MPT base driver resume routine. 2178 * @pdev: Pointer to pci_dev structure 2179 */ 2180 int 2181 mpt_resume(struct pci_dev *pdev) 2182 { 2183 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2184 u32 device_state = pdev->current_state; 2185 int recovery_state; 2186 int err; 2187 2188 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous " 2189 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2190 device_state); 2191 2192 pci_set_power_state(pdev, PCI_D0); 2193 pci_enable_wake(pdev, PCI_D0, 0); 2194 pci_restore_state(pdev); 2195 ioc->pcidev = pdev; 2196 err = mpt_mapresources(ioc); 2197 if (err) 2198 return err; 2199 2200 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 2201 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 2202 ioc->add_sge = &mpt_add_sge_64bit_1078; 2203 else 2204 ioc->add_sge = &mpt_add_sge_64bit; 2205 ioc->add_chain = &mpt_add_chain_64bit; 2206 ioc->sg_addr_size = 8; 2207 } else { 2208 2209 ioc->add_sge = &mpt_add_sge; 2210 ioc->add_chain = &mpt_add_chain; 2211 ioc->sg_addr_size = 4; 2212 } 2213 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 2214 2215 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n", 2216 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT), 2217 CHIPREG_READ32(&ioc->chip->Doorbell)); 2218 2219 /* 2220 * Errata workaround for SAS pci express: 2221 * Upon returning to the D0 state, the contents of the doorbell will be 2222 * stale data, and this will incorrectly signal to the host driver that 2223 * the firmware is ready to process mpt commands. The workaround is 2224 * to issue a diagnostic reset. 2225 */ 2226 if (ioc->bus_type == SAS && (pdev->device == 2227 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device == 2228 MPI_MANUFACTPAGE_DEVID_SAS1064E)) { 2229 if (KickStart(ioc, 1, CAN_SLEEP) < 0) { 2230 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n", 2231 ioc->name); 2232 goto out; 2233 } 2234 } 2235 2236 /* bring ioc to operational state */ 2237 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name); 2238 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2239 CAN_SLEEP); 2240 if (recovery_state != 0) 2241 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, " 2242 "error:[%x]\n", ioc->name, recovery_state); 2243 else 2244 printk(MYIOC_s_INFO_FMT 2245 "pci-resume: success\n", ioc->name); 2246 out: 2247 return 0; 2248 2249 } 2250 #endif 2251 2252 static int 2253 mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase) 2254 { 2255 if ((MptDriverClass[index] == MPTSPI_DRIVER && 2256 ioc->bus_type != SPI) || 2257 (MptDriverClass[index] == MPTFC_DRIVER && 2258 ioc->bus_type != FC) || 2259 (MptDriverClass[index] == MPTSAS_DRIVER && 2260 ioc->bus_type != SAS)) 2261 /* make sure we only call the relevant reset handler 2262 * for the bus */ 2263 return 0; 2264 return (MptResetHandlers[index])(ioc, reset_phase); 2265 } 2266 2267 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2268 /** 2269 * mpt_do_ioc_recovery - Initialize or recover MPT adapter. 2270 * @ioc: Pointer to MPT adapter structure 2271 * @reason: Event word / reason 2272 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 2273 * 2274 * This routine performs all the steps necessary to bring the IOC 2275 * to a OPERATIONAL state. 2276 * 2277 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 2278 * MPT adapter. 2279 * 2280 * Returns: 2281 * 0 for success 2282 * -1 if failed to get board READY 2283 * -2 if READY but IOCFacts Failed 2284 * -3 if READY but PrimeIOCFifos Failed 2285 * -4 if READY but IOCInit Failed 2286 * -5 if failed to enable_device and/or request_selected_regions 2287 * -6 if failed to upload firmware 2288 */ 2289 static int 2290 mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag) 2291 { 2292 int hard_reset_done = 0; 2293 int alt_ioc_ready = 0; 2294 int hard; 2295 int rc=0; 2296 int ii; 2297 int ret = 0; 2298 int reset_alt_ioc_active = 0; 2299 int irq_allocated = 0; 2300 u8 *a; 2301 2302 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name, 2303 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery"); 2304 2305 /* Disable reply interrupts (also blocks FreeQ) */ 2306 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2307 ioc->active = 0; 2308 2309 if (ioc->alt_ioc) { 2310 if (ioc->alt_ioc->active || 2311 reason == MPT_HOSTEVENT_IOC_RECOVER) { 2312 reset_alt_ioc_active = 1; 2313 /* Disable alt-IOC's reply interrupts 2314 * (and FreeQ) for a bit 2315 **/ 2316 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2317 0xFFFFFFFF); 2318 ioc->alt_ioc->active = 0; 2319 } 2320 } 2321 2322 hard = 1; 2323 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) 2324 hard = 0; 2325 2326 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) { 2327 if (hard_reset_done == -4) { 2328 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n", 2329 ioc->name); 2330 2331 if (reset_alt_ioc_active && ioc->alt_ioc) { 2332 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */ 2333 dprintk(ioc, printk(MYIOC_s_INFO_FMT 2334 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name)); 2335 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM); 2336 ioc->alt_ioc->active = 1; 2337 } 2338 2339 } else { 2340 printk(MYIOC_s_WARN_FMT 2341 "NOT READY WARNING!\n", ioc->name); 2342 } 2343 ret = -1; 2344 goto out; 2345 } 2346 2347 /* hard_reset_done = 0 if a soft reset was performed 2348 * and 1 if a hard reset was performed. 2349 */ 2350 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) { 2351 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0) 2352 alt_ioc_ready = 1; 2353 else 2354 printk(MYIOC_s_WARN_FMT 2355 ": alt-ioc Not ready WARNING!\n", 2356 ioc->alt_ioc->name); 2357 } 2358 2359 for (ii=0; ii<5; ii++) { 2360 /* Get IOC facts! Allow 5 retries */ 2361 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0) 2362 break; 2363 } 2364 2365 2366 if (ii == 5) { 2367 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2368 "Retry IocFacts failed rc=%x\n", ioc->name, rc)); 2369 ret = -2; 2370 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2371 MptDisplayIocCapabilities(ioc); 2372 } 2373 2374 if (alt_ioc_ready) { 2375 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) { 2376 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2377 "Initial Alt IocFacts failed rc=%x\n", 2378 ioc->name, rc)); 2379 /* Retry - alt IOC was initialized once 2380 */ 2381 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason); 2382 } 2383 if (rc) { 2384 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2385 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc)); 2386 alt_ioc_ready = 0; 2387 reset_alt_ioc_active = 0; 2388 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2389 MptDisplayIocCapabilities(ioc->alt_ioc); 2390 } 2391 } 2392 2393 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) && 2394 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) { 2395 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2396 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM | 2397 IORESOURCE_IO); 2398 if (pci_enable_device(ioc->pcidev)) 2399 return -5; 2400 if (pci_request_selected_regions(ioc->pcidev, ioc->bars, 2401 "mpt")) 2402 return -5; 2403 } 2404 2405 /* 2406 * Device is reset now. It must have de-asserted the interrupt line 2407 * (if it was asserted) and it should be safe to register for the 2408 * interrupt now. 2409 */ 2410 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2411 ioc->pci_irq = -1; 2412 if (ioc->pcidev->irq) { 2413 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev)) 2414 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n", 2415 ioc->name); 2416 else 2417 ioc->msi_enable = 0; 2418 rc = request_irq(ioc->pcidev->irq, mpt_interrupt, 2419 IRQF_SHARED, ioc->name, ioc); 2420 if (rc < 0) { 2421 printk(MYIOC_s_ERR_FMT "Unable to allocate " 2422 "interrupt %d!\n", 2423 ioc->name, ioc->pcidev->irq); 2424 if (ioc->msi_enable) 2425 pci_disable_msi(ioc->pcidev); 2426 ret = -EBUSY; 2427 goto out; 2428 } 2429 irq_allocated = 1; 2430 ioc->pci_irq = ioc->pcidev->irq; 2431 pci_set_master(ioc->pcidev); /* ?? */ 2432 pci_set_drvdata(ioc->pcidev, ioc); 2433 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2434 "installed at interrupt %d\n", ioc->name, 2435 ioc->pcidev->irq)); 2436 } 2437 } 2438 2439 /* Prime reply & request queues! 2440 * (mucho alloc's) Must be done prior to 2441 * init as upper addresses are needed for init. 2442 * If fails, continue with alt-ioc processing 2443 */ 2444 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n", 2445 ioc->name)); 2446 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0)) 2447 ret = -3; 2448 2449 /* May need to check/upload firmware & data here! 2450 * If fails, continue with alt-ioc processing 2451 */ 2452 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n", 2453 ioc->name)); 2454 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0)) 2455 ret = -4; 2456 // NEW! 2457 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) { 2458 printk(MYIOC_s_WARN_FMT 2459 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n", 2460 ioc->alt_ioc->name, rc); 2461 alt_ioc_ready = 0; 2462 reset_alt_ioc_active = 0; 2463 } 2464 2465 if (alt_ioc_ready) { 2466 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) { 2467 alt_ioc_ready = 0; 2468 reset_alt_ioc_active = 0; 2469 printk(MYIOC_s_WARN_FMT 2470 ": alt-ioc: (%d) init failure WARNING!\n", 2471 ioc->alt_ioc->name, rc); 2472 } 2473 } 2474 2475 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){ 2476 if (ioc->upload_fw) { 2477 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2478 "firmware upload required!\n", ioc->name)); 2479 2480 /* Controller is not operational, cannot do upload 2481 */ 2482 if (ret == 0) { 2483 rc = mpt_do_upload(ioc, sleepFlag); 2484 if (rc == 0) { 2485 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 2486 /* 2487 * Maintain only one pointer to FW memory 2488 * so there will not be two attempt to 2489 * downloadboot onboard dual function 2490 * chips (mpt_adapter_disable, 2491 * mpt_diag_reset) 2492 */ 2493 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2494 "mpt_upload: alt_%s has cached_fw=%p \n", 2495 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw)); 2496 ioc->cached_fw = NULL; 2497 } 2498 } else { 2499 printk(MYIOC_s_WARN_FMT 2500 "firmware upload failure!\n", ioc->name); 2501 ret = -6; 2502 } 2503 } 2504 } 2505 } 2506 2507 /* Enable MPT base driver management of EventNotification 2508 * and EventAck handling. 2509 */ 2510 if ((ret == 0) && (!ioc->facts.EventState)) { 2511 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2512 "SendEventNotification\n", 2513 ioc->name)); 2514 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */ 2515 } 2516 2517 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState) 2518 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag); 2519 2520 if (ret == 0) { 2521 /* Enable! (reply interrupt) */ 2522 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 2523 ioc->active = 1; 2524 } 2525 if (rc == 0) { /* alt ioc */ 2526 if (reset_alt_ioc_active && ioc->alt_ioc) { 2527 /* (re)Enable alt-IOC! (reply interrupt) */ 2528 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc" 2529 "reply irq re-enabled\n", 2530 ioc->alt_ioc->name)); 2531 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2532 MPI_HIM_DIM); 2533 ioc->alt_ioc->active = 1; 2534 } 2535 } 2536 2537 2538 /* Add additional "reason" check before call to GetLanConfigPages 2539 * (combined with GetIoUnitPage2 call). This prevents a somewhat 2540 * recursive scenario; GetLanConfigPages times out, timer expired 2541 * routine calls HardResetHandler, which calls into here again, 2542 * and we try GetLanConfigPages again... 2543 */ 2544 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2545 2546 /* 2547 * Initialize link list for inactive raid volumes. 2548 */ 2549 mutex_init(&ioc->raid_data.inactive_list_mutex); 2550 INIT_LIST_HEAD(&ioc->raid_data.inactive_list); 2551 2552 switch (ioc->bus_type) { 2553 2554 case SAS: 2555 /* clear persistency table */ 2556 if(ioc->facts.IOCExceptions & 2557 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) { 2558 ret = mptbase_sas_persist_operation(ioc, 2559 MPI_SAS_OP_CLEAR_NOT_PRESENT); 2560 if(ret != 0) 2561 goto out; 2562 } 2563 2564 /* Find IM volumes 2565 */ 2566 mpt_findImVolumes(ioc); 2567 2568 /* Check, and possibly reset, the coalescing value 2569 */ 2570 mpt_read_ioc_pg_1(ioc); 2571 2572 break; 2573 2574 case FC: 2575 if ((ioc->pfacts[0].ProtocolFlags & 2576 MPI_PORTFACTS_PROTOCOL_LAN) && 2577 (ioc->lan_cnfg_page0.Header.PageLength == 0)) { 2578 /* 2579 * Pre-fetch the ports LAN MAC address! 2580 * (LANPage1_t stuff) 2581 */ 2582 (void) GetLanConfigPages(ioc); 2583 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 2584 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2585 "LanAddr = %pMR\n", ioc->name, a)); 2586 } 2587 break; 2588 2589 case SPI: 2590 /* Get NVRAM and adapter maximums from SPP 0 and 2 2591 */ 2592 mpt_GetScsiPortSettings(ioc, 0); 2593 2594 /* Get version and length of SDP 1 2595 */ 2596 mpt_readScsiDevicePageHeaders(ioc, 0); 2597 2598 /* Find IM volumes 2599 */ 2600 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02) 2601 mpt_findImVolumes(ioc); 2602 2603 /* Check, and possibly reset, the coalescing value 2604 */ 2605 mpt_read_ioc_pg_1(ioc); 2606 2607 mpt_read_ioc_pg_4(ioc); 2608 2609 break; 2610 } 2611 2612 GetIoUnitPage2(ioc); 2613 mpt_get_manufacturing_pg_0(ioc); 2614 } 2615 2616 out: 2617 if ((ret != 0) && irq_allocated) { 2618 free_irq(ioc->pci_irq, ioc); 2619 if (ioc->msi_enable) 2620 pci_disable_msi(ioc->pcidev); 2621 } 2622 return ret; 2623 } 2624 2625 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2626 /** 2627 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function 2628 * @ioc: Pointer to MPT adapter structure 2629 * @pdev: Pointer to (struct pci_dev) structure 2630 * 2631 * Search for PCI bus/dev_function which matches 2632 * PCI bus/dev_function (+/-1) for newly discovered 929, 2633 * 929X, 1030 or 1035. 2634 * 2635 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters 2636 * using alt_ioc pointer fields in their %MPT_ADAPTER structures. 2637 */ 2638 static void 2639 mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev) 2640 { 2641 struct pci_dev *peer=NULL; 2642 unsigned int slot = PCI_SLOT(pdev->devfn); 2643 unsigned int func = PCI_FUNC(pdev->devfn); 2644 MPT_ADAPTER *ioc_srch; 2645 2646 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x," 2647 " searching for devfn match on %x or %x\n", 2648 ioc->name, pci_name(pdev), pdev->bus->number, 2649 pdev->devfn, func-1, func+1)); 2650 2651 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1)); 2652 if (!peer) { 2653 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1)); 2654 if (!peer) 2655 return; 2656 } 2657 2658 list_for_each_entry(ioc_srch, &ioc_list, list) { 2659 struct pci_dev *_pcidev = ioc_srch->pcidev; 2660 if (_pcidev == peer) { 2661 /* Paranoia checks */ 2662 if (ioc->alt_ioc != NULL) { 2663 printk(MYIOC_s_WARN_FMT 2664 "Oops, already bound (%s <==> %s)!\n", 2665 ioc->name, ioc->name, ioc->alt_ioc->name); 2666 break; 2667 } else if (ioc_srch->alt_ioc != NULL) { 2668 printk(MYIOC_s_WARN_FMT 2669 "Oops, already bound (%s <==> %s)!\n", 2670 ioc_srch->name, ioc_srch->name, 2671 ioc_srch->alt_ioc->name); 2672 break; 2673 } 2674 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2675 "FOUND! binding %s <==> %s\n", 2676 ioc->name, ioc->name, ioc_srch->name)); 2677 ioc_srch->alt_ioc = ioc; 2678 ioc->alt_ioc = ioc_srch; 2679 } 2680 } 2681 pci_dev_put(peer); 2682 } 2683 2684 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2685 /** 2686 * mpt_adapter_disable - Disable misbehaving MPT adapter. 2687 * @ioc: Pointer to MPT adapter structure 2688 */ 2689 static void 2690 mpt_adapter_disable(MPT_ADAPTER *ioc) 2691 { 2692 int sz; 2693 int ret; 2694 2695 if (ioc->cached_fw != NULL) { 2696 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2697 "%s: Pushing FW onto adapter\n", __func__, ioc->name)); 2698 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *) 2699 ioc->cached_fw, CAN_SLEEP)) < 0) { 2700 printk(MYIOC_s_WARN_FMT 2701 ": firmware downloadboot failure (%d)!\n", 2702 ioc->name, ret); 2703 } 2704 } 2705 2706 /* 2707 * Put the controller into ready state (if its not already) 2708 */ 2709 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) { 2710 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, 2711 CAN_SLEEP)) { 2712 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) 2713 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit " 2714 "reset failed to put ioc in ready state!\n", 2715 ioc->name, __func__); 2716 } else 2717 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset " 2718 "failed!\n", ioc->name, __func__); 2719 } 2720 2721 2722 /* Disable adapter interrupts! */ 2723 synchronize_irq(ioc->pcidev->irq); 2724 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2725 ioc->active = 0; 2726 2727 /* Clear any lingering interrupt */ 2728 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2729 CHIPREG_READ32(&ioc->chip->IntStatus); 2730 2731 if (ioc->alloc != NULL) { 2732 sz = ioc->alloc_sz; 2733 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n", 2734 ioc->name, ioc->alloc, ioc->alloc_sz)); 2735 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 2736 ioc->alloc_dma); 2737 ioc->reply_frames = NULL; 2738 ioc->req_frames = NULL; 2739 ioc->alloc = NULL; 2740 ioc->alloc_total -= sz; 2741 } 2742 2743 if (ioc->sense_buf_pool != NULL) { 2744 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 2745 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 2746 ioc->sense_buf_pool_dma); 2747 ioc->sense_buf_pool = NULL; 2748 ioc->alloc_total -= sz; 2749 } 2750 2751 if (ioc->events != NULL){ 2752 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS); 2753 kfree(ioc->events); 2754 ioc->events = NULL; 2755 ioc->alloc_total -= sz; 2756 } 2757 2758 mpt_free_fw_memory(ioc); 2759 2760 kfree(ioc->spi_data.nvram); 2761 mpt_inactive_raid_list_free(ioc); 2762 kfree(ioc->raid_data.pIocPg2); 2763 kfree(ioc->raid_data.pIocPg3); 2764 ioc->spi_data.nvram = NULL; 2765 ioc->raid_data.pIocPg3 = NULL; 2766 2767 if (ioc->spi_data.pIocPg4 != NULL) { 2768 sz = ioc->spi_data.IocPg4Sz; 2769 dma_free_coherent(&ioc->pcidev->dev, sz, 2770 ioc->spi_data.pIocPg4, 2771 ioc->spi_data.IocPg4_dma); 2772 ioc->spi_data.pIocPg4 = NULL; 2773 ioc->alloc_total -= sz; 2774 } 2775 2776 if (ioc->ReqToChain != NULL) { 2777 kfree(ioc->ReqToChain); 2778 kfree(ioc->RequestNB); 2779 ioc->ReqToChain = NULL; 2780 } 2781 2782 kfree(ioc->ChainToChain); 2783 ioc->ChainToChain = NULL; 2784 2785 if (ioc->HostPageBuffer != NULL) { 2786 if((ret = mpt_host_page_access_control(ioc, 2787 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) { 2788 printk(MYIOC_s_ERR_FMT 2789 ": %s: host page buffers free failed (%d)!\n", 2790 ioc->name, __func__, ret); 2791 } 2792 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2793 "HostPageBuffer free @ %p, sz=%d bytes\n", 2794 ioc->name, ioc->HostPageBuffer, 2795 ioc->HostPageBuffer_sz)); 2796 dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz, 2797 ioc->HostPageBuffer, ioc->HostPageBuffer_dma); 2798 ioc->HostPageBuffer = NULL; 2799 ioc->HostPageBuffer_sz = 0; 2800 ioc->alloc_total -= ioc->HostPageBuffer_sz; 2801 } 2802 2803 pci_set_drvdata(ioc->pcidev, NULL); 2804 } 2805 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2806 /** 2807 * mpt_adapter_dispose - Free all resources associated with an MPT adapter 2808 * @ioc: Pointer to MPT adapter structure 2809 * 2810 * This routine unregisters h/w resources and frees all alloc'd memory 2811 * associated with a MPT adapter structure. 2812 */ 2813 static void 2814 mpt_adapter_dispose(MPT_ADAPTER *ioc) 2815 { 2816 int sz_first, sz_last; 2817 2818 if (ioc == NULL) 2819 return; 2820 2821 sz_first = ioc->alloc_total; 2822 2823 mpt_adapter_disable(ioc); 2824 2825 if (ioc->pci_irq != -1) { 2826 free_irq(ioc->pci_irq, ioc); 2827 if (ioc->msi_enable) 2828 pci_disable_msi(ioc->pcidev); 2829 ioc->pci_irq = -1; 2830 } 2831 2832 if (ioc->memmap != NULL) { 2833 iounmap(ioc->memmap); 2834 ioc->memmap = NULL; 2835 } 2836 2837 pci_disable_device(ioc->pcidev); 2838 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2839 2840 /* Zap the adapter lookup ptr! */ 2841 list_del(&ioc->list); 2842 2843 sz_last = ioc->alloc_total; 2844 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n", 2845 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first)); 2846 2847 if (ioc->alt_ioc) 2848 ioc->alt_ioc->alt_ioc = NULL; 2849 2850 kfree(ioc); 2851 } 2852 2853 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2854 /** 2855 * MptDisplayIocCapabilities - Disply IOC's capabilities. 2856 * @ioc: Pointer to MPT adapter structure 2857 */ 2858 static void 2859 MptDisplayIocCapabilities(MPT_ADAPTER *ioc) 2860 { 2861 int i = 0; 2862 2863 printk(KERN_INFO "%s: ", ioc->name); 2864 if (ioc->prod_name) 2865 pr_cont("%s: ", ioc->prod_name); 2866 pr_cont("Capabilities={"); 2867 2868 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { 2869 pr_cont("Initiator"); 2870 i++; 2871 } 2872 2873 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2874 pr_cont("%sTarget", i ? "," : ""); 2875 i++; 2876 } 2877 2878 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 2879 pr_cont("%sLAN", i ? "," : ""); 2880 i++; 2881 } 2882 2883 #if 0 2884 /* 2885 * This would probably evoke more questions than it's worth 2886 */ 2887 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2888 pr_cont("%sLogBusAddr", i ? "," : ""); 2889 i++; 2890 } 2891 #endif 2892 2893 pr_cont("}\n"); 2894 } 2895 2896 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2897 /** 2898 * MakeIocReady - Get IOC to a READY state, using KickStart if needed. 2899 * @ioc: Pointer to MPT_ADAPTER structure 2900 * @force: Force hard KickStart of IOC 2901 * @sleepFlag: Specifies whether the process can sleep 2902 * 2903 * Returns: 2904 * 1 - DIAG reset and READY 2905 * 0 - READY initially OR soft reset and READY 2906 * -1 - Any failure on KickStart 2907 * -2 - Msg Unit Reset Failed 2908 * -3 - IO Unit Reset Failed 2909 * -4 - IOC owned by a PEER 2910 */ 2911 static int 2912 MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag) 2913 { 2914 u32 ioc_state; 2915 int statefault = 0; 2916 int cntdn; 2917 int hard_reset_done = 0; 2918 int r; 2919 int ii; 2920 int whoinit; 2921 2922 /* Get current [raw] IOC state */ 2923 ioc_state = mpt_GetIocState(ioc, 0); 2924 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state)); 2925 2926 /* 2927 * Check to see if IOC got left/stuck in doorbell handshake 2928 * grip of death. If so, hard reset the IOC. 2929 */ 2930 if (ioc_state & MPI_DOORBELL_ACTIVE) { 2931 statefault = 1; 2932 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n", 2933 ioc->name); 2934 } 2935 2936 /* Is it already READY? */ 2937 if (!statefault && 2938 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) { 2939 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2940 "IOC is in READY state\n", ioc->name)); 2941 return 0; 2942 } 2943 2944 /* 2945 * Check to see if IOC is in FAULT state. 2946 */ 2947 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 2948 statefault = 2; 2949 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n", 2950 ioc->name); 2951 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n", 2952 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK); 2953 } 2954 2955 /* 2956 * Hmmm... Did it get left operational? 2957 */ 2958 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) { 2959 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n", 2960 ioc->name)); 2961 2962 /* Check WhoInit. 2963 * If PCI Peer, exit. 2964 * Else, if no fault conditions are present, issue a MessageUnitReset 2965 * Else, fall through to KickStart case 2966 */ 2967 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT; 2968 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2969 "whoinit 0x%x statefault %d force %d\n", 2970 ioc->name, whoinit, statefault, force)); 2971 if (whoinit == MPI_WHOINIT_PCI_PEER) 2972 return -4; 2973 else { 2974 if ((statefault == 0 ) && (force == 0)) { 2975 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0) 2976 return 0; 2977 } 2978 statefault = 3; 2979 } 2980 } 2981 2982 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag); 2983 if (hard_reset_done < 0) 2984 return -1; 2985 2986 /* 2987 * Loop here waiting for IOC to come READY. 2988 */ 2989 ii = 0; 2990 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */ 2991 2992 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 2993 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) { 2994 /* 2995 * BIOS or previous driver load left IOC in OP state. 2996 * Reset messaging FIFOs. 2997 */ 2998 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) { 2999 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name); 3000 return -2; 3001 } 3002 } else if (ioc_state == MPI_IOC_STATE_RESET) { 3003 /* 3004 * Something is wrong. Try to get IOC back 3005 * to a known state. 3006 */ 3007 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) { 3008 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name); 3009 return -3; 3010 } 3011 } 3012 3013 ii++; cntdn--; 3014 if (!cntdn) { 3015 printk(MYIOC_s_ERR_FMT 3016 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 3017 ioc->name, ioc_state, (int)((ii+5)/HZ)); 3018 return -ETIME; 3019 } 3020 3021 if (sleepFlag == CAN_SLEEP) { 3022 msleep(1); 3023 } else { 3024 mdelay (1); /* 1 msec delay */ 3025 } 3026 3027 } 3028 3029 if (statefault < 3) { 3030 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name, 3031 statefault == 1 ? "stuck handshake" : "IOC FAULT"); 3032 } 3033 3034 return hard_reset_done; 3035 } 3036 3037 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3038 /** 3039 * mpt_GetIocState - Get the current state of a MPT adapter. 3040 * @ioc: Pointer to MPT_ADAPTER structure 3041 * @cooked: Request raw or cooked IOC state 3042 * 3043 * Returns all IOC Doorbell register bits if cooked==0, else just the 3044 * Doorbell bits in MPI_IOC_STATE_MASK. 3045 */ 3046 u32 3047 mpt_GetIocState(MPT_ADAPTER *ioc, int cooked) 3048 { 3049 u32 s, sc; 3050 3051 /* Get! */ 3052 s = CHIPREG_READ32(&ioc->chip->Doorbell); 3053 sc = s & MPI_IOC_STATE_MASK; 3054 3055 /* Save! */ 3056 ioc->last_state = sc; 3057 3058 return cooked ? sc : s; 3059 } 3060 3061 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3062 /** 3063 * GetIocFacts - Send IOCFacts request to MPT adapter. 3064 * @ioc: Pointer to MPT_ADAPTER structure 3065 * @sleepFlag: Specifies whether the process can sleep 3066 * @reason: If recovery, only update facts. 3067 * 3068 * Returns 0 for success, non-zero for failure. 3069 */ 3070 static int 3071 GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason) 3072 { 3073 IOCFacts_t get_facts; 3074 IOCFactsReply_t *facts; 3075 int r; 3076 int req_sz; 3077 int reply_sz; 3078 int sz; 3079 u32 vv; 3080 u8 shiftFactor=1; 3081 3082 /* IOC *must* NOT be in RESET state! */ 3083 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3084 printk(KERN_ERR MYNAM 3085 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n", 3086 ioc->name, ioc->last_state); 3087 return -44; 3088 } 3089 3090 facts = &ioc->facts; 3091 3092 /* Destination (reply area)... */ 3093 reply_sz = sizeof(*facts); 3094 memset(facts, 0, reply_sz); 3095 3096 /* Request area (get_facts on the stack right now!) */ 3097 req_sz = sizeof(get_facts); 3098 memset(&get_facts, 0, req_sz); 3099 3100 get_facts.Function = MPI_FUNCTION_IOC_FACTS; 3101 /* Assert: All other get_facts fields are zero! */ 3102 3103 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3104 "Sending get IocFacts request req_sz=%d reply_sz=%d\n", 3105 ioc->name, req_sz, reply_sz)); 3106 3107 /* No non-zero fields in the get_facts request are greater than 3108 * 1 byte in size, so we can just fire it off as is. 3109 */ 3110 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts, 3111 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag); 3112 if (r != 0) 3113 return r; 3114 3115 /* 3116 * Now byte swap (GRRR) the necessary fields before any further 3117 * inspection of reply contents. 3118 * 3119 * But need to do some sanity checks on MsgLength (byte) field 3120 * to make sure we don't zero IOC's req_sz! 3121 */ 3122 /* Did we get a valid reply? */ 3123 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) { 3124 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3125 /* 3126 * If not been here, done that, save off first WhoInit value 3127 */ 3128 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN) 3129 ioc->FirstWhoInit = facts->WhoInit; 3130 } 3131 3132 facts->MsgVersion = le16_to_cpu(facts->MsgVersion); 3133 facts->MsgContext = le32_to_cpu(facts->MsgContext); 3134 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions); 3135 facts->IOCStatus = le16_to_cpu(facts->IOCStatus); 3136 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo); 3137 /* CHECKME! IOCStatus, IOCLogInfo */ 3138 3139 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth); 3140 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize); 3141 3142 /* 3143 * FC f/w version changed between 1.1 and 1.2 3144 * Old: u16{Major(4),Minor(4),SubMinor(8)} 3145 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)} 3146 */ 3147 if (facts->MsgVersion < MPI_VERSION_01_02) { 3148 /* 3149 * Handle old FC f/w style, convert to new... 3150 */ 3151 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion); 3152 facts->FWVersion.Word = 3153 ((oldv<<12) & 0xFF000000) | 3154 ((oldv<<8) & 0x000FFF00); 3155 } else 3156 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word); 3157 3158 facts->ProductID = le16_to_cpu(facts->ProductID); 3159 3160 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK) 3161 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI) 3162 ioc->ir_firmware = 1; 3163 3164 facts->CurrentHostMfaHighAddr = 3165 le32_to_cpu(facts->CurrentHostMfaHighAddr); 3166 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits); 3167 facts->CurrentSenseBufferHighAddr = 3168 le32_to_cpu(facts->CurrentSenseBufferHighAddr); 3169 facts->CurReplyFrameSize = 3170 le16_to_cpu(facts->CurReplyFrameSize); 3171 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities); 3172 3173 /* 3174 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx 3175 * Older MPI-1.00.xx struct had 13 dwords, and enlarged 3176 * to 14 in MPI-1.01.0x. 3177 */ 3178 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 && 3179 facts->MsgVersion > MPI_VERSION_01_00) { 3180 facts->FWImageSize = le32_to_cpu(facts->FWImageSize); 3181 } 3182 3183 facts->FWImageSize = ALIGN(facts->FWImageSize, 4); 3184 3185 if (!facts->RequestFrameSize) { 3186 /* Something is wrong! */ 3187 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n", 3188 ioc->name); 3189 return -55; 3190 } 3191 3192 r = sz = facts->BlockSize; 3193 vv = ((63 / (sz * 4)) + 1) & 0x03; 3194 ioc->NB_for_64_byte_frame = vv; 3195 while ( sz ) 3196 { 3197 shiftFactor++; 3198 sz = sz >> 1; 3199 } 3200 ioc->NBShiftFactor = shiftFactor; 3201 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3202 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n", 3203 ioc->name, vv, shiftFactor, r)); 3204 3205 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3206 /* 3207 * Set values for this IOC's request & reply frame sizes, 3208 * and request & reply queue depths... 3209 */ 3210 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4); 3211 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits); 3212 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 3213 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth); 3214 3215 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n", 3216 ioc->name, ioc->reply_sz, ioc->reply_depth)); 3217 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n", 3218 ioc->name, ioc->req_sz, ioc->req_depth)); 3219 3220 /* Get port facts! */ 3221 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 ) 3222 return r; 3223 } 3224 } else { 3225 printk(MYIOC_s_ERR_FMT 3226 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n", 3227 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t, 3228 RequestFrameSize)/sizeof(u32))); 3229 return -66; 3230 } 3231 3232 return 0; 3233 } 3234 3235 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3236 /** 3237 * GetPortFacts - Send PortFacts request to MPT adapter. 3238 * @ioc: Pointer to MPT_ADAPTER structure 3239 * @portnum: Port number 3240 * @sleepFlag: Specifies whether the process can sleep 3241 * 3242 * Returns 0 for success, non-zero for failure. 3243 */ 3244 static int 3245 GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3246 { 3247 PortFacts_t get_pfacts; 3248 PortFactsReply_t *pfacts; 3249 int ii; 3250 int req_sz; 3251 int reply_sz; 3252 int max_id; 3253 3254 /* IOC *must* NOT be in RESET state! */ 3255 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3256 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n", 3257 ioc->name, ioc->last_state ); 3258 return -4; 3259 } 3260 3261 pfacts = &ioc->pfacts[portnum]; 3262 3263 /* Destination (reply area)... */ 3264 reply_sz = sizeof(*pfacts); 3265 memset(pfacts, 0, reply_sz); 3266 3267 /* Request area (get_pfacts on the stack right now!) */ 3268 req_sz = sizeof(get_pfacts); 3269 memset(&get_pfacts, 0, req_sz); 3270 3271 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS; 3272 get_pfacts.PortNumber = portnum; 3273 /* Assert: All other get_pfacts fields are zero! */ 3274 3275 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n", 3276 ioc->name, portnum)); 3277 3278 /* No non-zero fields in the get_pfacts request are greater than 3279 * 1 byte in size, so we can just fire it off as is. 3280 */ 3281 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts, 3282 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag); 3283 if (ii != 0) 3284 return ii; 3285 3286 /* Did we get a valid reply? */ 3287 3288 /* Now byte swap the necessary fields in the response. */ 3289 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext); 3290 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus); 3291 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo); 3292 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices); 3293 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID); 3294 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags); 3295 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers); 3296 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs); 3297 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets); 3298 3299 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID : 3300 pfacts->MaxDevices; 3301 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id; 3302 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256; 3303 3304 /* 3305 * Place all the devices on channels 3306 * 3307 * (for debuging) 3308 */ 3309 if (mpt_channel_mapping) { 3310 ioc->devices_per_bus = 1; 3311 ioc->number_of_buses = (max_id > 255) ? 255 : max_id; 3312 } 3313 3314 return 0; 3315 } 3316 3317 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3318 /** 3319 * SendIocInit - Send IOCInit request to MPT adapter. 3320 * @ioc: Pointer to MPT_ADAPTER structure 3321 * @sleepFlag: Specifies whether the process can sleep 3322 * 3323 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state. 3324 * 3325 * Returns 0 for success, non-zero for failure. 3326 */ 3327 static int 3328 SendIocInit(MPT_ADAPTER *ioc, int sleepFlag) 3329 { 3330 IOCInit_t ioc_init; 3331 MPIDefaultReply_t init_reply; 3332 u32 state; 3333 int r; 3334 int count; 3335 int cntdn; 3336 3337 memset(&ioc_init, 0, sizeof(ioc_init)); 3338 memset(&init_reply, 0, sizeof(init_reply)); 3339 3340 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER; 3341 ioc_init.Function = MPI_FUNCTION_IOC_INIT; 3342 3343 /* If we are in a recovery mode and we uploaded the FW image, 3344 * then this pointer is not NULL. Skip the upload a second time. 3345 * Set this flag if cached_fw set for either IOC. 3346 */ 3347 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 3348 ioc->upload_fw = 1; 3349 else 3350 ioc->upload_fw = 0; 3351 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n", 3352 ioc->name, ioc->upload_fw, ioc->facts.Flags)); 3353 3354 ioc_init.MaxDevices = (U8)ioc->devices_per_bus; 3355 ioc_init.MaxBuses = (U8)ioc->number_of_buses; 3356 3357 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n", 3358 ioc->name, ioc->facts.MsgVersion)); 3359 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) { 3360 // set MsgVersion and HeaderVersion host driver was built with 3361 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION); 3362 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION); 3363 3364 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) { 3365 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE; 3366 } else if(mpt_host_page_alloc(ioc, &ioc_init)) 3367 return -99; 3368 } 3369 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */ 3370 3371 if (ioc->sg_addr_size == sizeof(u64)) { 3372 /* Save the upper 32-bits of the request 3373 * (reply) and sense buffers. 3374 */ 3375 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32)); 3376 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32)); 3377 } else { 3378 /* Force 32-bit addressing */ 3379 ioc_init.HostMfaHighAddr = cpu_to_le32(0); 3380 ioc_init.SenseBufferHighAddr = cpu_to_le32(0); 3381 } 3382 3383 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr; 3384 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr; 3385 ioc->facts.MaxDevices = ioc_init.MaxDevices; 3386 ioc->facts.MaxBuses = ioc_init.MaxBuses; 3387 3388 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n", 3389 ioc->name, &ioc_init)); 3390 3391 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init, 3392 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag); 3393 if (r != 0) { 3394 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r); 3395 return r; 3396 } 3397 3398 /* No need to byte swap the multibyte fields in the reply 3399 * since we don't even look at its contents. 3400 */ 3401 3402 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n", 3403 ioc->name, &ioc_init)); 3404 3405 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) { 3406 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r); 3407 return r; 3408 } 3409 3410 /* YIKES! SUPER IMPORTANT!!! 3411 * Poll IocState until _OPERATIONAL while IOC is doing 3412 * LoopInit and TargetDiscovery! 3413 */ 3414 count = 0; 3415 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */ 3416 state = mpt_GetIocState(ioc, 1); 3417 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) { 3418 if (sleepFlag == CAN_SLEEP) { 3419 msleep(1); 3420 } else { 3421 mdelay(1); 3422 } 3423 3424 if (!cntdn) { 3425 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n", 3426 ioc->name, (int)((count+5)/HZ)); 3427 return -9; 3428 } 3429 3430 state = mpt_GetIocState(ioc, 1); 3431 count++; 3432 } 3433 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n", 3434 ioc->name, count)); 3435 3436 ioc->aen_event_read_flag=0; 3437 return r; 3438 } 3439 3440 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3441 /** 3442 * SendPortEnable - Send PortEnable request to MPT adapter port. 3443 * @ioc: Pointer to MPT_ADAPTER structure 3444 * @portnum: Port number to enable 3445 * @sleepFlag: Specifies whether the process can sleep 3446 * 3447 * Send PortEnable to bring IOC to OPERATIONAL state. 3448 * 3449 * Returns 0 for success, non-zero for failure. 3450 */ 3451 static int 3452 SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3453 { 3454 PortEnable_t port_enable; 3455 MPIDefaultReply_t reply_buf; 3456 int rc; 3457 int req_sz; 3458 int reply_sz; 3459 3460 /* Destination... */ 3461 reply_sz = sizeof(MPIDefaultReply_t); 3462 memset(&reply_buf, 0, reply_sz); 3463 3464 req_sz = sizeof(PortEnable_t); 3465 memset(&port_enable, 0, req_sz); 3466 3467 port_enable.Function = MPI_FUNCTION_PORT_ENABLE; 3468 port_enable.PortNumber = portnum; 3469 /* port_enable.ChainOffset = 0; */ 3470 /* port_enable.MsgFlags = 0; */ 3471 /* port_enable.MsgContext = 0; */ 3472 3473 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n", 3474 ioc->name, portnum, &port_enable)); 3475 3476 /* RAID FW may take a long time to enable 3477 */ 3478 if (ioc->ir_firmware || ioc->bus_type == SAS) { 3479 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3480 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3481 300 /*seconds*/, sleepFlag); 3482 } else { 3483 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3484 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3485 30 /*seconds*/, sleepFlag); 3486 } 3487 return rc; 3488 } 3489 3490 /** 3491 * mpt_alloc_fw_memory - allocate firmware memory 3492 * @ioc: Pointer to MPT_ADAPTER structure 3493 * @size: total FW bytes 3494 * 3495 * If memory has already been allocated, the same (cached) value 3496 * is returned. 3497 * 3498 * Return 0 if successful, or non-zero for failure 3499 **/ 3500 int 3501 mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size) 3502 { 3503 int rc; 3504 3505 if (ioc->cached_fw) { 3506 rc = 0; /* use already allocated memory */ 3507 goto out; 3508 } 3509 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 3510 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */ 3511 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma; 3512 rc = 0; 3513 goto out; 3514 } 3515 ioc->cached_fw = dma_alloc_coherent(&ioc->pcidev->dev, size, 3516 &ioc->cached_fw_dma, GFP_ATOMIC); 3517 if (!ioc->cached_fw) { 3518 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n", 3519 ioc->name); 3520 rc = -1; 3521 } else { 3522 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n", 3523 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size)); 3524 ioc->alloc_total += size; 3525 rc = 0; 3526 } 3527 out: 3528 return rc; 3529 } 3530 3531 /** 3532 * mpt_free_fw_memory - free firmware memory 3533 * @ioc: Pointer to MPT_ADAPTER structure 3534 * 3535 * If alt_img is NULL, delete from ioc structure. 3536 * Else, delete a secondary image in same format. 3537 **/ 3538 void 3539 mpt_free_fw_memory(MPT_ADAPTER *ioc) 3540 { 3541 int sz; 3542 3543 if (!ioc->cached_fw) 3544 return; 3545 3546 sz = ioc->facts.FWImageSize; 3547 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n", 3548 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3549 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->cached_fw, 3550 ioc->cached_fw_dma); 3551 ioc->alloc_total -= sz; 3552 ioc->cached_fw = NULL; 3553 } 3554 3555 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3556 /** 3557 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port. 3558 * @ioc: Pointer to MPT_ADAPTER structure 3559 * @sleepFlag: Specifies whether the process can sleep 3560 * 3561 * Returns 0 for success, >0 for handshake failure 3562 * <0 for fw upload failure. 3563 * 3564 * Remark: If bound IOC and a successful FWUpload was performed 3565 * on the bound IOC, the second image is discarded 3566 * and memory is free'd. Both channels must upload to prevent 3567 * IOC from running in degraded mode. 3568 */ 3569 static int 3570 mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag) 3571 { 3572 u8 reply[sizeof(FWUploadReply_t)]; 3573 FWUpload_t *prequest; 3574 FWUploadReply_t *preply; 3575 FWUploadTCSGE_t *ptcsge; 3576 u32 flagsLength; 3577 int ii, sz, reply_sz; 3578 int cmdStatus; 3579 int request_size; 3580 /* If the image size is 0, we are done. 3581 */ 3582 if ((sz = ioc->facts.FWImageSize) == 0) 3583 return 0; 3584 3585 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0) 3586 return -ENOMEM; 3587 3588 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n", 3589 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3590 3591 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) : 3592 kzalloc(ioc->req_sz, GFP_KERNEL); 3593 if (!prequest) { 3594 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed " 3595 "while allocating memory \n", ioc->name)); 3596 mpt_free_fw_memory(ioc); 3597 return -ENOMEM; 3598 } 3599 3600 preply = (FWUploadReply_t *)&reply; 3601 3602 reply_sz = sizeof(reply); 3603 memset(preply, 0, reply_sz); 3604 3605 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; 3606 prequest->Function = MPI_FUNCTION_FW_UPLOAD; 3607 3608 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL; 3609 ptcsge->DetailsLength = 12; 3610 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; 3611 ptcsge->ImageSize = cpu_to_le32(sz); 3612 ptcsge++; 3613 3614 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz; 3615 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma); 3616 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) + 3617 ioc->SGE_size; 3618 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload " 3619 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest, 3620 ioc->facts.FWImageSize, request_size)); 3621 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest); 3622 3623 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest, 3624 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag); 3625 3626 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed " 3627 "rc=%x \n", ioc->name, ii)); 3628 3629 cmdStatus = -EFAULT; 3630 if (ii == 0) { 3631 /* Handshake transfer was complete and successful. 3632 * Check the Reply Frame. 3633 */ 3634 int status; 3635 status = le16_to_cpu(preply->IOCStatus) & 3636 MPI_IOCSTATUS_MASK; 3637 if (status == MPI_IOCSTATUS_SUCCESS && 3638 ioc->facts.FWImageSize == 3639 le32_to_cpu(preply->ActualImageSize)) 3640 cmdStatus = 0; 3641 } 3642 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n", 3643 ioc->name, cmdStatus)); 3644 3645 3646 if (cmdStatus) { 3647 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, " 3648 "freeing image \n", ioc->name)); 3649 mpt_free_fw_memory(ioc); 3650 } 3651 kfree(prequest); 3652 3653 return cmdStatus; 3654 } 3655 3656 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3657 /** 3658 * mpt_downloadboot - DownloadBoot code 3659 * @ioc: Pointer to MPT_ADAPTER structure 3660 * @pFwHeader: Pointer to firmware header info 3661 * @sleepFlag: Specifies whether the process can sleep 3662 * 3663 * FwDownloadBoot requires Programmed IO access. 3664 * 3665 * Returns 0 for success 3666 * -1 FW Image size is 0 3667 * -2 No valid cached_fw Pointer 3668 * <0 for fw upload failure. 3669 */ 3670 static int 3671 mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag) 3672 { 3673 MpiExtImageHeader_t *pExtImage; 3674 u32 fwSize; 3675 u32 diag0val; 3676 int count; 3677 u32 *ptrFw; 3678 u32 diagRwData; 3679 u32 nextImage; 3680 u32 load_addr; 3681 u32 ioc_state=0; 3682 3683 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n", 3684 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader)); 3685 3686 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3687 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3688 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3689 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3690 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3691 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3692 3693 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM)); 3694 3695 /* wait 1 msec */ 3696 if (sleepFlag == CAN_SLEEP) { 3697 msleep(1); 3698 } else { 3699 mdelay (1); 3700 } 3701 3702 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3703 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 3704 3705 for (count = 0; count < 30; count ++) { 3706 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3707 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 3708 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n", 3709 ioc->name, count)); 3710 break; 3711 } 3712 /* wait .1 sec */ 3713 if (sleepFlag == CAN_SLEEP) { 3714 msleep (100); 3715 } else { 3716 mdelay (100); 3717 } 3718 } 3719 3720 if ( count == 30 ) { 3721 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! " 3722 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n", 3723 ioc->name, diag0val)); 3724 return -3; 3725 } 3726 3727 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3728 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3729 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3730 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3731 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3732 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3733 3734 /* Set the DiagRwEn and Disable ARM bits */ 3735 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM)); 3736 3737 fwSize = (pFwHeader->ImageSize + 3)/4; 3738 ptrFw = (u32 *) pFwHeader; 3739 3740 /* Write the LoadStartAddress to the DiagRw Address Register 3741 * using Programmed IO 3742 */ 3743 if (ioc->errata_flag_1064) 3744 pci_enable_io_access(ioc->pcidev); 3745 3746 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress); 3747 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n", 3748 ioc->name, pFwHeader->LoadStartAddress)); 3749 3750 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n", 3751 ioc->name, fwSize*4, ptrFw)); 3752 while (fwSize--) { 3753 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3754 } 3755 3756 nextImage = pFwHeader->NextImageHeaderOffset; 3757 while (nextImage) { 3758 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage); 3759 3760 load_addr = pExtImage->LoadStartAddress; 3761 3762 fwSize = (pExtImage->ImageSize + 3) >> 2; 3763 ptrFw = (u32 *)pExtImage; 3764 3765 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n", 3766 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr)); 3767 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr); 3768 3769 while (fwSize--) { 3770 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3771 } 3772 nextImage = pExtImage->NextImageHeaderOffset; 3773 } 3774 3775 /* Write the IopResetVectorRegAddr */ 3776 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr)); 3777 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr); 3778 3779 /* Write the IopResetVectorValue */ 3780 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue)); 3781 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue); 3782 3783 /* Clear the internal flash bad bit - autoincrementing register, 3784 * so must do two writes. 3785 */ 3786 if (ioc->bus_type == SPI) { 3787 /* 3788 * 1030 and 1035 H/W errata, workaround to access 3789 * the ClearFlashBadSignatureBit 3790 */ 3791 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3792 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData); 3793 diagRwData |= 0x40000000; 3794 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3795 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData); 3796 3797 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ { 3798 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3799 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | 3800 MPI_DIAG_CLEAR_FLASH_BAD_SIG); 3801 3802 /* wait 1 msec */ 3803 if (sleepFlag == CAN_SLEEP) { 3804 msleep (1); 3805 } else { 3806 mdelay (1); 3807 } 3808 } 3809 3810 if (ioc->errata_flag_1064) 3811 pci_disable_io_access(ioc->pcidev); 3812 3813 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3814 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, " 3815 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n", 3816 ioc->name, diag0val)); 3817 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE); 3818 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n", 3819 ioc->name, diag0val)); 3820 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 3821 3822 /* Write 0xFF to reset the sequencer */ 3823 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3824 3825 if (ioc->bus_type == SAS) { 3826 ioc_state = mpt_GetIocState(ioc, 0); 3827 if ( (GetIocFacts(ioc, sleepFlag, 3828 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) { 3829 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n", 3830 ioc->name, ioc_state)); 3831 return -EFAULT; 3832 } 3833 } 3834 3835 for (count=0; count<HZ*20; count++) { 3836 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) { 3837 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3838 "downloadboot successful! (count=%d) IocState=%x\n", 3839 ioc->name, count, ioc_state)); 3840 if (ioc->bus_type == SAS) { 3841 return 0; 3842 } 3843 if ((SendIocInit(ioc, sleepFlag)) != 0) { 3844 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3845 "downloadboot: SendIocInit failed\n", 3846 ioc->name)); 3847 return -EFAULT; 3848 } 3849 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3850 "downloadboot: SendIocInit successful\n", 3851 ioc->name)); 3852 return 0; 3853 } 3854 if (sleepFlag == CAN_SLEEP) { 3855 msleep (10); 3856 } else { 3857 mdelay (10); 3858 } 3859 } 3860 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3861 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state)); 3862 return -EFAULT; 3863 } 3864 3865 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3866 /** 3867 * KickStart - Perform hard reset of MPT adapter. 3868 * @ioc: Pointer to MPT_ADAPTER structure 3869 * @force: Force hard reset 3870 * @sleepFlag: Specifies whether the process can sleep 3871 * 3872 * This routine places MPT adapter in diagnostic mode via the 3873 * WriteSequence register, and then performs a hard reset of adapter 3874 * via the Diagnostic register. 3875 * 3876 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread) 3877 * or NO_SLEEP (interrupt thread, use mdelay) 3878 * force - 1 if doorbell active, board fault state 3879 * board operational, IOC_RECOVERY or 3880 * IOC_BRINGUP and there is an alt_ioc. 3881 * 0 else 3882 * 3883 * Returns: 3884 * 1 - hard reset, READY 3885 * 0 - no reset due to History bit, READY 3886 * -1 - no reset due to History bit but not READY 3887 * OR reset but failed to come READY 3888 * -2 - no reset, could not enter DIAG mode 3889 * -3 - reset but bad FW bit 3890 */ 3891 static int 3892 KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag) 3893 { 3894 int hard_reset_done = 0; 3895 u32 ioc_state=0; 3896 int cnt,cntdn; 3897 3898 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name)); 3899 if (ioc->bus_type == SPI) { 3900 /* Always issue a Msg Unit Reset first. This will clear some 3901 * SCSI bus hang conditions. 3902 */ 3903 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 3904 3905 if (sleepFlag == CAN_SLEEP) { 3906 msleep (1000); 3907 } else { 3908 mdelay (1000); 3909 } 3910 } 3911 3912 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag); 3913 if (hard_reset_done < 0) 3914 return hard_reset_done; 3915 3916 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n", 3917 ioc->name)); 3918 3919 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */ 3920 for (cnt=0; cnt<cntdn; cnt++) { 3921 ioc_state = mpt_GetIocState(ioc, 1); 3922 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) { 3923 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n", 3924 ioc->name, cnt)); 3925 return hard_reset_done; 3926 } 3927 if (sleepFlag == CAN_SLEEP) { 3928 msleep (10); 3929 } else { 3930 mdelay (10); 3931 } 3932 } 3933 3934 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n", 3935 ioc->name, mpt_GetIocState(ioc, 0))); 3936 return -1; 3937 } 3938 3939 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3940 /** 3941 * mpt_diag_reset - Perform hard reset of the adapter. 3942 * @ioc: Pointer to MPT_ADAPTER structure 3943 * @ignore: Set if to honor and clear to ignore 3944 * the reset history bit 3945 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread, 3946 * else set to NO_SLEEP (use mdelay instead) 3947 * 3948 * This routine places the adapter in diagnostic mode via the 3949 * WriteSequence register and then performs a hard reset of adapter 3950 * via the Diagnostic register. Adapter should be in ready state 3951 * upon successful completion. 3952 * 3953 * Returns: 1 hard reset successful 3954 * 0 no reset performed because reset history bit set 3955 * -2 enabling diagnostic mode failed 3956 * -3 diagnostic reset failed 3957 */ 3958 static int 3959 mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag) 3960 { 3961 u32 diag0val; 3962 u32 doorbell; 3963 int hard_reset_done = 0; 3964 int count = 0; 3965 u32 diag1val = 0; 3966 MpiFwHeader_t *cached_fw; /* Pointer to FW */ 3967 u8 cb_idx; 3968 3969 /* Clear any existing interrupts */ 3970 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 3971 3972 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) { 3973 3974 if (!ignore) 3975 return 0; 3976 3977 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset " 3978 "address=%p\n", ioc->name, __func__, 3979 &ioc->chip->Doorbell, &ioc->chip->Reset_1078)); 3980 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07); 3981 if (sleepFlag == CAN_SLEEP) 3982 msleep(1); 3983 else 3984 mdelay(1); 3985 3986 /* 3987 * Call each currently registered protocol IOC reset handler 3988 * with pre-reset indication. 3989 * NOTE: If we're doing _IOC_BRINGUP, there can be no 3990 * MptResetHandlers[] registered yet. 3991 */ 3992 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 3993 if (MptResetHandlers[cb_idx]) 3994 (*(MptResetHandlers[cb_idx]))(ioc, 3995 MPT_IOC_PRE_RESET); 3996 } 3997 3998 for (count = 0; count < 60; count ++) { 3999 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 4000 doorbell &= MPI_IOC_STATE_MASK; 4001 4002 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4003 "looking for READY STATE: doorbell=%x" 4004 " count=%d\n", 4005 ioc->name, doorbell, count)); 4006 4007 if (doorbell == MPI_IOC_STATE_READY) { 4008 return 1; 4009 } 4010 4011 /* wait 1 sec */ 4012 if (sleepFlag == CAN_SLEEP) 4013 msleep(1000); 4014 else 4015 mdelay(1000); 4016 } 4017 return -1; 4018 } 4019 4020 /* Use "Diagnostic reset" method! (only thing available!) */ 4021 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4022 4023 if (ioc->debug_level & MPT_DEBUG) { 4024 if (ioc->alt_ioc) 4025 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4026 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n", 4027 ioc->name, diag0val, diag1val)); 4028 } 4029 4030 /* Do the reset if we are told to ignore the reset history 4031 * or if the reset history is 0 4032 */ 4033 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) { 4034 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4035 /* Write magic sequence to WriteSequence register 4036 * Loop until in diagnostic mode 4037 */ 4038 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4039 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4040 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4041 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4042 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4043 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4044 4045 /* wait 100 msec */ 4046 if (sleepFlag == CAN_SLEEP) { 4047 msleep (100); 4048 } else { 4049 mdelay (100); 4050 } 4051 4052 count++; 4053 if (count > 20) { 4054 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4055 ioc->name, diag0val); 4056 return -2; 4057 4058 } 4059 4060 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4061 4062 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n", 4063 ioc->name, diag0val)); 4064 } 4065 4066 if (ioc->debug_level & MPT_DEBUG) { 4067 if (ioc->alt_ioc) 4068 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4069 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n", 4070 ioc->name, diag0val, diag1val)); 4071 } 4072 /* 4073 * Disable the ARM (Bug fix) 4074 * 4075 */ 4076 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM); 4077 mdelay(1); 4078 4079 /* 4080 * Now hit the reset bit in the Diagnostic register 4081 * (THE BIG HAMMER!) (Clears DRWE bit). 4082 */ 4083 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 4084 hard_reset_done = 1; 4085 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n", 4086 ioc->name)); 4087 4088 /* 4089 * Call each currently registered protocol IOC reset handler 4090 * with pre-reset indication. 4091 * NOTE: If we're doing _IOC_BRINGUP, there can be no 4092 * MptResetHandlers[] registered yet. 4093 */ 4094 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 4095 if (MptResetHandlers[cb_idx]) { 4096 mpt_signal_reset(cb_idx, 4097 ioc, MPT_IOC_PRE_RESET); 4098 if (ioc->alt_ioc) { 4099 mpt_signal_reset(cb_idx, 4100 ioc->alt_ioc, MPT_IOC_PRE_RESET); 4101 } 4102 } 4103 } 4104 4105 if (ioc->cached_fw) 4106 cached_fw = (MpiFwHeader_t *)ioc->cached_fw; 4107 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) 4108 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw; 4109 else 4110 cached_fw = NULL; 4111 if (cached_fw) { 4112 /* If the DownloadBoot operation fails, the 4113 * IOC will be left unusable. This is a fatal error 4114 * case. _diag_reset will return < 0 4115 */ 4116 for (count = 0; count < 30; count ++) { 4117 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4118 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 4119 break; 4120 } 4121 4122 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n", 4123 ioc->name, diag0val, count)); 4124 /* wait 1 sec */ 4125 if (sleepFlag == CAN_SLEEP) { 4126 msleep (1000); 4127 } else { 4128 mdelay (1000); 4129 } 4130 } 4131 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) { 4132 printk(MYIOC_s_WARN_FMT 4133 "firmware downloadboot failure (%d)!\n", ioc->name, count); 4134 } 4135 4136 } else { 4137 /* Wait for FW to reload and for board 4138 * to go to the READY state. 4139 * Maximum wait is 60 seconds. 4140 * If fail, no error will check again 4141 * with calling program. 4142 */ 4143 for (count = 0; count < 60; count ++) { 4144 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 4145 doorbell &= MPI_IOC_STATE_MASK; 4146 4147 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4148 "looking for READY STATE: doorbell=%x" 4149 " count=%d\n", ioc->name, doorbell, count)); 4150 4151 if (doorbell == MPI_IOC_STATE_READY) { 4152 break; 4153 } 4154 4155 /* wait 1 sec */ 4156 if (sleepFlag == CAN_SLEEP) { 4157 msleep (1000); 4158 } else { 4159 mdelay (1000); 4160 } 4161 } 4162 4163 if (doorbell != MPI_IOC_STATE_READY) 4164 printk(MYIOC_s_ERR_FMT "Failed to come READY " 4165 "after reset! IocState=%x", ioc->name, 4166 doorbell); 4167 } 4168 } 4169 4170 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4171 if (ioc->debug_level & MPT_DEBUG) { 4172 if (ioc->alt_ioc) 4173 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4174 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n", 4175 ioc->name, diag0val, diag1val)); 4176 } 4177 4178 /* Clear RESET_HISTORY bit! Place board in the 4179 * diagnostic mode to update the diag register. 4180 */ 4181 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4182 count = 0; 4183 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4184 /* Write magic sequence to WriteSequence register 4185 * Loop until in diagnostic mode 4186 */ 4187 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4188 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4189 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4190 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4191 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4192 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4193 4194 /* wait 100 msec */ 4195 if (sleepFlag == CAN_SLEEP) { 4196 msleep (100); 4197 } else { 4198 mdelay (100); 4199 } 4200 4201 count++; 4202 if (count > 20) { 4203 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4204 ioc->name, diag0val); 4205 break; 4206 } 4207 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4208 } 4209 diag0val &= ~MPI_DIAG_RESET_HISTORY; 4210 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 4211 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4212 if (diag0val & MPI_DIAG_RESET_HISTORY) { 4213 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n", 4214 ioc->name); 4215 } 4216 4217 /* Disable Diagnostic Mode 4218 */ 4219 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF); 4220 4221 /* Check FW reload status flags. 4222 */ 4223 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4224 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) { 4225 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n", 4226 ioc->name, diag0val); 4227 return -3; 4228 } 4229 4230 if (ioc->debug_level & MPT_DEBUG) { 4231 if (ioc->alt_ioc) 4232 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4233 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n", 4234 ioc->name, diag0val, diag1val)); 4235 } 4236 4237 /* 4238 * Reset flag that says we've enabled event notification 4239 */ 4240 ioc->facts.EventState = 0; 4241 4242 if (ioc->alt_ioc) 4243 ioc->alt_ioc->facts.EventState = 0; 4244 4245 return hard_reset_done; 4246 } 4247 4248 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4249 /** 4250 * SendIocReset - Send IOCReset request to MPT adapter. 4251 * @ioc: Pointer to MPT_ADAPTER structure 4252 * @reset_type: reset type, expected values are 4253 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET 4254 * @sleepFlag: Specifies whether the process can sleep 4255 * 4256 * Send IOCReset request to the MPT adapter. 4257 * 4258 * Returns 0 for success, non-zero for failure. 4259 */ 4260 static int 4261 SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag) 4262 { 4263 int r; 4264 u32 state; 4265 int cntdn, count; 4266 4267 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n", 4268 ioc->name, reset_type)); 4269 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT); 4270 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4271 return r; 4272 4273 /* FW ACK'd request, wait for READY state 4274 */ 4275 count = 0; 4276 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */ 4277 4278 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 4279 cntdn--; 4280 count++; 4281 if (!cntdn) { 4282 if (sleepFlag != CAN_SLEEP) 4283 count *= 10; 4284 4285 printk(MYIOC_s_ERR_FMT 4286 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 4287 ioc->name, state, (int)((count+5)/HZ)); 4288 return -ETIME; 4289 } 4290 4291 if (sleepFlag == CAN_SLEEP) { 4292 msleep(1); 4293 } else { 4294 mdelay (1); /* 1 msec delay */ 4295 } 4296 } 4297 4298 /* TODO! 4299 * Cleanup all event stuff for this IOC; re-issue EventNotification 4300 * request if needed. 4301 */ 4302 if (ioc->facts.Function) 4303 ioc->facts.EventState = 0; 4304 4305 return 0; 4306 } 4307 4308 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4309 /** 4310 * initChainBuffers - Allocate memory for and initialize chain buffers 4311 * @ioc: Pointer to MPT_ADAPTER structure 4312 * 4313 * Allocates memory for and initializes chain buffers, 4314 * chain buffer control arrays and spinlock. 4315 */ 4316 static int 4317 initChainBuffers(MPT_ADAPTER *ioc) 4318 { 4319 u8 *mem; 4320 int sz, ii, num_chain; 4321 int scale, num_sge, numSGE; 4322 4323 /* ReqToChain size must equal the req_depth 4324 * index = req_idx 4325 */ 4326 if (ioc->ReqToChain == NULL) { 4327 sz = ioc->req_depth * sizeof(int); 4328 mem = kmalloc(sz, GFP_ATOMIC); 4329 if (mem == NULL) 4330 return -1; 4331 4332 ioc->ReqToChain = (int *) mem; 4333 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n", 4334 ioc->name, mem, sz)); 4335 mem = kmalloc(sz, GFP_ATOMIC); 4336 if (mem == NULL) 4337 return -1; 4338 4339 ioc->RequestNB = (int *) mem; 4340 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n", 4341 ioc->name, mem, sz)); 4342 } 4343 for (ii = 0; ii < ioc->req_depth; ii++) { 4344 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN; 4345 } 4346 4347 /* ChainToChain size must equal the total number 4348 * of chain buffers to be allocated. 4349 * index = chain_idx 4350 * 4351 * Calculate the number of chain buffers needed(plus 1) per I/O 4352 * then multiply the maximum number of simultaneous cmds 4353 * 4354 * num_sge = num sge in request frame + last chain buffer 4355 * scale = num sge per chain buffer if no chain element 4356 */ 4357 scale = ioc->req_sz / ioc->SGE_size; 4358 if (ioc->sg_addr_size == sizeof(u64)) 4359 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size; 4360 else 4361 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size; 4362 4363 if (ioc->sg_addr_size == sizeof(u64)) { 4364 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale + 4365 (ioc->req_sz - 60) / ioc->SGE_size; 4366 } else { 4367 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) + 4368 scale + (ioc->req_sz - 64) / ioc->SGE_size; 4369 } 4370 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n", 4371 ioc->name, num_sge, numSGE)); 4372 4373 if (ioc->bus_type == FC) { 4374 if (numSGE > MPT_SCSI_FC_SG_DEPTH) 4375 numSGE = MPT_SCSI_FC_SG_DEPTH; 4376 } else { 4377 if (numSGE > MPT_SCSI_SG_DEPTH) 4378 numSGE = MPT_SCSI_SG_DEPTH; 4379 } 4380 4381 num_chain = 1; 4382 while (numSGE - num_sge > 0) { 4383 num_chain++; 4384 num_sge += (scale - 1); 4385 } 4386 num_chain++; 4387 4388 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n", 4389 ioc->name, numSGE, num_sge, num_chain)); 4390 4391 if (ioc->bus_type == SPI) 4392 num_chain *= MPT_SCSI_CAN_QUEUE; 4393 else if (ioc->bus_type == SAS) 4394 num_chain *= MPT_SAS_CAN_QUEUE; 4395 else 4396 num_chain *= MPT_FC_CAN_QUEUE; 4397 4398 ioc->num_chain = num_chain; 4399 4400 sz = num_chain * sizeof(int); 4401 if (ioc->ChainToChain == NULL) { 4402 mem = kmalloc(sz, GFP_ATOMIC); 4403 if (mem == NULL) 4404 return -1; 4405 4406 ioc->ChainToChain = (int *) mem; 4407 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n", 4408 ioc->name, mem, sz)); 4409 } else { 4410 mem = (u8 *) ioc->ChainToChain; 4411 } 4412 memset(mem, 0xFF, sz); 4413 return num_chain; 4414 } 4415 4416 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4417 /** 4418 * PrimeIocFifos - Initialize IOC request and reply FIFOs. 4419 * @ioc: Pointer to MPT_ADAPTER structure 4420 * 4421 * This routine allocates memory for the MPT reply and request frame 4422 * pools (if necessary), and primes the IOC reply FIFO with 4423 * reply frames. 4424 * 4425 * Returns 0 for success, non-zero for failure. 4426 */ 4427 static int 4428 PrimeIocFifos(MPT_ADAPTER *ioc) 4429 { 4430 MPT_FRAME_HDR *mf; 4431 unsigned long flags; 4432 dma_addr_t alloc_dma; 4433 u8 *mem; 4434 int i, reply_sz, sz, total_size, num_chain; 4435 u64 dma_mask; 4436 4437 dma_mask = 0; 4438 4439 /* Prime reply FIFO... */ 4440 4441 if (ioc->reply_frames == NULL) { 4442 if ( (num_chain = initChainBuffers(ioc)) < 0) 4443 return -1; 4444 /* 4445 * 1078 errata workaround for the 36GB limitation 4446 */ 4447 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 && 4448 ioc->dma_mask > DMA_BIT_MASK(35)) { 4449 if (!dma_set_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32)) 4450 && !dma_set_coherent_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32))) { 4451 dma_mask = DMA_BIT_MASK(35); 4452 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4453 "setting 35 bit addressing for " 4454 "Request/Reply/Chain and Sense Buffers\n", 4455 ioc->name)); 4456 } else { 4457 /*Reseting DMA mask to 64 bit*/ 4458 dma_set_mask(&ioc->pcidev->dev, 4459 DMA_BIT_MASK(64)); 4460 dma_set_coherent_mask(&ioc->pcidev->dev, 4461 DMA_BIT_MASK(64)); 4462 4463 printk(MYIOC_s_ERR_FMT 4464 "failed setting 35 bit addressing for " 4465 "Request/Reply/Chain and Sense Buffers\n", 4466 ioc->name); 4467 return -1; 4468 } 4469 } 4470 4471 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth); 4472 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n", 4473 ioc->name, ioc->reply_sz, ioc->reply_depth)); 4474 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n", 4475 ioc->name, reply_sz, reply_sz)); 4476 4477 sz = (ioc->req_sz * ioc->req_depth); 4478 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n", 4479 ioc->name, ioc->req_sz, ioc->req_depth)); 4480 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n", 4481 ioc->name, sz, sz)); 4482 total_size += sz; 4483 4484 sz = num_chain * ioc->req_sz; /* chain buffer pool size */ 4485 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n", 4486 ioc->name, ioc->req_sz, num_chain)); 4487 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n", 4488 ioc->name, sz, sz, num_chain)); 4489 4490 total_size += sz; 4491 mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size, 4492 &alloc_dma, GFP_KERNEL); 4493 if (mem == NULL) { 4494 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n", 4495 ioc->name); 4496 goto out_fail; 4497 } 4498 4499 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n", 4500 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size)); 4501 4502 memset(mem, 0, total_size); 4503 ioc->alloc_total += total_size; 4504 ioc->alloc = mem; 4505 ioc->alloc_dma = alloc_dma; 4506 ioc->alloc_sz = total_size; 4507 ioc->reply_frames = (MPT_FRAME_HDR *) mem; 4508 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4509 4510 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4511 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4512 4513 alloc_dma += reply_sz; 4514 mem += reply_sz; 4515 4516 /* Request FIFO - WE manage this! */ 4517 4518 ioc->req_frames = (MPT_FRAME_HDR *) mem; 4519 ioc->req_frames_dma = alloc_dma; 4520 4521 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n", 4522 ioc->name, mem, (void *)(ulong)alloc_dma)); 4523 4524 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4525 4526 for (i = 0; i < ioc->req_depth; i++) { 4527 alloc_dma += ioc->req_sz; 4528 mem += ioc->req_sz; 4529 } 4530 4531 ioc->ChainBuffer = mem; 4532 ioc->ChainBufferDMA = alloc_dma; 4533 4534 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n", 4535 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA)); 4536 4537 /* Initialize the free chain Q. 4538 */ 4539 4540 INIT_LIST_HEAD(&ioc->FreeChainQ); 4541 4542 /* Post the chain buffers to the FreeChainQ. 4543 */ 4544 mem = (u8 *)ioc->ChainBuffer; 4545 for (i=0; i < num_chain; i++) { 4546 mf = (MPT_FRAME_HDR *) mem; 4547 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ); 4548 mem += ioc->req_sz; 4549 } 4550 4551 /* Initialize Request frames linked list 4552 */ 4553 alloc_dma = ioc->req_frames_dma; 4554 mem = (u8 *) ioc->req_frames; 4555 4556 spin_lock_irqsave(&ioc->FreeQlock, flags); 4557 INIT_LIST_HEAD(&ioc->FreeQ); 4558 for (i = 0; i < ioc->req_depth; i++) { 4559 mf = (MPT_FRAME_HDR *) mem; 4560 4561 /* Queue REQUESTs *internally*! */ 4562 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ); 4563 4564 mem += ioc->req_sz; 4565 } 4566 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 4567 4568 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4569 ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz, 4570 &ioc->sense_buf_pool_dma, GFP_KERNEL); 4571 if (ioc->sense_buf_pool == NULL) { 4572 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n", 4573 ioc->name); 4574 goto out_fail; 4575 } 4576 4577 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF); 4578 ioc->alloc_total += sz; 4579 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n", 4580 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma)); 4581 4582 } 4583 4584 /* Post Reply frames to FIFO 4585 */ 4586 alloc_dma = ioc->alloc_dma; 4587 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4588 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4589 4590 for (i = 0; i < ioc->reply_depth; i++) { 4591 /* Write each address to the IOC! */ 4592 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma); 4593 alloc_dma += ioc->reply_sz; 4594 } 4595 4596 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev, 4597 ioc->dma_mask) && !dma_set_coherent_mask(&ioc->pcidev->dev, 4598 ioc->dma_mask)) 4599 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4600 "restoring 64 bit addressing\n", ioc->name)); 4601 4602 return 0; 4603 4604 out_fail: 4605 4606 if (ioc->alloc != NULL) { 4607 sz = ioc->alloc_sz; 4608 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 4609 ioc->alloc_dma); 4610 ioc->reply_frames = NULL; 4611 ioc->req_frames = NULL; 4612 ioc->alloc_total -= sz; 4613 } 4614 if (ioc->sense_buf_pool != NULL) { 4615 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4616 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 4617 ioc->sense_buf_pool_dma); 4618 ioc->sense_buf_pool = NULL; 4619 } 4620 4621 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev, 4622 DMA_BIT_MASK(64)) && !dma_set_coherent_mask(&ioc->pcidev->dev, 4623 DMA_BIT_MASK(64))) 4624 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4625 "restoring 64 bit addressing\n", ioc->name)); 4626 4627 return -1; 4628 } 4629 4630 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4631 /** 4632 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply 4633 * from IOC via doorbell handshake method. 4634 * @ioc: Pointer to MPT_ADAPTER structure 4635 * @reqBytes: Size of the request in bytes 4636 * @req: Pointer to MPT request frame 4637 * @replyBytes: Expected size of the reply in bytes 4638 * @u16reply: Pointer to area where reply should be written 4639 * @maxwait: Max wait time for a reply (in seconds) 4640 * @sleepFlag: Specifies whether the process can sleep 4641 * 4642 * NOTES: It is the callers responsibility to byte-swap fields in the 4643 * request which are greater than 1 byte in size. It is also the 4644 * callers responsibility to byte-swap response fields which are 4645 * greater than 1 byte in size. 4646 * 4647 * Returns 0 for success, non-zero for failure. 4648 */ 4649 static int 4650 mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req, 4651 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag) 4652 { 4653 MPIDefaultReply_t *mptReply; 4654 int failcnt = 0; 4655 int t; 4656 4657 /* 4658 * Get ready to cache a handshake reply 4659 */ 4660 ioc->hs_reply_idx = 0; 4661 mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4662 mptReply->MsgLength = 0; 4663 4664 /* 4665 * Make sure there are no doorbells (WRITE 0 to IntStatus reg), 4666 * then tell IOC that we want to handshake a request of N words. 4667 * (WRITE u32val to Doorbell reg). 4668 */ 4669 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4670 CHIPREG_WRITE32(&ioc->chip->Doorbell, 4671 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 4672 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 4673 4674 /* 4675 * Wait for IOC's doorbell handshake int 4676 */ 4677 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4678 failcnt++; 4679 4680 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n", 4681 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4682 4683 /* Read doorbell and check for active bit */ 4684 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 4685 return -1; 4686 4687 /* 4688 * Clear doorbell int (WRITE 0 to IntStatus reg), 4689 * then wait for IOC to ACKnowledge that it's ready for 4690 * our handshake request. 4691 */ 4692 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4693 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4694 failcnt++; 4695 4696 if (!failcnt) { 4697 int ii; 4698 u8 *req_as_bytes = (u8 *) req; 4699 4700 /* 4701 * Stuff request words via doorbell handshake, 4702 * with ACK from IOC for each. 4703 */ 4704 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) { 4705 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) | 4706 (req_as_bytes[(ii*4) + 1] << 8) | 4707 (req_as_bytes[(ii*4) + 2] << 16) | 4708 (req_as_bytes[(ii*4) + 3] << 24)); 4709 4710 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 4711 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4712 failcnt++; 4713 } 4714 4715 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req)); 4716 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req); 4717 4718 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n", 4719 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : "")); 4720 4721 /* 4722 * Wait for completion of doorbell handshake reply from the IOC 4723 */ 4724 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0) 4725 failcnt++; 4726 4727 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n", 4728 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : "")); 4729 4730 /* 4731 * Copy out the cached reply... 4732 */ 4733 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++) 4734 u16reply[ii] = ioc->hs_reply[ii]; 4735 } else { 4736 return -99; 4737 } 4738 4739 return -failcnt; 4740 } 4741 4742 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4743 /** 4744 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge 4745 * @ioc: Pointer to MPT_ADAPTER structure 4746 * @howlong: How long to wait (in seconds) 4747 * @sleepFlag: Specifies whether the process can sleep 4748 * 4749 * This routine waits (up to ~2 seconds max) for IOC doorbell 4750 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS 4751 * bit in its IntStatus register being clear. 4752 * 4753 * Returns a negative value on failure, else wait loop count. 4754 */ 4755 static int 4756 WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4757 { 4758 int cntdn; 4759 int count = 0; 4760 u32 intstat=0; 4761 4762 cntdn = 1000 * howlong; 4763 4764 if (sleepFlag == CAN_SLEEP) { 4765 while (--cntdn) { 4766 msleep (1); 4767 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4768 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4769 break; 4770 count++; 4771 } 4772 } else { 4773 while (--cntdn) { 4774 udelay (1000); 4775 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4776 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4777 break; 4778 count++; 4779 } 4780 } 4781 4782 if (cntdn) { 4783 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n", 4784 ioc->name, count)); 4785 return count; 4786 } 4787 4788 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n", 4789 ioc->name, count, intstat); 4790 return -1; 4791 } 4792 4793 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4794 /** 4795 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit 4796 * @ioc: Pointer to MPT_ADAPTER structure 4797 * @howlong: How long to wait (in seconds) 4798 * @sleepFlag: Specifies whether the process can sleep 4799 * 4800 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt 4801 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register. 4802 * 4803 * Returns a negative value on failure, else wait loop count. 4804 */ 4805 static int 4806 WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4807 { 4808 int cntdn; 4809 int count = 0; 4810 u32 intstat=0; 4811 4812 cntdn = 1000 * howlong; 4813 if (sleepFlag == CAN_SLEEP) { 4814 while (--cntdn) { 4815 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4816 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4817 break; 4818 msleep(1); 4819 count++; 4820 } 4821 } else { 4822 while (--cntdn) { 4823 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4824 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4825 break; 4826 udelay (1000); 4827 count++; 4828 } 4829 } 4830 4831 if (cntdn) { 4832 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n", 4833 ioc->name, count, howlong)); 4834 return count; 4835 } 4836 4837 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n", 4838 ioc->name, count, intstat); 4839 return -1; 4840 } 4841 4842 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4843 /** 4844 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply. 4845 * @ioc: Pointer to MPT_ADAPTER structure 4846 * @howlong: How long to wait (in seconds) 4847 * @sleepFlag: Specifies whether the process can sleep 4848 * 4849 * This routine polls the IOC for a handshake reply, 16 bits at a time. 4850 * Reply is cached to IOC private area large enough to hold a maximum 4851 * of 128 bytes of reply data. 4852 * 4853 * Returns a negative value on failure, else size of reply in WORDS. 4854 */ 4855 static int 4856 WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4857 { 4858 int u16cnt = 0; 4859 int failcnt = 0; 4860 int t; 4861 u16 *hs_reply = ioc->hs_reply; 4862 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4863 u16 hword; 4864 4865 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0; 4866 4867 /* 4868 * Get first two u16's so we can look at IOC's intended reply MsgLength 4869 */ 4870 u16cnt=0; 4871 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) { 4872 failcnt++; 4873 } else { 4874 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4875 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4876 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4877 failcnt++; 4878 else { 4879 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4880 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4881 } 4882 } 4883 4884 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n", 4885 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply), 4886 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4887 4888 /* 4889 * If no error (and IOC said MsgLength is > 0), piece together 4890 * reply 16 bits at a time. 4891 */ 4892 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) { 4893 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4894 failcnt++; 4895 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4896 /* don't overflow our IOC hs_reply[] buffer! */ 4897 if (u16cnt < ARRAY_SIZE(ioc->hs_reply)) 4898 hs_reply[u16cnt] = hword; 4899 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4900 } 4901 4902 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4903 failcnt++; 4904 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4905 4906 if (failcnt) { 4907 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n", 4908 ioc->name); 4909 return -failcnt; 4910 } 4911 #if 0 4912 else if (u16cnt != (2 * mptReply->MsgLength)) { 4913 return -101; 4914 } 4915 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 4916 return -102; 4917 } 4918 #endif 4919 4920 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name)); 4921 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply); 4922 4923 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n", 4924 ioc->name, t, u16cnt/2)); 4925 return u16cnt/2; 4926 } 4927 4928 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4929 /** 4930 * GetLanConfigPages - Fetch LANConfig pages. 4931 * @ioc: Pointer to MPT_ADAPTER structure 4932 * 4933 * Return: 0 for success 4934 * -ENOMEM if no memory available 4935 * -EPERM if not allowed due to ISR context 4936 * -EAGAIN if no msg frames currently available 4937 * -EFAULT for non-successful reply or no reply (timeout) 4938 */ 4939 static int 4940 GetLanConfigPages(MPT_ADAPTER *ioc) 4941 { 4942 ConfigPageHeader_t hdr; 4943 CONFIGPARMS cfg; 4944 LANPage0_t *ppage0_alloc; 4945 dma_addr_t page0_dma; 4946 LANPage1_t *ppage1_alloc; 4947 dma_addr_t page1_dma; 4948 int rc = 0; 4949 int data_sz; 4950 int copy_sz; 4951 4952 /* Get LAN Page 0 header */ 4953 hdr.PageVersion = 0; 4954 hdr.PageLength = 0; 4955 hdr.PageNumber = 0; 4956 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 4957 cfg.cfghdr.hdr = &hdr; 4958 cfg.physAddr = -1; 4959 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 4960 cfg.dir = 0; 4961 cfg.pageAddr = 0; 4962 cfg.timeout = 0; 4963 4964 if ((rc = mpt_config(ioc, &cfg)) != 0) 4965 return rc; 4966 4967 if (hdr.PageLength > 0) { 4968 data_sz = hdr.PageLength * 4; 4969 ppage0_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma); 4970 rc = -ENOMEM; 4971 if (ppage0_alloc) { 4972 memset((u8 *)ppage0_alloc, 0, data_sz); 4973 cfg.physAddr = page0_dma; 4974 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 4975 4976 if ((rc = mpt_config(ioc, &cfg)) == 0) { 4977 /* save the data */ 4978 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz); 4979 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz); 4980 4981 } 4982 4983 dma_free_coherent(&ioc->pcidev->dev, data_sz, 4984 (u8 *)ppage0_alloc, page0_dma); 4985 4986 /* FIXME! 4987 * Normalize endianness of structure data, 4988 * by byte-swapping all > 1 byte fields! 4989 */ 4990 4991 } 4992 4993 if (rc) 4994 return rc; 4995 } 4996 4997 /* Get LAN Page 1 header */ 4998 hdr.PageVersion = 0; 4999 hdr.PageLength = 0; 5000 hdr.PageNumber = 1; 5001 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 5002 cfg.cfghdr.hdr = &hdr; 5003 cfg.physAddr = -1; 5004 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5005 cfg.dir = 0; 5006 cfg.pageAddr = 0; 5007 5008 if ((rc = mpt_config(ioc, &cfg)) != 0) 5009 return rc; 5010 5011 if (hdr.PageLength == 0) 5012 return 0; 5013 5014 data_sz = hdr.PageLength * 4; 5015 rc = -ENOMEM; 5016 ppage1_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma); 5017 if (ppage1_alloc) { 5018 memset((u8 *)ppage1_alloc, 0, data_sz); 5019 cfg.physAddr = page1_dma; 5020 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5021 5022 if ((rc = mpt_config(ioc, &cfg)) == 0) { 5023 /* save the data */ 5024 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz); 5025 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz); 5026 } 5027 5028 dma_free_coherent(&ioc->pcidev->dev, data_sz, 5029 (u8 *)ppage1_alloc, page1_dma); 5030 5031 /* FIXME! 5032 * Normalize endianness of structure data, 5033 * by byte-swapping all > 1 byte fields! 5034 */ 5035 5036 } 5037 5038 return rc; 5039 } 5040 5041 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5042 /** 5043 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table 5044 * @ioc: Pointer to MPT_ADAPTER structure 5045 * @persist_opcode: see below 5046 * 5047 * =============================== ====================================== 5048 * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for 5049 * devices not currently present. 5050 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings 5051 * =============================== ====================================== 5052 * 5053 * NOTE: Don't use not this function during interrupt time. 5054 * 5055 * Returns 0 for success, non-zero error 5056 */ 5057 5058 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5059 int 5060 mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode) 5061 { 5062 SasIoUnitControlRequest_t *sasIoUnitCntrReq; 5063 SasIoUnitControlReply_t *sasIoUnitCntrReply; 5064 MPT_FRAME_HDR *mf = NULL; 5065 MPIHeader_t *mpi_hdr; 5066 int ret = 0; 5067 unsigned long timeleft; 5068 5069 mutex_lock(&ioc->mptbase_cmds.mutex); 5070 5071 /* init the internal cmd struct */ 5072 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 5073 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 5074 5075 /* insure garbage is not sent to fw */ 5076 switch(persist_opcode) { 5077 5078 case MPI_SAS_OP_CLEAR_NOT_PRESENT: 5079 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT: 5080 break; 5081 5082 default: 5083 ret = -1; 5084 goto out; 5085 } 5086 5087 printk(KERN_DEBUG "%s: persist_opcode=%x\n", 5088 __func__, persist_opcode); 5089 5090 /* Get a MF for this command. 5091 */ 5092 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 5093 printk(KERN_DEBUG "%s: no msg frames!\n", __func__); 5094 ret = -1; 5095 goto out; 5096 } 5097 5098 mpi_hdr = (MPIHeader_t *) mf; 5099 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf; 5100 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t)); 5101 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL; 5102 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext; 5103 sasIoUnitCntrReq->Operation = persist_opcode; 5104 5105 mpt_put_msg_frame(mpt_base_index, ioc, mf); 5106 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ); 5107 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 5108 ret = -ETIME; 5109 printk(KERN_DEBUG "%s: failed\n", __func__); 5110 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 5111 goto out; 5112 if (!timeleft) { 5113 printk(MYIOC_s_WARN_FMT 5114 "Issuing Reset from %s!!, doorbell=0x%08x\n", 5115 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 5116 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP); 5117 mpt_free_msg_frame(ioc, mf); 5118 } 5119 goto out; 5120 } 5121 5122 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 5123 ret = -1; 5124 goto out; 5125 } 5126 5127 sasIoUnitCntrReply = 5128 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply; 5129 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) { 5130 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n", 5131 __func__, sasIoUnitCntrReply->IOCStatus, 5132 sasIoUnitCntrReply->IOCLogInfo); 5133 printk(KERN_DEBUG "%s: failed\n", __func__); 5134 ret = -1; 5135 } else 5136 printk(KERN_DEBUG "%s: success\n", __func__); 5137 out: 5138 5139 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 5140 mutex_unlock(&ioc->mptbase_cmds.mutex); 5141 return ret; 5142 } 5143 5144 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5145 5146 static void 5147 mptbase_raid_process_event_data(MPT_ADAPTER *ioc, 5148 MpiEventDataRaid_t * pRaidEventData) 5149 { 5150 int volume; 5151 int reason; 5152 int disk; 5153 int status; 5154 int flags; 5155 int state; 5156 5157 volume = pRaidEventData->VolumeID; 5158 reason = pRaidEventData->ReasonCode; 5159 disk = pRaidEventData->PhysDiskNum; 5160 status = le32_to_cpu(pRaidEventData->SettingsStatus); 5161 flags = (status >> 0) & 0xff; 5162 state = (status >> 8) & 0xff; 5163 5164 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) { 5165 return; 5166 } 5167 5168 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED && 5169 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) || 5170 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) { 5171 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n", 5172 ioc->name, disk, volume); 5173 } else { 5174 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n", 5175 ioc->name, volume); 5176 } 5177 5178 switch(reason) { 5179 case MPI_EVENT_RAID_RC_VOLUME_CREATED: 5180 printk(MYIOC_s_INFO_FMT " volume has been created\n", 5181 ioc->name); 5182 break; 5183 5184 case MPI_EVENT_RAID_RC_VOLUME_DELETED: 5185 5186 printk(MYIOC_s_INFO_FMT " volume has been deleted\n", 5187 ioc->name); 5188 break; 5189 5190 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED: 5191 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n", 5192 ioc->name); 5193 break; 5194 5195 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED: 5196 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n", 5197 ioc->name, 5198 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL 5199 ? "optimal" 5200 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED 5201 ? "degraded" 5202 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED 5203 ? "failed" 5204 : "state unknown", 5205 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED 5206 ? ", enabled" : "", 5207 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED 5208 ? ", quiesced" : "", 5209 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 5210 ? ", resync in progress" : "" ); 5211 break; 5212 5213 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED: 5214 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n", 5215 ioc->name, disk); 5216 break; 5217 5218 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED: 5219 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n", 5220 ioc->name); 5221 break; 5222 5223 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED: 5224 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n", 5225 ioc->name); 5226 break; 5227 5228 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED: 5229 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n", 5230 ioc->name); 5231 break; 5232 5233 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED: 5234 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n", 5235 ioc->name, 5236 state == MPI_PHYSDISK0_STATUS_ONLINE 5237 ? "online" 5238 : state == MPI_PHYSDISK0_STATUS_MISSING 5239 ? "missing" 5240 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE 5241 ? "not compatible" 5242 : state == MPI_PHYSDISK0_STATUS_FAILED 5243 ? "failed" 5244 : state == MPI_PHYSDISK0_STATUS_INITIALIZING 5245 ? "initializing" 5246 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED 5247 ? "offline requested" 5248 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED 5249 ? "failed requested" 5250 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE 5251 ? "offline" 5252 : "state unknown", 5253 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 5254 ? ", out of sync" : "", 5255 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED 5256 ? ", quiesced" : "" ); 5257 break; 5258 5259 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED: 5260 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n", 5261 ioc->name, disk); 5262 break; 5263 5264 case MPI_EVENT_RAID_RC_SMART_DATA: 5265 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n", 5266 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ); 5267 break; 5268 5269 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED: 5270 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n", 5271 ioc->name, disk); 5272 break; 5273 } 5274 } 5275 5276 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5277 /** 5278 * GetIoUnitPage2 - Retrieve BIOS version and boot order information. 5279 * @ioc: Pointer to MPT_ADAPTER structure 5280 * 5281 * Returns: 0 for success 5282 * -ENOMEM if no memory available 5283 * -EPERM if not allowed due to ISR context 5284 * -EAGAIN if no msg frames currently available 5285 * -EFAULT for non-successful reply or no reply (timeout) 5286 */ 5287 static int 5288 GetIoUnitPage2(MPT_ADAPTER *ioc) 5289 { 5290 ConfigPageHeader_t hdr; 5291 CONFIGPARMS cfg; 5292 IOUnitPage2_t *ppage_alloc; 5293 dma_addr_t page_dma; 5294 int data_sz; 5295 int rc; 5296 5297 /* Get the page header */ 5298 hdr.PageVersion = 0; 5299 hdr.PageLength = 0; 5300 hdr.PageNumber = 2; 5301 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT; 5302 cfg.cfghdr.hdr = &hdr; 5303 cfg.physAddr = -1; 5304 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5305 cfg.dir = 0; 5306 cfg.pageAddr = 0; 5307 cfg.timeout = 0; 5308 5309 if ((rc = mpt_config(ioc, &cfg)) != 0) 5310 return rc; 5311 5312 if (hdr.PageLength == 0) 5313 return 0; 5314 5315 /* Read the config page */ 5316 data_sz = hdr.PageLength * 4; 5317 rc = -ENOMEM; 5318 ppage_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma); 5319 if (ppage_alloc) { 5320 memset((u8 *)ppage_alloc, 0, data_sz); 5321 cfg.physAddr = page_dma; 5322 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5323 5324 /* If Good, save data */ 5325 if ((rc = mpt_config(ioc, &cfg)) == 0) 5326 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion); 5327 5328 dma_free_coherent(&ioc->pcidev->dev, data_sz, 5329 (u8 *)ppage_alloc, page_dma); 5330 } 5331 5332 return rc; 5333 } 5334 5335 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5336 /** 5337 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2 5338 * @ioc: Pointer to a Adapter Strucutre 5339 * @portnum: IOC port number 5340 * 5341 * Return: -EFAULT if read of config page header fails 5342 * or if no nvram 5343 * If read of SCSI Port Page 0 fails, 5344 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5345 * Adapter settings: async, narrow 5346 * Return 1 5347 * If read of SCSI Port Page 2 fails, 5348 * Adapter settings valid 5349 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5350 * Return 1 5351 * Else 5352 * Both valid 5353 * Return 0 5354 * CHECK - what type of locking mechanisms should be used???? 5355 */ 5356 static int 5357 mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum) 5358 { 5359 u8 *pbuf; 5360 dma_addr_t buf_dma; 5361 CONFIGPARMS cfg; 5362 ConfigPageHeader_t header; 5363 int ii; 5364 int data, rc = 0; 5365 5366 /* Allocate memory 5367 */ 5368 if (!ioc->spi_data.nvram) { 5369 int sz; 5370 u8 *mem; 5371 sz = MPT_MAX_SCSI_DEVICES * sizeof(int); 5372 mem = kmalloc(sz, GFP_ATOMIC); 5373 if (mem == NULL) 5374 return -EFAULT; 5375 5376 ioc->spi_data.nvram = (int *) mem; 5377 5378 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n", 5379 ioc->name, ioc->spi_data.nvram, sz)); 5380 } 5381 5382 /* Invalidate NVRAM information 5383 */ 5384 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5385 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID; 5386 } 5387 5388 /* Read SPP0 header, allocate memory, then read page. 5389 */ 5390 header.PageVersion = 0; 5391 header.PageLength = 0; 5392 header.PageNumber = 0; 5393 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5394 cfg.cfghdr.hdr = &header; 5395 cfg.physAddr = -1; 5396 cfg.pageAddr = portnum; 5397 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5398 cfg.dir = 0; 5399 cfg.timeout = 0; /* use default */ 5400 if (mpt_config(ioc, &cfg) != 0) 5401 return -EFAULT; 5402 5403 if (header.PageLength > 0) { 5404 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5405 if (pbuf) { 5406 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5407 cfg.physAddr = buf_dma; 5408 if (mpt_config(ioc, &cfg) != 0) { 5409 ioc->spi_data.maxBusWidth = MPT_NARROW; 5410 ioc->spi_data.maxSyncOffset = 0; 5411 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5412 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN; 5413 rc = 1; 5414 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5415 "Unable to read PortPage0 minSyncFactor=%x\n", 5416 ioc->name, ioc->spi_data.minSyncFactor)); 5417 } else { 5418 /* Save the Port Page 0 data 5419 */ 5420 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf; 5421 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities); 5422 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface); 5423 5424 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) { 5425 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS; 5426 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5427 "noQas due to Capabilities=%x\n", 5428 ioc->name, pPP0->Capabilities)); 5429 } 5430 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0; 5431 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK; 5432 if (data) { 5433 ioc->spi_data.maxSyncOffset = (u8) (data >> 16); 5434 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK; 5435 ioc->spi_data.minSyncFactor = (u8) (data >> 8); 5436 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5437 "PortPage0 minSyncFactor=%x\n", 5438 ioc->name, ioc->spi_data.minSyncFactor)); 5439 } else { 5440 ioc->spi_data.maxSyncOffset = 0; 5441 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5442 } 5443 5444 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK; 5445 5446 /* Update the minSyncFactor based on bus type. 5447 */ 5448 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) || 5449 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) { 5450 5451 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) { 5452 ioc->spi_data.minSyncFactor = MPT_ULTRA; 5453 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5454 "HVD or SE detected, minSyncFactor=%x\n", 5455 ioc->name, ioc->spi_data.minSyncFactor)); 5456 } 5457 } 5458 } 5459 if (pbuf) { 5460 dma_free_coherent(&ioc->pcidev->dev, 5461 header.PageLength * 4, pbuf, 5462 buf_dma); 5463 } 5464 } 5465 } 5466 5467 /* SCSI Port Page 2 - Read the header then the page. 5468 */ 5469 header.PageVersion = 0; 5470 header.PageLength = 0; 5471 header.PageNumber = 2; 5472 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5473 cfg.cfghdr.hdr = &header; 5474 cfg.physAddr = -1; 5475 cfg.pageAddr = portnum; 5476 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5477 cfg.dir = 0; 5478 if (mpt_config(ioc, &cfg) != 0) 5479 return -EFAULT; 5480 5481 if (header.PageLength > 0) { 5482 /* Allocate memory and read SCSI Port Page 2 5483 */ 5484 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5485 if (pbuf) { 5486 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM; 5487 cfg.physAddr = buf_dma; 5488 if (mpt_config(ioc, &cfg) != 0) { 5489 /* Nvram data is left with INVALID mark 5490 */ 5491 rc = 1; 5492 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) { 5493 5494 /* This is an ATTO adapter, read Page2 accordingly 5495 */ 5496 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf; 5497 ATTODeviceInfo_t *pdevice = NULL; 5498 u16 ATTOFlags; 5499 5500 /* Save the Port Page 2 data 5501 * (reformat into a 32bit quantity) 5502 */ 5503 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5504 pdevice = &pPP2->DeviceSettings[ii]; 5505 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags); 5506 data = 0; 5507 5508 /* Translate ATTO device flags to LSI format 5509 */ 5510 if (ATTOFlags & ATTOFLAG_DISC) 5511 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE); 5512 if (ATTOFlags & ATTOFLAG_ID_ENB) 5513 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE); 5514 if (ATTOFlags & ATTOFLAG_LUN_ENB) 5515 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE); 5516 if (ATTOFlags & ATTOFLAG_TAGGED) 5517 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE); 5518 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB)) 5519 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE); 5520 5521 data = (data << 16) | (pdevice->Period << 8) | 10; 5522 ioc->spi_data.nvram[ii] = data; 5523 } 5524 } else { 5525 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf; 5526 MpiDeviceInfo_t *pdevice = NULL; 5527 5528 /* 5529 * Save "Set to Avoid SCSI Bus Resets" flag 5530 */ 5531 ioc->spi_data.bus_reset = 5532 (le32_to_cpu(pPP2->PortFlags) & 5533 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ? 5534 0 : 1 ; 5535 5536 /* Save the Port Page 2 data 5537 * (reformat into a 32bit quantity) 5538 */ 5539 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK; 5540 ioc->spi_data.PortFlags = data; 5541 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5542 pdevice = &pPP2->DeviceSettings[ii]; 5543 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) | 5544 (pdevice->SyncFactor << 8) | pdevice->Timeout; 5545 ioc->spi_data.nvram[ii] = data; 5546 } 5547 } 5548 5549 dma_free_coherent(&ioc->pcidev->dev, 5550 header.PageLength * 4, pbuf, 5551 buf_dma); 5552 } 5553 } 5554 5555 /* Update Adapter limits with those from NVRAM 5556 * Comment: Don't need to do this. Target performance 5557 * parameters will never exceed the adapters limits. 5558 */ 5559 5560 return rc; 5561 } 5562 5563 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5564 /** 5565 * mpt_readScsiDevicePageHeaders - save version and length of SDP1 5566 * @ioc: Pointer to a Adapter Strucutre 5567 * @portnum: IOC port number 5568 * 5569 * Return: -EFAULT if read of config page header fails 5570 * or 0 if success. 5571 */ 5572 static int 5573 mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum) 5574 { 5575 CONFIGPARMS cfg; 5576 ConfigPageHeader_t header; 5577 5578 /* Read the SCSI Device Page 1 header 5579 */ 5580 header.PageVersion = 0; 5581 header.PageLength = 0; 5582 header.PageNumber = 1; 5583 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5584 cfg.cfghdr.hdr = &header; 5585 cfg.physAddr = -1; 5586 cfg.pageAddr = portnum; 5587 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5588 cfg.dir = 0; 5589 cfg.timeout = 0; 5590 if (mpt_config(ioc, &cfg) != 0) 5591 return -EFAULT; 5592 5593 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion; 5594 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength; 5595 5596 header.PageVersion = 0; 5597 header.PageLength = 0; 5598 header.PageNumber = 0; 5599 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5600 if (mpt_config(ioc, &cfg) != 0) 5601 return -EFAULT; 5602 5603 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion; 5604 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength; 5605 5606 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n", 5607 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length)); 5608 5609 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n", 5610 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length)); 5611 return 0; 5612 } 5613 5614 /** 5615 * mpt_inactive_raid_list_free - This clears this link list. 5616 * @ioc : pointer to per adapter structure 5617 **/ 5618 static void 5619 mpt_inactive_raid_list_free(MPT_ADAPTER *ioc) 5620 { 5621 struct inactive_raid_component_info *component_info, *pNext; 5622 5623 if (list_empty(&ioc->raid_data.inactive_list)) 5624 return; 5625 5626 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5627 list_for_each_entry_safe(component_info, pNext, 5628 &ioc->raid_data.inactive_list, list) { 5629 list_del(&component_info->list); 5630 kfree(component_info); 5631 } 5632 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5633 } 5634 5635 /** 5636 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume 5637 * 5638 * @ioc : pointer to per adapter structure 5639 * @channel : volume channel 5640 * @id : volume target id 5641 **/ 5642 static void 5643 mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id) 5644 { 5645 CONFIGPARMS cfg; 5646 ConfigPageHeader_t hdr; 5647 dma_addr_t dma_handle; 5648 pRaidVolumePage0_t buffer = NULL; 5649 int i; 5650 RaidPhysDiskPage0_t phys_disk; 5651 struct inactive_raid_component_info *component_info; 5652 int handle_inactive_volumes; 5653 5654 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5655 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5656 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME; 5657 cfg.pageAddr = (channel << 8) + id; 5658 cfg.cfghdr.hdr = &hdr; 5659 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5660 5661 if (mpt_config(ioc, &cfg) != 0) 5662 goto out; 5663 5664 if (!hdr.PageLength) 5665 goto out; 5666 5667 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5668 &dma_handle); 5669 5670 if (!buffer) 5671 goto out; 5672 5673 cfg.physAddr = dma_handle; 5674 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5675 5676 if (mpt_config(ioc, &cfg) != 0) 5677 goto out; 5678 5679 if (!buffer->NumPhysDisks) 5680 goto out; 5681 5682 handle_inactive_volumes = 5683 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE || 5684 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 || 5685 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED || 5686 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0; 5687 5688 if (!handle_inactive_volumes) 5689 goto out; 5690 5691 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5692 for (i = 0; i < buffer->NumPhysDisks; i++) { 5693 if(mpt_raid_phys_disk_pg0(ioc, 5694 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) 5695 continue; 5696 5697 if ((component_info = kmalloc(sizeof (*component_info), 5698 GFP_KERNEL)) == NULL) 5699 continue; 5700 5701 component_info->volumeID = id; 5702 component_info->volumeBus = channel; 5703 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum; 5704 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus; 5705 component_info->d.PhysDiskID = phys_disk.PhysDiskID; 5706 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC; 5707 5708 list_add_tail(&component_info->list, 5709 &ioc->raid_data.inactive_list); 5710 } 5711 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5712 5713 out: 5714 if (buffer) 5715 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5716 buffer, dma_handle); 5717 } 5718 5719 /** 5720 * mpt_raid_phys_disk_pg0 - returns phys disk page zero 5721 * @ioc: Pointer to a Adapter Structure 5722 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5723 * @phys_disk: requested payload data returned 5724 * 5725 * Return: 5726 * 0 on success 5727 * -EFAULT if read of config page header fails or data pointer not NULL 5728 * -ENOMEM if pci_alloc failed 5729 **/ 5730 int 5731 mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, 5732 RaidPhysDiskPage0_t *phys_disk) 5733 { 5734 CONFIGPARMS cfg; 5735 ConfigPageHeader_t hdr; 5736 dma_addr_t dma_handle; 5737 pRaidPhysDiskPage0_t buffer = NULL; 5738 int rc; 5739 5740 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5741 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5742 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t)); 5743 5744 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION; 5745 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5746 cfg.cfghdr.hdr = &hdr; 5747 cfg.physAddr = -1; 5748 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5749 5750 if (mpt_config(ioc, &cfg) != 0) { 5751 rc = -EFAULT; 5752 goto out; 5753 } 5754 5755 if (!hdr.PageLength) { 5756 rc = -EFAULT; 5757 goto out; 5758 } 5759 5760 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5761 &dma_handle); 5762 5763 if (!buffer) { 5764 rc = -ENOMEM; 5765 goto out; 5766 } 5767 5768 cfg.physAddr = dma_handle; 5769 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5770 cfg.pageAddr = phys_disk_num; 5771 5772 if (mpt_config(ioc, &cfg) != 0) { 5773 rc = -EFAULT; 5774 goto out; 5775 } 5776 5777 rc = 0; 5778 memcpy(phys_disk, buffer, sizeof(*buffer)); 5779 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA); 5780 5781 out: 5782 5783 if (buffer) 5784 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5785 buffer, dma_handle); 5786 5787 return rc; 5788 } 5789 5790 /** 5791 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num 5792 * @ioc: Pointer to a Adapter Structure 5793 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5794 * 5795 * Return: 5796 * returns number paths 5797 **/ 5798 int 5799 mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num) 5800 { 5801 CONFIGPARMS cfg; 5802 ConfigPageHeader_t hdr; 5803 dma_addr_t dma_handle; 5804 pRaidPhysDiskPage1_t buffer = NULL; 5805 int rc; 5806 5807 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5808 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5809 5810 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5811 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5812 hdr.PageNumber = 1; 5813 cfg.cfghdr.hdr = &hdr; 5814 cfg.physAddr = -1; 5815 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5816 5817 if (mpt_config(ioc, &cfg) != 0) { 5818 rc = 0; 5819 goto out; 5820 } 5821 5822 if (!hdr.PageLength) { 5823 rc = 0; 5824 goto out; 5825 } 5826 5827 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5828 &dma_handle); 5829 5830 if (!buffer) { 5831 rc = 0; 5832 goto out; 5833 } 5834 5835 cfg.physAddr = dma_handle; 5836 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5837 cfg.pageAddr = phys_disk_num; 5838 5839 if (mpt_config(ioc, &cfg) != 0) { 5840 rc = 0; 5841 goto out; 5842 } 5843 5844 rc = buffer->NumPhysDiskPaths; 5845 out: 5846 5847 if (buffer) 5848 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5849 buffer, dma_handle); 5850 5851 return rc; 5852 } 5853 EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths); 5854 5855 /** 5856 * mpt_raid_phys_disk_pg1 - returns phys disk page 1 5857 * @ioc: Pointer to a Adapter Structure 5858 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5859 * @phys_disk: requested payload data returned 5860 * 5861 * Return: 5862 * 0 on success 5863 * -EFAULT if read of config page header fails or data pointer not NULL 5864 * -ENOMEM if pci_alloc failed 5865 **/ 5866 int 5867 mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, 5868 RaidPhysDiskPage1_t *phys_disk) 5869 { 5870 CONFIGPARMS cfg; 5871 ConfigPageHeader_t hdr; 5872 dma_addr_t dma_handle; 5873 pRaidPhysDiskPage1_t buffer = NULL; 5874 int rc; 5875 int i; 5876 __le64 sas_address; 5877 5878 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5879 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5880 rc = 0; 5881 5882 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5883 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5884 hdr.PageNumber = 1; 5885 cfg.cfghdr.hdr = &hdr; 5886 cfg.physAddr = -1; 5887 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5888 5889 if (mpt_config(ioc, &cfg) != 0) { 5890 rc = -EFAULT; 5891 goto out; 5892 } 5893 5894 if (!hdr.PageLength) { 5895 rc = -EFAULT; 5896 goto out; 5897 } 5898 5899 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5900 &dma_handle); 5901 5902 if (!buffer) { 5903 rc = -ENOMEM; 5904 goto out; 5905 } 5906 5907 cfg.physAddr = dma_handle; 5908 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5909 cfg.pageAddr = phys_disk_num; 5910 5911 if (mpt_config(ioc, &cfg) != 0) { 5912 rc = -EFAULT; 5913 goto out; 5914 } 5915 5916 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths; 5917 phys_disk->PhysDiskNum = phys_disk_num; 5918 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) { 5919 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID; 5920 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus; 5921 phys_disk->Path[i].OwnerIdentifier = 5922 buffer->Path[i].OwnerIdentifier; 5923 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags); 5924 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64)); 5925 sas_address = le64_to_cpu(sas_address); 5926 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64)); 5927 memcpy(&sas_address, 5928 &buffer->Path[i].OwnerWWID, sizeof(__le64)); 5929 sas_address = le64_to_cpu(sas_address); 5930 memcpy(&phys_disk->Path[i].OwnerWWID, 5931 &sas_address, sizeof(__le64)); 5932 } 5933 5934 out: 5935 5936 if (buffer) 5937 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, 5938 buffer, dma_handle); 5939 5940 return rc; 5941 } 5942 EXPORT_SYMBOL(mpt_raid_phys_disk_pg1); 5943 5944 5945 /** 5946 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes 5947 * @ioc: Pointer to a Adapter Strucutre 5948 * 5949 * Return: 5950 * 0 on success 5951 * -EFAULT if read of config page header fails or data pointer not NULL 5952 * -ENOMEM if pci_alloc failed 5953 **/ 5954 int 5955 mpt_findImVolumes(MPT_ADAPTER *ioc) 5956 { 5957 IOCPage2_t *pIoc2; 5958 u8 *mem; 5959 dma_addr_t ioc2_dma; 5960 CONFIGPARMS cfg; 5961 ConfigPageHeader_t header; 5962 int rc = 0; 5963 int iocpage2sz; 5964 int i; 5965 5966 if (!ioc->ir_firmware) 5967 return 0; 5968 5969 /* Free the old page 5970 */ 5971 kfree(ioc->raid_data.pIocPg2); 5972 ioc->raid_data.pIocPg2 = NULL; 5973 mpt_inactive_raid_list_free(ioc); 5974 5975 /* Read IOCP2 header then the page. 5976 */ 5977 header.PageVersion = 0; 5978 header.PageLength = 0; 5979 header.PageNumber = 2; 5980 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 5981 cfg.cfghdr.hdr = &header; 5982 cfg.physAddr = -1; 5983 cfg.pageAddr = 0; 5984 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5985 cfg.dir = 0; 5986 cfg.timeout = 0; 5987 if (mpt_config(ioc, &cfg) != 0) 5988 return -EFAULT; 5989 5990 if (header.PageLength == 0) 5991 return -EFAULT; 5992 5993 iocpage2sz = header.PageLength * 4; 5994 pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma); 5995 if (!pIoc2) 5996 return -ENOMEM; 5997 5998 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5999 cfg.physAddr = ioc2_dma; 6000 if (mpt_config(ioc, &cfg) != 0) 6001 goto out; 6002 6003 mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL); 6004 if (!mem) { 6005 rc = -ENOMEM; 6006 goto out; 6007 } 6008 6009 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem; 6010 6011 mpt_read_ioc_pg_3(ioc); 6012 6013 for (i = 0; i < pIoc2->NumActiveVolumes ; i++) 6014 mpt_inactive_raid_volumes(ioc, 6015 pIoc2->RaidVolume[i].VolumeBus, 6016 pIoc2->RaidVolume[i].VolumeID); 6017 6018 out: 6019 dma_free_coherent(&ioc->pcidev->dev, iocpage2sz, pIoc2, ioc2_dma); 6020 6021 return rc; 6022 } 6023 6024 static int 6025 mpt_read_ioc_pg_3(MPT_ADAPTER *ioc) 6026 { 6027 IOCPage3_t *pIoc3; 6028 u8 *mem; 6029 CONFIGPARMS cfg; 6030 ConfigPageHeader_t header; 6031 dma_addr_t ioc3_dma; 6032 int iocpage3sz = 0; 6033 6034 /* Free the old page 6035 */ 6036 kfree(ioc->raid_data.pIocPg3); 6037 ioc->raid_data.pIocPg3 = NULL; 6038 6039 /* There is at least one physical disk. 6040 * Read and save IOC Page 3 6041 */ 6042 header.PageVersion = 0; 6043 header.PageLength = 0; 6044 header.PageNumber = 3; 6045 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6046 cfg.cfghdr.hdr = &header; 6047 cfg.physAddr = -1; 6048 cfg.pageAddr = 0; 6049 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6050 cfg.dir = 0; 6051 cfg.timeout = 0; 6052 if (mpt_config(ioc, &cfg) != 0) 6053 return 0; 6054 6055 if (header.PageLength == 0) 6056 return 0; 6057 6058 /* Read Header good, alloc memory 6059 */ 6060 iocpage3sz = header.PageLength * 4; 6061 pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma); 6062 if (!pIoc3) 6063 return 0; 6064 6065 /* Read the Page and save the data 6066 * into malloc'd memory. 6067 */ 6068 cfg.physAddr = ioc3_dma; 6069 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6070 if (mpt_config(ioc, &cfg) == 0) { 6071 mem = kmalloc(iocpage3sz, GFP_KERNEL); 6072 if (mem) { 6073 memcpy(mem, (u8 *)pIoc3, iocpage3sz); 6074 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem; 6075 } 6076 } 6077 6078 dma_free_coherent(&ioc->pcidev->dev, iocpage3sz, pIoc3, ioc3_dma); 6079 6080 return 0; 6081 } 6082 6083 static void 6084 mpt_read_ioc_pg_4(MPT_ADAPTER *ioc) 6085 { 6086 IOCPage4_t *pIoc4; 6087 CONFIGPARMS cfg; 6088 ConfigPageHeader_t header; 6089 dma_addr_t ioc4_dma; 6090 int iocpage4sz; 6091 6092 /* Read and save IOC Page 4 6093 */ 6094 header.PageVersion = 0; 6095 header.PageLength = 0; 6096 header.PageNumber = 4; 6097 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6098 cfg.cfghdr.hdr = &header; 6099 cfg.physAddr = -1; 6100 cfg.pageAddr = 0; 6101 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6102 cfg.dir = 0; 6103 cfg.timeout = 0; 6104 if (mpt_config(ioc, &cfg) != 0) 6105 return; 6106 6107 if (header.PageLength == 0) 6108 return; 6109 6110 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) { 6111 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */ 6112 pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma); 6113 if (!pIoc4) 6114 return; 6115 ioc->alloc_total += iocpage4sz; 6116 } else { 6117 ioc4_dma = ioc->spi_data.IocPg4_dma; 6118 iocpage4sz = ioc->spi_data.IocPg4Sz; 6119 } 6120 6121 /* Read the Page into dma memory. 6122 */ 6123 cfg.physAddr = ioc4_dma; 6124 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6125 if (mpt_config(ioc, &cfg) == 0) { 6126 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4; 6127 ioc->spi_data.IocPg4_dma = ioc4_dma; 6128 ioc->spi_data.IocPg4Sz = iocpage4sz; 6129 } else { 6130 dma_free_coherent(&ioc->pcidev->dev, iocpage4sz, pIoc4, 6131 ioc4_dma); 6132 ioc->spi_data.pIocPg4 = NULL; 6133 ioc->alloc_total -= iocpage4sz; 6134 } 6135 } 6136 6137 static void 6138 mpt_read_ioc_pg_1(MPT_ADAPTER *ioc) 6139 { 6140 IOCPage1_t *pIoc1; 6141 CONFIGPARMS cfg; 6142 ConfigPageHeader_t header; 6143 dma_addr_t ioc1_dma; 6144 int iocpage1sz = 0; 6145 u32 tmp; 6146 6147 /* Check the Coalescing Timeout in IOC Page 1 6148 */ 6149 header.PageVersion = 0; 6150 header.PageLength = 0; 6151 header.PageNumber = 1; 6152 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6153 cfg.cfghdr.hdr = &header; 6154 cfg.physAddr = -1; 6155 cfg.pageAddr = 0; 6156 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6157 cfg.dir = 0; 6158 cfg.timeout = 0; 6159 if (mpt_config(ioc, &cfg) != 0) 6160 return; 6161 6162 if (header.PageLength == 0) 6163 return; 6164 6165 /* Read Header good, alloc memory 6166 */ 6167 iocpage1sz = header.PageLength * 4; 6168 pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma); 6169 if (!pIoc1) 6170 return; 6171 6172 /* Read the Page and check coalescing timeout 6173 */ 6174 cfg.physAddr = ioc1_dma; 6175 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6176 if (mpt_config(ioc, &cfg) == 0) { 6177 6178 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING; 6179 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) { 6180 tmp = le32_to_cpu(pIoc1->CoalescingTimeout); 6181 6182 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n", 6183 ioc->name, tmp)); 6184 6185 if (tmp > MPT_COALESCING_TIMEOUT) { 6186 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT); 6187 6188 /* Write NVRAM and current 6189 */ 6190 cfg.dir = 1; 6191 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT; 6192 if (mpt_config(ioc, &cfg) == 0) { 6193 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n", 6194 ioc->name, MPT_COALESCING_TIMEOUT)); 6195 6196 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM; 6197 if (mpt_config(ioc, &cfg) == 0) { 6198 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6199 "Reset NVRAM Coalescing Timeout to = %d\n", 6200 ioc->name, MPT_COALESCING_TIMEOUT)); 6201 } else { 6202 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6203 "Reset NVRAM Coalescing Timeout Failed\n", 6204 ioc->name)); 6205 } 6206 6207 } else { 6208 dprintk(ioc, printk(MYIOC_s_WARN_FMT 6209 "Reset of Current Coalescing Timeout Failed!\n", 6210 ioc->name)); 6211 } 6212 } 6213 6214 } else { 6215 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name)); 6216 } 6217 } 6218 6219 dma_free_coherent(&ioc->pcidev->dev, iocpage1sz, pIoc1, ioc1_dma); 6220 6221 return; 6222 } 6223 6224 static void 6225 mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc) 6226 { 6227 CONFIGPARMS cfg; 6228 ConfigPageHeader_t hdr; 6229 dma_addr_t buf_dma; 6230 ManufacturingPage0_t *pbuf = NULL; 6231 6232 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 6233 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 6234 6235 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING; 6236 cfg.cfghdr.hdr = &hdr; 6237 cfg.physAddr = -1; 6238 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6239 cfg.timeout = 10; 6240 6241 if (mpt_config(ioc, &cfg) != 0) 6242 goto out; 6243 6244 if (!cfg.cfghdr.hdr->PageLength) 6245 goto out; 6246 6247 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6248 pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma); 6249 if (!pbuf) 6250 goto out; 6251 6252 cfg.physAddr = buf_dma; 6253 6254 if (mpt_config(ioc, &cfg) != 0) 6255 goto out; 6256 6257 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name)); 6258 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly)); 6259 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer)); 6260 6261 out: 6262 6263 if (pbuf) 6264 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, pbuf, 6265 buf_dma); 6266 } 6267 6268 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6269 /** 6270 * SendEventNotification - Send EventNotification (on or off) request to adapter 6271 * @ioc: Pointer to MPT_ADAPTER structure 6272 * @EvSwitch: Event switch flags 6273 * @sleepFlag: Specifies whether the process can sleep 6274 */ 6275 static int 6276 SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag) 6277 { 6278 EventNotification_t evn; 6279 MPIDefaultReply_t reply_buf; 6280 6281 memset(&evn, 0, sizeof(EventNotification_t)); 6282 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t)); 6283 6284 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION; 6285 evn.Switch = EvSwitch; 6286 evn.MsgContext = cpu_to_le32(mpt_base_index << 16); 6287 6288 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6289 "Sending EventNotification (%d) request %p\n", 6290 ioc->name, EvSwitch, &evn)); 6291 6292 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t), 6293 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30, 6294 sleepFlag); 6295 } 6296 6297 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6298 /** 6299 * SendEventAck - Send EventAck request to MPT adapter. 6300 * @ioc: Pointer to MPT_ADAPTER structure 6301 * @evnp: Pointer to original EventNotification request 6302 */ 6303 static int 6304 SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp) 6305 { 6306 EventAck_t *pAck; 6307 6308 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6309 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n", 6310 ioc->name, __func__)); 6311 return -1; 6312 } 6313 6314 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name)); 6315 6316 pAck->Function = MPI_FUNCTION_EVENT_ACK; 6317 pAck->ChainOffset = 0; 6318 pAck->Reserved[0] = pAck->Reserved[1] = 0; 6319 pAck->MsgFlags = 0; 6320 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0; 6321 pAck->Event = evnp->Event; 6322 pAck->EventContext = evnp->EventContext; 6323 6324 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck); 6325 6326 return 0; 6327 } 6328 6329 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6330 /** 6331 * mpt_config - Generic function to issue config message 6332 * @ioc: Pointer to an adapter structure 6333 * @pCfg: Pointer to a configuration structure. Struct contains 6334 * action, page address, direction, physical address 6335 * and pointer to a configuration page header 6336 * Page header is updated. 6337 * 6338 * Returns 0 for success 6339 * -EAGAIN if no msg frames currently available 6340 * -EFAULT for non-successful reply or no reply (timeout) 6341 */ 6342 int 6343 mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg) 6344 { 6345 Config_t *pReq; 6346 ConfigReply_t *pReply; 6347 ConfigExtendedPageHeader_t *pExtHdr = NULL; 6348 MPT_FRAME_HDR *mf; 6349 int ii; 6350 int flagsLength; 6351 long timeout; 6352 int ret; 6353 u8 page_type = 0, extend_page; 6354 unsigned long timeleft; 6355 unsigned long flags; 6356 u8 issue_hard_reset = 0; 6357 u8 retry_count = 0; 6358 6359 might_sleep(); 6360 6361 /* don't send a config page during diag reset */ 6362 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6363 if (ioc->ioc_reset_in_progress) { 6364 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6365 "%s: busy with host reset\n", ioc->name, __func__)); 6366 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6367 return -EBUSY; 6368 } 6369 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6370 6371 /* don't send if no chance of success */ 6372 if (!ioc->active || 6373 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) { 6374 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6375 "%s: ioc not operational, %d, %xh\n", 6376 ioc->name, __func__, ioc->active, 6377 mpt_GetIocState(ioc, 0))); 6378 return -EFAULT; 6379 } 6380 6381 retry_config: 6382 mutex_lock(&ioc->mptbase_cmds.mutex); 6383 /* init the internal cmd struct */ 6384 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 6385 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 6386 6387 /* Get and Populate a free Frame 6388 */ 6389 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6390 dcprintk(ioc, printk(MYIOC_s_WARN_FMT 6391 "mpt_config: no msg frames!\n", ioc->name)); 6392 ret = -EAGAIN; 6393 goto out; 6394 } 6395 6396 pReq = (Config_t *)mf; 6397 pReq->Action = pCfg->action; 6398 pReq->Reserved = 0; 6399 pReq->ChainOffset = 0; 6400 pReq->Function = MPI_FUNCTION_CONFIG; 6401 6402 /* Assume page type is not extended and clear "reserved" fields. */ 6403 pReq->ExtPageLength = 0; 6404 pReq->ExtPageType = 0; 6405 pReq->MsgFlags = 0; 6406 6407 for (ii=0; ii < 8; ii++) 6408 pReq->Reserved2[ii] = 0; 6409 6410 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion; 6411 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength; 6412 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber; 6413 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); 6414 6415 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) { 6416 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr; 6417 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength); 6418 pReq->ExtPageType = pExtHdr->ExtPageType; 6419 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 6420 6421 /* Page Length must be treated as a reserved field for the 6422 * extended header. 6423 */ 6424 pReq->Header.PageLength = 0; 6425 } 6426 6427 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr); 6428 6429 /* Add a SGE to the config request. 6430 */ 6431 if (pCfg->dir) 6432 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE; 6433 else 6434 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ; 6435 6436 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == 6437 MPI_CONFIG_PAGETYPE_EXTENDED) { 6438 flagsLength |= pExtHdr->ExtPageLength * 4; 6439 page_type = pReq->ExtPageType; 6440 extend_page = 1; 6441 } else { 6442 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4; 6443 page_type = pReq->Header.PageType; 6444 extend_page = 0; 6445 } 6446 6447 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6448 "Sending Config request type 0x%x, page 0x%x and action %d\n", 6449 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action)); 6450 6451 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr); 6452 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout; 6453 mpt_put_msg_frame(mpt_base_index, ioc, mf); 6454 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 6455 timeout); 6456 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 6457 ret = -ETIME; 6458 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6459 "Failed Sending Config request type 0x%x, page 0x%x," 6460 " action %d, status %xh, time left %ld\n\n", 6461 ioc->name, page_type, pReq->Header.PageNumber, 6462 pReq->Action, ioc->mptbase_cmds.status, timeleft)); 6463 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 6464 goto out; 6465 if (!timeleft) { 6466 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6467 if (ioc->ioc_reset_in_progress) { 6468 spin_unlock_irqrestore(&ioc->taskmgmt_lock, 6469 flags); 6470 printk(MYIOC_s_INFO_FMT "%s: host reset in" 6471 " progress mpt_config timed out.!!\n", 6472 __func__, ioc->name); 6473 mutex_unlock(&ioc->mptbase_cmds.mutex); 6474 return -EFAULT; 6475 } 6476 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6477 issue_hard_reset = 1; 6478 } 6479 goto out; 6480 } 6481 6482 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 6483 ret = -1; 6484 goto out; 6485 } 6486 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply; 6487 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK; 6488 if (ret == MPI_IOCSTATUS_SUCCESS) { 6489 if (extend_page) { 6490 pCfg->cfghdr.ehdr->ExtPageLength = 6491 le16_to_cpu(pReply->ExtPageLength); 6492 pCfg->cfghdr.ehdr->ExtPageType = 6493 pReply->ExtPageType; 6494 } 6495 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion; 6496 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength; 6497 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber; 6498 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType; 6499 6500 } 6501 6502 if (retry_count) 6503 printk(MYIOC_s_INFO_FMT "Retry completed " 6504 "ret=0x%x timeleft=%ld\n", 6505 ioc->name, ret, timeleft); 6506 6507 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n", 6508 ret, le32_to_cpu(pReply->IOCLogInfo))); 6509 6510 out: 6511 6512 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 6513 mutex_unlock(&ioc->mptbase_cmds.mutex); 6514 if (issue_hard_reset) { 6515 issue_hard_reset = 0; 6516 printk(MYIOC_s_WARN_FMT 6517 "Issuing Reset from %s!!, doorbell=0x%08x\n", 6518 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 6519 if (retry_count == 0) { 6520 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0) 6521 retry_count++; 6522 } else 6523 mpt_HardResetHandler(ioc, CAN_SLEEP); 6524 6525 mpt_free_msg_frame(ioc, mf); 6526 /* attempt one retry for a timed out command */ 6527 if (retry_count < 2) { 6528 printk(MYIOC_s_INFO_FMT 6529 "Attempting Retry Config request" 6530 " type 0x%x, page 0x%x," 6531 " action %d\n", ioc->name, page_type, 6532 pCfg->cfghdr.hdr->PageNumber, pCfg->action); 6533 retry_count++; 6534 goto retry_config; 6535 } 6536 } 6537 return ret; 6538 6539 } 6540 6541 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6542 /** 6543 * mpt_ioc_reset - Base cleanup for hard reset 6544 * @ioc: Pointer to the adapter structure 6545 * @reset_phase: Indicates pre- or post-reset functionality 6546 * 6547 * Remark: Frees resources with internally generated commands. 6548 */ 6549 static int 6550 mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase) 6551 { 6552 switch (reset_phase) { 6553 case MPT_IOC_SETUP_RESET: 6554 ioc->taskmgmt_quiesce_io = 1; 6555 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6556 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); 6557 break; 6558 case MPT_IOC_PRE_RESET: 6559 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6560 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__)); 6561 break; 6562 case MPT_IOC_POST_RESET: 6563 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6564 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); 6565 /* wake up mptbase_cmds */ 6566 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 6567 ioc->mptbase_cmds.status |= 6568 MPT_MGMT_STATUS_DID_IOCRESET; 6569 complete(&ioc->mptbase_cmds.done); 6570 } 6571 /* wake up taskmgmt_cmds */ 6572 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) { 6573 ioc->taskmgmt_cmds.status |= 6574 MPT_MGMT_STATUS_DID_IOCRESET; 6575 complete(&ioc->taskmgmt_cmds.done); 6576 } 6577 break; 6578 default: 6579 break; 6580 } 6581 6582 return 1; /* currently means nothing really */ 6583 } 6584 6585 6586 #ifdef CONFIG_PROC_FS /* { */ 6587 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6588 /* 6589 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff... 6590 */ 6591 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6592 /** 6593 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries. 6594 * 6595 * Returns 0 for success, non-zero for failure. 6596 */ 6597 static int 6598 procmpt_create(void) 6599 { 6600 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL); 6601 if (mpt_proc_root_dir == NULL) 6602 return -ENOTDIR; 6603 6604 proc_create_single("summary", S_IRUGO, mpt_proc_root_dir, 6605 mpt_summary_proc_show); 6606 proc_create_single("version", S_IRUGO, mpt_proc_root_dir, 6607 mpt_version_proc_show); 6608 return 0; 6609 } 6610 6611 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6612 /** 6613 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries. 6614 * 6615 * Returns 0 for success, non-zero for failure. 6616 */ 6617 static void 6618 procmpt_destroy(void) 6619 { 6620 remove_proc_entry("version", mpt_proc_root_dir); 6621 remove_proc_entry("summary", mpt_proc_root_dir); 6622 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL); 6623 } 6624 6625 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6626 /* 6627 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary. 6628 */ 6629 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan); 6630 6631 static int mpt_summary_proc_show(struct seq_file *m, void *v) 6632 { 6633 MPT_ADAPTER *ioc = m->private; 6634 6635 if (ioc) { 6636 seq_mpt_print_ioc_summary(ioc, m, 1); 6637 } else { 6638 list_for_each_entry(ioc, &ioc_list, list) { 6639 seq_mpt_print_ioc_summary(ioc, m, 1); 6640 } 6641 } 6642 6643 return 0; 6644 } 6645 6646 static int mpt_version_proc_show(struct seq_file *m, void *v) 6647 { 6648 u8 cb_idx; 6649 int scsi, fc, sas, lan, ctl, targ, dmp; 6650 char *drvname; 6651 6652 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON); 6653 seq_printf(m, " Fusion MPT base driver\n"); 6654 6655 scsi = fc = sas = lan = ctl = targ = dmp = 0; 6656 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6657 drvname = NULL; 6658 if (MptCallbacks[cb_idx]) { 6659 switch (MptDriverClass[cb_idx]) { 6660 case MPTSPI_DRIVER: 6661 if (!scsi++) drvname = "SPI host"; 6662 break; 6663 case MPTFC_DRIVER: 6664 if (!fc++) drvname = "FC host"; 6665 break; 6666 case MPTSAS_DRIVER: 6667 if (!sas++) drvname = "SAS host"; 6668 break; 6669 case MPTLAN_DRIVER: 6670 if (!lan++) drvname = "LAN"; 6671 break; 6672 case MPTSTM_DRIVER: 6673 if (!targ++) drvname = "SCSI target"; 6674 break; 6675 case MPTCTL_DRIVER: 6676 if (!ctl++) drvname = "ioctl"; 6677 break; 6678 } 6679 6680 if (drvname) 6681 seq_printf(m, " Fusion MPT %s driver\n", drvname); 6682 } 6683 } 6684 6685 return 0; 6686 } 6687 6688 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v) 6689 { 6690 MPT_ADAPTER *ioc = m->private; 6691 char expVer[32]; 6692 int sz; 6693 int p; 6694 6695 mpt_get_fw_exp_ver(expVer, ioc); 6696 6697 seq_printf(m, "%s:", ioc->name); 6698 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 6699 seq_printf(m, " (f/w download boot flag set)"); 6700 // if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL) 6701 // seq_printf(m, " CONFIG_CHECKSUM_FAIL!"); 6702 6703 seq_printf(m, "\n ProductID = 0x%04x (%s)\n", 6704 ioc->facts.ProductID, 6705 ioc->prod_name); 6706 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer); 6707 if (ioc->facts.FWImageSize) 6708 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize); 6709 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion); 6710 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit); 6711 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState); 6712 6713 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n", 6714 ioc->facts.CurrentHostMfaHighAddr); 6715 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n", 6716 ioc->facts.CurrentSenseBufferHighAddr); 6717 6718 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth); 6719 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize); 6720 6721 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n", 6722 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma); 6723 /* 6724 * Rounding UP to nearest 4-kB boundary here... 6725 */ 6726 sz = (ioc->req_sz * ioc->req_depth) + 128; 6727 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000; 6728 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n", 6729 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz); 6730 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n", 6731 4*ioc->facts.RequestFrameSize, 6732 ioc->facts.GlobalCredits); 6733 6734 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n", 6735 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma); 6736 sz = (ioc->reply_sz * ioc->reply_depth) + 128; 6737 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n", 6738 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz); 6739 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n", 6740 ioc->facts.CurReplyFrameSize, 6741 ioc->facts.ReplyQueueDepth); 6742 6743 seq_printf(m, " MaxDevices = %d\n", 6744 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices); 6745 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses); 6746 6747 /* per-port info */ 6748 for (p=0; p < ioc->facts.NumberOfPorts; p++) { 6749 seq_printf(m, " PortNumber = %d (of %d)\n", 6750 p+1, 6751 ioc->facts.NumberOfPorts); 6752 if (ioc->bus_type == FC) { 6753 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 6754 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6755 seq_printf(m, " LanAddr = %pMR\n", a); 6756 } 6757 seq_printf(m, " WWN = %08X%08X:%08X%08X\n", 6758 ioc->fc_port_page0[p].WWNN.High, 6759 ioc->fc_port_page0[p].WWNN.Low, 6760 ioc->fc_port_page0[p].WWPN.High, 6761 ioc->fc_port_page0[p].WWPN.Low); 6762 } 6763 } 6764 6765 return 0; 6766 } 6767 #endif /* CONFIG_PROC_FS } */ 6768 6769 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6770 static void 6771 mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc) 6772 { 6773 buf[0] ='\0'; 6774 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) { 6775 sprintf(buf, " (Exp %02d%02d)", 6776 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */ 6777 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */ 6778 6779 /* insider hack! */ 6780 if ((ioc->facts.FWVersion.Word >> 8) & 0x80) 6781 strcat(buf, " [MDBG]"); 6782 } 6783 } 6784 6785 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6786 /** 6787 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer. 6788 * @ioc: Pointer to MPT_ADAPTER structure 6789 * @buffer: Pointer to buffer where IOC summary info should be written 6790 * @size: Pointer to number of bytes we wrote (set by this routine) 6791 * @len: Offset at which to start writing in buffer 6792 * @showlan: Display LAN stuff? 6793 * 6794 * This routine writes (english readable) ASCII text, which represents 6795 * a summary of IOC information, to a buffer. 6796 */ 6797 void 6798 mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan) 6799 { 6800 char expVer[32]; 6801 int y; 6802 6803 mpt_get_fw_exp_ver(expVer, ioc); 6804 6805 /* 6806 * Shorter summary of attached ioc's... 6807 */ 6808 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6809 ioc->name, 6810 ioc->prod_name, 6811 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6812 ioc->facts.FWVersion.Word, 6813 expVer, 6814 ioc->facts.NumberOfPorts, 6815 ioc->req_depth); 6816 6817 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6818 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6819 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a); 6820 } 6821 6822 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq); 6823 6824 if (!ioc->active) 6825 y += sprintf(buffer+len+y, " (disabled)"); 6826 6827 y += sprintf(buffer+len+y, "\n"); 6828 6829 *size = y; 6830 } 6831 6832 #ifdef CONFIG_PROC_FS 6833 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan) 6834 { 6835 char expVer[32]; 6836 6837 mpt_get_fw_exp_ver(expVer, ioc); 6838 6839 /* 6840 * Shorter summary of attached ioc's... 6841 */ 6842 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6843 ioc->name, 6844 ioc->prod_name, 6845 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6846 ioc->facts.FWVersion.Word, 6847 expVer, 6848 ioc->facts.NumberOfPorts, 6849 ioc->req_depth); 6850 6851 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6852 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6853 seq_printf(m, ", LanAddr=%pMR", a); 6854 } 6855 6856 seq_printf(m, ", IRQ=%d", ioc->pci_irq); 6857 6858 if (!ioc->active) 6859 seq_printf(m, " (disabled)"); 6860 6861 seq_putc(m, '\n'); 6862 } 6863 #endif 6864 6865 /** 6866 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management 6867 * @ioc: Pointer to MPT_ADAPTER structure 6868 * 6869 * Returns 0 for SUCCESS or -1 if FAILED. 6870 * 6871 * If -1 is return, then it was not possible to set the flags 6872 **/ 6873 int 6874 mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6875 { 6876 unsigned long flags; 6877 int retval; 6878 6879 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6880 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress || 6881 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) { 6882 retval = -1; 6883 goto out; 6884 } 6885 retval = 0; 6886 ioc->taskmgmt_in_progress = 1; 6887 ioc->taskmgmt_quiesce_io = 1; 6888 if (ioc->alt_ioc) { 6889 ioc->alt_ioc->taskmgmt_in_progress = 1; 6890 ioc->alt_ioc->taskmgmt_quiesce_io = 1; 6891 } 6892 out: 6893 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6894 return retval; 6895 } 6896 EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag); 6897 6898 /** 6899 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management 6900 * @ioc: Pointer to MPT_ADAPTER structure 6901 * 6902 **/ 6903 void 6904 mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6905 { 6906 unsigned long flags; 6907 6908 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6909 ioc->taskmgmt_in_progress = 0; 6910 ioc->taskmgmt_quiesce_io = 0; 6911 if (ioc->alt_ioc) { 6912 ioc->alt_ioc->taskmgmt_in_progress = 0; 6913 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 6914 } 6915 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6916 } 6917 EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag); 6918 6919 6920 /** 6921 * mpt_halt_firmware - Halts the firmware if it is operational and panic 6922 * the kernel 6923 * @ioc: Pointer to MPT_ADAPTER structure 6924 * 6925 **/ 6926 void 6927 mpt_halt_firmware(MPT_ADAPTER *ioc) 6928 { 6929 u32 ioc_raw_state; 6930 6931 ioc_raw_state = mpt_GetIocState(ioc, 0); 6932 6933 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 6934 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n", 6935 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6936 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name, 6937 ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6938 } else { 6939 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00); 6940 panic("%s: Firmware is halted due to command timeout\n", 6941 ioc->name); 6942 } 6943 } 6944 EXPORT_SYMBOL(mpt_halt_firmware); 6945 6946 /** 6947 * mpt_SoftResetHandler - Issues a less expensive reset 6948 * @ioc: Pointer to MPT_ADAPTER structure 6949 * @sleepFlag: Indicates if sleep or schedule must be called. 6950 * 6951 * Returns 0 for SUCCESS or -1 if FAILED. 6952 * 6953 * Message Unit Reset - instructs the IOC to reset the Reply Post and 6954 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded. 6955 * All posted buffers are freed, and event notification is turned off. 6956 * IOC doesn't reply to any outstanding request. This will transfer IOC 6957 * to READY state. 6958 **/ 6959 static int 6960 mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 6961 { 6962 int rc; 6963 int ii; 6964 u8 cb_idx; 6965 unsigned long flags; 6966 u32 ioc_state; 6967 unsigned long time_count; 6968 6969 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n", 6970 ioc->name)); 6971 6972 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 6973 6974 if (mpt_fwfault_debug) 6975 mpt_halt_firmware(ioc); 6976 6977 if (ioc_state == MPI_IOC_STATE_FAULT || 6978 ioc_state == MPI_IOC_STATE_RESET) { 6979 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6980 "skipping, either in FAULT or RESET state!\n", ioc->name)); 6981 return -1; 6982 } 6983 6984 if (ioc->bus_type == FC) { 6985 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6986 "skipping, because the bus type is FC!\n", ioc->name)); 6987 return -1; 6988 } 6989 6990 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6991 if (ioc->ioc_reset_in_progress) { 6992 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6993 return -1; 6994 } 6995 ioc->ioc_reset_in_progress = 1; 6996 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6997 6998 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6999 if (MptResetHandlers[cb_idx]) 7000 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 7001 } 7002 7003 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7004 if (ioc->taskmgmt_in_progress) { 7005 ioc->ioc_reset_in_progress = 0; 7006 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7007 return -1; 7008 } 7009 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7010 /* Disable reply interrupts (also blocks FreeQ) */ 7011 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 7012 ioc->active = 0; 7013 time_count = jiffies; 7014 7015 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 7016 7017 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7018 if (MptResetHandlers[cb_idx]) 7019 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET); 7020 } 7021 7022 if (rc) 7023 goto out; 7024 7025 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 7026 if (ioc_state != MPI_IOC_STATE_READY) 7027 goto out; 7028 7029 for (ii = 0; ii < 5; ii++) { 7030 /* Get IOC facts! Allow 5 retries */ 7031 rc = GetIocFacts(ioc, sleepFlag, 7032 MPT_HOSTEVENT_IOC_RECOVER); 7033 if (rc == 0) 7034 break; 7035 if (sleepFlag == CAN_SLEEP) 7036 msleep(100); 7037 else 7038 mdelay(100); 7039 } 7040 if (ii == 5) 7041 goto out; 7042 7043 rc = PrimeIocFifos(ioc); 7044 if (rc != 0) 7045 goto out; 7046 7047 rc = SendIocInit(ioc, sleepFlag); 7048 if (rc != 0) 7049 goto out; 7050 7051 rc = SendEventNotification(ioc, 1, sleepFlag); 7052 if (rc != 0) 7053 goto out; 7054 7055 if (ioc->hard_resets < -1) 7056 ioc->hard_resets++; 7057 7058 /* 7059 * At this point, we know soft reset succeeded. 7060 */ 7061 7062 ioc->active = 1; 7063 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 7064 7065 out: 7066 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7067 ioc->ioc_reset_in_progress = 0; 7068 ioc->taskmgmt_quiesce_io = 0; 7069 ioc->taskmgmt_in_progress = 0; 7070 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7071 7072 if (ioc->active) { /* otherwise, hard reset coming */ 7073 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7074 if (MptResetHandlers[cb_idx]) 7075 mpt_signal_reset(cb_idx, ioc, 7076 MPT_IOC_POST_RESET); 7077 } 7078 } 7079 7080 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7081 "SoftResetHandler: completed (%d seconds): %s\n", 7082 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000, 7083 ((rc == 0) ? "SUCCESS" : "FAILED"))); 7084 7085 return rc; 7086 } 7087 7088 /** 7089 * mpt_Soft_Hard_ResetHandler - Try less expensive reset 7090 * @ioc: Pointer to MPT_ADAPTER structure 7091 * @sleepFlag: Indicates if sleep or schedule must be called. 7092 * 7093 * Returns 0 for SUCCESS or -1 if FAILED. 7094 * Try for softreset first, only if it fails go for expensive 7095 * HardReset. 7096 **/ 7097 int 7098 mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) { 7099 int ret = -1; 7100 7101 ret = mpt_SoftResetHandler(ioc, sleepFlag); 7102 if (ret == 0) 7103 return ret; 7104 ret = mpt_HardResetHandler(ioc, sleepFlag); 7105 return ret; 7106 } 7107 EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler); 7108 7109 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7110 /* 7111 * Reset Handling 7112 */ 7113 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7114 /** 7115 * mpt_HardResetHandler - Generic reset handler 7116 * @ioc: Pointer to MPT_ADAPTER structure 7117 * @sleepFlag: Indicates if sleep or schedule must be called. 7118 * 7119 * Issues SCSI Task Management call based on input arg values. 7120 * If TaskMgmt fails, returns associated SCSI request. 7121 * 7122 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer) 7123 * or a non-interrupt thread. In the former, must not call schedule(). 7124 * 7125 * Note: A return of -1 is a FATAL error case, as it means a 7126 * FW reload/initialization failed. 7127 * 7128 * Returns 0 for SUCCESS or -1 if FAILED. 7129 */ 7130 int 7131 mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 7132 { 7133 int rc; 7134 u8 cb_idx; 7135 unsigned long flags; 7136 unsigned long time_count; 7137 7138 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name)); 7139 #ifdef MFCNT 7140 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name); 7141 printk("MF count 0x%x !\n", ioc->mfcnt); 7142 #endif 7143 if (mpt_fwfault_debug) 7144 mpt_halt_firmware(ioc); 7145 7146 /* Reset the adapter. Prevent more than 1 call to 7147 * mpt_do_ioc_recovery at any instant in time. 7148 */ 7149 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7150 if (ioc->ioc_reset_in_progress) { 7151 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7152 ioc->wait_on_reset_completion = 1; 7153 do { 7154 ssleep(1); 7155 } while (ioc->ioc_reset_in_progress == 1); 7156 ioc->wait_on_reset_completion = 0; 7157 return ioc->reset_status; 7158 } 7159 if (ioc->wait_on_reset_completion) { 7160 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7161 rc = 0; 7162 time_count = jiffies; 7163 goto exit; 7164 } 7165 ioc->ioc_reset_in_progress = 1; 7166 if (ioc->alt_ioc) 7167 ioc->alt_ioc->ioc_reset_in_progress = 1; 7168 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7169 7170 7171 /* The SCSI driver needs to adjust timeouts on all current 7172 * commands prior to the diagnostic reset being issued. 7173 * Prevents timeouts occurring during a diagnostic reset...very bad. 7174 * For all other protocol drivers, this is a no-op. 7175 */ 7176 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7177 if (MptResetHandlers[cb_idx]) { 7178 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 7179 if (ioc->alt_ioc) 7180 mpt_signal_reset(cb_idx, ioc->alt_ioc, 7181 MPT_IOC_SETUP_RESET); 7182 } 7183 } 7184 7185 time_count = jiffies; 7186 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag); 7187 if (rc != 0) { 7188 printk(KERN_WARNING MYNAM 7189 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n", 7190 rc, ioc->name, mpt_GetIocState(ioc, 0)); 7191 } else { 7192 if (ioc->hard_resets < -1) 7193 ioc->hard_resets++; 7194 } 7195 7196 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7197 ioc->ioc_reset_in_progress = 0; 7198 ioc->taskmgmt_quiesce_io = 0; 7199 ioc->taskmgmt_in_progress = 0; 7200 ioc->reset_status = rc; 7201 if (ioc->alt_ioc) { 7202 ioc->alt_ioc->ioc_reset_in_progress = 0; 7203 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 7204 ioc->alt_ioc->taskmgmt_in_progress = 0; 7205 } 7206 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7207 7208 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7209 if (MptResetHandlers[cb_idx]) { 7210 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET); 7211 if (ioc->alt_ioc) 7212 mpt_signal_reset(cb_idx, 7213 ioc->alt_ioc, MPT_IOC_POST_RESET); 7214 } 7215 } 7216 exit: 7217 dtmprintk(ioc, 7218 printk(MYIOC_s_DEBUG_FMT 7219 "HardResetHandler: completed (%d seconds): %s\n", ioc->name, 7220 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ? 7221 "SUCCESS" : "FAILED"))); 7222 7223 return rc; 7224 } 7225 7226 #ifdef CONFIG_FUSION_LOGGING 7227 static void 7228 mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply) 7229 { 7230 char *ds = NULL; 7231 u32 evData0; 7232 int ii; 7233 u8 event; 7234 char *evStr = ioc->evStr; 7235 7236 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7237 evData0 = le32_to_cpu(pEventReply->Data[0]); 7238 7239 switch(event) { 7240 case MPI_EVENT_NONE: 7241 ds = "None"; 7242 break; 7243 case MPI_EVENT_LOG_DATA: 7244 ds = "Log Data"; 7245 break; 7246 case MPI_EVENT_STATE_CHANGE: 7247 ds = "State Change"; 7248 break; 7249 case MPI_EVENT_UNIT_ATTENTION: 7250 ds = "Unit Attention"; 7251 break; 7252 case MPI_EVENT_IOC_BUS_RESET: 7253 ds = "IOC Bus Reset"; 7254 break; 7255 case MPI_EVENT_EXT_BUS_RESET: 7256 ds = "External Bus Reset"; 7257 break; 7258 case MPI_EVENT_RESCAN: 7259 ds = "Bus Rescan Event"; 7260 break; 7261 case MPI_EVENT_LINK_STATUS_CHANGE: 7262 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE) 7263 ds = "Link Status(FAILURE) Change"; 7264 else 7265 ds = "Link Status(ACTIVE) Change"; 7266 break; 7267 case MPI_EVENT_LOOP_STATE_CHANGE: 7268 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP) 7269 ds = "Loop State(LIP) Change"; 7270 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE) 7271 ds = "Loop State(LPE) Change"; 7272 else 7273 ds = "Loop State(LPB) Change"; 7274 break; 7275 case MPI_EVENT_LOGOUT: 7276 ds = "Logout"; 7277 break; 7278 case MPI_EVENT_EVENT_CHANGE: 7279 if (evData0) 7280 ds = "Events ON"; 7281 else 7282 ds = "Events OFF"; 7283 break; 7284 case MPI_EVENT_INTEGRATED_RAID: 7285 { 7286 u8 ReasonCode = (u8)(evData0 >> 16); 7287 switch (ReasonCode) { 7288 case MPI_EVENT_RAID_RC_VOLUME_CREATED : 7289 ds = "Integrated Raid: Volume Created"; 7290 break; 7291 case MPI_EVENT_RAID_RC_VOLUME_DELETED : 7292 ds = "Integrated Raid: Volume Deleted"; 7293 break; 7294 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED : 7295 ds = "Integrated Raid: Volume Settings Changed"; 7296 break; 7297 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED : 7298 ds = "Integrated Raid: Volume Status Changed"; 7299 break; 7300 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED : 7301 ds = "Integrated Raid: Volume Physdisk Changed"; 7302 break; 7303 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED : 7304 ds = "Integrated Raid: Physdisk Created"; 7305 break; 7306 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED : 7307 ds = "Integrated Raid: Physdisk Deleted"; 7308 break; 7309 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED : 7310 ds = "Integrated Raid: Physdisk Settings Changed"; 7311 break; 7312 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED : 7313 ds = "Integrated Raid: Physdisk Status Changed"; 7314 break; 7315 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED : 7316 ds = "Integrated Raid: Domain Validation Needed"; 7317 break; 7318 case MPI_EVENT_RAID_RC_SMART_DATA : 7319 ds = "Integrated Raid; Smart Data"; 7320 break; 7321 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED : 7322 ds = "Integrated Raid: Replace Action Started"; 7323 break; 7324 default: 7325 ds = "Integrated Raid"; 7326 break; 7327 } 7328 break; 7329 } 7330 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE: 7331 ds = "SCSI Device Status Change"; 7332 break; 7333 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: 7334 { 7335 u8 id = (u8)(evData0); 7336 u8 channel = (u8)(evData0 >> 8); 7337 u8 ReasonCode = (u8)(evData0 >> 16); 7338 switch (ReasonCode) { 7339 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED: 7340 snprintf(evStr, EVENT_DESCR_STR_SZ, 7341 "SAS Device Status Change: Added: " 7342 "id=%d channel=%d", id, channel); 7343 break; 7344 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING: 7345 snprintf(evStr, EVENT_DESCR_STR_SZ, 7346 "SAS Device Status Change: Deleted: " 7347 "id=%d channel=%d", id, channel); 7348 break; 7349 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7350 snprintf(evStr, EVENT_DESCR_STR_SZ, 7351 "SAS Device Status Change: SMART Data: " 7352 "id=%d channel=%d", id, channel); 7353 break; 7354 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED: 7355 snprintf(evStr, EVENT_DESCR_STR_SZ, 7356 "SAS Device Status Change: No Persistency: " 7357 "id=%d channel=%d", id, channel); 7358 break; 7359 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7360 snprintf(evStr, EVENT_DESCR_STR_SZ, 7361 "SAS Device Status Change: Unsupported Device " 7362 "Discovered : id=%d channel=%d", id, channel); 7363 break; 7364 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7365 snprintf(evStr, EVENT_DESCR_STR_SZ, 7366 "SAS Device Status Change: Internal Device " 7367 "Reset : id=%d channel=%d", id, channel); 7368 break; 7369 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7370 snprintf(evStr, EVENT_DESCR_STR_SZ, 7371 "SAS Device Status Change: Internal Task " 7372 "Abort : id=%d channel=%d", id, channel); 7373 break; 7374 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7375 snprintf(evStr, EVENT_DESCR_STR_SZ, 7376 "SAS Device Status Change: Internal Abort " 7377 "Task Set : id=%d channel=%d", id, channel); 7378 break; 7379 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7380 snprintf(evStr, EVENT_DESCR_STR_SZ, 7381 "SAS Device Status Change: Internal Clear " 7382 "Task Set : id=%d channel=%d", id, channel); 7383 break; 7384 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7385 snprintf(evStr, EVENT_DESCR_STR_SZ, 7386 "SAS Device Status Change: Internal Query " 7387 "Task : id=%d channel=%d", id, channel); 7388 break; 7389 default: 7390 snprintf(evStr, EVENT_DESCR_STR_SZ, 7391 "SAS Device Status Change: Unknown: " 7392 "id=%d channel=%d", id, channel); 7393 break; 7394 } 7395 break; 7396 } 7397 case MPI_EVENT_ON_BUS_TIMER_EXPIRED: 7398 ds = "Bus Timer Expired"; 7399 break; 7400 case MPI_EVENT_QUEUE_FULL: 7401 { 7402 u16 curr_depth = (u16)(evData0 >> 16); 7403 u8 channel = (u8)(evData0 >> 8); 7404 u8 id = (u8)(evData0); 7405 7406 snprintf(evStr, EVENT_DESCR_STR_SZ, 7407 "Queue Full: channel=%d id=%d depth=%d", 7408 channel, id, curr_depth); 7409 break; 7410 } 7411 case MPI_EVENT_SAS_SES: 7412 ds = "SAS SES Event"; 7413 break; 7414 case MPI_EVENT_PERSISTENT_TABLE_FULL: 7415 ds = "Persistent Table Full"; 7416 break; 7417 case MPI_EVENT_SAS_PHY_LINK_STATUS: 7418 { 7419 u8 LinkRates = (u8)(evData0 >> 8); 7420 u8 PhyNumber = (u8)(evData0); 7421 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >> 7422 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT; 7423 switch (LinkRates) { 7424 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN: 7425 snprintf(evStr, EVENT_DESCR_STR_SZ, 7426 "SAS PHY Link Status: Phy=%d:" 7427 " Rate Unknown",PhyNumber); 7428 break; 7429 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED: 7430 snprintf(evStr, EVENT_DESCR_STR_SZ, 7431 "SAS PHY Link Status: Phy=%d:" 7432 " Phy Disabled",PhyNumber); 7433 break; 7434 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION: 7435 snprintf(evStr, EVENT_DESCR_STR_SZ, 7436 "SAS PHY Link Status: Phy=%d:" 7437 " Failed Speed Nego",PhyNumber); 7438 break; 7439 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE: 7440 snprintf(evStr, EVENT_DESCR_STR_SZ, 7441 "SAS PHY Link Status: Phy=%d:" 7442 " Sata OOB Completed",PhyNumber); 7443 break; 7444 case MPI_EVENT_SAS_PLS_LR_RATE_1_5: 7445 snprintf(evStr, EVENT_DESCR_STR_SZ, 7446 "SAS PHY Link Status: Phy=%d:" 7447 " Rate 1.5 Gbps",PhyNumber); 7448 break; 7449 case MPI_EVENT_SAS_PLS_LR_RATE_3_0: 7450 snprintf(evStr, EVENT_DESCR_STR_SZ, 7451 "SAS PHY Link Status: Phy=%d:" 7452 " Rate 3.0 Gbps", PhyNumber); 7453 break; 7454 case MPI_EVENT_SAS_PLS_LR_RATE_6_0: 7455 snprintf(evStr, EVENT_DESCR_STR_SZ, 7456 "SAS PHY Link Status: Phy=%d:" 7457 " Rate 6.0 Gbps", PhyNumber); 7458 break; 7459 default: 7460 snprintf(evStr, EVENT_DESCR_STR_SZ, 7461 "SAS PHY Link Status: Phy=%d", PhyNumber); 7462 break; 7463 } 7464 break; 7465 } 7466 case MPI_EVENT_SAS_DISCOVERY_ERROR: 7467 ds = "SAS Discovery Error"; 7468 break; 7469 case MPI_EVENT_IR_RESYNC_UPDATE: 7470 { 7471 u8 resync_complete = (u8)(evData0 >> 16); 7472 snprintf(evStr, EVENT_DESCR_STR_SZ, 7473 "IR Resync Update: Complete = %d:",resync_complete); 7474 break; 7475 } 7476 case MPI_EVENT_IR2: 7477 { 7478 u8 id = (u8)(evData0); 7479 u8 channel = (u8)(evData0 >> 8); 7480 u8 phys_num = (u8)(evData0 >> 24); 7481 u8 ReasonCode = (u8)(evData0 >> 16); 7482 7483 switch (ReasonCode) { 7484 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED: 7485 snprintf(evStr, EVENT_DESCR_STR_SZ, 7486 "IR2: LD State Changed: " 7487 "id=%d channel=%d phys_num=%d", 7488 id, channel, phys_num); 7489 break; 7490 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED: 7491 snprintf(evStr, EVENT_DESCR_STR_SZ, 7492 "IR2: PD State Changed " 7493 "id=%d channel=%d phys_num=%d", 7494 id, channel, phys_num); 7495 break; 7496 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL: 7497 snprintf(evStr, EVENT_DESCR_STR_SZ, 7498 "IR2: Bad Block Table Full: " 7499 "id=%d channel=%d phys_num=%d", 7500 id, channel, phys_num); 7501 break; 7502 case MPI_EVENT_IR2_RC_PD_INSERTED: 7503 snprintf(evStr, EVENT_DESCR_STR_SZ, 7504 "IR2: PD Inserted: " 7505 "id=%d channel=%d phys_num=%d", 7506 id, channel, phys_num); 7507 break; 7508 case MPI_EVENT_IR2_RC_PD_REMOVED: 7509 snprintf(evStr, EVENT_DESCR_STR_SZ, 7510 "IR2: PD Removed: " 7511 "id=%d channel=%d phys_num=%d", 7512 id, channel, phys_num); 7513 break; 7514 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED: 7515 snprintf(evStr, EVENT_DESCR_STR_SZ, 7516 "IR2: Foreign CFG Detected: " 7517 "id=%d channel=%d phys_num=%d", 7518 id, channel, phys_num); 7519 break; 7520 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR: 7521 snprintf(evStr, EVENT_DESCR_STR_SZ, 7522 "IR2: Rebuild Medium Error: " 7523 "id=%d channel=%d phys_num=%d", 7524 id, channel, phys_num); 7525 break; 7526 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED: 7527 snprintf(evStr, EVENT_DESCR_STR_SZ, 7528 "IR2: Dual Port Added: " 7529 "id=%d channel=%d phys_num=%d", 7530 id, channel, phys_num); 7531 break; 7532 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED: 7533 snprintf(evStr, EVENT_DESCR_STR_SZ, 7534 "IR2: Dual Port Removed: " 7535 "id=%d channel=%d phys_num=%d", 7536 id, channel, phys_num); 7537 break; 7538 default: 7539 ds = "IR2"; 7540 break; 7541 } 7542 break; 7543 } 7544 case MPI_EVENT_SAS_DISCOVERY: 7545 { 7546 if (evData0) 7547 ds = "SAS Discovery: Start"; 7548 else 7549 ds = "SAS Discovery: Stop"; 7550 break; 7551 } 7552 case MPI_EVENT_LOG_ENTRY_ADDED: 7553 ds = "SAS Log Entry Added"; 7554 break; 7555 7556 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE: 7557 { 7558 u8 phy_num = (u8)(evData0); 7559 u8 port_num = (u8)(evData0 >> 8); 7560 u8 port_width = (u8)(evData0 >> 16); 7561 u8 primitive = (u8)(evData0 >> 24); 7562 snprintf(evStr, EVENT_DESCR_STR_SZ, 7563 "SAS Broadcast Primitive: phy=%d port=%d " 7564 "width=%d primitive=0x%02x", 7565 phy_num, port_num, port_width, primitive); 7566 break; 7567 } 7568 7569 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 7570 { 7571 u8 reason = (u8)(evData0); 7572 7573 switch (reason) { 7574 case MPI_EVENT_SAS_INIT_RC_ADDED: 7575 ds = "SAS Initiator Status Change: Added"; 7576 break; 7577 case MPI_EVENT_SAS_INIT_RC_REMOVED: 7578 ds = "SAS Initiator Status Change: Deleted"; 7579 break; 7580 default: 7581 ds = "SAS Initiator Status Change"; 7582 break; 7583 } 7584 break; 7585 } 7586 7587 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW: 7588 { 7589 u8 max_init = (u8)(evData0); 7590 u8 current_init = (u8)(evData0 >> 8); 7591 7592 snprintf(evStr, EVENT_DESCR_STR_SZ, 7593 "SAS Initiator Device Table Overflow: max initiators=%02d " 7594 "current initiators=%02d", 7595 max_init, current_init); 7596 break; 7597 } 7598 case MPI_EVENT_SAS_SMP_ERROR: 7599 { 7600 u8 status = (u8)(evData0); 7601 u8 port_num = (u8)(evData0 >> 8); 7602 u8 result = (u8)(evData0 >> 16); 7603 7604 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID) 7605 snprintf(evStr, EVENT_DESCR_STR_SZ, 7606 "SAS SMP Error: port=%d result=0x%02x", 7607 port_num, result); 7608 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR) 7609 snprintf(evStr, EVENT_DESCR_STR_SZ, 7610 "SAS SMP Error: port=%d : CRC Error", 7611 port_num); 7612 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT) 7613 snprintf(evStr, EVENT_DESCR_STR_SZ, 7614 "SAS SMP Error: port=%d : Timeout", 7615 port_num); 7616 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION) 7617 snprintf(evStr, EVENT_DESCR_STR_SZ, 7618 "SAS SMP Error: port=%d : No Destination", 7619 port_num); 7620 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION) 7621 snprintf(evStr, EVENT_DESCR_STR_SZ, 7622 "SAS SMP Error: port=%d : Bad Destination", 7623 port_num); 7624 else 7625 snprintf(evStr, EVENT_DESCR_STR_SZ, 7626 "SAS SMP Error: port=%d : status=0x%02x", 7627 port_num, status); 7628 break; 7629 } 7630 7631 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE: 7632 { 7633 u8 reason = (u8)(evData0); 7634 7635 switch (reason) { 7636 case MPI_EVENT_SAS_EXP_RC_ADDED: 7637 ds = "Expander Status Change: Added"; 7638 break; 7639 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING: 7640 ds = "Expander Status Change: Deleted"; 7641 break; 7642 default: 7643 ds = "Expander Status Change"; 7644 break; 7645 } 7646 break; 7647 } 7648 7649 /* 7650 * MPT base "custom" events may be added here... 7651 */ 7652 default: 7653 ds = "Unknown"; 7654 break; 7655 } 7656 if (ds) 7657 strlcpy(evStr, ds, EVENT_DESCR_STR_SZ); 7658 7659 7660 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7661 "MPT event:(%02Xh) : %s\n", 7662 ioc->name, event, evStr)); 7663 7664 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM 7665 ": Event data:\n")); 7666 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++) 7667 devtverboseprintk(ioc, printk(" %08x", 7668 le32_to_cpu(pEventReply->Data[ii]))); 7669 devtverboseprintk(ioc, printk(KERN_DEBUG "\n")); 7670 } 7671 #endif 7672 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7673 /** 7674 * ProcessEventNotification - Route EventNotificationReply to all event handlers 7675 * @ioc: Pointer to MPT_ADAPTER structure 7676 * @pEventReply: Pointer to EventNotification reply frame 7677 * @evHandlers: Pointer to integer, number of event handlers 7678 * 7679 * Routes a received EventNotificationReply to all currently registered 7680 * event handlers. 7681 * Returns sum of event handlers return values. 7682 */ 7683 static int 7684 ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers) 7685 { 7686 u16 evDataLen; 7687 u32 evData0 = 0; 7688 int ii; 7689 u8 cb_idx; 7690 int r = 0; 7691 int handlers = 0; 7692 u8 event; 7693 7694 /* 7695 * Do platform normalization of values 7696 */ 7697 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7698 evDataLen = le16_to_cpu(pEventReply->EventDataLength); 7699 if (evDataLen) { 7700 evData0 = le32_to_cpu(pEventReply->Data[0]); 7701 } 7702 7703 #ifdef CONFIG_FUSION_LOGGING 7704 if (evDataLen) 7705 mpt_display_event_info(ioc, pEventReply); 7706 #endif 7707 7708 /* 7709 * Do general / base driver event processing 7710 */ 7711 switch(event) { 7712 case MPI_EVENT_EVENT_CHANGE: /* 0A */ 7713 if (evDataLen) { 7714 u8 evState = evData0 & 0xFF; 7715 7716 /* CHECKME! What if evState unexpectedly says OFF (0)? */ 7717 7718 /* Update EventState field in cached IocFacts */ 7719 if (ioc->facts.Function) { 7720 ioc->facts.EventState = evState; 7721 } 7722 } 7723 break; 7724 case MPI_EVENT_INTEGRATED_RAID: 7725 mptbase_raid_process_event_data(ioc, 7726 (MpiEventDataRaid_t *)pEventReply->Data); 7727 break; 7728 default: 7729 break; 7730 } 7731 7732 /* 7733 * Should this event be logged? Events are written sequentially. 7734 * When buffer is full, start again at the top. 7735 */ 7736 if (ioc->events && (ioc->eventTypes & ( 1 << event))) { 7737 int idx; 7738 7739 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE; 7740 7741 ioc->events[idx].event = event; 7742 ioc->events[idx].eventContext = ioc->eventContext; 7743 7744 for (ii = 0; ii < 2; ii++) { 7745 if (ii < evDataLen) 7746 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]); 7747 else 7748 ioc->events[idx].data[ii] = 0; 7749 } 7750 7751 ioc->eventContext++; 7752 } 7753 7754 7755 /* 7756 * Call each currently registered protocol event handler. 7757 */ 7758 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7759 if (MptEvHandlers[cb_idx]) { 7760 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7761 "Routing Event to event handler #%d\n", 7762 ioc->name, cb_idx)); 7763 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply); 7764 handlers++; 7765 } 7766 } 7767 /* FIXME? Examine results here? */ 7768 7769 /* 7770 * If needed, send (a single) EventAck. 7771 */ 7772 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) { 7773 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7774 "EventAck required\n",ioc->name)); 7775 if ((ii = SendEventAck(ioc, pEventReply)) != 0) { 7776 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n", 7777 ioc->name, ii)); 7778 } 7779 } 7780 7781 *evHandlers = handlers; 7782 return r; 7783 } 7784 7785 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7786 /** 7787 * mpt_fc_log_info - Log information returned from Fibre Channel IOC. 7788 * @ioc: Pointer to MPT_ADAPTER structure 7789 * @log_info: U32 LogInfo reply word from the IOC 7790 * 7791 * Refer to lsi/mpi_log_fc.h. 7792 */ 7793 static void 7794 mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info) 7795 { 7796 char *desc = "unknown"; 7797 7798 switch (log_info & 0xFF000000) { 7799 case MPI_IOCLOGINFO_FC_INIT_BASE: 7800 desc = "FCP Initiator"; 7801 break; 7802 case MPI_IOCLOGINFO_FC_TARGET_BASE: 7803 desc = "FCP Target"; 7804 break; 7805 case MPI_IOCLOGINFO_FC_LAN_BASE: 7806 desc = "LAN"; 7807 break; 7808 case MPI_IOCLOGINFO_FC_MSG_BASE: 7809 desc = "MPI Message Layer"; 7810 break; 7811 case MPI_IOCLOGINFO_FC_LINK_BASE: 7812 desc = "FC Link"; 7813 break; 7814 case MPI_IOCLOGINFO_FC_CTX_BASE: 7815 desc = "Context Manager"; 7816 break; 7817 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET: 7818 desc = "Invalid Field Offset"; 7819 break; 7820 case MPI_IOCLOGINFO_FC_STATE_CHANGE: 7821 desc = "State Change Info"; 7822 break; 7823 } 7824 7825 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n", 7826 ioc->name, log_info, desc, (log_info & 0xFFFFFF)); 7827 } 7828 7829 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7830 /** 7831 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC. 7832 * @ioc: Pointer to MPT_ADAPTER structure 7833 * @log_info: U32 LogInfo word from the IOC 7834 * 7835 * Refer to lsi/sp_log.h. 7836 */ 7837 static void 7838 mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info) 7839 { 7840 u32 info = log_info & 0x00FF0000; 7841 char *desc = "unknown"; 7842 7843 switch (info) { 7844 case 0x00010000: 7845 desc = "bug! MID not found"; 7846 break; 7847 7848 case 0x00020000: 7849 desc = "Parity Error"; 7850 break; 7851 7852 case 0x00030000: 7853 desc = "ASYNC Outbound Overrun"; 7854 break; 7855 7856 case 0x00040000: 7857 desc = "SYNC Offset Error"; 7858 break; 7859 7860 case 0x00050000: 7861 desc = "BM Change"; 7862 break; 7863 7864 case 0x00060000: 7865 desc = "Msg In Overflow"; 7866 break; 7867 7868 case 0x00070000: 7869 desc = "DMA Error"; 7870 break; 7871 7872 case 0x00080000: 7873 desc = "Outbound DMA Overrun"; 7874 break; 7875 7876 case 0x00090000: 7877 desc = "Task Management"; 7878 break; 7879 7880 case 0x000A0000: 7881 desc = "Device Problem"; 7882 break; 7883 7884 case 0x000B0000: 7885 desc = "Invalid Phase Change"; 7886 break; 7887 7888 case 0x000C0000: 7889 desc = "Untagged Table Size"; 7890 break; 7891 7892 } 7893 7894 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc); 7895 } 7896 7897 /* strings for sas loginfo */ 7898 static char *originator_str[] = { 7899 "IOP", /* 00h */ 7900 "PL", /* 01h */ 7901 "IR" /* 02h */ 7902 }; 7903 static char *iop_code_str[] = { 7904 NULL, /* 00h */ 7905 "Invalid SAS Address", /* 01h */ 7906 NULL, /* 02h */ 7907 "Invalid Page", /* 03h */ 7908 "Diag Message Error", /* 04h */ 7909 "Task Terminated", /* 05h */ 7910 "Enclosure Management", /* 06h */ 7911 "Target Mode" /* 07h */ 7912 }; 7913 static char *pl_code_str[] = { 7914 NULL, /* 00h */ 7915 "Open Failure", /* 01h */ 7916 "Invalid Scatter Gather List", /* 02h */ 7917 "Wrong Relative Offset or Frame Length", /* 03h */ 7918 "Frame Transfer Error", /* 04h */ 7919 "Transmit Frame Connected Low", /* 05h */ 7920 "SATA Non-NCQ RW Error Bit Set", /* 06h */ 7921 "SATA Read Log Receive Data Error", /* 07h */ 7922 "SATA NCQ Fail All Commands After Error", /* 08h */ 7923 "SATA Error in Receive Set Device Bit FIS", /* 09h */ 7924 "Receive Frame Invalid Message", /* 0Ah */ 7925 "Receive Context Message Valid Error", /* 0Bh */ 7926 "Receive Frame Current Frame Error", /* 0Ch */ 7927 "SATA Link Down", /* 0Dh */ 7928 "Discovery SATA Init W IOS", /* 0Eh */ 7929 "Config Invalid Page", /* 0Fh */ 7930 "Discovery SATA Init Timeout", /* 10h */ 7931 "Reset", /* 11h */ 7932 "Abort", /* 12h */ 7933 "IO Not Yet Executed", /* 13h */ 7934 "IO Executed", /* 14h */ 7935 "Persistent Reservation Out Not Affiliation " 7936 "Owner", /* 15h */ 7937 "Open Transmit DMA Abort", /* 16h */ 7938 "IO Device Missing Delay Retry", /* 17h */ 7939 "IO Cancelled Due to Receive Error", /* 18h */ 7940 NULL, /* 19h */ 7941 NULL, /* 1Ah */ 7942 NULL, /* 1Bh */ 7943 NULL, /* 1Ch */ 7944 NULL, /* 1Dh */ 7945 NULL, /* 1Eh */ 7946 NULL, /* 1Fh */ 7947 "Enclosure Management" /* 20h */ 7948 }; 7949 static char *ir_code_str[] = { 7950 "Raid Action Error", /* 00h */ 7951 NULL, /* 00h */ 7952 NULL, /* 01h */ 7953 NULL, /* 02h */ 7954 NULL, /* 03h */ 7955 NULL, /* 04h */ 7956 NULL, /* 05h */ 7957 NULL, /* 06h */ 7958 NULL /* 07h */ 7959 }; 7960 static char *raid_sub_code_str[] = { 7961 NULL, /* 00h */ 7962 "Volume Creation Failed: Data Passed too " 7963 "Large", /* 01h */ 7964 "Volume Creation Failed: Duplicate Volumes " 7965 "Attempted", /* 02h */ 7966 "Volume Creation Failed: Max Number " 7967 "Supported Volumes Exceeded", /* 03h */ 7968 "Volume Creation Failed: DMA Error", /* 04h */ 7969 "Volume Creation Failed: Invalid Volume Type", /* 05h */ 7970 "Volume Creation Failed: Error Reading " 7971 "MFG Page 4", /* 06h */ 7972 "Volume Creation Failed: Creating Internal " 7973 "Structures", /* 07h */ 7974 NULL, /* 08h */ 7975 NULL, /* 09h */ 7976 NULL, /* 0Ah */ 7977 NULL, /* 0Bh */ 7978 NULL, /* 0Ch */ 7979 NULL, /* 0Dh */ 7980 NULL, /* 0Eh */ 7981 NULL, /* 0Fh */ 7982 "Activation failed: Already Active Volume", /* 10h */ 7983 "Activation failed: Unsupported Volume Type", /* 11h */ 7984 "Activation failed: Too Many Active Volumes", /* 12h */ 7985 "Activation failed: Volume ID in Use", /* 13h */ 7986 "Activation failed: Reported Failure", /* 14h */ 7987 "Activation failed: Importing a Volume", /* 15h */ 7988 NULL, /* 16h */ 7989 NULL, /* 17h */ 7990 NULL, /* 18h */ 7991 NULL, /* 19h */ 7992 NULL, /* 1Ah */ 7993 NULL, /* 1Bh */ 7994 NULL, /* 1Ch */ 7995 NULL, /* 1Dh */ 7996 NULL, /* 1Eh */ 7997 NULL, /* 1Fh */ 7998 "Phys Disk failed: Too Many Phys Disks", /* 20h */ 7999 "Phys Disk failed: Data Passed too Large", /* 21h */ 8000 "Phys Disk failed: DMA Error", /* 22h */ 8001 "Phys Disk failed: Invalid <channel:id>", /* 23h */ 8002 "Phys Disk failed: Creating Phys Disk Config " 8003 "Page", /* 24h */ 8004 NULL, /* 25h */ 8005 NULL, /* 26h */ 8006 NULL, /* 27h */ 8007 NULL, /* 28h */ 8008 NULL, /* 29h */ 8009 NULL, /* 2Ah */ 8010 NULL, /* 2Bh */ 8011 NULL, /* 2Ch */ 8012 NULL, /* 2Dh */ 8013 NULL, /* 2Eh */ 8014 NULL, /* 2Fh */ 8015 "Compatibility Error: IR Disabled", /* 30h */ 8016 "Compatibility Error: Inquiry Command Failed", /* 31h */ 8017 "Compatibility Error: Device not Direct Access " 8018 "Device ", /* 32h */ 8019 "Compatibility Error: Removable Device Found", /* 33h */ 8020 "Compatibility Error: Device SCSI Version not " 8021 "2 or Higher", /* 34h */ 8022 "Compatibility Error: SATA Device, 48 BIT LBA " 8023 "not Supported", /* 35h */ 8024 "Compatibility Error: Device doesn't have " 8025 "512 Byte Block Sizes", /* 36h */ 8026 "Compatibility Error: Volume Type Check Failed", /* 37h */ 8027 "Compatibility Error: Volume Type is " 8028 "Unsupported by FW", /* 38h */ 8029 "Compatibility Error: Disk Drive too Small for " 8030 "use in Volume", /* 39h */ 8031 "Compatibility Error: Phys Disk for Create " 8032 "Volume not Found", /* 3Ah */ 8033 "Compatibility Error: Too Many or too Few " 8034 "Disks for Volume Type", /* 3Bh */ 8035 "Compatibility Error: Disk stripe Sizes " 8036 "Must be 64KB", /* 3Ch */ 8037 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */ 8038 }; 8039 8040 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8041 /** 8042 * mpt_sas_log_info - Log information returned from SAS IOC. 8043 * @ioc: Pointer to MPT_ADAPTER structure 8044 * @log_info: U32 LogInfo reply word from the IOC 8045 * @cb_idx: callback function's handle 8046 * 8047 * Refer to lsi/mpi_log_sas.h. 8048 **/ 8049 static void 8050 mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx) 8051 { 8052 union loginfo_type { 8053 u32 loginfo; 8054 struct { 8055 u32 subcode:16; 8056 u32 code:8; 8057 u32 originator:4; 8058 u32 bus_type:4; 8059 } dw; 8060 }; 8061 union loginfo_type sas_loginfo; 8062 char *originator_desc = NULL; 8063 char *code_desc = NULL; 8064 char *sub_code_desc = NULL; 8065 8066 sas_loginfo.loginfo = log_info; 8067 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) && 8068 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str))) 8069 return; 8070 8071 originator_desc = originator_str[sas_loginfo.dw.originator]; 8072 8073 switch (sas_loginfo.dw.originator) { 8074 8075 case 0: /* IOP */ 8076 if (sas_loginfo.dw.code < 8077 ARRAY_SIZE(iop_code_str)) 8078 code_desc = iop_code_str[sas_loginfo.dw.code]; 8079 break; 8080 case 1: /* PL */ 8081 if (sas_loginfo.dw.code < 8082 ARRAY_SIZE(pl_code_str)) 8083 code_desc = pl_code_str[sas_loginfo.dw.code]; 8084 break; 8085 case 2: /* IR */ 8086 if (sas_loginfo.dw.code >= 8087 ARRAY_SIZE(ir_code_str)) 8088 break; 8089 code_desc = ir_code_str[sas_loginfo.dw.code]; 8090 if (sas_loginfo.dw.subcode >= 8091 ARRAY_SIZE(raid_sub_code_str)) 8092 break; 8093 if (sas_loginfo.dw.code == 0) 8094 sub_code_desc = 8095 raid_sub_code_str[sas_loginfo.dw.subcode]; 8096 break; 8097 default: 8098 return; 8099 } 8100 8101 if (sub_code_desc != NULL) 8102 printk(MYIOC_s_INFO_FMT 8103 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8104 " SubCode={%s} cb_idx %s\n", 8105 ioc->name, log_info, originator_desc, code_desc, 8106 sub_code_desc, MptCallbacksName[cb_idx]); 8107 else if (code_desc != NULL) 8108 printk(MYIOC_s_INFO_FMT 8109 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8110 " SubCode(0x%04x) cb_idx %s\n", 8111 ioc->name, log_info, originator_desc, code_desc, 8112 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]); 8113 else 8114 printk(MYIOC_s_INFO_FMT 8115 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x)," 8116 " SubCode(0x%04x) cb_idx %s\n", 8117 ioc->name, log_info, originator_desc, 8118 sas_loginfo.dw.code, sas_loginfo.dw.subcode, 8119 MptCallbacksName[cb_idx]); 8120 } 8121 8122 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8123 /** 8124 * mpt_iocstatus_info_config - IOCSTATUS information for config pages 8125 * @ioc: Pointer to MPT_ADAPTER structure 8126 * @ioc_status: U32 IOCStatus word from IOC 8127 * @mf: Pointer to MPT request frame 8128 * 8129 * Refer to lsi/mpi.h. 8130 **/ 8131 static void 8132 mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8133 { 8134 Config_t *pReq = (Config_t *)mf; 8135 char extend_desc[EVENT_DESCR_STR_SZ]; 8136 char *desc = NULL; 8137 u32 form; 8138 u8 page_type; 8139 8140 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED) 8141 page_type = pReq->ExtPageType; 8142 else 8143 page_type = pReq->Header.PageType; 8144 8145 /* 8146 * ignore invalid page messages for GET_NEXT_HANDLE 8147 */ 8148 form = le32_to_cpu(pReq->PageAddress); 8149 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) { 8150 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE || 8151 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER || 8152 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) { 8153 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) == 8154 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE) 8155 return; 8156 } 8157 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE) 8158 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) == 8159 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 8160 return; 8161 } 8162 8163 snprintf(extend_desc, EVENT_DESCR_STR_SZ, 8164 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh", 8165 page_type, pReq->Header.PageNumber, pReq->Action, form); 8166 8167 switch (ioc_status) { 8168 8169 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8170 desc = "Config Page Invalid Action"; 8171 break; 8172 8173 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8174 desc = "Config Page Invalid Type"; 8175 break; 8176 8177 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8178 desc = "Config Page Invalid Page"; 8179 break; 8180 8181 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8182 desc = "Config Page Invalid Data"; 8183 break; 8184 8185 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8186 desc = "Config Page No Defaults"; 8187 break; 8188 8189 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8190 desc = "Config Page Can't Commit"; 8191 break; 8192 } 8193 8194 if (!desc) 8195 return; 8196 8197 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n", 8198 ioc->name, ioc_status, desc, extend_desc)); 8199 } 8200 8201 /** 8202 * mpt_iocstatus_info - IOCSTATUS information returned from IOC. 8203 * @ioc: Pointer to MPT_ADAPTER structure 8204 * @ioc_status: U32 IOCStatus word from IOC 8205 * @mf: Pointer to MPT request frame 8206 * 8207 * Refer to lsi/mpi.h. 8208 **/ 8209 static void 8210 mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8211 { 8212 u32 status = ioc_status & MPI_IOCSTATUS_MASK; 8213 char *desc = NULL; 8214 8215 switch (status) { 8216 8217 /****************************************************************************/ 8218 /* Common IOCStatus values for all replies */ 8219 /****************************************************************************/ 8220 8221 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */ 8222 desc = "Invalid Function"; 8223 break; 8224 8225 case MPI_IOCSTATUS_BUSY: /* 0x0002 */ 8226 desc = "Busy"; 8227 break; 8228 8229 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */ 8230 desc = "Invalid SGL"; 8231 break; 8232 8233 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */ 8234 desc = "Internal Error"; 8235 break; 8236 8237 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */ 8238 desc = "Reserved"; 8239 break; 8240 8241 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */ 8242 desc = "Insufficient Resources"; 8243 break; 8244 8245 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */ 8246 desc = "Invalid Field"; 8247 break; 8248 8249 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */ 8250 desc = "Invalid State"; 8251 break; 8252 8253 /****************************************************************************/ 8254 /* Config IOCStatus values */ 8255 /****************************************************************************/ 8256 8257 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8258 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8259 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8260 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8261 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8262 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8263 mpt_iocstatus_info_config(ioc, status, mf); 8264 break; 8265 8266 /****************************************************************************/ 8267 /* SCSIIO Reply (SPI, FCP, SAS) initiator values */ 8268 /* */ 8269 /* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */ 8270 /* */ 8271 /****************************************************************************/ 8272 8273 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */ 8274 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */ 8275 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */ 8276 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */ 8277 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */ 8278 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */ 8279 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */ 8280 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */ 8281 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */ 8282 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */ 8283 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */ 8284 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */ 8285 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */ 8286 break; 8287 8288 /****************************************************************************/ 8289 /* SCSI Target values */ 8290 /****************************************************************************/ 8291 8292 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */ 8293 desc = "Target: Priority IO"; 8294 break; 8295 8296 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */ 8297 desc = "Target: Invalid Port"; 8298 break; 8299 8300 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */ 8301 desc = "Target Invalid IO Index:"; 8302 break; 8303 8304 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */ 8305 desc = "Target: Aborted"; 8306 break; 8307 8308 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */ 8309 desc = "Target: No Conn Retryable"; 8310 break; 8311 8312 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */ 8313 desc = "Target: No Connection"; 8314 break; 8315 8316 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */ 8317 desc = "Target: Transfer Count Mismatch"; 8318 break; 8319 8320 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */ 8321 desc = "Target: STS Data not Sent"; 8322 break; 8323 8324 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */ 8325 desc = "Target: Data Offset Error"; 8326 break; 8327 8328 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */ 8329 desc = "Target: Too Much Write Data"; 8330 break; 8331 8332 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */ 8333 desc = "Target: IU Too Short"; 8334 break; 8335 8336 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */ 8337 desc = "Target: ACK NAK Timeout"; 8338 break; 8339 8340 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */ 8341 desc = "Target: Nak Received"; 8342 break; 8343 8344 /****************************************************************************/ 8345 /* Fibre Channel Direct Access values */ 8346 /****************************************************************************/ 8347 8348 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */ 8349 desc = "FC: Aborted"; 8350 break; 8351 8352 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */ 8353 desc = "FC: RX ID Invalid"; 8354 break; 8355 8356 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */ 8357 desc = "FC: DID Invalid"; 8358 break; 8359 8360 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */ 8361 desc = "FC: Node Logged Out"; 8362 break; 8363 8364 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */ 8365 desc = "FC: Exchange Canceled"; 8366 break; 8367 8368 /****************************************************************************/ 8369 /* LAN values */ 8370 /****************************************************************************/ 8371 8372 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */ 8373 desc = "LAN: Device not Found"; 8374 break; 8375 8376 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */ 8377 desc = "LAN: Device Failure"; 8378 break; 8379 8380 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */ 8381 desc = "LAN: Transmit Error"; 8382 break; 8383 8384 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */ 8385 desc = "LAN: Transmit Aborted"; 8386 break; 8387 8388 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */ 8389 desc = "LAN: Receive Error"; 8390 break; 8391 8392 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */ 8393 desc = "LAN: Receive Aborted"; 8394 break; 8395 8396 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */ 8397 desc = "LAN: Partial Packet"; 8398 break; 8399 8400 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */ 8401 desc = "LAN: Canceled"; 8402 break; 8403 8404 /****************************************************************************/ 8405 /* Serial Attached SCSI values */ 8406 /****************************************************************************/ 8407 8408 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */ 8409 desc = "SAS: SMP Request Failed"; 8410 break; 8411 8412 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */ 8413 desc = "SAS: SMP Data Overrun"; 8414 break; 8415 8416 default: 8417 desc = "Others"; 8418 break; 8419 } 8420 8421 if (!desc) 8422 return; 8423 8424 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n", 8425 ioc->name, status, desc)); 8426 } 8427 8428 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8429 EXPORT_SYMBOL(mpt_attach); 8430 EXPORT_SYMBOL(mpt_detach); 8431 #ifdef CONFIG_PM 8432 EXPORT_SYMBOL(mpt_resume); 8433 EXPORT_SYMBOL(mpt_suspend); 8434 #endif 8435 EXPORT_SYMBOL(ioc_list); 8436 EXPORT_SYMBOL(mpt_register); 8437 EXPORT_SYMBOL(mpt_deregister); 8438 EXPORT_SYMBOL(mpt_event_register); 8439 EXPORT_SYMBOL(mpt_event_deregister); 8440 EXPORT_SYMBOL(mpt_reset_register); 8441 EXPORT_SYMBOL(mpt_reset_deregister); 8442 EXPORT_SYMBOL(mpt_device_driver_register); 8443 EXPORT_SYMBOL(mpt_device_driver_deregister); 8444 EXPORT_SYMBOL(mpt_get_msg_frame); 8445 EXPORT_SYMBOL(mpt_put_msg_frame); 8446 EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri); 8447 EXPORT_SYMBOL(mpt_free_msg_frame); 8448 EXPORT_SYMBOL(mpt_send_handshake_request); 8449 EXPORT_SYMBOL(mpt_verify_adapter); 8450 EXPORT_SYMBOL(mpt_GetIocState); 8451 EXPORT_SYMBOL(mpt_print_ioc_summary); 8452 EXPORT_SYMBOL(mpt_HardResetHandler); 8453 EXPORT_SYMBOL(mpt_config); 8454 EXPORT_SYMBOL(mpt_findImVolumes); 8455 EXPORT_SYMBOL(mpt_alloc_fw_memory); 8456 EXPORT_SYMBOL(mpt_free_fw_memory); 8457 EXPORT_SYMBOL(mptbase_sas_persist_operation); 8458 EXPORT_SYMBOL(mpt_raid_phys_disk_pg0); 8459 8460 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8461 /** 8462 * fusion_init - Fusion MPT base driver initialization routine. 8463 * 8464 * Returns 0 for success, non-zero for failure. 8465 */ 8466 static int __init 8467 fusion_init(void) 8468 { 8469 u8 cb_idx; 8470 8471 show_mptmod_ver(my_NAME, my_VERSION); 8472 printk(KERN_INFO COPYRIGHT "\n"); 8473 8474 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 8475 MptCallbacks[cb_idx] = NULL; 8476 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 8477 MptEvHandlers[cb_idx] = NULL; 8478 MptResetHandlers[cb_idx] = NULL; 8479 } 8480 8481 /* Register ourselves (mptbase) in order to facilitate 8482 * EventNotification handling. 8483 */ 8484 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER, 8485 "mptbase_reply"); 8486 8487 /* Register for hard reset handling callbacks. 8488 */ 8489 mpt_reset_register(mpt_base_index, mpt_ioc_reset); 8490 8491 #ifdef CONFIG_PROC_FS 8492 (void) procmpt_create(); 8493 #endif 8494 return 0; 8495 } 8496 8497 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8498 /** 8499 * fusion_exit - Perform driver unload cleanup. 8500 * 8501 * This routine frees all resources associated with each MPT adapter 8502 * and removes all %MPT_PROCFS_MPTBASEDIR entries. 8503 */ 8504 static void __exit 8505 fusion_exit(void) 8506 { 8507 8508 mpt_reset_deregister(mpt_base_index); 8509 8510 #ifdef CONFIG_PROC_FS 8511 procmpt_destroy(); 8512 #endif 8513 } 8514 8515 module_init(fusion_init); 8516 module_exit(fusion_exit); 8517