1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include "iris_core.h" 7 #include "iris_hfi_gen2.h" 8 #include "iris_platform_common.h" 9 #include "iris_vpu_common.h" 10 11 #define VIDEO_ARCH_LX 1 12 13 static void iris_set_sm8550_preset_registers(struct iris_core *core) 14 { 15 writel(0x0, core->reg_base + 0xB0088); 16 } 17 18 static const struct icc_info sm8550_icc_table[] = { 19 { "cpu-cfg", 1000, 1000 }, 20 { "video-mem", 1000, 15000000 }, 21 }; 22 23 static const char * const sm8550_clk_reset_table[] = { "bus" }; 24 25 static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" }; 26 27 static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" }; 28 29 static const struct platform_clk_data sm8550_clk_table[] = { 30 {IRIS_AXI_CLK, "iface" }, 31 {IRIS_CTRL_CLK, "core" }, 32 {IRIS_HW_CLK, "vcodec0_core" }, 33 }; 34 35 static struct ubwc_config_data ubwc_config_sm8550 = { 36 .max_channels = 8, 37 .mal_length = 32, 38 .highest_bank_bit = 16, 39 .bank_swzl_level = 0, 40 .bank_swz2_level = 1, 41 .bank_swz3_level = 1, 42 .bank_spreading = 1, 43 }; 44 45 static struct tz_cp_config tz_cp_config_sm8550 = { 46 .cp_start = 0, 47 .cp_size = 0x25800000, 48 .cp_nonpixel_start = 0x01000000, 49 .cp_nonpixel_size = 0x24800000, 50 }; 51 52 struct iris_platform_data sm8550_data = { 53 .get_instance = iris_hfi_gen2_get_instance, 54 .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, 55 .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, 56 .vpu_ops = &iris_vpu3_ops, 57 .set_preset_registers = iris_set_sm8550_preset_registers, 58 .icc_tbl = sm8550_icc_table, 59 .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), 60 .clk_rst_tbl = sm8550_clk_reset_table, 61 .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), 62 .pmdomain_tbl = sm8550_pmdomain_table, 63 .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), 64 .opp_pd_tbl = sm8550_opp_pd_table, 65 .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), 66 .clk_tbl = sm8550_clk_table, 67 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), 68 /* Upper bound of DMA address range */ 69 .dma_mask = 0xe0000000 - 1, 70 .fwname = "qcom/vpu/vpu30_p4.mbn", 71 .pas_id = IRIS_PAS_ID, 72 .tz_cp_config_data = &tz_cp_config_sm8550, 73 .core_arch = VIDEO_ARCH_LX, 74 .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, 75 .ubwc_config = &ubwc_config_sm8550, 76 .num_vpp_pipe = 4, 77 }; 78