1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_PLATFORM_COMMON_H__ 7 #define __IRIS_PLATFORM_COMMON_H__ 8 9 #include <linux/bits.h> 10 11 struct iris_core; 12 struct iris_inst; 13 14 #define IRIS_PAS_ID 9 15 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ 16 #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ 17 18 #define REGISTER_BIT_DEPTH(luma, chroma) ((luma) << 16 | (chroma)) 19 #define BIT_DEPTH_8 REGISTER_BIT_DEPTH(8, 8) 20 #define CODED_FRAMES_PROGRESSIVE 0x0 21 #define DEFAULT_MAX_HOST_BUF_COUNT 64 22 #define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256 23 #define DEFAULT_FPS 30 24 25 enum stage_type { 26 STAGE_1 = 1, 27 STAGE_2 = 2, 28 }; 29 30 enum pipe_type { 31 PIPE_1 = 1, 32 PIPE_2 = 2, 33 PIPE_4 = 4, 34 }; 35 36 extern struct iris_platform_data sm8550_data; 37 38 enum platform_clk_type { 39 IRIS_AXI_CLK, 40 IRIS_CTRL_CLK, 41 IRIS_HW_CLK, 42 }; 43 44 struct platform_clk_data { 45 enum platform_clk_type clk_type; 46 const char *clk_name; 47 }; 48 49 struct tz_cp_config { 50 u32 cp_start; 51 u32 cp_size; 52 u32 cp_nonpixel_start; 53 u32 cp_nonpixel_size; 54 }; 55 56 struct ubwc_config_data { 57 u32 max_channels; 58 u32 mal_length; 59 u32 highest_bank_bit; 60 u32 bank_swzl_level; 61 u32 bank_swz2_level; 62 u32 bank_swz3_level; 63 u32 bank_spreading; 64 }; 65 66 struct platform_inst_caps { 67 u32 min_frame_width; 68 u32 max_frame_width; 69 u32 min_frame_height; 70 u32 max_frame_height; 71 u32 max_mbpf; 72 u32 mb_cycles_vsp; 73 u32 mb_cycles_vpp; 74 u32 mb_cycles_fw; 75 u32 mb_cycles_fw_vpp; 76 u32 num_comv; 77 }; 78 79 enum platform_inst_fw_cap_type { 80 PROFILE = 1, 81 LEVEL, 82 INPUT_BUF_HOST_MAX_COUNT, 83 STAGE, 84 PIPE, 85 POC, 86 CODED_FRAMES, 87 BIT_DEPTH, 88 RAP_FRAME, 89 DEBLOCK, 90 INST_FW_CAP_MAX, 91 }; 92 93 enum platform_inst_fw_cap_flags { 94 CAP_FLAG_DYNAMIC_ALLOWED = BIT(0), 95 CAP_FLAG_MENU = BIT(1), 96 CAP_FLAG_INPUT_PORT = BIT(2), 97 CAP_FLAG_OUTPUT_PORT = BIT(3), 98 CAP_FLAG_CLIENT_SET = BIT(4), 99 CAP_FLAG_BITMASK = BIT(5), 100 CAP_FLAG_VOLATILE = BIT(6), 101 }; 102 103 struct platform_inst_fw_cap { 104 enum platform_inst_fw_cap_type cap_id; 105 s64 min; 106 s64 max; 107 s64 step_or_mask; 108 s64 value; 109 u32 hfi_id; 110 enum platform_inst_fw_cap_flags flags; 111 int (*set)(struct iris_inst *inst, 112 enum platform_inst_fw_cap_type cap_id); 113 }; 114 115 struct bw_info { 116 u32 mbs_per_sec; 117 u32 bw_ddr; 118 }; 119 120 struct iris_core_power { 121 u64 clk_freq; 122 u64 icc_bw; 123 }; 124 125 struct iris_inst_power { 126 u64 min_freq; 127 u32 icc_bw; 128 }; 129 130 struct icc_vote_data { 131 u32 height, width; 132 u32 fps; 133 }; 134 135 enum platform_pm_domain_type { 136 IRIS_CTRL_POWER_DOMAIN, 137 IRIS_HW_POWER_DOMAIN, 138 }; 139 140 struct iris_platform_data { 141 void (*init_hfi_command_ops)(struct iris_core *core); 142 void (*init_hfi_response_ops)(struct iris_core *core); 143 struct iris_inst *(*get_instance)(void); 144 const struct vpu_ops *vpu_ops; 145 void (*set_preset_registers)(struct iris_core *core); 146 const struct icc_info *icc_tbl; 147 unsigned int icc_tbl_size; 148 const struct bw_info *bw_tbl_dec; 149 unsigned int bw_tbl_dec_size; 150 const char * const *pmdomain_tbl; 151 unsigned int pmdomain_tbl_size; 152 const char * const *opp_pd_tbl; 153 unsigned int opp_pd_tbl_size; 154 const struct platform_clk_data *clk_tbl; 155 unsigned int clk_tbl_size; 156 const char * const *clk_rst_tbl; 157 unsigned int clk_rst_tbl_size; 158 u64 dma_mask; 159 const char *fwname; 160 u32 pas_id; 161 struct platform_inst_caps *inst_caps; 162 struct platform_inst_fw_cap *inst_fw_caps; 163 u32 inst_fw_caps_size; 164 struct tz_cp_config *tz_cp_config_data; 165 u32 core_arch; 166 u32 hw_response_timeout; 167 struct ubwc_config_data *ubwc_config; 168 u32 num_vpp_pipe; 169 u32 max_session_count; 170 u32 max_core_mbpf; 171 const u32 *input_config_params; 172 unsigned int input_config_params_size; 173 const u32 *output_config_params; 174 unsigned int output_config_params_size; 175 const u32 *dec_input_prop; 176 unsigned int dec_input_prop_size; 177 const u32 *dec_output_prop; 178 unsigned int dec_output_prop_size; 179 const u32 *dec_ip_int_buf_tbl; 180 unsigned int dec_ip_int_buf_tbl_size; 181 const u32 *dec_op_int_buf_tbl; 182 unsigned int dec_op_int_buf_tbl_size; 183 }; 184 185 #endif 186