1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_PLATFORM_COMMON_H__ 7 #define __IRIS_PLATFORM_COMMON_H__ 8 9 #include <linux/bits.h> 10 11 struct iris_core; 12 struct iris_inst; 13 14 #define IRIS_PAS_ID 9 15 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ 16 #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ 17 18 #define REGISTER_BIT_DEPTH(luma, chroma) ((luma) << 16 | (chroma)) 19 #define BIT_DEPTH_8 REGISTER_BIT_DEPTH(8, 8) 20 #define CODED_FRAMES_PROGRESSIVE 0x0 21 #define DEFAULT_MAX_HOST_BUF_COUNT 64 22 #define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256 23 enum stage_type { 24 STAGE_1 = 1, 25 STAGE_2 = 2, 26 }; 27 28 enum pipe_type { 29 PIPE_1 = 1, 30 PIPE_2 = 2, 31 PIPE_4 = 4, 32 }; 33 34 extern struct iris_platform_data sm8550_data; 35 36 enum platform_clk_type { 37 IRIS_AXI_CLK, 38 IRIS_CTRL_CLK, 39 IRIS_HW_CLK, 40 }; 41 42 struct platform_clk_data { 43 enum platform_clk_type clk_type; 44 const char *clk_name; 45 }; 46 47 struct tz_cp_config { 48 u32 cp_start; 49 u32 cp_size; 50 u32 cp_nonpixel_start; 51 u32 cp_nonpixel_size; 52 }; 53 54 struct ubwc_config_data { 55 u32 max_channels; 56 u32 mal_length; 57 u32 highest_bank_bit; 58 u32 bank_swzl_level; 59 u32 bank_swz2_level; 60 u32 bank_swz3_level; 61 u32 bank_spreading; 62 }; 63 64 struct platform_inst_caps { 65 u32 min_frame_width; 66 u32 max_frame_width; 67 u32 min_frame_height; 68 u32 max_frame_height; 69 u32 max_mbpf; 70 u32 num_comv; 71 }; 72 73 enum platform_inst_fw_cap_type { 74 PROFILE = 1, 75 LEVEL, 76 INPUT_BUF_HOST_MAX_COUNT, 77 STAGE, 78 PIPE, 79 POC, 80 CODED_FRAMES, 81 BIT_DEPTH, 82 RAP_FRAME, 83 DEBLOCK, 84 INST_FW_CAP_MAX, 85 }; 86 87 enum platform_inst_fw_cap_flags { 88 CAP_FLAG_DYNAMIC_ALLOWED = BIT(0), 89 CAP_FLAG_MENU = BIT(1), 90 CAP_FLAG_INPUT_PORT = BIT(2), 91 CAP_FLAG_OUTPUT_PORT = BIT(3), 92 CAP_FLAG_CLIENT_SET = BIT(4), 93 CAP_FLAG_BITMASK = BIT(5), 94 CAP_FLAG_VOLATILE = BIT(6), 95 }; 96 97 struct platform_inst_fw_cap { 98 enum platform_inst_fw_cap_type cap_id; 99 s64 min; 100 s64 max; 101 s64 step_or_mask; 102 s64 value; 103 u32 hfi_id; 104 enum platform_inst_fw_cap_flags flags; 105 int (*set)(struct iris_inst *inst, 106 enum platform_inst_fw_cap_type cap_id); 107 }; 108 109 struct iris_core_power { 110 u64 clk_freq; 111 u64 icc_bw; 112 }; 113 114 enum platform_pm_domain_type { 115 IRIS_CTRL_POWER_DOMAIN, 116 IRIS_HW_POWER_DOMAIN, 117 }; 118 119 struct iris_platform_data { 120 void (*init_hfi_command_ops)(struct iris_core *core); 121 void (*init_hfi_response_ops)(struct iris_core *core); 122 struct iris_inst *(*get_instance)(void); 123 const struct vpu_ops *vpu_ops; 124 void (*set_preset_registers)(struct iris_core *core); 125 const struct icc_info *icc_tbl; 126 unsigned int icc_tbl_size; 127 const char * const *pmdomain_tbl; 128 unsigned int pmdomain_tbl_size; 129 const char * const *opp_pd_tbl; 130 unsigned int opp_pd_tbl_size; 131 const struct platform_clk_data *clk_tbl; 132 unsigned int clk_tbl_size; 133 const char * const *clk_rst_tbl; 134 unsigned int clk_rst_tbl_size; 135 u64 dma_mask; 136 const char *fwname; 137 u32 pas_id; 138 struct platform_inst_caps *inst_caps; 139 struct platform_inst_fw_cap *inst_fw_caps; 140 u32 inst_fw_caps_size; 141 struct tz_cp_config *tz_cp_config_data; 142 u32 core_arch; 143 u32 hw_response_timeout; 144 struct ubwc_config_data *ubwc_config; 145 u32 num_vpp_pipe; 146 u32 max_session_count; 147 u32 max_core_mbpf; 148 const u32 *input_config_params; 149 unsigned int input_config_params_size; 150 const u32 *output_config_params; 151 unsigned int output_config_params_size; 152 const u32 *dec_input_prop; 153 unsigned int dec_input_prop_size; 154 const u32 *dec_output_prop; 155 unsigned int dec_output_prop_size; 156 const u32 *dec_ip_int_buf_tbl; 157 unsigned int dec_ip_int_buf_tbl_size; 158 const u32 *dec_op_int_buf_tbl; 159 unsigned int dec_op_int_buf_tbl_size; 160 }; 161 162 #endif 163