1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_PLATFORM_COMMON_H__ 7 #define __IRIS_PLATFORM_COMMON_H__ 8 9 struct iris_core; 10 11 #define IRIS_PAS_ID 9 12 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ 13 #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ 14 15 extern struct iris_platform_data sm8550_data; 16 17 enum platform_clk_type { 18 IRIS_AXI_CLK, 19 IRIS_CTRL_CLK, 20 IRIS_HW_CLK, 21 }; 22 23 struct platform_clk_data { 24 enum platform_clk_type clk_type; 25 const char *clk_name; 26 }; 27 28 struct tz_cp_config { 29 u32 cp_start; 30 u32 cp_size; 31 u32 cp_nonpixel_start; 32 u32 cp_nonpixel_size; 33 }; 34 35 struct ubwc_config_data { 36 u32 max_channels; 37 u32 mal_length; 38 u32 highest_bank_bit; 39 u32 bank_swzl_level; 40 u32 bank_swz2_level; 41 u32 bank_swz3_level; 42 u32 bank_spreading; 43 }; 44 45 struct iris_core_power { 46 u64 clk_freq; 47 u64 icc_bw; 48 }; 49 50 enum platform_pm_domain_type { 51 IRIS_CTRL_POWER_DOMAIN, 52 IRIS_HW_POWER_DOMAIN, 53 }; 54 55 struct iris_platform_data { 56 void (*init_hfi_command_ops)(struct iris_core *core); 57 void (*init_hfi_response_ops)(struct iris_core *core); 58 struct iris_inst *(*get_instance)(void); 59 const struct vpu_ops *vpu_ops; 60 void (*set_preset_registers)(struct iris_core *core); 61 const struct icc_info *icc_tbl; 62 unsigned int icc_tbl_size; 63 const char * const *pmdomain_tbl; 64 unsigned int pmdomain_tbl_size; 65 const char * const *opp_pd_tbl; 66 unsigned int opp_pd_tbl_size; 67 const struct platform_clk_data *clk_tbl; 68 unsigned int clk_tbl_size; 69 const char * const *clk_rst_tbl; 70 unsigned int clk_rst_tbl_size; 71 u64 dma_mask; 72 const char *fwname; 73 u32 pas_id; 74 struct tz_cp_config *tz_cp_config_data; 75 u32 core_arch; 76 u32 hw_response_timeout; 77 struct ubwc_config_data *ubwc_config; 78 u32 num_vpp_pipe; 79 }; 80 81 #endif 82