1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_PLATFORM_COMMON_H__ 7 #define __IRIS_PLATFORM_COMMON_H__ 8 9 struct iris_core; 10 11 #define IRIS_PAS_ID 9 12 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ 13 #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ 14 15 extern struct iris_platform_data sm8550_data; 16 17 enum platform_clk_type { 18 IRIS_AXI_CLK, 19 IRIS_CTRL_CLK, 20 IRIS_HW_CLK, 21 }; 22 23 struct platform_clk_data { 24 enum platform_clk_type clk_type; 25 const char *clk_name; 26 }; 27 28 struct tz_cp_config { 29 u32 cp_start; 30 u32 cp_size; 31 u32 cp_nonpixel_start; 32 u32 cp_nonpixel_size; 33 }; 34 35 struct ubwc_config_data { 36 u32 max_channels; 37 u32 mal_length; 38 u32 highest_bank_bit; 39 u32 bank_swzl_level; 40 u32 bank_swz2_level; 41 u32 bank_swz3_level; 42 u32 bank_spreading; 43 }; 44 45 struct platform_inst_caps { 46 u32 max_mbpf; 47 }; 48 struct iris_core_power { 49 u64 clk_freq; 50 u64 icc_bw; 51 }; 52 53 enum platform_pm_domain_type { 54 IRIS_CTRL_POWER_DOMAIN, 55 IRIS_HW_POWER_DOMAIN, 56 }; 57 58 struct iris_platform_data { 59 void (*init_hfi_command_ops)(struct iris_core *core); 60 void (*init_hfi_response_ops)(struct iris_core *core); 61 struct iris_inst *(*get_instance)(void); 62 const struct vpu_ops *vpu_ops; 63 void (*set_preset_registers)(struct iris_core *core); 64 const struct icc_info *icc_tbl; 65 unsigned int icc_tbl_size; 66 const char * const *pmdomain_tbl; 67 unsigned int pmdomain_tbl_size; 68 const char * const *opp_pd_tbl; 69 unsigned int opp_pd_tbl_size; 70 const struct platform_clk_data *clk_tbl; 71 unsigned int clk_tbl_size; 72 const char * const *clk_rst_tbl; 73 unsigned int clk_rst_tbl_size; 74 u64 dma_mask; 75 const char *fwname; 76 u32 pas_id; 77 struct platform_inst_caps *inst_caps; 78 struct tz_cp_config *tz_cp_config_data; 79 u32 core_arch; 80 u32 hw_response_timeout; 81 struct ubwc_config_data *ubwc_config; 82 u32 num_vpp_pipe; 83 u32 max_session_count; 84 }; 85 86 #endif 87