1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_PLATFORM_COMMON_H__ 7 #define __IRIS_PLATFORM_COMMON_H__ 8 9 struct iris_core; 10 11 #define IRIS_PAS_ID 9 12 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ 13 #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */ 14 15 extern struct iris_platform_data sm8550_data; 16 17 enum platform_clk_type { 18 IRIS_AXI_CLK, 19 IRIS_CTRL_CLK, 20 IRIS_HW_CLK, 21 }; 22 23 struct platform_clk_data { 24 enum platform_clk_type clk_type; 25 const char *clk_name; 26 }; 27 28 struct tz_cp_config { 29 u32 cp_start; 30 u32 cp_size; 31 u32 cp_nonpixel_start; 32 u32 cp_nonpixel_size; 33 }; 34 35 struct ubwc_config_data { 36 u32 max_channels; 37 u32 mal_length; 38 u32 highest_bank_bit; 39 u32 bank_swzl_level; 40 u32 bank_swz2_level; 41 u32 bank_swz3_level; 42 u32 bank_spreading; 43 }; 44 45 struct platform_inst_caps { 46 u32 min_frame_width; 47 u32 max_frame_width; 48 u32 min_frame_height; 49 u32 max_frame_height; 50 u32 max_mbpf; 51 }; 52 53 enum platform_inst_fw_cap_type { 54 PROFILE = 1, 55 LEVEL, 56 DEBLOCK, 57 INST_FW_CAP_MAX, 58 }; 59 60 enum platform_inst_fw_cap_flags { 61 CAP_FLAG_DYNAMIC_ALLOWED = BIT(0), 62 CAP_FLAG_MENU = BIT(1), 63 CAP_FLAG_INPUT_PORT = BIT(2), 64 CAP_FLAG_OUTPUT_PORT = BIT(3), 65 CAP_FLAG_CLIENT_SET = BIT(4), 66 CAP_FLAG_BITMASK = BIT(5), 67 CAP_FLAG_VOLATILE = BIT(6), 68 }; 69 70 struct platform_inst_fw_cap { 71 enum platform_inst_fw_cap_type cap_id; 72 s64 min; 73 s64 max; 74 s64 step_or_mask; 75 s64 value; 76 u32 hfi_id; 77 enum platform_inst_fw_cap_flags flags; 78 }; 79 80 struct iris_core_power { 81 u64 clk_freq; 82 u64 icc_bw; 83 }; 84 85 enum platform_pm_domain_type { 86 IRIS_CTRL_POWER_DOMAIN, 87 IRIS_HW_POWER_DOMAIN, 88 }; 89 90 struct iris_platform_data { 91 void (*init_hfi_command_ops)(struct iris_core *core); 92 void (*init_hfi_response_ops)(struct iris_core *core); 93 struct iris_inst *(*get_instance)(void); 94 const struct vpu_ops *vpu_ops; 95 void (*set_preset_registers)(struct iris_core *core); 96 const struct icc_info *icc_tbl; 97 unsigned int icc_tbl_size; 98 const char * const *pmdomain_tbl; 99 unsigned int pmdomain_tbl_size; 100 const char * const *opp_pd_tbl; 101 unsigned int opp_pd_tbl_size; 102 const struct platform_clk_data *clk_tbl; 103 unsigned int clk_tbl_size; 104 const char * const *clk_rst_tbl; 105 unsigned int clk_rst_tbl_size; 106 u64 dma_mask; 107 const char *fwname; 108 u32 pas_id; 109 struct platform_inst_caps *inst_caps; 110 struct platform_inst_fw_cap *inst_fw_caps; 111 u32 inst_fw_caps_size; 112 struct tz_cp_config *tz_cp_config_data; 113 u32 core_arch; 114 u32 hw_response_timeout; 115 struct ubwc_config_data *ubwc_config; 116 u32 num_vpp_pipe; 117 u32 max_session_count; 118 }; 119 120 #endif 121