1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2016 4 * 5 * Author: Benjamin Gaignard <[email protected]> 6 * 7 */ 8 9 #include <linux/iio/iio.h> 10 #include <linux/iio/sysfs.h> 11 #include <linux/iio/timer/stm32-timer-trigger.h> 12 #include <linux/iio/trigger.h> 13 #include <linux/mfd/stm32-timers.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 19 #define MAX_TRIGGERS 7 20 #define MAX_VALIDS 5 21 22 /* List the triggers created by each timer */ 23 static const void *triggers_table[][MAX_TRIGGERS] = { 24 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, 25 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, 26 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, 27 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, 28 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, 29 { TIM6_TRGO,}, 30 { TIM7_TRGO,}, 31 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, 32 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, 33 { TIM10_OC1,}, 34 { TIM11_OC1,}, 35 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, 36 { TIM13_OC1,}, 37 { TIM14_OC1,}, 38 { TIM15_TRGO,}, 39 { TIM16_OC1,}, 40 { TIM17_OC1,}, 41 }; 42 43 /* List the triggers accepted by each timer */ 44 static const void *valids_table[][MAX_VALIDS] = { 45 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 46 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 47 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,}, 48 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 49 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,}, 50 { }, /* timer 6 */ 51 { }, /* timer 7 */ 52 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 53 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,}, 54 { }, /* timer 10 */ 55 { }, /* timer 11 */ 56 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 57 }; 58 59 static const void *stm32h7_valids_table[][MAX_VALIDS] = { 60 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 61 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 62 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,}, 63 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 64 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 65 { }, /* timer 6 */ 66 { }, /* timer 7 */ 67 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 68 { }, /* timer 9 */ 69 { }, /* timer 10 */ 70 { }, /* timer 11 */ 71 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 72 { }, /* timer 13 */ 73 { }, /* timer 14 */ 74 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,}, 75 { }, /* timer 16 */ 76 { }, /* timer 17 */ 77 }; 78 79 struct stm32_timer_trigger_regs { 80 u32 cr1; 81 u32 cr2; 82 u32 psc; 83 u32 arr; 84 u32 cnt; 85 u32 smcr; 86 }; 87 88 struct stm32_timer_trigger { 89 struct device *dev; 90 struct regmap *regmap; 91 struct clk *clk; 92 bool enabled; 93 u32 max_arr; 94 const void *triggers; 95 const void *valids; 96 bool has_trgo2; 97 struct mutex lock; /* concurrent sysfs configuration */ 98 struct list_head tr_list; 99 struct stm32_timer_trigger_regs bak; 100 }; 101 102 struct stm32_timer_trigger_cfg { 103 const void *(*valids_table)[MAX_VALIDS]; 104 const unsigned int num_valids_table; 105 }; 106 107 static bool stm32_timer_is_trgo2_name(const char *name) 108 { 109 return !!strstr(name, "trgo2"); 110 } 111 112 static bool stm32_timer_is_trgo_name(const char *name) 113 { 114 return (!!strstr(name, "trgo") && !strstr(name, "trgo2")); 115 } 116 117 static int stm32_timer_start(struct stm32_timer_trigger *priv, 118 struct iio_trigger *trig, 119 unsigned int frequency) 120 { 121 unsigned long long prd, div; 122 int prescaler = 0, ret; 123 u32 ccer; 124 125 /* Period and prescaler values depends of clock rate */ 126 div = (unsigned long long)clk_get_rate(priv->clk); 127 128 do_div(div, frequency); 129 130 prd = div; 131 132 /* 133 * Increase prescaler value until we get a result that fit 134 * with auto reload register maximum value. 135 */ 136 while (div > priv->max_arr) { 137 prescaler++; 138 div = prd; 139 do_div(div, (prescaler + 1)); 140 } 141 prd = div; 142 143 if (prescaler > MAX_TIM_PSC) { 144 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); 145 return -EINVAL; 146 } 147 148 /* Check if nobody else use the timer */ 149 regmap_read(priv->regmap, TIM_CCER, &ccer); 150 if (ccer & TIM_CCER_CCXE) 151 return -EBUSY; 152 153 guard(mutex)(&priv->lock); 154 if (!priv->enabled) { 155 priv->enabled = true; 156 ret = clk_enable(priv->clk); 157 if (ret) 158 return ret; 159 } 160 161 regmap_write(priv->regmap, TIM_PSC, prescaler); 162 regmap_write(priv->regmap, TIM_ARR, prd - 1); 163 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 164 165 /* Force master mode to update mode */ 166 if (stm32_timer_is_trgo2_name(trig->name)) 167 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 168 0x2 << TIM_CR2_MMS2_SHIFT); 169 else 170 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 171 0x2 << TIM_CR2_MMS_SHIFT); 172 173 /* Make sure that registers are updated */ 174 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 175 176 /* Enable controller */ 177 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 178 179 return 0; 180 } 181 182 static void stm32_timer_stop(struct stm32_timer_trigger *priv, 183 struct iio_trigger *trig) 184 { 185 u32 ccer; 186 187 regmap_read(priv->regmap, TIM_CCER, &ccer); 188 if (ccer & TIM_CCER_CCXE) 189 return; 190 191 mutex_lock(&priv->lock); 192 /* Stop timer */ 193 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 194 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 195 regmap_write(priv->regmap, TIM_PSC, 0); 196 regmap_write(priv->regmap, TIM_ARR, 0); 197 198 /* Force disable master mode */ 199 if (stm32_timer_is_trgo2_name(trig->name)) 200 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); 201 else 202 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS); 203 204 /* Make sure that registers are updated */ 205 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 206 207 if (priv->enabled) { 208 priv->enabled = false; 209 clk_disable(priv->clk); 210 } 211 mutex_unlock(&priv->lock); 212 } 213 214 static ssize_t stm32_tt_store_frequency(struct device *dev, 215 struct device_attribute *attr, 216 const char *buf, size_t len) 217 { 218 struct iio_trigger *trig = to_iio_trigger(dev); 219 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 220 unsigned int freq; 221 int ret; 222 223 ret = kstrtouint(buf, 10, &freq); 224 if (ret) 225 return ret; 226 227 if (freq == 0) { 228 stm32_timer_stop(priv, trig); 229 } else { 230 ret = stm32_timer_start(priv, trig, freq); 231 if (ret) 232 return ret; 233 } 234 235 return len; 236 } 237 238 static ssize_t stm32_tt_read_frequency(struct device *dev, 239 struct device_attribute *attr, char *buf) 240 { 241 struct iio_trigger *trig = to_iio_trigger(dev); 242 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 243 u32 psc, arr, cr1; 244 unsigned long long freq = 0; 245 246 regmap_read(priv->regmap, TIM_CR1, &cr1); 247 regmap_read(priv->regmap, TIM_PSC, &psc); 248 regmap_read(priv->regmap, TIM_ARR, &arr); 249 250 if (cr1 & TIM_CR1_CEN) { 251 freq = (unsigned long long)clk_get_rate(priv->clk); 252 do_div(freq, psc + 1); 253 do_div(freq, arr + 1); 254 } 255 256 return sprintf(buf, "%d\n", (unsigned int)freq); 257 } 258 259 static IIO_DEV_ATTR_SAMP_FREQ(0660, 260 stm32_tt_read_frequency, 261 stm32_tt_store_frequency); 262 263 #define MASTER_MODE_MAX 7 264 #define MASTER_MODE2_MAX 15 265 266 static char *master_mode_table[] = { 267 "reset", 268 "enable", 269 "update", 270 "compare_pulse", 271 "OC1REF", 272 "OC2REF", 273 "OC3REF", 274 "OC4REF", 275 /* Master mode selection 2 only */ 276 "OC5REF", 277 "OC6REF", 278 "compare_pulse_OC4REF", 279 "compare_pulse_OC6REF", 280 "compare_pulse_OC4REF_r_or_OC6REF_r", 281 "compare_pulse_OC4REF_r_or_OC6REF_f", 282 "compare_pulse_OC5REF_r_or_OC6REF_r", 283 "compare_pulse_OC5REF_r_or_OC6REF_f", 284 }; 285 286 static ssize_t stm32_tt_show_master_mode(struct device *dev, 287 struct device_attribute *attr, 288 char *buf) 289 { 290 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 291 struct iio_trigger *trig = to_iio_trigger(dev); 292 u32 cr2; 293 294 regmap_read(priv->regmap, TIM_CR2, &cr2); 295 296 if (stm32_timer_is_trgo2_name(trig->name)) 297 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT; 298 else 299 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; 300 301 return sysfs_emit(buf, "%s\n", master_mode_table[cr2]); 302 } 303 304 static ssize_t stm32_tt_store_master_mode(struct device *dev, 305 struct device_attribute *attr, 306 const char *buf, size_t len) 307 { 308 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 309 struct iio_trigger *trig = to_iio_trigger(dev); 310 u32 mask, shift, master_mode_max; 311 int i, ret; 312 313 if (stm32_timer_is_trgo2_name(trig->name)) { 314 mask = TIM_CR2_MMS2; 315 shift = TIM_CR2_MMS2_SHIFT; 316 master_mode_max = MASTER_MODE2_MAX; 317 } else { 318 mask = TIM_CR2_MMS; 319 shift = TIM_CR2_MMS_SHIFT; 320 master_mode_max = MASTER_MODE_MAX; 321 } 322 323 for (i = 0; i <= master_mode_max; i++) { 324 if (!strncmp(master_mode_table[i], buf, 325 strlen(master_mode_table[i]))) { 326 guard(mutex)(&priv->lock); 327 if (!priv->enabled) { 328 /* Clock should be enabled first */ 329 priv->enabled = true; 330 ret = clk_enable(priv->clk); 331 if (ret) 332 return ret; 333 } 334 regmap_update_bits(priv->regmap, TIM_CR2, mask, 335 i << shift); 336 return len; 337 } 338 } 339 340 return -EINVAL; 341 } 342 343 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev, 344 struct device_attribute *attr, 345 char *buf) 346 { 347 struct iio_trigger *trig = to_iio_trigger(dev); 348 unsigned int i, master_mode_max; 349 size_t len = 0; 350 351 if (stm32_timer_is_trgo2_name(trig->name)) 352 master_mode_max = MASTER_MODE2_MAX; 353 else 354 master_mode_max = MASTER_MODE_MAX; 355 356 for (i = 0; i <= master_mode_max; i++) 357 len += scnprintf(buf + len, PAGE_SIZE - len, 358 "%s ", master_mode_table[i]); 359 360 /* replace trailing space by newline */ 361 buf[len - 1] = '\n'; 362 363 return len; 364 } 365 366 static IIO_DEVICE_ATTR(master_mode_available, 0444, 367 stm32_tt_show_master_mode_avail, NULL, 0); 368 369 static IIO_DEVICE_ATTR(master_mode, 0660, 370 stm32_tt_show_master_mode, 371 stm32_tt_store_master_mode, 372 0); 373 374 static struct attribute *stm32_trigger_attrs[] = { 375 &iio_dev_attr_sampling_frequency.dev_attr.attr, 376 &iio_dev_attr_master_mode.dev_attr.attr, 377 &iio_dev_attr_master_mode_available.dev_attr.attr, 378 NULL, 379 }; 380 381 static const struct attribute_group stm32_trigger_attr_group = { 382 .attrs = stm32_trigger_attrs, 383 }; 384 385 static const struct attribute_group *stm32_trigger_attr_groups[] = { 386 &stm32_trigger_attr_group, 387 NULL, 388 }; 389 390 static const struct iio_trigger_ops timer_trigger_ops = { 391 }; 392 393 static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv) 394 { 395 struct iio_trigger *tr; 396 397 list_for_each_entry(tr, &priv->tr_list, alloc_list) 398 iio_trigger_unregister(tr); 399 } 400 401 static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv) 402 { 403 int ret; 404 const char * const *cur = priv->triggers; 405 406 INIT_LIST_HEAD(&priv->tr_list); 407 408 while (cur && *cur) { 409 struct iio_trigger *trig; 410 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur); 411 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur); 412 413 if (cur_is_trgo2 && !priv->has_trgo2) { 414 cur++; 415 continue; 416 } 417 418 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); 419 if (!trig) 420 return -ENOMEM; 421 422 trig->dev.parent = priv->dev->parent; 423 trig->ops = &timer_trigger_ops; 424 425 /* 426 * sampling frequency and master mode attributes 427 * should only be available on trgo/trgo2 triggers 428 */ 429 if (cur_is_trgo || cur_is_trgo2) 430 trig->dev.groups = stm32_trigger_attr_groups; 431 432 iio_trigger_set_drvdata(trig, priv); 433 434 ret = iio_trigger_register(trig); 435 if (ret) { 436 stm32_unregister_iio_triggers(priv); 437 return ret; 438 } 439 440 list_add_tail(&trig->alloc_list, &priv->tr_list); 441 cur++; 442 } 443 444 return 0; 445 } 446 447 static int stm32_counter_read_raw(struct iio_dev *indio_dev, 448 struct iio_chan_spec const *chan, 449 int *val, int *val2, long mask) 450 { 451 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 452 u32 dat; 453 454 switch (mask) { 455 case IIO_CHAN_INFO_RAW: 456 regmap_read(priv->regmap, TIM_CNT, &dat); 457 *val = dat; 458 return IIO_VAL_INT; 459 460 case IIO_CHAN_INFO_ENABLE: 461 regmap_read(priv->regmap, TIM_CR1, &dat); 462 *val = (dat & TIM_CR1_CEN) ? 1 : 0; 463 return IIO_VAL_INT; 464 465 case IIO_CHAN_INFO_SCALE: 466 regmap_read(priv->regmap, TIM_SMCR, &dat); 467 dat &= TIM_SMCR_SMS; 468 469 *val = 1; 470 *val2 = 0; 471 472 /* in quadrature case scale = 0.25 */ 473 if (dat == 3) 474 *val2 = 2; 475 476 return IIO_VAL_FRACTIONAL_LOG2; 477 } 478 479 return -EINVAL; 480 } 481 482 static int stm32_counter_write_raw(struct iio_dev *indio_dev, 483 struct iio_chan_spec const *chan, 484 int val, int val2, long mask) 485 { 486 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 487 int ret; 488 489 switch (mask) { 490 case IIO_CHAN_INFO_RAW: 491 return regmap_write(priv->regmap, TIM_CNT, val); 492 493 case IIO_CHAN_INFO_SCALE: 494 /* fixed scale */ 495 return -EINVAL; 496 497 case IIO_CHAN_INFO_ENABLE: { 498 guard(mutex)(&priv->lock); 499 if (val) { 500 if (!priv->enabled) { 501 priv->enabled = true; 502 ret = clk_enable(priv->clk); 503 if (ret) 504 return ret; 505 } 506 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 507 } else { 508 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 509 if (priv->enabled) { 510 priv->enabled = false; 511 clk_disable(priv->clk); 512 } 513 } 514 515 return 0; 516 } 517 default: 518 return -EINVAL; 519 } 520 } 521 522 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, 523 struct iio_trigger *trig) 524 { 525 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 526 const char * const *cur = priv->valids; 527 unsigned int i = 0; 528 529 if (!is_stm32_timer_trigger(trig)) 530 return -EINVAL; 531 532 while (cur && *cur) { 533 if (!strncmp(trig->name, *cur, strlen(trig->name))) { 534 regmap_update_bits(priv->regmap, 535 TIM_SMCR, TIM_SMCR_TS, 536 i << TIM_SMCR_TS_SHIFT); 537 return 0; 538 } 539 cur++; 540 i++; 541 } 542 543 return -EINVAL; 544 } 545 546 static const struct iio_info stm32_trigger_info = { 547 .validate_trigger = stm32_counter_validate_trigger, 548 .read_raw = stm32_counter_read_raw, 549 .write_raw = stm32_counter_write_raw 550 }; 551 552 static const char *const stm32_trigger_modes[] = { 553 "trigger", 554 }; 555 556 static int stm32_set_trigger_mode(struct iio_dev *indio_dev, 557 const struct iio_chan_spec *chan, 558 unsigned int mode) 559 { 560 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 561 562 regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS); 563 564 return 0; 565 } 566 567 static int stm32_get_trigger_mode(struct iio_dev *indio_dev, 568 const struct iio_chan_spec *chan) 569 { 570 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 571 u32 smcr; 572 573 regmap_read(priv->regmap, TIM_SMCR, &smcr); 574 575 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; 576 } 577 578 static const struct iio_enum stm32_trigger_mode_enum = { 579 .items = stm32_trigger_modes, 580 .num_items = ARRAY_SIZE(stm32_trigger_modes), 581 .set = stm32_set_trigger_mode, 582 .get = stm32_get_trigger_mode 583 }; 584 585 static const char *const stm32_enable_modes[] = { 586 "always", 587 "gated", 588 "triggered", 589 }; 590 591 static int stm32_enable_mode2sms(int mode) 592 { 593 switch (mode) { 594 case 0: 595 return 0; 596 case 1: 597 return 5; 598 case 2: 599 return 6; 600 } 601 602 return -EINVAL; 603 } 604 605 static int stm32_set_enable_mode(struct iio_dev *indio_dev, 606 const struct iio_chan_spec *chan, 607 unsigned int mode) 608 { 609 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 610 int sms = stm32_enable_mode2sms(mode); 611 int ret; 612 613 if (sms < 0) 614 return sms; 615 /* 616 * Triggered mode sets CEN bit automatically by hardware. So, first 617 * enable counter clock, so it can use it. Keeps it in sync with CEN. 618 */ 619 scoped_guard(mutex, &priv->lock) { 620 if (sms == 6 && !priv->enabled) { 621 ret = clk_enable(priv->clk); 622 if (ret) 623 return ret; 624 625 priv->enabled = true; 626 } 627 } 628 629 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 630 631 return 0; 632 } 633 634 static int stm32_sms2enable_mode(int mode) 635 { 636 switch (mode) { 637 case 0: 638 return 0; 639 case 5: 640 return 1; 641 case 6: 642 return 2; 643 } 644 645 return -EINVAL; 646 } 647 648 static int stm32_get_enable_mode(struct iio_dev *indio_dev, 649 const struct iio_chan_spec *chan) 650 { 651 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 652 u32 smcr; 653 654 regmap_read(priv->regmap, TIM_SMCR, &smcr); 655 smcr &= TIM_SMCR_SMS; 656 657 return stm32_sms2enable_mode(smcr); 658 } 659 660 static const struct iio_enum stm32_enable_mode_enum = { 661 .items = stm32_enable_modes, 662 .num_items = ARRAY_SIZE(stm32_enable_modes), 663 .set = stm32_set_enable_mode, 664 .get = stm32_get_enable_mode 665 }; 666 667 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev, 668 uintptr_t private, 669 const struct iio_chan_spec *chan, 670 char *buf) 671 { 672 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 673 u32 arr; 674 675 regmap_read(priv->regmap, TIM_ARR, &arr); 676 677 return snprintf(buf, PAGE_SIZE, "%u\n", arr); 678 } 679 680 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, 681 uintptr_t private, 682 const struct iio_chan_spec *chan, 683 const char *buf, size_t len) 684 { 685 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 686 unsigned int preset; 687 int ret; 688 689 ret = kstrtouint(buf, 0, &preset); 690 if (ret) 691 return ret; 692 693 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 694 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 695 regmap_write(priv->regmap, TIM_ARR, preset); 696 697 return len; 698 } 699 700 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { 701 { 702 .name = "preset", 703 .shared = IIO_SEPARATE, 704 .read = stm32_count_get_preset, 705 .write = stm32_count_set_preset 706 }, 707 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), 708 IIO_ENUM_AVAILABLE("enable_mode", IIO_SHARED_BY_TYPE, &stm32_enable_mode_enum), 709 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum), 710 IIO_ENUM_AVAILABLE("trigger_mode", IIO_SHARED_BY_TYPE, &stm32_trigger_mode_enum), 711 {} 712 }; 713 714 static const struct iio_chan_spec stm32_trigger_channel = { 715 .type = IIO_COUNT, 716 .channel = 0, 717 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 718 BIT(IIO_CHAN_INFO_ENABLE) | 719 BIT(IIO_CHAN_INFO_SCALE), 720 .ext_info = stm32_trigger_count_info, 721 .indexed = 1 722 }; 723 724 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev) 725 { 726 struct iio_dev *indio_dev; 727 int ret; 728 729 indio_dev = devm_iio_device_alloc(dev, 730 sizeof(struct stm32_timer_trigger)); 731 if (!indio_dev) 732 return NULL; 733 734 indio_dev->name = dev_name(dev); 735 indio_dev->info = &stm32_trigger_info; 736 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; 737 indio_dev->num_channels = 1; 738 indio_dev->channels = &stm32_trigger_channel; 739 740 ret = devm_iio_device_register(dev, indio_dev); 741 if (ret) 742 return NULL; 743 744 return iio_priv(indio_dev); 745 } 746 747 /** 748 * is_stm32_timer_trigger 749 * @trig: trigger to be checked 750 * 751 * return true if the trigger is a valid stm32 iio timer trigger 752 * either return false 753 */ 754 bool is_stm32_timer_trigger(struct iio_trigger *trig) 755 { 756 return (trig->ops == &timer_trigger_ops); 757 } 758 EXPORT_SYMBOL(is_stm32_timer_trigger); 759 760 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) 761 { 762 u32 val; 763 764 /* 765 * Master mode selection 2 bits can only be written and read back when 766 * timer supports it. 767 */ 768 regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); 769 regmap_read(priv->regmap, TIM_CR2, &val); 770 regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); 771 priv->has_trgo2 = !!val; 772 } 773 774 static int stm32_timer_trigger_probe(struct platform_device *pdev) 775 { 776 struct device *dev = &pdev->dev; 777 struct stm32_timer_trigger *priv; 778 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 779 const struct stm32_timer_trigger_cfg *cfg; 780 unsigned int index; 781 int ret; 782 783 ret = device_property_read_u32(dev, "reg", &index); 784 if (ret) 785 return ret; 786 787 cfg = device_get_match_data(dev); 788 789 if (index >= ARRAY_SIZE(triggers_table) || 790 index >= cfg->num_valids_table) 791 return -EINVAL; 792 793 /* Create an IIO device only if we have triggers to be validated */ 794 if (*cfg->valids_table[index]) 795 priv = stm32_setup_counter_device(dev); 796 else 797 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 798 799 if (!priv) 800 return -ENOMEM; 801 802 priv->dev = dev; 803 priv->regmap = ddata->regmap; 804 priv->clk = ddata->clk; 805 priv->max_arr = ddata->max_arr; 806 priv->triggers = triggers_table[index]; 807 priv->valids = cfg->valids_table[index]; 808 stm32_timer_detect_trgo2(priv); 809 mutex_init(&priv->lock); 810 811 ret = stm32_register_iio_triggers(priv); 812 if (ret) 813 return ret; 814 815 platform_set_drvdata(pdev, priv); 816 817 return 0; 818 } 819 820 static void stm32_timer_trigger_remove(struct platform_device *pdev) 821 { 822 struct stm32_timer_trigger *priv = platform_get_drvdata(pdev); 823 u32 val; 824 825 /* Unregister triggers before everything can be safely turned off */ 826 stm32_unregister_iio_triggers(priv); 827 828 /* Check if nobody else use the timer, then disable it */ 829 regmap_read(priv->regmap, TIM_CCER, &val); 830 if (!(val & TIM_CCER_CCXE)) 831 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 832 833 if (priv->enabled) 834 clk_disable(priv->clk); 835 } 836 837 static int stm32_timer_trigger_suspend(struct device *dev) 838 { 839 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 840 841 /* Only take care of enabled timer: don't disturb other MFD child */ 842 if (priv->enabled) { 843 /* Backup registers that may get lost in low power mode */ 844 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); 845 regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2); 846 regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc); 847 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr); 848 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt); 849 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); 850 851 /* Disable the timer */ 852 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 853 clk_disable(priv->clk); 854 } 855 856 return 0; 857 } 858 859 static int stm32_timer_trigger_resume(struct device *dev) 860 { 861 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 862 int ret; 863 864 if (priv->enabled) { 865 ret = clk_enable(priv->clk); 866 if (ret) 867 return ret; 868 869 /* restore master/slave modes */ 870 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr); 871 regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2); 872 873 /* restore sampling_frequency (trgo / trgo2 triggers) */ 874 regmap_write(priv->regmap, TIM_PSC, priv->bak.psc); 875 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr); 876 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt); 877 878 /* Also re-enables the timer */ 879 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); 880 } 881 882 return 0; 883 } 884 885 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops, 886 stm32_timer_trigger_suspend, 887 stm32_timer_trigger_resume); 888 889 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = { 890 .valids_table = valids_table, 891 .num_valids_table = ARRAY_SIZE(valids_table), 892 }; 893 894 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = { 895 .valids_table = stm32h7_valids_table, 896 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table), 897 }; 898 899 static const struct of_device_id stm32_trig_of_match[] = { 900 { 901 .compatible = "st,stm32-timer-trigger", 902 .data = (void *)&stm32_timer_trg_cfg, 903 }, { 904 .compatible = "st,stm32h7-timer-trigger", 905 .data = (void *)&stm32h7_timer_trg_cfg, 906 }, 907 { /* end node */ }, 908 }; 909 MODULE_DEVICE_TABLE(of, stm32_trig_of_match); 910 911 static struct platform_driver stm32_timer_trigger_driver = { 912 .probe = stm32_timer_trigger_probe, 913 .remove = stm32_timer_trigger_remove, 914 .driver = { 915 .name = "stm32-timer-trigger", 916 .of_match_table = stm32_trig_of_match, 917 .pm = pm_sleep_ptr(&stm32_timer_trigger_pm_ops), 918 }, 919 }; 920 module_platform_driver(stm32_timer_trigger_driver); 921 922 MODULE_ALIAS("platform:stm32-timer-trigger"); 923 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); 924 MODULE_LICENSE("GPL v2"); 925