1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 Lucas Stach, Pengutronix 4 */ 5 6 #include <drm/drm_fourcc.h> 7 #include <linux/clk.h> 8 #include <linux/err.h> 9 #include <linux/genalloc.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <video/imx-ipu-v3.h> 14 15 #include "ipu-prv.h" 16 17 #define IPU_PRE_MAX_WIDTH 2048 18 #define IPU_PRE_NUM_SCANLINES 8 19 20 #define IPU_PRE_CTRL 0x000 21 #define IPU_PRE_CTRL_SET 0x004 22 #define IPU_PRE_CTRL_ENABLE (1 << 0) 23 #define IPU_PRE_CTRL_BLOCK_EN (1 << 1) 24 #define IPU_PRE_CTRL_BLOCK_16 (1 << 2) 25 #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4) 26 #define IPU_PRE_CTRL_VFLIP (1 << 5) 27 #define IPU_PRE_CTRL_SO (1 << 6) 28 #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7) 29 #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8) 30 #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9) 31 #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11) 32 #define IPU_PRE_CTRL_EN_REPEAT (1 << 28) 33 #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29) 34 #define IPU_PRE_CTRL_CLKGATE (1 << 30) 35 #define IPU_PRE_CTRL_SFTRST (1 << 31) 36 37 #define IPU_PRE_CUR_BUF 0x030 38 39 #define IPU_PRE_NEXT_BUF 0x040 40 41 #define IPU_PRE_TPR_CTRL 0x070 42 #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0) 43 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff 44 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT (1 << 0) 45 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF (1 << 4) 46 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF (1 << 5) 47 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED (1 << 6) 48 49 #define IPU_PRE_PREFETCH_ENG_CTRL 0x080 50 #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0) 51 #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1) 52 #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 53 #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8) 54 #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11) 55 #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12) 56 #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14) 57 #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15) 58 59 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0 60 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0) 61 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16) 62 63 #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0 64 #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0) 65 #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16) 66 67 #define IPU_PRE_STORE_ENG_CTRL 0x110 68 #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0) 69 #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1) 70 #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 71 72 #define IPU_PRE_STORE_ENG_STATUS 0x120 73 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff 74 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0 75 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff 76 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16 77 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30) 78 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31) 79 80 #define IPU_PRE_STORE_ENG_SIZE 0x130 81 #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0) 82 #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16) 83 84 #define IPU_PRE_STORE_ENG_PITCH 0x140 85 #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0) 86 87 #define IPU_PRE_STORE_ENG_ADDR 0x150 88 89 struct ipu_pre { 90 struct list_head list; 91 struct device *dev; 92 93 void __iomem *regs; 94 struct clk *clk_axi; 95 struct gen_pool *iram; 96 97 dma_addr_t buffer_paddr; 98 void *buffer_virt; 99 bool in_use; 100 unsigned int safe_window_end; 101 unsigned int last_bufaddr; 102 }; 103 104 static DEFINE_MUTEX(ipu_pre_list_mutex); 105 static LIST_HEAD(ipu_pre_list); 106 static int available_pres; 107 108 int ipu_pre_get_available_count(void) 109 { 110 return available_pres; 111 } 112 113 struct ipu_pre * 114 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index) 115 { 116 struct device_node *pre_node __free(device_node) = 117 of_parse_phandle(dev->of_node, name, index); 118 struct ipu_pre *pre; 119 120 mutex_lock(&ipu_pre_list_mutex); 121 list_for_each_entry(pre, &ipu_pre_list, list) { 122 if (pre_node == pre->dev->of_node) { 123 mutex_unlock(&ipu_pre_list_mutex); 124 device_link_add(dev, pre->dev, 125 DL_FLAG_AUTOREMOVE_CONSUMER); 126 return pre; 127 } 128 } 129 mutex_unlock(&ipu_pre_list_mutex); 130 131 return NULL; 132 } 133 134 int ipu_pre_get(struct ipu_pre *pre) 135 { 136 u32 val; 137 138 if (pre->in_use) 139 return -EBUSY; 140 141 /* first get the engine out of reset and remove clock gating */ 142 writel(0, pre->regs + IPU_PRE_CTRL); 143 144 /* init defaults that should be applied to all streams */ 145 val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN | 146 IPU_PRE_CTRL_HANDSHAKE_EN | 147 IPU_PRE_CTRL_TPR_REST_SEL | 148 IPU_PRE_CTRL_SDW_UPDATE; 149 writel(val, pre->regs + IPU_PRE_CTRL); 150 151 pre->in_use = true; 152 return 0; 153 } 154 155 void ipu_pre_put(struct ipu_pre *pre) 156 { 157 writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL); 158 159 pre->in_use = false; 160 } 161 162 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, 163 unsigned int height, unsigned int stride, u32 format, 164 uint64_t modifier, unsigned int bufaddr) 165 { 166 const struct drm_format_info *info = drm_format_info(format); 167 u32 active_bpp = info->cpp[0] >> 1; 168 u32 val; 169 170 /* calculate safe window for ctrl register updates */ 171 if (modifier == DRM_FORMAT_MOD_LINEAR) 172 pre->safe_window_end = height - 2; 173 else 174 pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1; 175 176 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF); 177 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 178 pre->last_bufaddr = bufaddr; 179 180 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | 181 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) | 182 IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) | 183 IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS | 184 IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN; 185 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL); 186 187 val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) | 188 IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height); 189 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE); 190 191 val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride); 192 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH); 193 194 val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) | 195 IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) | 196 IPU_PRE_STORE_ENG_CTRL_STORE_EN; 197 writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL); 198 199 val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) | 200 IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height); 201 writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE); 202 203 val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride); 204 writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH); 205 206 writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR); 207 208 val = readl(pre->regs + IPU_PRE_TPR_CTRL); 209 val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK; 210 if (modifier != DRM_FORMAT_MOD_LINEAR) { 211 /* only support single buffer formats for now */ 212 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF; 213 if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED) 214 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED; 215 if (info->cpp[0] == 2) 216 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT; 217 } 218 writel(val, pre->regs + IPU_PRE_TPR_CTRL); 219 220 val = readl(pre->regs + IPU_PRE_CTRL); 221 val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE | 222 IPU_PRE_CTRL_SDW_UPDATE; 223 if (modifier == DRM_FORMAT_MOD_LINEAR) 224 val &= ~IPU_PRE_CTRL_BLOCK_EN; 225 else 226 val |= IPU_PRE_CTRL_BLOCK_EN; 227 writel(val, pre->regs + IPU_PRE_CTRL); 228 } 229 230 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr) 231 { 232 unsigned long timeout = jiffies + msecs_to_jiffies(5); 233 unsigned short current_yblock; 234 u32 val; 235 236 if (bufaddr == pre->last_bufaddr) 237 return; 238 239 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 240 pre->last_bufaddr = bufaddr; 241 242 do { 243 if (time_after(jiffies, timeout)) { 244 dev_warn(pre->dev, "timeout waiting for PRE safe window\n"); 245 return; 246 } 247 248 val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS); 249 current_yblock = 250 (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) & 251 IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK; 252 } while (current_yblock == 0 || current_yblock >= pre->safe_window_end); 253 254 writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET); 255 } 256 257 bool ipu_pre_update_pending(struct ipu_pre *pre) 258 { 259 return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) & 260 IPU_PRE_CTRL_SDW_UPDATE); 261 } 262 263 u32 ipu_pre_get_baddr(struct ipu_pre *pre) 264 { 265 return (u32)pre->buffer_paddr; 266 } 267 268 static int ipu_pre_probe(struct platform_device *pdev) 269 { 270 struct device *dev = &pdev->dev; 271 struct ipu_pre *pre; 272 273 pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL); 274 if (!pre) 275 return -ENOMEM; 276 277 pre->regs = devm_platform_ioremap_resource(pdev, 0); 278 if (IS_ERR(pre->regs)) 279 return PTR_ERR(pre->regs); 280 281 pre->clk_axi = devm_clk_get(dev, "axi"); 282 if (IS_ERR(pre->clk_axi)) 283 return PTR_ERR(pre->clk_axi); 284 285 pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0); 286 if (!pre->iram) 287 return -EPROBE_DEFER; 288 289 /* 290 * Allocate IRAM buffer with maximum size. This could be made dynamic, 291 * but as there is no other user of this IRAM region and we can fit all 292 * max sized buffers into it, there is no need yet. 293 */ 294 pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH * 295 IPU_PRE_NUM_SCANLINES * 4, 296 &pre->buffer_paddr); 297 if (!pre->buffer_virt) 298 return -ENOMEM; 299 300 clk_prepare_enable(pre->clk_axi); 301 302 pre->dev = dev; 303 platform_set_drvdata(pdev, pre); 304 mutex_lock(&ipu_pre_list_mutex); 305 list_add(&pre->list, &ipu_pre_list); 306 available_pres++; 307 mutex_unlock(&ipu_pre_list_mutex); 308 309 return 0; 310 } 311 312 static int ipu_pre_remove(struct platform_device *pdev) 313 { 314 struct ipu_pre *pre = platform_get_drvdata(pdev); 315 316 mutex_lock(&ipu_pre_list_mutex); 317 list_del(&pre->list); 318 available_pres--; 319 mutex_unlock(&ipu_pre_list_mutex); 320 321 clk_disable_unprepare(pre->clk_axi); 322 323 if (pre->buffer_virt) 324 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt, 325 IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4); 326 return 0; 327 } 328 329 static const struct of_device_id ipu_pre_dt_ids[] = { 330 { .compatible = "fsl,imx6qp-pre", }, 331 { /* sentinel */ }, 332 }; 333 334 struct platform_driver ipu_pre_drv = { 335 .probe = ipu_pre_probe, 336 .remove = ipu_pre_remove, 337 .driver = { 338 .name = "imx-ipu-pre", 339 .of_match_table = ipu_pre_dt_ids, 340 }, 341 }; 342