1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 Lucas Stach, Pengutronix 4 */ 5 6 #include <drm/drm_fourcc.h> 7 #include <linux/clk.h> 8 #include <linux/err.h> 9 #include <linux/genalloc.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <video/imx-ipu-v3.h> 14 15 #include "ipu-prv.h" 16 17 #define IPU_PRE_MAX_WIDTH 2048 18 #define IPU_PRE_NUM_SCANLINES 8 19 20 #define IPU_PRE_CTRL 0x000 21 #define IPU_PRE_CTRL_SET 0x004 22 #define IPU_PRE_CTRL_ENABLE (1 << 0) 23 #define IPU_PRE_CTRL_BLOCK_EN (1 << 1) 24 #define IPU_PRE_CTRL_BLOCK_16 (1 << 2) 25 #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4) 26 #define IPU_PRE_CTRL_VFLIP (1 << 5) 27 #define IPU_PRE_CTRL_SO (1 << 6) 28 #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7) 29 #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8) 30 #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9) 31 #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11) 32 #define IPU_PRE_CTRL_EN_REPEAT (1 << 28) 33 #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29) 34 #define IPU_PRE_CTRL_CLKGATE (1 << 30) 35 #define IPU_PRE_CTRL_SFTRST (1 << 31) 36 37 #define IPU_PRE_CUR_BUF 0x030 38 39 #define IPU_PRE_NEXT_BUF 0x040 40 41 #define IPU_PRE_TPR_CTRL 0x070 42 #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0) 43 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff 44 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT (1 << 0) 45 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF (1 << 4) 46 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF (1 << 5) 47 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED (1 << 6) 48 49 #define IPU_PRE_PREFETCH_ENG_CTRL 0x080 50 #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0) 51 #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1) 52 #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 53 #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8) 54 #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11) 55 #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12) 56 #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14) 57 #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15) 58 59 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0 60 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0) 61 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16) 62 63 #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0 64 #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0) 65 #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16) 66 67 #define IPU_PRE_STORE_ENG_CTRL 0x110 68 #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0) 69 #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1) 70 #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 71 72 #define IPU_PRE_STORE_ENG_STATUS 0x120 73 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff 74 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0 75 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff 76 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16 77 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30) 78 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31) 79 80 #define IPU_PRE_STORE_ENG_SIZE 0x130 81 #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0) 82 #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16) 83 84 #define IPU_PRE_STORE_ENG_PITCH 0x140 85 #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0) 86 87 #define IPU_PRE_STORE_ENG_ADDR 0x150 88 89 struct ipu_pre { 90 struct list_head list; 91 struct device *dev; 92 93 void __iomem *regs; 94 struct clk *clk_axi; 95 struct gen_pool *iram; 96 97 dma_addr_t buffer_paddr; 98 void *buffer_virt; 99 100 struct { 101 bool in_use; 102 uint64_t modifier; 103 unsigned int height; 104 unsigned int safe_window_end; 105 unsigned int bufaddr; 106 u32 ctrl; 107 u8 cpp; 108 } cur; 109 }; 110 111 static DEFINE_MUTEX(ipu_pre_list_mutex); 112 static LIST_HEAD(ipu_pre_list); 113 static int available_pres; 114 115 int ipu_pre_get_available_count(void) 116 { 117 return available_pres; 118 } 119 120 struct ipu_pre * 121 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index) 122 { 123 struct device_node *pre_node __free(device_node) = 124 of_parse_phandle(dev->of_node, name, index); 125 struct ipu_pre *pre; 126 127 mutex_lock(&ipu_pre_list_mutex); 128 list_for_each_entry(pre, &ipu_pre_list, list) { 129 if (pre_node == pre->dev->of_node) { 130 mutex_unlock(&ipu_pre_list_mutex); 131 device_link_add(dev, pre->dev, 132 DL_FLAG_AUTOREMOVE_CONSUMER); 133 return pre; 134 } 135 } 136 mutex_unlock(&ipu_pre_list_mutex); 137 138 return NULL; 139 } 140 141 int ipu_pre_get(struct ipu_pre *pre) 142 { 143 u32 val; 144 145 if (pre->cur.in_use) 146 return -EBUSY; 147 148 /* first get the engine out of reset and remove clock gating */ 149 writel(0, pre->regs + IPU_PRE_CTRL); 150 151 /* init defaults that should be applied to all streams */ 152 val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN | 153 IPU_PRE_CTRL_HANDSHAKE_EN | 154 IPU_PRE_CTRL_TPR_REST_SEL | 155 IPU_PRE_CTRL_SDW_UPDATE; 156 writel(val, pre->regs + IPU_PRE_CTRL); 157 158 pre->cur.in_use = true; 159 return 0; 160 } 161 162 void ipu_pre_put(struct ipu_pre *pre) 163 { 164 writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL); 165 166 pre->cur.in_use = false; 167 } 168 169 static inline void 170 ipu_pre_update_safe_window(struct ipu_pre *pre) 171 { 172 if (pre->cur.modifier == DRM_FORMAT_MOD_LINEAR) 173 pre->cur.safe_window_end = pre->cur.height - 2; 174 else 175 pre->cur.safe_window_end = DIV_ROUND_UP(pre->cur.height, 4) - 1; 176 } 177 178 static void 179 ipu_pre_configure_modifier(struct ipu_pre *pre, uint64_t modifier) 180 { 181 u32 val; 182 183 val = readl(pre->regs + IPU_PRE_TPR_CTRL); 184 val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK; 185 if (modifier != DRM_FORMAT_MOD_LINEAR) { 186 /* only support single buffer formats for now */ 187 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF; 188 if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED) 189 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED; 190 if (pre->cur.cpp == 2) 191 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT; 192 } 193 writel(val, pre->regs + IPU_PRE_TPR_CTRL); 194 195 if (modifier == DRM_FORMAT_MOD_LINEAR) 196 pre->cur.ctrl &= ~IPU_PRE_CTRL_BLOCK_EN; 197 else 198 pre->cur.ctrl |= IPU_PRE_CTRL_BLOCK_EN; 199 200 pre->cur.modifier = modifier; 201 } 202 203 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, 204 unsigned int height, unsigned int stride, u32 format, 205 uint64_t modifier, unsigned int bufaddr) 206 { 207 const struct drm_format_info *info = drm_format_info(format); 208 u32 active_bpp = info->cpp[0] >> 1; 209 u32 val; 210 211 pre->cur.bufaddr = bufaddr; 212 pre->cur.height = height; 213 pre->cur.cpp = info->cpp[0]; 214 pre->cur.ctrl = readl(pre->regs + IPU_PRE_CTRL); 215 216 /* calculate safe window for ctrl register updates */ 217 ipu_pre_update_safe_window(pre); 218 219 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF); 220 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 221 222 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | 223 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) | 224 IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) | 225 IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS | 226 IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN; 227 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL); 228 229 val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) | 230 IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height); 231 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE); 232 233 val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride); 234 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH); 235 236 val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) | 237 IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) | 238 IPU_PRE_STORE_ENG_CTRL_STORE_EN; 239 writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL); 240 241 val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) | 242 IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height); 243 writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE); 244 245 val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride); 246 writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH); 247 248 writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR); 249 250 ipu_pre_configure_modifier(pre, modifier); 251 252 pre->cur.ctrl |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE; 253 writel(pre->cur.ctrl | IPU_PRE_CTRL_SDW_UPDATE, 254 pre->regs + IPU_PRE_CTRL); 255 } 256 257 void ipu_pre_update(struct ipu_pre *pre, uint64_t modifier, unsigned int bufaddr) 258 { 259 unsigned long timeout = jiffies + msecs_to_jiffies(5); 260 unsigned short current_yblock; 261 u32 val; 262 263 if (bufaddr == pre->cur.bufaddr && 264 modifier == pre->cur.modifier) 265 return; 266 267 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 268 pre->cur.bufaddr = bufaddr; 269 270 if (modifier != pre->cur.modifier) 271 ipu_pre_configure_modifier(pre, modifier); 272 273 do { 274 if (time_after(jiffies, timeout)) { 275 dev_warn(pre->dev, "timeout waiting for PRE safe window\n"); 276 return; 277 } 278 279 val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS); 280 current_yblock = 281 (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) & 282 IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK; 283 } while (current_yblock == 0 || 284 current_yblock >= pre->cur.safe_window_end); 285 286 writel(pre->cur.ctrl | IPU_PRE_CTRL_SDW_UPDATE, 287 pre->regs + IPU_PRE_CTRL); 288 289 /* calculate safe window for the next update with the new modifier */ 290 ipu_pre_update_safe_window(pre); 291 } 292 293 bool ipu_pre_update_pending(struct ipu_pre *pre) 294 { 295 return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) & 296 IPU_PRE_CTRL_SDW_UPDATE); 297 } 298 299 u32 ipu_pre_get_baddr(struct ipu_pre *pre) 300 { 301 return (u32)pre->buffer_paddr; 302 } 303 304 static int ipu_pre_probe(struct platform_device *pdev) 305 { 306 struct device *dev = &pdev->dev; 307 struct ipu_pre *pre; 308 309 pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL); 310 if (!pre) 311 return -ENOMEM; 312 313 pre->regs = devm_platform_ioremap_resource(pdev, 0); 314 if (IS_ERR(pre->regs)) 315 return PTR_ERR(pre->regs); 316 317 pre->clk_axi = devm_clk_get(dev, "axi"); 318 if (IS_ERR(pre->clk_axi)) 319 return PTR_ERR(pre->clk_axi); 320 321 pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0); 322 if (!pre->iram) 323 return -EPROBE_DEFER; 324 325 /* 326 * Allocate IRAM buffer with maximum size. This could be made dynamic, 327 * but as there is no other user of this IRAM region and we can fit all 328 * max sized buffers into it, there is no need yet. 329 */ 330 pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH * 331 IPU_PRE_NUM_SCANLINES * 4, 332 &pre->buffer_paddr); 333 if (!pre->buffer_virt) 334 return -ENOMEM; 335 336 clk_prepare_enable(pre->clk_axi); 337 338 pre->dev = dev; 339 platform_set_drvdata(pdev, pre); 340 mutex_lock(&ipu_pre_list_mutex); 341 list_add(&pre->list, &ipu_pre_list); 342 available_pres++; 343 mutex_unlock(&ipu_pre_list_mutex); 344 345 return 0; 346 } 347 348 static int ipu_pre_remove(struct platform_device *pdev) 349 { 350 struct ipu_pre *pre = platform_get_drvdata(pdev); 351 352 mutex_lock(&ipu_pre_list_mutex); 353 list_del(&pre->list); 354 available_pres--; 355 mutex_unlock(&ipu_pre_list_mutex); 356 357 clk_disable_unprepare(pre->clk_axi); 358 359 if (pre->buffer_virt) 360 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt, 361 IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4); 362 return 0; 363 } 364 365 static const struct of_device_id ipu_pre_dt_ids[] = { 366 { .compatible = "fsl,imx6qp-pre", }, 367 { /* sentinel */ }, 368 }; 369 370 struct platform_driver ipu_pre_drv = { 371 .probe = ipu_pre_probe, 372 .remove = ipu_pre_remove, 373 .driver = { 374 .name = "imx-ipu-pre", 375 .of_match_table = ipu_pre_dt_ids, 376 }, 377 }; 378