1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012-2015, NVIDIA Corporation. 4 */ 5 6 #ifndef HOST1X_DEV_H 7 #define HOST1X_DEV_H 8 9 #include <linux/device.h> 10 #include <linux/iommu.h> 11 #include <linux/iova.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 15 #include "cdma.h" 16 #include "channel.h" 17 #include "context.h" 18 #include "intr.h" 19 #include "job.h" 20 #include "syncpt.h" 21 22 struct host1x_syncpt; 23 struct host1x_syncpt_base; 24 struct host1x_channel; 25 struct host1x_cdma; 26 struct host1x_job; 27 struct push_buffer; 28 struct output; 29 struct dentry; 30 31 struct host1x_channel_ops { 32 int (*init)(struct host1x_channel *channel, struct host1x *host, 33 unsigned int id); 34 int (*submit)(struct host1x_job *job); 35 }; 36 37 struct host1x_cdma_ops { 38 void (*start)(struct host1x_cdma *cdma); 39 void (*stop)(struct host1x_cdma *cdma); 40 void (*flush)(struct host1x_cdma *cdma); 41 int (*timeout_init)(struct host1x_cdma *cdma); 42 void (*timeout_destroy)(struct host1x_cdma *cdma); 43 void (*freeze)(struct host1x_cdma *cdma); 44 void (*resume)(struct host1x_cdma *cdma, u32 getptr); 45 void (*timeout_cpu_incr)(struct host1x_cdma *cdma, u32 getptr, 46 u32 syncpt_incrs, u32 syncval, u32 nr_slots); 47 }; 48 49 struct host1x_pushbuffer_ops { 50 void (*init)(struct push_buffer *pb); 51 }; 52 53 struct host1x_debug_ops { 54 void (*debug_init)(struct dentry *de); 55 void (*show_channel_cdma)(struct host1x *host, 56 struct host1x_channel *ch, 57 struct output *o); 58 void (*show_channel_fifo)(struct host1x *host, 59 struct host1x_channel *ch, 60 struct output *o); 61 void (*show_mlocks)(struct host1x *host, struct output *output); 62 63 }; 64 65 struct host1x_syncpt_ops { 66 void (*restore)(struct host1x_syncpt *syncpt); 67 void (*restore_wait_base)(struct host1x_syncpt *syncpt); 68 void (*load_wait_base)(struct host1x_syncpt *syncpt); 69 u32 (*load)(struct host1x_syncpt *syncpt); 70 int (*cpu_incr)(struct host1x_syncpt *syncpt); 71 void (*assign_to_channel)(struct host1x_syncpt *syncpt, 72 struct host1x_channel *channel); 73 void (*enable_protection)(struct host1x *host); 74 }; 75 76 struct host1x_intr_ops { 77 int (*init_host_sync)(struct host1x *host, u32 cpm, 78 void (*syncpt_thresh_work)(struct work_struct *work)); 79 void (*set_syncpt_threshold)( 80 struct host1x *host, unsigned int id, u32 thresh); 81 void (*enable_syncpt_intr)(struct host1x *host, unsigned int id); 82 void (*disable_syncpt_intr)(struct host1x *host, unsigned int id); 83 void (*disable_all_syncpt_intrs)(struct host1x *host); 84 int (*free_syncpt_irq)(struct host1x *host); 85 }; 86 87 struct host1x_sid_entry { 88 unsigned int base; 89 unsigned int offset; 90 unsigned int limit; 91 }; 92 93 struct host1x_info { 94 unsigned int nb_channels; /* host1x: number of channels supported */ 95 unsigned int nb_pts; /* host1x: number of syncpoints supported */ 96 unsigned int nb_bases; /* host1x: number of syncpoint bases supported */ 97 unsigned int nb_mlocks; /* host1x: number of mlocks supported */ 98 int (*init)(struct host1x *host1x); /* initialize per SoC ops */ 99 unsigned int sync_offset; /* offset of syncpoint registers */ 100 u64 dma_mask; /* mask of addressable memory */ 101 bool has_wide_gather; /* supports GATHER_W opcode */ 102 bool has_hypervisor; /* has hypervisor registers */ 103 bool has_common; /* has common registers separate from hypervisor */ 104 unsigned int num_sid_entries; 105 const struct host1x_sid_entry *sid_table; 106 /* 107 * On T20-T148, the boot chain may setup DC to increment syncpoints 108 * 26/27 on VBLANK. As such we cannot use these syncpoints until 109 * the display driver disables VBLANK increments. 110 */ 111 bool reserve_vblank_syncpts; 112 }; 113 114 struct host1x { 115 const struct host1x_info *info; 116 117 void __iomem *regs; 118 void __iomem *hv_regs; /* hypervisor region */ 119 void __iomem *common_regs; 120 struct host1x_syncpt *syncpt; 121 struct host1x_syncpt_base *bases; 122 struct device *dev; 123 struct clk *clk; 124 struct reset_control_bulk_data resets[2]; 125 unsigned int nresets; 126 127 struct iommu_group *group; 128 struct iommu_domain *domain; 129 struct iova_domain iova; 130 dma_addr_t iova_end; 131 132 struct mutex intr_mutex; 133 int intr_syncpt_irq; 134 135 const struct host1x_syncpt_ops *syncpt_op; 136 const struct host1x_intr_ops *intr_op; 137 const struct host1x_channel_ops *channel_op; 138 const struct host1x_cdma_ops *cdma_op; 139 const struct host1x_pushbuffer_ops *cdma_pb_op; 140 const struct host1x_debug_ops *debug_op; 141 142 struct host1x_syncpt *nop_sp; 143 144 struct mutex syncpt_mutex; 145 146 struct host1x_channel_list channel_list; 147 struct host1x_memory_context_list context_list; 148 149 struct dentry *debugfs; 150 151 struct mutex devices_lock; 152 struct list_head devices; 153 154 struct list_head list; 155 156 struct device_dma_parameters dma_parms; 157 158 struct host1x_bo_cache cache; 159 }; 160 161 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r); 162 void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v); 163 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r); 164 void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v); 165 u32 host1x_sync_readl(struct host1x *host1x, u32 r); 166 void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v); 167 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r); 168 169 static inline void host1x_hw_syncpt_restore(struct host1x *host, 170 struct host1x_syncpt *sp) 171 { 172 host->syncpt_op->restore(sp); 173 } 174 175 static inline void host1x_hw_syncpt_restore_wait_base(struct host1x *host, 176 struct host1x_syncpt *sp) 177 { 178 host->syncpt_op->restore_wait_base(sp); 179 } 180 181 static inline void host1x_hw_syncpt_load_wait_base(struct host1x *host, 182 struct host1x_syncpt *sp) 183 { 184 host->syncpt_op->load_wait_base(sp); 185 } 186 187 static inline u32 host1x_hw_syncpt_load(struct host1x *host, 188 struct host1x_syncpt *sp) 189 { 190 return host->syncpt_op->load(sp); 191 } 192 193 static inline int host1x_hw_syncpt_cpu_incr(struct host1x *host, 194 struct host1x_syncpt *sp) 195 { 196 return host->syncpt_op->cpu_incr(sp); 197 } 198 199 static inline void host1x_hw_syncpt_assign_to_channel( 200 struct host1x *host, struct host1x_syncpt *sp, 201 struct host1x_channel *ch) 202 { 203 return host->syncpt_op->assign_to_channel(sp, ch); 204 } 205 206 static inline void host1x_hw_syncpt_enable_protection(struct host1x *host) 207 { 208 return host->syncpt_op->enable_protection(host); 209 } 210 211 static inline int host1x_hw_intr_init_host_sync(struct host1x *host, u32 cpm, 212 void (*syncpt_thresh_work)(struct work_struct *)) 213 { 214 return host->intr_op->init_host_sync(host, cpm, syncpt_thresh_work); 215 } 216 217 static inline void host1x_hw_intr_set_syncpt_threshold(struct host1x *host, 218 unsigned int id, 219 u32 thresh) 220 { 221 host->intr_op->set_syncpt_threshold(host, id, thresh); 222 } 223 224 static inline void host1x_hw_intr_enable_syncpt_intr(struct host1x *host, 225 unsigned int id) 226 { 227 host->intr_op->enable_syncpt_intr(host, id); 228 } 229 230 static inline void host1x_hw_intr_disable_syncpt_intr(struct host1x *host, 231 unsigned int id) 232 { 233 host->intr_op->disable_syncpt_intr(host, id); 234 } 235 236 static inline void host1x_hw_intr_disable_all_syncpt_intrs(struct host1x *host) 237 { 238 host->intr_op->disable_all_syncpt_intrs(host); 239 } 240 241 static inline int host1x_hw_intr_free_syncpt_irq(struct host1x *host) 242 { 243 return host->intr_op->free_syncpt_irq(host); 244 } 245 246 static inline int host1x_hw_channel_init(struct host1x *host, 247 struct host1x_channel *channel, 248 unsigned int id) 249 { 250 return host->channel_op->init(channel, host, id); 251 } 252 253 static inline int host1x_hw_channel_submit(struct host1x *host, 254 struct host1x_job *job) 255 { 256 return host->channel_op->submit(job); 257 } 258 259 static inline void host1x_hw_cdma_start(struct host1x *host, 260 struct host1x_cdma *cdma) 261 { 262 host->cdma_op->start(cdma); 263 } 264 265 static inline void host1x_hw_cdma_stop(struct host1x *host, 266 struct host1x_cdma *cdma) 267 { 268 host->cdma_op->stop(cdma); 269 } 270 271 static inline void host1x_hw_cdma_flush(struct host1x *host, 272 struct host1x_cdma *cdma) 273 { 274 host->cdma_op->flush(cdma); 275 } 276 277 static inline int host1x_hw_cdma_timeout_init(struct host1x *host, 278 struct host1x_cdma *cdma) 279 { 280 return host->cdma_op->timeout_init(cdma); 281 } 282 283 static inline void host1x_hw_cdma_timeout_destroy(struct host1x *host, 284 struct host1x_cdma *cdma) 285 { 286 host->cdma_op->timeout_destroy(cdma); 287 } 288 289 static inline void host1x_hw_cdma_freeze(struct host1x *host, 290 struct host1x_cdma *cdma) 291 { 292 host->cdma_op->freeze(cdma); 293 } 294 295 static inline void host1x_hw_cdma_resume(struct host1x *host, 296 struct host1x_cdma *cdma, u32 getptr) 297 { 298 host->cdma_op->resume(cdma, getptr); 299 } 300 301 static inline void host1x_hw_cdma_timeout_cpu_incr(struct host1x *host, 302 struct host1x_cdma *cdma, 303 u32 getptr, 304 u32 syncpt_incrs, 305 u32 syncval, u32 nr_slots) 306 { 307 host->cdma_op->timeout_cpu_incr(cdma, getptr, syncpt_incrs, syncval, 308 nr_slots); 309 } 310 311 static inline void host1x_hw_pushbuffer_init(struct host1x *host, 312 struct push_buffer *pb) 313 { 314 host->cdma_pb_op->init(pb); 315 } 316 317 static inline void host1x_hw_debug_init(struct host1x *host, struct dentry *de) 318 { 319 if (host->debug_op && host->debug_op->debug_init) 320 host->debug_op->debug_init(de); 321 } 322 323 static inline void host1x_hw_show_channel_cdma(struct host1x *host, 324 struct host1x_channel *channel, 325 struct output *o) 326 { 327 host->debug_op->show_channel_cdma(host, channel, o); 328 } 329 330 static inline void host1x_hw_show_channel_fifo(struct host1x *host, 331 struct host1x_channel *channel, 332 struct output *o) 333 { 334 host->debug_op->show_channel_fifo(host, channel, o); 335 } 336 337 static inline void host1x_hw_show_mlocks(struct host1x *host, struct output *o) 338 { 339 host->debug_op->show_mlocks(host, o); 340 } 341 342 extern struct platform_driver tegra_mipi_driver; 343 344 #endif 345