1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2013, NVIDIA Corporation. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/reset.h> 13 14 #include <soc/tegra/common.h> 15 16 #include "drm.h" 17 #include "gem.h" 18 #include "gr2d.h" 19 20 enum { 21 RST_MC, 22 RST_GR2D, 23 RST_GR2D_MAX, 24 }; 25 26 struct gr2d_soc { 27 unsigned int version; 28 }; 29 30 struct gr2d { 31 struct tegra_drm_client client; 32 struct host1x_channel *channel; 33 struct clk *clk; 34 35 struct reset_control_bulk_data resets[RST_GR2D_MAX]; 36 unsigned int nresets; 37 38 const struct gr2d_soc *soc; 39 40 DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS); 41 }; 42 43 static inline struct gr2d *to_gr2d(struct tegra_drm_client *client) 44 { 45 return container_of(client, struct gr2d, client); 46 } 47 48 static int gr2d_init(struct host1x_client *client) 49 { 50 struct tegra_drm_client *drm = host1x_to_drm_client(client); 51 struct drm_device *dev = dev_get_drvdata(client->host); 52 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 53 struct gr2d *gr2d = to_gr2d(drm); 54 int err; 55 56 gr2d->channel = host1x_channel_request(client); 57 if (!gr2d->channel) 58 return -ENOMEM; 59 60 client->syncpts[0] = host1x_syncpt_request(client, flags); 61 if (!client->syncpts[0]) { 62 err = -ENOMEM; 63 dev_err(client->dev, "failed to request syncpoint: %d\n", err); 64 goto put; 65 } 66 67 err = host1x_client_iommu_attach(client); 68 if (err < 0) { 69 dev_err(client->dev, "failed to attach to domain: %d\n", err); 70 goto free; 71 } 72 73 pm_runtime_enable(client->dev); 74 pm_runtime_use_autosuspend(client->dev); 75 pm_runtime_set_autosuspend_delay(client->dev, 200); 76 77 err = tegra_drm_register_client(dev->dev_private, drm); 78 if (err < 0) { 79 dev_err(client->dev, "failed to register client: %d\n", err); 80 goto disable_rpm; 81 } 82 83 return 0; 84 85 disable_rpm: 86 pm_runtime_dont_use_autosuspend(client->dev); 87 pm_runtime_force_suspend(client->dev); 88 89 host1x_client_iommu_detach(client); 90 free: 91 host1x_syncpt_put(client->syncpts[0]); 92 put: 93 host1x_channel_put(gr2d->channel); 94 return err; 95 } 96 97 static int gr2d_exit(struct host1x_client *client) 98 { 99 struct tegra_drm_client *drm = host1x_to_drm_client(client); 100 struct drm_device *dev = dev_get_drvdata(client->host); 101 struct tegra_drm *tegra = dev->dev_private; 102 struct gr2d *gr2d = to_gr2d(drm); 103 int err; 104 105 err = tegra_drm_unregister_client(tegra, drm); 106 if (err < 0) 107 return err; 108 109 pm_runtime_dont_use_autosuspend(client->dev); 110 pm_runtime_force_suspend(client->dev); 111 112 host1x_client_iommu_detach(client); 113 host1x_syncpt_put(client->syncpts[0]); 114 host1x_channel_put(gr2d->channel); 115 116 gr2d->channel = NULL; 117 118 return 0; 119 } 120 121 static const struct host1x_client_ops gr2d_client_ops = { 122 .init = gr2d_init, 123 .exit = gr2d_exit, 124 }; 125 126 static int gr2d_open_channel(struct tegra_drm_client *client, 127 struct tegra_drm_context *context) 128 { 129 struct gr2d *gr2d = to_gr2d(client); 130 int err; 131 132 err = pm_runtime_resume_and_get(client->base.dev); 133 if (err) 134 return err; 135 136 context->channel = host1x_channel_get(gr2d->channel); 137 if (!context->channel) { 138 pm_runtime_put(client->base.dev); 139 return -ENOMEM; 140 } 141 142 return 0; 143 } 144 145 static void gr2d_close_channel(struct tegra_drm_context *context) 146 { 147 host1x_channel_put(context->channel); 148 pm_runtime_put(context->client->base.dev); 149 } 150 151 static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset) 152 { 153 struct gr2d *gr2d = dev_get_drvdata(dev); 154 155 switch (class) { 156 case HOST1X_CLASS_HOST1X: 157 if (offset == 0x2b) 158 return 1; 159 160 break; 161 162 case HOST1X_CLASS_GR2D: 163 case HOST1X_CLASS_GR2D_SB: 164 if (offset >= GR2D_NUM_REGS) 165 break; 166 167 if (test_bit(offset, gr2d->addr_regs)) 168 return 1; 169 170 break; 171 } 172 173 return 0; 174 } 175 176 static int gr2d_is_valid_class(u32 class) 177 { 178 return (class == HOST1X_CLASS_GR2D || 179 class == HOST1X_CLASS_GR2D_SB); 180 } 181 182 static const struct tegra_drm_client_ops gr2d_ops = { 183 .open_channel = gr2d_open_channel, 184 .close_channel = gr2d_close_channel, 185 .is_addr_reg = gr2d_is_addr_reg, 186 .is_valid_class = gr2d_is_valid_class, 187 .submit = tegra_drm_submit, 188 }; 189 190 static const struct gr2d_soc tegra20_gr2d_soc = { 191 .version = 0x20, 192 }; 193 194 static const struct gr2d_soc tegra30_gr2d_soc = { 195 .version = 0x30, 196 }; 197 198 static const struct gr2d_soc tegra114_gr2d_soc = { 199 .version = 0x35, 200 }; 201 202 static const struct of_device_id gr2d_match[] = { 203 { .compatible = "nvidia,tegra114-gr2d", .data = &tegra114_gr2d_soc }, 204 { .compatible = "nvidia,tegra30-gr2d", .data = &tegra30_gr2d_soc }, 205 { .compatible = "nvidia,tegra20-gr2d", .data = &tegra20_gr2d_soc }, 206 { }, 207 }; 208 MODULE_DEVICE_TABLE(of, gr2d_match); 209 210 static const u32 gr2d_addr_regs[] = { 211 GR2D_UA_BASE_ADDR, 212 GR2D_VA_BASE_ADDR, 213 GR2D_PAT_BASE_ADDR, 214 GR2D_DSTA_BASE_ADDR, 215 GR2D_DSTB_BASE_ADDR, 216 GR2D_DSTC_BASE_ADDR, 217 GR2D_SRCA_BASE_ADDR, 218 GR2D_SRCB_BASE_ADDR, 219 GR2D_PATBASE_ADDR, 220 GR2D_SRC_BASE_ADDR_SB, 221 GR2D_DSTA_BASE_ADDR_SB, 222 GR2D_DSTB_BASE_ADDR_SB, 223 GR2D_UA_BASE_ADDR_SB, 224 GR2D_VA_BASE_ADDR_SB, 225 }; 226 227 static int gr2d_get_resets(struct device *dev, struct gr2d *gr2d) 228 { 229 int err; 230 231 gr2d->resets[RST_MC].id = "mc"; 232 gr2d->resets[RST_GR2D].id = "2d"; 233 gr2d->nresets = RST_GR2D_MAX; 234 235 err = devm_reset_control_bulk_get_optional_exclusive_released( 236 dev, gr2d->nresets, gr2d->resets); 237 if (err) { 238 dev_err(dev, "failed to get reset: %d\n", err); 239 return err; 240 } 241 242 if (WARN_ON(!gr2d->resets[RST_GR2D].rstc)) 243 return -ENOENT; 244 245 return 0; 246 } 247 248 static int gr2d_probe(struct platform_device *pdev) 249 { 250 struct device *dev = &pdev->dev; 251 struct host1x_syncpt **syncpts; 252 struct gr2d *gr2d; 253 unsigned int i; 254 int err; 255 256 gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL); 257 if (!gr2d) 258 return -ENOMEM; 259 260 platform_set_drvdata(pdev, gr2d); 261 262 gr2d->soc = of_device_get_match_data(dev); 263 264 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 265 if (!syncpts) 266 return -ENOMEM; 267 268 gr2d->clk = devm_clk_get(dev, NULL); 269 if (IS_ERR(gr2d->clk)) { 270 dev_err(dev, "cannot get clock\n"); 271 return PTR_ERR(gr2d->clk); 272 } 273 274 err = gr2d_get_resets(dev, gr2d); 275 if (err) 276 return err; 277 278 INIT_LIST_HEAD(&gr2d->client.base.list); 279 gr2d->client.base.ops = &gr2d_client_ops; 280 gr2d->client.base.dev = dev; 281 gr2d->client.base.class = HOST1X_CLASS_GR2D; 282 gr2d->client.base.syncpts = syncpts; 283 gr2d->client.base.num_syncpts = 1; 284 285 INIT_LIST_HEAD(&gr2d->client.list); 286 gr2d->client.version = gr2d->soc->version; 287 gr2d->client.ops = &gr2d_ops; 288 289 err = devm_tegra_core_dev_init_opp_table_common(dev); 290 if (err) 291 return err; 292 293 err = host1x_client_register(&gr2d->client.base); 294 if (err < 0) { 295 dev_err(dev, "failed to register host1x client: %d\n", err); 296 return err; 297 } 298 299 /* initialize address register map */ 300 for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++) 301 set_bit(gr2d_addr_regs[i], gr2d->addr_regs); 302 303 return 0; 304 } 305 306 static int gr2d_remove(struct platform_device *pdev) 307 { 308 struct gr2d *gr2d = platform_get_drvdata(pdev); 309 int err; 310 311 err = host1x_client_unregister(&gr2d->client.base); 312 if (err < 0) { 313 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 314 err); 315 return err; 316 } 317 318 return 0; 319 } 320 321 static int __maybe_unused gr2d_runtime_suspend(struct device *dev) 322 { 323 struct gr2d *gr2d = dev_get_drvdata(dev); 324 int err; 325 326 host1x_channel_stop(gr2d->channel); 327 reset_control_bulk_release(gr2d->nresets, gr2d->resets); 328 329 /* 330 * GR2D module shouldn't be reset while hardware is idling, otherwise 331 * host1x's cmdproc will stuck on trying to access any G2 register 332 * after reset. GR2D module could be either hot-reset or reset after 333 * power-gating of the HEG partition. Hence we will put in reset only 334 * the memory client part of the module, the HEG GENPD will take care 335 * of resetting GR2D module across power-gating. 336 * 337 * On Tegra20 there is no HEG partition, but it's okay to have 338 * undetermined h/w state since userspace is expected to reprogram 339 * the state on each job submission anyways. 340 */ 341 err = reset_control_acquire(gr2d->resets[RST_MC].rstc); 342 if (err) { 343 dev_err(dev, "failed to acquire MC reset: %d\n", err); 344 goto acquire_reset; 345 } 346 347 err = reset_control_assert(gr2d->resets[RST_MC].rstc); 348 reset_control_release(gr2d->resets[RST_MC].rstc); 349 if (err) { 350 dev_err(dev, "failed to assert MC reset: %d\n", err); 351 goto acquire_reset; 352 } 353 354 clk_disable_unprepare(gr2d->clk); 355 356 return 0; 357 358 acquire_reset: 359 reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); 360 reset_control_bulk_deassert(gr2d->nresets, gr2d->resets); 361 362 return err; 363 } 364 365 static int __maybe_unused gr2d_runtime_resume(struct device *dev) 366 { 367 struct gr2d *gr2d = dev_get_drvdata(dev); 368 int err; 369 370 err = reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); 371 if (err) { 372 dev_err(dev, "failed to acquire reset: %d\n", err); 373 return err; 374 } 375 376 err = clk_prepare_enable(gr2d->clk); 377 if (err) { 378 dev_err(dev, "failed to enable clock: %d\n", err); 379 goto release_reset; 380 } 381 382 usleep_range(2000, 4000); 383 384 /* this is a reset array which deasserts both 2D MC and 2D itself */ 385 err = reset_control_bulk_deassert(gr2d->nresets, gr2d->resets); 386 if (err) { 387 dev_err(dev, "failed to deassert reset: %d\n", err); 388 goto disable_clk; 389 } 390 391 return 0; 392 393 disable_clk: 394 clk_disable_unprepare(gr2d->clk); 395 release_reset: 396 reset_control_bulk_release(gr2d->nresets, gr2d->resets); 397 398 return err; 399 } 400 401 static const struct dev_pm_ops tegra_gr2d_pm = { 402 SET_RUNTIME_PM_OPS(gr2d_runtime_suspend, gr2d_runtime_resume, NULL) 403 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 404 pm_runtime_force_resume) 405 }; 406 407 struct platform_driver tegra_gr2d_driver = { 408 .driver = { 409 .name = "tegra-gr2d", 410 .of_match_table = gr2d_match, 411 .pm = &tegra_gr2d_pm, 412 }, 413 .probe = gr2d_probe, 414 .remove = gr2d_remove, 415 }; 416