1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* Copyright 2017-2019 Qiang Yu <[email protected]> */ 3 4 #include <linux/regulator/consumer.h> 5 #include <linux/reset.h> 6 #include <linux/clk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/platform_device.h> 9 10 #include "lima_device.h" 11 #include "lima_gp.h" 12 #include "lima_pp.h" 13 #include "lima_mmu.h" 14 #include "lima_pmu.h" 15 #include "lima_l2_cache.h" 16 #include "lima_dlbu.h" 17 #include "lima_bcast.h" 18 #include "lima_vm.h" 19 20 struct lima_ip_desc { 21 char *name; 22 char *irq_name; 23 bool must_have[lima_gpu_num]; 24 int offset[lima_gpu_num]; 25 26 int (*init)(struct lima_ip *ip); 27 void (*fini)(struct lima_ip *ip); 28 }; 29 30 #define LIMA_IP_DESC(ipname, mst0, mst1, off0, off1, func, irq) \ 31 [lima_ip_##ipname] = { \ 32 .name = #ipname, \ 33 .irq_name = irq, \ 34 .must_have = { \ 35 [lima_gpu_mali400] = mst0, \ 36 [lima_gpu_mali450] = mst1, \ 37 }, \ 38 .offset = { \ 39 [lima_gpu_mali400] = off0, \ 40 [lima_gpu_mali450] = off1, \ 41 }, \ 42 .init = lima_##func##_init, \ 43 .fini = lima_##func##_fini, \ 44 } 45 46 static struct lima_ip_desc lima_ip_desc[lima_ip_num] = { 47 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"), 48 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL), 49 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL), 50 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL), 51 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"), 52 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"), 53 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"), 54 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"), 55 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"), 56 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"), 57 LIMA_IP_DESC(pp5, false, false, -1, 0x2A000, pp, "pp5"), 58 LIMA_IP_DESC(pp6, false, false, -1, 0x2C000, pp, "pp6"), 59 LIMA_IP_DESC(pp7, false, false, -1, 0x2E000, pp, "pp7"), 60 LIMA_IP_DESC(gpmmu, true, true, 0x03000, 0x03000, mmu, "gpmmu"), 61 LIMA_IP_DESC(ppmmu0, true, true, 0x04000, 0x04000, mmu, "ppmmu0"), 62 LIMA_IP_DESC(ppmmu1, false, false, 0x05000, 0x05000, mmu, "ppmmu1"), 63 LIMA_IP_DESC(ppmmu2, false, false, 0x06000, 0x06000, mmu, "ppmmu2"), 64 LIMA_IP_DESC(ppmmu3, false, false, 0x07000, 0x07000, mmu, "ppmmu3"), 65 LIMA_IP_DESC(ppmmu4, false, false, -1, 0x1C000, mmu, "ppmmu4"), 66 LIMA_IP_DESC(ppmmu5, false, false, -1, 0x1D000, mmu, "ppmmu5"), 67 LIMA_IP_DESC(ppmmu6, false, false, -1, 0x1E000, mmu, "ppmmu6"), 68 LIMA_IP_DESC(ppmmu7, false, false, -1, 0x1F000, mmu, "ppmmu7"), 69 LIMA_IP_DESC(dlbu, false, true, -1, 0x14000, dlbu, NULL), 70 LIMA_IP_DESC(bcast, false, true, -1, 0x13000, bcast, NULL), 71 LIMA_IP_DESC(pp_bcast, false, true, -1, 0x16000, pp_bcast, "pp"), 72 LIMA_IP_DESC(ppmmu_bcast, false, true, -1, 0x15000, mmu, NULL), 73 }; 74 75 const char *lima_ip_name(struct lima_ip *ip) 76 { 77 return lima_ip_desc[ip->id].name; 78 } 79 80 static int lima_clk_init(struct lima_device *dev) 81 { 82 int err; 83 84 dev->clk_bus = devm_clk_get(dev->dev, "bus"); 85 if (IS_ERR(dev->clk_bus)) { 86 err = PTR_ERR(dev->clk_bus); 87 dev_err(dev->dev, "get bus clk failed %d\n", err); 88 return err; 89 } 90 91 dev->clk_gpu = devm_clk_get(dev->dev, "core"); 92 if (IS_ERR(dev->clk_gpu)) { 93 err = PTR_ERR(dev->clk_gpu); 94 dev_err(dev->dev, "get core clk failed %d\n", err); 95 return err; 96 } 97 98 err = clk_prepare_enable(dev->clk_bus); 99 if (err) 100 return err; 101 102 err = clk_prepare_enable(dev->clk_gpu); 103 if (err) 104 goto error_out0; 105 106 dev->reset = devm_reset_control_get_optional(dev->dev, NULL); 107 if (IS_ERR(dev->reset)) { 108 err = PTR_ERR(dev->reset); 109 goto error_out1; 110 } else if (dev->reset != NULL) { 111 err = reset_control_deassert(dev->reset); 112 if (err) 113 goto error_out1; 114 } 115 116 return 0; 117 118 error_out1: 119 clk_disable_unprepare(dev->clk_gpu); 120 error_out0: 121 clk_disable_unprepare(dev->clk_bus); 122 return err; 123 } 124 125 static void lima_clk_fini(struct lima_device *dev) 126 { 127 if (dev->reset != NULL) 128 reset_control_assert(dev->reset); 129 clk_disable_unprepare(dev->clk_gpu); 130 clk_disable_unprepare(dev->clk_bus); 131 } 132 133 static int lima_regulator_init(struct lima_device *dev) 134 { 135 int ret; 136 137 dev->regulator = devm_regulator_get_optional(dev->dev, "mali"); 138 if (IS_ERR(dev->regulator)) { 139 ret = PTR_ERR(dev->regulator); 140 dev->regulator = NULL; 141 if (ret == -ENODEV) 142 return 0; 143 if (ret != -EPROBE_DEFER) 144 dev_err(dev->dev, "failed to get regulator: %d\n", ret); 145 return ret; 146 } 147 148 ret = regulator_enable(dev->regulator); 149 if (ret < 0) { 150 dev_err(dev->dev, "failed to enable regulator: %d\n", ret); 151 return ret; 152 } 153 154 return 0; 155 } 156 157 static void lima_regulator_fini(struct lima_device *dev) 158 { 159 if (dev->regulator) 160 regulator_disable(dev->regulator); 161 } 162 163 static int lima_init_ip(struct lima_device *dev, int index) 164 { 165 struct lima_ip_desc *desc = lima_ip_desc + index; 166 struct lima_ip *ip = dev->ip + index; 167 int offset = desc->offset[dev->id]; 168 bool must = desc->must_have[dev->id]; 169 int err; 170 171 if (offset < 0) 172 return 0; 173 174 ip->dev = dev; 175 ip->id = index; 176 ip->iomem = dev->iomem + offset; 177 if (desc->irq_name) { 178 err = platform_get_irq_byname(dev->pdev, desc->irq_name); 179 if (err < 0) 180 goto out; 181 ip->irq = err; 182 } 183 184 err = desc->init(ip); 185 if (!err) { 186 ip->present = true; 187 return 0; 188 } 189 190 out: 191 return must ? err : 0; 192 } 193 194 static void lima_fini_ip(struct lima_device *ldev, int index) 195 { 196 struct lima_ip_desc *desc = lima_ip_desc + index; 197 struct lima_ip *ip = ldev->ip + index; 198 199 if (ip->present) 200 desc->fini(ip); 201 } 202 203 static int lima_init_gp_pipe(struct lima_device *dev) 204 { 205 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp; 206 int err; 207 208 err = lima_sched_pipe_init(pipe, "gp"); 209 if (err) 210 return err; 211 212 pipe->l2_cache[pipe->num_l2_cache++] = dev->ip + lima_ip_l2_cache0; 213 pipe->mmu[pipe->num_mmu++] = dev->ip + lima_ip_gpmmu; 214 pipe->processor[pipe->num_processor++] = dev->ip + lima_ip_gp; 215 216 err = lima_gp_pipe_init(dev); 217 if (err) { 218 lima_sched_pipe_fini(pipe); 219 return err; 220 } 221 222 return 0; 223 } 224 225 static void lima_fini_gp_pipe(struct lima_device *dev) 226 { 227 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp; 228 229 lima_gp_pipe_fini(dev); 230 lima_sched_pipe_fini(pipe); 231 } 232 233 static int lima_init_pp_pipe(struct lima_device *dev) 234 { 235 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; 236 int err, i; 237 238 err = lima_sched_pipe_init(pipe, "pp"); 239 if (err) 240 return err; 241 242 for (i = 0; i < LIMA_SCHED_PIPE_MAX_PROCESSOR; i++) { 243 struct lima_ip *pp = dev->ip + lima_ip_pp0 + i; 244 struct lima_ip *ppmmu = dev->ip + lima_ip_ppmmu0 + i; 245 struct lima_ip *l2_cache; 246 247 if (dev->id == lima_gpu_mali400) 248 l2_cache = dev->ip + lima_ip_l2_cache0; 249 else 250 l2_cache = dev->ip + lima_ip_l2_cache1 + (i >> 2); 251 252 if (pp->present && ppmmu->present && l2_cache->present) { 253 pipe->mmu[pipe->num_mmu++] = ppmmu; 254 pipe->processor[pipe->num_processor++] = pp; 255 if (!pipe->l2_cache[i >> 2]) 256 pipe->l2_cache[pipe->num_l2_cache++] = l2_cache; 257 } 258 } 259 260 if (dev->ip[lima_ip_bcast].present) { 261 pipe->bcast_processor = dev->ip + lima_ip_pp_bcast; 262 pipe->bcast_mmu = dev->ip + lima_ip_ppmmu_bcast; 263 } 264 265 err = lima_pp_pipe_init(dev); 266 if (err) { 267 lima_sched_pipe_fini(pipe); 268 return err; 269 } 270 271 return 0; 272 } 273 274 static void lima_fini_pp_pipe(struct lima_device *dev) 275 { 276 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; 277 278 lima_pp_pipe_fini(dev); 279 lima_sched_pipe_fini(pipe); 280 } 281 282 int lima_device_init(struct lima_device *ldev) 283 { 284 int err, i; 285 struct resource *res; 286 287 dma_set_coherent_mask(ldev->dev, DMA_BIT_MASK(32)); 288 289 err = lima_clk_init(ldev); 290 if (err) { 291 dev_err(ldev->dev, "clk init fail %d\n", err); 292 return err; 293 } 294 295 err = lima_regulator_init(ldev); 296 if (err) 297 goto err_out0; 298 299 ldev->empty_vm = lima_vm_create(ldev); 300 if (!ldev->empty_vm) { 301 err = -ENOMEM; 302 goto err_out1; 303 } 304 305 ldev->va_start = 0; 306 if (ldev->id == lima_gpu_mali450) { 307 ldev->va_end = LIMA_VA_RESERVE_START; 308 ldev->dlbu_cpu = dma_alloc_wc( 309 ldev->dev, LIMA_PAGE_SIZE, 310 &ldev->dlbu_dma, GFP_KERNEL); 311 if (!ldev->dlbu_cpu) { 312 err = -ENOMEM; 313 goto err_out2; 314 } 315 } else 316 ldev->va_end = LIMA_VA_RESERVE_END; 317 318 res = platform_get_resource(ldev->pdev, IORESOURCE_MEM, 0); 319 ldev->iomem = devm_ioremap_resource(ldev->dev, res); 320 if (IS_ERR(ldev->iomem)) { 321 dev_err(ldev->dev, "fail to ioremap iomem\n"); 322 err = PTR_ERR(ldev->iomem); 323 goto err_out3; 324 } 325 326 for (i = 0; i < lima_ip_num; i++) { 327 err = lima_init_ip(ldev, i); 328 if (err) 329 goto err_out4; 330 } 331 332 err = lima_init_gp_pipe(ldev); 333 if (err) 334 goto err_out4; 335 336 err = lima_init_pp_pipe(ldev); 337 if (err) 338 goto err_out5; 339 340 dev_info(ldev->dev, "bus rate = %lu\n", clk_get_rate(ldev->clk_bus)); 341 dev_info(ldev->dev, "mod rate = %lu", clk_get_rate(ldev->clk_gpu)); 342 343 return 0; 344 345 err_out5: 346 lima_fini_gp_pipe(ldev); 347 err_out4: 348 while (--i >= 0) 349 lima_fini_ip(ldev, i); 350 err_out3: 351 if (ldev->dlbu_cpu) 352 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE, 353 ldev->dlbu_cpu, ldev->dlbu_dma); 354 err_out2: 355 lima_vm_put(ldev->empty_vm); 356 err_out1: 357 lima_regulator_fini(ldev); 358 err_out0: 359 lima_clk_fini(ldev); 360 return err; 361 } 362 363 void lima_device_fini(struct lima_device *ldev) 364 { 365 int i; 366 367 lima_fini_pp_pipe(ldev); 368 lima_fini_gp_pipe(ldev); 369 370 for (i = lima_ip_num - 1; i >= 0; i--) 371 lima_fini_ip(ldev, i); 372 373 if (ldev->dlbu_cpu) 374 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE, 375 ldev->dlbu_cpu, ldev->dlbu_dma); 376 377 lima_vm_put(ldev->empty_vm); 378 379 lima_regulator_fini(ldev); 380 381 lima_clk_fini(ldev); 382 } 383