1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* Copyright 2017-2019 Qiang Yu <[email protected]> */ 3 4 #include <linux/regulator/consumer.h> 5 #include <linux/reset.h> 6 #include <linux/clk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/platform_device.h> 9 10 #include "lima_device.h" 11 #include "lima_gp.h" 12 #include "lima_pp.h" 13 #include "lima_mmu.h" 14 #include "lima_pmu.h" 15 #include "lima_l2_cache.h" 16 #include "lima_dlbu.h" 17 #include "lima_bcast.h" 18 #include "lima_vm.h" 19 20 struct lima_ip_desc { 21 char *name; 22 char *irq_name; 23 bool must_have[lima_gpu_num]; 24 int offset[lima_gpu_num]; 25 26 int (*init)(struct lima_ip *ip); 27 void (*fini)(struct lima_ip *ip); 28 }; 29 30 #define LIMA_IP_DESC(ipname, mst0, mst1, off0, off1, func, irq) \ 31 [lima_ip_##ipname] = { \ 32 .name = #ipname, \ 33 .irq_name = irq, \ 34 .must_have = { \ 35 [lima_gpu_mali400] = mst0, \ 36 [lima_gpu_mali450] = mst1, \ 37 }, \ 38 .offset = { \ 39 [lima_gpu_mali400] = off0, \ 40 [lima_gpu_mali450] = off1, \ 41 }, \ 42 .init = lima_##func##_init, \ 43 .fini = lima_##func##_fini, \ 44 } 45 46 static struct lima_ip_desc lima_ip_desc[lima_ip_num] = { 47 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"), 48 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL), 49 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL), 50 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL), 51 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"), 52 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"), 53 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"), 54 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"), 55 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"), 56 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"), 57 LIMA_IP_DESC(pp5, false, false, -1, 0x2A000, pp, "pp5"), 58 LIMA_IP_DESC(pp6, false, false, -1, 0x2C000, pp, "pp6"), 59 LIMA_IP_DESC(pp7, false, false, -1, 0x2E000, pp, "pp7"), 60 LIMA_IP_DESC(gpmmu, true, true, 0x03000, 0x03000, mmu, "gpmmu"), 61 LIMA_IP_DESC(ppmmu0, true, true, 0x04000, 0x04000, mmu, "ppmmu0"), 62 LIMA_IP_DESC(ppmmu1, false, false, 0x05000, 0x05000, mmu, "ppmmu1"), 63 LIMA_IP_DESC(ppmmu2, false, false, 0x06000, 0x06000, mmu, "ppmmu2"), 64 LIMA_IP_DESC(ppmmu3, false, false, 0x07000, 0x07000, mmu, "ppmmu3"), 65 LIMA_IP_DESC(ppmmu4, false, false, -1, 0x1C000, mmu, "ppmmu4"), 66 LIMA_IP_DESC(ppmmu5, false, false, -1, 0x1D000, mmu, "ppmmu5"), 67 LIMA_IP_DESC(ppmmu6, false, false, -1, 0x1E000, mmu, "ppmmu6"), 68 LIMA_IP_DESC(ppmmu7, false, false, -1, 0x1F000, mmu, "ppmmu7"), 69 LIMA_IP_DESC(dlbu, false, true, -1, 0x14000, dlbu, NULL), 70 LIMA_IP_DESC(bcast, false, true, -1, 0x13000, bcast, NULL), 71 LIMA_IP_DESC(pp_bcast, false, true, -1, 0x16000, pp_bcast, "pp"), 72 LIMA_IP_DESC(ppmmu_bcast, false, true, -1, 0x15000, mmu, NULL), 73 }; 74 75 const char *lima_ip_name(struct lima_ip *ip) 76 { 77 return lima_ip_desc[ip->id].name; 78 } 79 80 static int lima_clk_init(struct lima_device *dev) 81 { 82 int err; 83 84 dev->clk_bus = devm_clk_get(dev->dev, "bus"); 85 if (IS_ERR(dev->clk_bus)) { 86 dev_err(dev->dev, "get bus clk failed %ld\n", PTR_ERR(dev->clk_bus)); 87 return PTR_ERR(dev->clk_bus); 88 } 89 90 dev->clk_gpu = devm_clk_get(dev->dev, "core"); 91 if (IS_ERR(dev->clk_gpu)) { 92 dev_err(dev->dev, "get core clk failed %ld\n", PTR_ERR(dev->clk_gpu)); 93 return PTR_ERR(dev->clk_gpu); 94 } 95 96 err = clk_prepare_enable(dev->clk_bus); 97 if (err) 98 return err; 99 100 err = clk_prepare_enable(dev->clk_gpu); 101 if (err) 102 goto error_out0; 103 104 dev->reset = devm_reset_control_get_optional(dev->dev, NULL); 105 if (IS_ERR(dev->reset)) { 106 err = PTR_ERR(dev->reset); 107 goto error_out1; 108 } else if (dev->reset != NULL) { 109 err = reset_control_deassert(dev->reset); 110 if (err) 111 goto error_out1; 112 } 113 114 return 0; 115 116 error_out1: 117 clk_disable_unprepare(dev->clk_gpu); 118 error_out0: 119 clk_disable_unprepare(dev->clk_bus); 120 return err; 121 } 122 123 static void lima_clk_fini(struct lima_device *dev) 124 { 125 if (dev->reset != NULL) 126 reset_control_assert(dev->reset); 127 clk_disable_unprepare(dev->clk_gpu); 128 clk_disable_unprepare(dev->clk_bus); 129 } 130 131 static int lima_regulator_init(struct lima_device *dev) 132 { 133 int ret; 134 135 dev->regulator = devm_regulator_get_optional(dev->dev, "mali"); 136 if (IS_ERR(dev->regulator)) { 137 ret = PTR_ERR(dev->regulator); 138 dev->regulator = NULL; 139 if (ret == -ENODEV) 140 return 0; 141 if (ret != -EPROBE_DEFER) 142 dev_err(dev->dev, "failed to get regulator: %d\n", ret); 143 return ret; 144 } 145 146 ret = regulator_enable(dev->regulator); 147 if (ret < 0) { 148 dev_err(dev->dev, "failed to enable regulator: %d\n", ret); 149 return ret; 150 } 151 152 return 0; 153 } 154 155 static void lima_regulator_fini(struct lima_device *dev) 156 { 157 if (dev->regulator) 158 regulator_disable(dev->regulator); 159 } 160 161 static int lima_init_ip(struct lima_device *dev, int index) 162 { 163 struct lima_ip_desc *desc = lima_ip_desc + index; 164 struct lima_ip *ip = dev->ip + index; 165 int offset = desc->offset[dev->id]; 166 bool must = desc->must_have[dev->id]; 167 int err; 168 169 if (offset < 0) 170 return 0; 171 172 ip->dev = dev; 173 ip->id = index; 174 ip->iomem = dev->iomem + offset; 175 if (desc->irq_name) { 176 err = platform_get_irq_byname(dev->pdev, desc->irq_name); 177 if (err < 0) 178 goto out; 179 ip->irq = err; 180 } 181 182 err = desc->init(ip); 183 if (!err) { 184 ip->present = true; 185 return 0; 186 } 187 188 out: 189 return must ? err : 0; 190 } 191 192 static void lima_fini_ip(struct lima_device *ldev, int index) 193 { 194 struct lima_ip_desc *desc = lima_ip_desc + index; 195 struct lima_ip *ip = ldev->ip + index; 196 197 if (ip->present) 198 desc->fini(ip); 199 } 200 201 static int lima_init_gp_pipe(struct lima_device *dev) 202 { 203 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp; 204 int err; 205 206 err = lima_sched_pipe_init(pipe, "gp"); 207 if (err) 208 return err; 209 210 pipe->l2_cache[pipe->num_l2_cache++] = dev->ip + lima_ip_l2_cache0; 211 pipe->mmu[pipe->num_mmu++] = dev->ip + lima_ip_gpmmu; 212 pipe->processor[pipe->num_processor++] = dev->ip + lima_ip_gp; 213 214 err = lima_gp_pipe_init(dev); 215 if (err) { 216 lima_sched_pipe_fini(pipe); 217 return err; 218 } 219 220 return 0; 221 } 222 223 static void lima_fini_gp_pipe(struct lima_device *dev) 224 { 225 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp; 226 227 lima_gp_pipe_fini(dev); 228 lima_sched_pipe_fini(pipe); 229 } 230 231 static int lima_init_pp_pipe(struct lima_device *dev) 232 { 233 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; 234 int err, i; 235 236 err = lima_sched_pipe_init(pipe, "pp"); 237 if (err) 238 return err; 239 240 for (i = 0; i < LIMA_SCHED_PIPE_MAX_PROCESSOR; i++) { 241 struct lima_ip *pp = dev->ip + lima_ip_pp0 + i; 242 struct lima_ip *ppmmu = dev->ip + lima_ip_ppmmu0 + i; 243 struct lima_ip *l2_cache; 244 245 if (dev->id == lima_gpu_mali400) 246 l2_cache = dev->ip + lima_ip_l2_cache0; 247 else 248 l2_cache = dev->ip + lima_ip_l2_cache1 + (i >> 2); 249 250 if (pp->present && ppmmu->present && l2_cache->present) { 251 pipe->mmu[pipe->num_mmu++] = ppmmu; 252 pipe->processor[pipe->num_processor++] = pp; 253 if (!pipe->l2_cache[i >> 2]) 254 pipe->l2_cache[pipe->num_l2_cache++] = l2_cache; 255 } 256 } 257 258 if (dev->ip[lima_ip_bcast].present) { 259 pipe->bcast_processor = dev->ip + lima_ip_pp_bcast; 260 pipe->bcast_mmu = dev->ip + lima_ip_ppmmu_bcast; 261 } 262 263 err = lima_pp_pipe_init(dev); 264 if (err) { 265 lima_sched_pipe_fini(pipe); 266 return err; 267 } 268 269 return 0; 270 } 271 272 static void lima_fini_pp_pipe(struct lima_device *dev) 273 { 274 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; 275 276 lima_pp_pipe_fini(dev); 277 lima_sched_pipe_fini(pipe); 278 } 279 280 int lima_device_init(struct lima_device *ldev) 281 { 282 int err, i; 283 struct resource *res; 284 285 dma_set_coherent_mask(ldev->dev, DMA_BIT_MASK(32)); 286 287 err = lima_clk_init(ldev); 288 if (err) { 289 dev_err(ldev->dev, "clk init fail %d\n", err); 290 return err; 291 } 292 293 err = lima_regulator_init(ldev); 294 if (err) 295 goto err_out0; 296 297 ldev->empty_vm = lima_vm_create(ldev); 298 if (!ldev->empty_vm) { 299 err = -ENOMEM; 300 goto err_out1; 301 } 302 303 ldev->va_start = 0; 304 if (ldev->id == lima_gpu_mali450) { 305 ldev->va_end = LIMA_VA_RESERVE_START; 306 ldev->dlbu_cpu = dma_alloc_wc( 307 ldev->dev, LIMA_PAGE_SIZE, 308 &ldev->dlbu_dma, GFP_KERNEL); 309 if (!ldev->dlbu_cpu) { 310 err = -ENOMEM; 311 goto err_out2; 312 } 313 } else 314 ldev->va_end = LIMA_VA_RESERVE_END; 315 316 res = platform_get_resource(ldev->pdev, IORESOURCE_MEM, 0); 317 ldev->iomem = devm_ioremap_resource(ldev->dev, res); 318 if (IS_ERR(ldev->iomem)) { 319 dev_err(ldev->dev, "fail to ioremap iomem\n"); 320 err = PTR_ERR(ldev->iomem); 321 goto err_out3; 322 } 323 324 for (i = 0; i < lima_ip_num; i++) { 325 err = lima_init_ip(ldev, i); 326 if (err) 327 goto err_out4; 328 } 329 330 err = lima_init_gp_pipe(ldev); 331 if (err) 332 goto err_out4; 333 334 err = lima_init_pp_pipe(ldev); 335 if (err) 336 goto err_out5; 337 338 dev_info(ldev->dev, "bus rate = %lu\n", clk_get_rate(ldev->clk_bus)); 339 dev_info(ldev->dev, "mod rate = %lu", clk_get_rate(ldev->clk_gpu)); 340 341 return 0; 342 343 err_out5: 344 lima_fini_gp_pipe(ldev); 345 err_out4: 346 while (--i >= 0) 347 lima_fini_ip(ldev, i); 348 err_out3: 349 if (ldev->dlbu_cpu) 350 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE, 351 ldev->dlbu_cpu, ldev->dlbu_dma); 352 err_out2: 353 lima_vm_put(ldev->empty_vm); 354 err_out1: 355 lima_regulator_fini(ldev); 356 err_out0: 357 lima_clk_fini(ldev); 358 return err; 359 } 360 361 void lima_device_fini(struct lima_device *ldev) 362 { 363 int i; 364 365 lima_fini_pp_pipe(ldev); 366 lima_fini_gp_pipe(ldev); 367 368 for (i = lima_ip_num - 1; i >= 0; i--) 369 lima_fini_ip(ldev, i); 370 371 if (ldev->dlbu_cpu) 372 dma_free_wc(ldev->dev, LIMA_PAGE_SIZE, 373 ldev->dlbu_cpu, ldev->dlbu_dma); 374 375 lima_vm_put(ldev->empty_vm); 376 377 lima_regulator_fini(ldev); 378 379 lima_clk_fini(ldev); 380 } 381