xref: /linux-6.15/drivers/gpu/drm/i915/intel_pcode.h (revision 5f38c3fb)
14dd4375bSJani Nikula /* SPDX-License-Identifier: MIT */
24dd4375bSJani Nikula /*
34dd4375bSJani Nikula  * Copyright © 2013-2021 Intel Corporation
44dd4375bSJani Nikula  */
54dd4375bSJani Nikula 
64dd4375bSJani Nikula #ifndef _INTEL_PCODE_H_
74dd4375bSJani Nikula #define _INTEL_PCODE_H_
84dd4375bSJani Nikula 
94dd4375bSJani Nikula #include <linux/types.h>
104dd4375bSJani Nikula 
11ee421bb4SAshutosh Dixit struct intel_uncore;
124dd4375bSJani Nikula 
13ee421bb4SAshutosh Dixit int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
14ee421bb4SAshutosh Dixit int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
156650ebcbSJani Nikula 			    int fast_timeout_us, int slow_timeout_ms);
16ee421bb4SAshutosh Dixit #define snb_pcode_write(uncore, mbox, val) \
17ee421bb4SAshutosh Dixit 	snb_pcode_write_timeout(uncore, mbox, val, 500, 0)
184dd4375bSJani Nikula 
19ee421bb4SAshutosh Dixit int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
204dd4375bSJani Nikula 		      u32 reply_mask, u32 reply, int timeout_base_ms);
214dd4375bSJani Nikula 
22ee421bb4SAshutosh Dixit int intel_pcode_init(struct intel_uncore *uncore);
234dd4375bSJani Nikula 
24*5f38c3fbSDale B Stimson /*
25*5f38c3fbSDale B Stimson  * Helpers for dGfx PCODE mailbox command formatting
26*5f38c3fbSDale B Stimson  */
27*5f38c3fbSDale B Stimson int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
28*5f38c3fbSDale B Stimson int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
29*5f38c3fbSDale B Stimson 
304dd4375bSJani Nikula #endif /* _INTEL_PCODE_H */
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