1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "g4x_dp.h" 7 #include "i915_drv.h" 8 #include "i915_reg.h" 9 #include "intel_crt.h" 10 #include "intel_crt_regs.h" 11 #include "intel_de.h" 12 #include "intel_display_types.h" 13 #include "intel_dpll.h" 14 #include "intel_fdi.h" 15 #include "intel_fdi_regs.h" 16 #include "intel_lvds.h" 17 #include "intel_lvds_regs.h" 18 #include "intel_pch_display.h" 19 #include "intel_pch_refclk.h" 20 #include "intel_pps.h" 21 #include "intel_sdvo.h" 22 23 bool intel_has_pch_trancoder(struct drm_i915_private *i915, 24 enum pipe pch_transcoder) 25 { 26 return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) || 27 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); 28 } 29 30 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) 31 { 32 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 33 34 if (HAS_PCH_LPT(i915)) 35 return PIPE_A; 36 else 37 return crtc->pipe; 38 } 39 40 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 41 enum pipe pipe, enum port port, 42 i915_reg_t dp_reg) 43 { 44 struct intel_display *display = &dev_priv->display; 45 enum pipe port_pipe; 46 bool state; 47 48 state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe); 49 50 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, 51 "PCH DP %c enabled on transcoder %c, should be disabled\n", 52 port_name(port), pipe_name(pipe)); 53 54 INTEL_DISPLAY_STATE_WARN(display, 55 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 56 "IBX PCH DP %c still using transcoder B\n", 57 port_name(port)); 58 } 59 60 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 61 enum pipe pipe, enum port port, 62 i915_reg_t hdmi_reg) 63 { 64 struct intel_display *display = &dev_priv->display; 65 enum pipe port_pipe; 66 bool state; 67 68 state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe); 69 70 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, 71 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", 72 port_name(port), pipe_name(pipe)); 73 74 INTEL_DISPLAY_STATE_WARN(display, 75 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, 76 "IBX PCH HDMI %c still using transcoder B\n", 77 port_name(port)); 78 } 79 80 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 81 enum pipe pipe) 82 { 83 struct intel_display *display = &dev_priv->display; 84 enum pipe port_pipe; 85 86 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); 87 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); 88 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); 89 90 INTEL_DISPLAY_STATE_WARN(display, 91 intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe, 92 "PCH VGA enabled on transcoder %c, should be disabled\n", 93 pipe_name(pipe)); 94 95 INTEL_DISPLAY_STATE_WARN(display, 96 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe, 97 "PCH LVDS enabled on transcoder %c, should be disabled\n", 98 pipe_name(pipe)); 99 100 /* PCH SDVOB multiplex with HDMIB */ 101 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); 102 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); 103 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); 104 } 105 106 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 107 enum pipe pipe) 108 { 109 struct intel_display *display = &dev_priv->display; 110 u32 val; 111 bool enabled; 112 113 val = intel_de_read(display, PCH_TRANSCONF(pipe)); 114 enabled = !!(val & TRANS_ENABLE); 115 INTEL_DISPLAY_STATE_WARN(display, enabled, 116 "transcoder assertion failed, should be off on pipe %c but is still active\n", 117 pipe_name(pipe)); 118 } 119 120 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, 121 enum port port, i915_reg_t hdmi_reg) 122 { 123 u32 val = intel_de_read(dev_priv, hdmi_reg); 124 125 if (val & SDVO_ENABLE || 126 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) 127 return; 128 129 drm_dbg_kms(&dev_priv->drm, 130 "Sanitizing transcoder select for HDMI %c\n", 131 port_name(port)); 132 133 val &= ~SDVO_PIPE_SEL_MASK; 134 val |= SDVO_PIPE_SEL(PIPE_A); 135 136 intel_de_write(dev_priv, hdmi_reg, val); 137 } 138 139 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, 140 enum port port, i915_reg_t dp_reg) 141 { 142 u32 val = intel_de_read(dev_priv, dp_reg); 143 144 if (val & DP_PORT_EN || 145 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) 146 return; 147 148 drm_dbg_kms(&dev_priv->drm, 149 "Sanitizing transcoder select for DP %c\n", 150 port_name(port)); 151 152 val &= ~DP_PIPE_SEL_MASK; 153 val |= DP_PIPE_SEL(PIPE_A); 154 155 intel_de_write(dev_priv, dp_reg, val); 156 } 157 158 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) 159 { 160 /* 161 * The BIOS may select transcoder B on some of the PCH 162 * ports even it doesn't enable the port. This would trip 163 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). 164 * Sanitize the transcoder select bits to prevent that. We 165 * assume that the BIOS never actually enabled the port, 166 * because if it did we'd actually have to toggle the port 167 * on and back off to make the transcoder A select stick 168 * (see. intel_dp_link_down(), intel_disable_hdmi(), 169 * intel_disable_sdvo()). 170 */ 171 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); 172 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C); 173 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D); 174 175 /* PCH SDVOB multiplex with HDMIB */ 176 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); 177 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC); 178 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID); 179 } 180 181 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, 182 const struct intel_link_m_n *m_n) 183 { 184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 185 enum pipe pipe = crtc->pipe; 186 187 intel_set_m_n(dev_priv, m_n, 188 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 189 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 190 } 191 192 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, 193 const struct intel_link_m_n *m_n) 194 { 195 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 196 enum pipe pipe = crtc->pipe; 197 198 intel_set_m_n(dev_priv, m_n, 199 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 200 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 201 } 202 203 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, 204 struct intel_link_m_n *m_n) 205 { 206 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 207 enum pipe pipe = crtc->pipe; 208 209 intel_get_m_n(dev_priv, m_n, 210 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), 211 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); 212 } 213 214 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, 215 struct intel_link_m_n *m_n) 216 { 217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 218 enum pipe pipe = crtc->pipe; 219 220 intel_get_m_n(dev_priv, m_n, 221 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), 222 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); 223 } 224 225 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, 226 enum pipe pch_transcoder) 227 { 228 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 229 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 230 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 231 232 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), 233 intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder))); 234 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), 235 intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder))); 236 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), 237 intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder))); 238 239 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), 240 intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder))); 241 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), 242 intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); 243 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), 244 intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); 245 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), 246 intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder))); 247 } 248 249 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 250 { 251 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 252 struct intel_display *display = to_intel_display(crtc); 253 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 254 enum pipe pipe = crtc->pipe; 255 i915_reg_t reg; 256 u32 val, pipeconf_val; 257 258 /* Make sure PCH DPLL is enabled */ 259 assert_shared_dpll_enabled(display, crtc_state->shared_dpll); 260 261 /* FDI must be feeding us bits for PCH ports */ 262 assert_fdi_tx_enabled(dev_priv, pipe); 263 assert_fdi_rx_enabled(dev_priv, pipe); 264 265 if (HAS_PCH_CPT(dev_priv)) { 266 reg = TRANS_CHICKEN2(pipe); 267 val = intel_de_read(display, reg); 268 /* 269 * Workaround: Set the timing override bit 270 * before enabling the pch transcoder. 271 */ 272 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 273 /* Configure frame start delay to match the CPU */ 274 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 275 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 276 intel_de_write(display, reg, val); 277 } 278 279 reg = PCH_TRANSCONF(pipe); 280 val = intel_de_read(display, reg); 281 pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe)); 282 283 if (HAS_PCH_IBX(dev_priv)) { 284 /* Configure frame start delay to match the CPU */ 285 val &= ~TRANS_FRAME_START_DELAY_MASK; 286 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 287 288 /* 289 * Make the BPC in transcoder be consistent with 290 * that in pipeconf reg. For HDMI we must use 8bpc 291 * here for both 8bpc and 12bpc. 292 */ 293 val &= ~TRANSCONF_BPC_MASK; 294 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 295 val |= TRANSCONF_BPC_8; 296 else 297 val |= pipeconf_val & TRANSCONF_BPC_MASK; 298 } 299 300 val &= ~TRANS_INTERLACE_MASK; 301 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) { 302 if (HAS_PCH_IBX(dev_priv) && 303 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 304 val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX; 305 else 306 val |= TRANS_INTERLACE_INTERLACED; 307 } else { 308 val |= TRANS_INTERLACE_PROGRESSIVE; 309 } 310 311 intel_de_write(display, reg, val | TRANS_ENABLE); 312 if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100)) 313 drm_err(display->drm, "failed to enable transcoder %c\n", 314 pipe_name(pipe)); 315 } 316 317 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) 318 { 319 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 320 enum pipe pipe = crtc->pipe; 321 i915_reg_t reg; 322 323 /* FDI relies on the transcoder */ 324 assert_fdi_tx_disabled(dev_priv, pipe); 325 assert_fdi_rx_disabled(dev_priv, pipe); 326 327 /* Ports must be off as well */ 328 assert_pch_ports_disabled(dev_priv, pipe); 329 330 reg = PCH_TRANSCONF(pipe); 331 intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0); 332 /* wait for PCH transcoder off, transcoder state */ 333 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) 334 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", 335 pipe_name(pipe)); 336 337 if (HAS_PCH_CPT(dev_priv)) 338 /* Workaround: Clear the timing override chicken bit again. */ 339 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), 340 TRANS_CHICKEN2_TIMING_OVERRIDE, 0); 341 } 342 343 void ilk_pch_pre_enable(struct intel_atomic_state *state, 344 struct intel_crtc *crtc) 345 { 346 const struct intel_crtc_state *crtc_state = 347 intel_atomic_get_new_crtc_state(state, crtc); 348 349 /* 350 * Note: FDI PLL enabling _must_ be done before we enable the 351 * cpu pipes, hence this is separate from all the other fdi/pch 352 * enabling. 353 */ 354 ilk_fdi_pll_enable(crtc_state); 355 } 356 357 /* 358 * Enable PCH resources required for PCH ports: 359 * - PCH PLLs 360 * - FDI training & RX/TX 361 * - update transcoder timings 362 * - DP transcoding bits 363 * - transcoder 364 */ 365 void ilk_pch_enable(struct intel_atomic_state *state, 366 struct intel_crtc *crtc) 367 { 368 struct intel_display *display = to_intel_display(state); 369 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 370 const struct intel_crtc_state *crtc_state = 371 intel_atomic_get_new_crtc_state(state, crtc); 372 enum pipe pipe = crtc->pipe; 373 u32 temp; 374 375 assert_pch_transcoder_disabled(dev_priv, pipe); 376 377 /* For PCH output, training FDI link */ 378 intel_fdi_link_train(crtc, crtc_state); 379 380 /* 381 * We need to program the right clock selection 382 * before writing the pixel multiplier into the DPLL. 383 */ 384 if (HAS_PCH_CPT(dev_priv)) { 385 u32 sel; 386 387 temp = intel_de_read(display, PCH_DPLL_SEL); 388 temp |= TRANS_DPLL_ENABLE(pipe); 389 sel = TRANS_DPLLB_SEL(pipe); 390 if (crtc_state->shared_dpll == 391 intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) 392 temp |= sel; 393 else 394 temp &= ~sel; 395 intel_de_write(display, PCH_DPLL_SEL, temp); 396 } 397 398 /* 399 * XXX: pch pll's can be enabled any time before we enable the PCH 400 * transcoder, and we actually should do this to not upset any PCH 401 * transcoder that already use the clock when we share it. 402 * 403 * Note that enable_shared_dpll tries to do the right thing, but 404 * get_shared_dpll unconditionally resets the pll - we need that 405 * to have the right LVDS enable sequence. 406 */ 407 intel_enable_shared_dpll(crtc_state); 408 409 /* set transcoder timing, panel must allow it */ 410 assert_pps_unlocked(display, pipe); 411 if (intel_crtc_has_dp_encoder(crtc_state)) { 412 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); 413 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2); 414 } 415 ilk_pch_transcoder_set_timings(crtc_state, pipe); 416 417 intel_fdi_normal_train(crtc); 418 419 /* For PCH DP, enable TRANS_DP_CTL */ 420 if (HAS_PCH_CPT(dev_priv) && 421 intel_crtc_has_dp_encoder(crtc_state)) { 422 const struct drm_display_mode *adjusted_mode = 423 &crtc_state->hw.adjusted_mode; 424 u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe)) 425 & TRANSCONF_BPC_MASK) >> 5; 426 i915_reg_t reg = TRANS_DP_CTL(pipe); 427 enum port port; 428 429 temp = intel_de_read(display, reg); 430 temp &= ~(TRANS_DP_PORT_SEL_MASK | 431 TRANS_DP_VSYNC_ACTIVE_HIGH | 432 TRANS_DP_HSYNC_ACTIVE_HIGH | 433 TRANS_DP_BPC_MASK); 434 temp |= TRANS_DP_OUTPUT_ENABLE; 435 temp |= bpc << 9; /* same format but at 11:9 */ 436 437 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 438 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 439 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 440 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 441 442 port = intel_get_crtc_new_encoder(state, crtc_state)->port; 443 drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); 444 temp |= TRANS_DP_PORT_SEL(port); 445 446 intel_de_write(display, reg, temp); 447 } 448 449 ilk_enable_pch_transcoder(crtc_state); 450 } 451 452 void ilk_pch_disable(struct intel_atomic_state *state, 453 struct intel_crtc *crtc) 454 { 455 ilk_fdi_disable(crtc); 456 } 457 458 void ilk_pch_post_disable(struct intel_atomic_state *state, 459 struct intel_crtc *crtc) 460 { 461 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 462 enum pipe pipe = crtc->pipe; 463 464 ilk_disable_pch_transcoder(crtc); 465 466 if (HAS_PCH_CPT(dev_priv)) { 467 /* disable TRANS_DP_CTL */ 468 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), 469 TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK, 470 TRANS_DP_PORT_SEL_NONE); 471 472 /* disable DPLL_SEL */ 473 intel_de_rmw(dev_priv, PCH_DPLL_SEL, 474 TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0); 475 } 476 477 ilk_fdi_pll_disable(crtc); 478 } 479 480 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) 481 { 482 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 484 485 /* read out port_clock from the DPLL */ 486 i9xx_crtc_clock_get(crtc_state); 487 488 /* 489 * In case there is an active pipe without active ports, 490 * we may need some idea for the dotclock anyway. 491 * Calculate one based on the FDI configuration. 492 */ 493 crtc_state->hw.adjusted_mode.crtc_clock = 494 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state), 495 &crtc_state->fdi_m_n); 496 } 497 498 void ilk_pch_get_config(struct intel_crtc_state *crtc_state) 499 { 500 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 501 struct intel_display *display = to_intel_display(crtc); 502 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 503 struct intel_shared_dpll *pll; 504 enum pipe pipe = crtc->pipe; 505 enum intel_dpll_id pll_id; 506 bool pll_active; 507 u32 tmp; 508 509 if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) 510 return; 511 512 crtc_state->has_pch_encoder = true; 513 514 tmp = intel_de_read(display, FDI_RX_CTL(pipe)); 515 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 516 FDI_DP_PORT_WIDTH_SHIFT) + 1; 517 518 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 519 &crtc_state->fdi_m_n); 520 521 if (HAS_PCH_IBX(dev_priv)) { 522 /* 523 * The pipe->pch transcoder and pch transcoder->pll 524 * mapping is fixed. 525 */ 526 pll_id = (enum intel_dpll_id) pipe; 527 } else { 528 tmp = intel_de_read(display, PCH_DPLL_SEL); 529 if (tmp & TRANS_DPLLB_SEL(pipe)) 530 pll_id = DPLL_ID_PCH_PLL_B; 531 else 532 pll_id = DPLL_ID_PCH_PLL_A; 533 } 534 535 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id); 536 pll = crtc_state->shared_dpll; 537 538 pll_active = intel_dpll_get_hw_state(display, pll, 539 &crtc_state->dpll_hw_state); 540 drm_WARN_ON(display->drm, !pll_active); 541 542 tmp = crtc_state->dpll_hw_state.i9xx.dpll; 543 crtc_state->pixel_multiplier = 544 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) 545 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; 546 547 ilk_pch_clock_get(crtc_state); 548 } 549 550 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 551 { 552 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 553 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 554 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 555 u32 val, pipeconf_val; 556 557 /* FDI must be feeding us bits for PCH ports */ 558 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 559 assert_fdi_rx_enabled(dev_priv, PIPE_A); 560 561 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); 562 /* Workaround: set timing override bit. */ 563 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 564 /* Configure frame start delay to match the CPU */ 565 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 566 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 567 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); 568 569 val = TRANS_ENABLE; 570 pipeconf_val = intel_de_read(dev_priv, 571 TRANSCONF(dev_priv, cpu_transcoder)); 572 573 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK) 574 val |= TRANS_INTERLACE_INTERLACED; 575 else 576 val |= TRANS_INTERLACE_PROGRESSIVE; 577 578 intel_de_write(dev_priv, LPT_TRANSCONF, val); 579 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, 580 TRANS_STATE_ENABLE, 100)) 581 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); 582 } 583 584 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 585 { 586 intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0); 587 /* wait for PCH transcoder off, transcoder state */ 588 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, 589 TRANS_STATE_ENABLE, 50)) 590 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); 591 592 /* Workaround: clear timing override bit. */ 593 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); 594 } 595 596 void lpt_pch_enable(struct intel_atomic_state *state, 597 struct intel_crtc *crtc) 598 { 599 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 600 const struct intel_crtc_state *crtc_state = 601 intel_atomic_get_new_crtc_state(state, crtc); 602 603 assert_pch_transcoder_disabled(dev_priv, PIPE_A); 604 605 lpt_program_iclkip(crtc_state); 606 607 /* Set transcoder timing. */ 608 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); 609 610 lpt_enable_pch_transcoder(crtc_state); 611 } 612 613 void lpt_pch_disable(struct intel_atomic_state *state, 614 struct intel_crtc *crtc) 615 { 616 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 617 618 lpt_disable_pch_transcoder(dev_priv); 619 620 lpt_disable_iclkip(dev_priv); 621 } 622 623 void lpt_pch_get_config(struct intel_crtc_state *crtc_state) 624 { 625 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 627 u32 tmp; 628 629 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0) 630 return; 631 632 crtc_state->has_pch_encoder = true; 633 634 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 635 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> 636 FDI_DP_PORT_WIDTH_SHIFT) + 1; 637 638 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 639 &crtc_state->fdi_m_n); 640 641 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 642 } 643 644 void intel_pch_sanitize(struct drm_i915_private *i915) 645 { 646 if (HAS_PCH_IBX(i915)) 647 ibx_sanitize_pch_ports(i915); 648 } 649