1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <[email protected]> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <[email protected]> 26 * Dave Airlie <[email protected]> 27 * Jesse Barnes <[email protected]> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_atomic.h" 45 #include "intel_backlight.h" 46 #include "intel_connector.h" 47 #include "intel_de.h" 48 #include "intel_display_types.h" 49 #include "intel_dpll.h" 50 #include "intel_fdi.h" 51 #include "intel_gmbus.h" 52 #include "intel_lvds.h" 53 #include "intel_lvds_regs.h" 54 #include "intel_panel.h" 55 #include "intel_pfit.h" 56 #include "intel_pps_regs.h" 57 58 /* Private structure for the integrated LVDS support */ 59 struct intel_lvds_pps { 60 struct intel_pps_delays delays; 61 62 int divider; 63 64 int port; 65 bool powerdown_on_reset; 66 }; 67 68 struct intel_lvds_encoder { 69 struct intel_encoder base; 70 71 bool is_dual_link; 72 i915_reg_t reg; 73 u32 a3_power; 74 75 struct intel_lvds_pps init_pps; 76 u32 init_lvds_val; 77 78 struct intel_connector *attached_connector; 79 }; 80 81 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) 82 { 83 return container_of(encoder, struct intel_lvds_encoder, base); 84 } 85 86 bool intel_lvds_port_enabled(struct drm_i915_private *i915, 87 i915_reg_t lvds_reg, enum pipe *pipe) 88 { 89 u32 val; 90 91 val = intel_de_read(i915, lvds_reg); 92 93 /* asserts want to know the pipe even if the port is disabled */ 94 if (HAS_PCH_CPT(i915)) 95 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); 96 else 97 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); 98 99 return val & LVDS_PORT_EN; 100 } 101 102 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 103 enum pipe *pipe) 104 { 105 struct intel_display *display = to_intel_display(encoder); 106 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 107 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 108 intel_wakeref_t wakeref; 109 bool ret; 110 111 wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); 112 if (!wakeref) 113 return false; 114 115 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); 116 117 intel_display_power_put(display, encoder->power_domain, wakeref); 118 119 return ret; 120 } 121 122 static void intel_lvds_get_config(struct intel_encoder *encoder, 123 struct intel_crtc_state *crtc_state) 124 { 125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 126 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 127 u32 tmp, flags = 0; 128 129 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); 130 131 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 132 if (tmp & LVDS_HSYNC_POLARITY) 133 flags |= DRM_MODE_FLAG_NHSYNC; 134 else 135 flags |= DRM_MODE_FLAG_PHSYNC; 136 if (tmp & LVDS_VSYNC_POLARITY) 137 flags |= DRM_MODE_FLAG_NVSYNC; 138 else 139 flags |= DRM_MODE_FLAG_PVSYNC; 140 141 crtc_state->hw.adjusted_mode.flags |= flags; 142 143 if (DISPLAY_VER(dev_priv) < 5) 144 crtc_state->gmch_pfit.lvds_border_bits = 145 tmp & LVDS_BORDER_ENABLE; 146 147 /* gen2/3 store dither state in pfit control, needs to match */ 148 if (DISPLAY_VER(dev_priv) < 4) { 149 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); 150 151 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE; 152 } 153 154 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 155 } 156 157 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 158 struct intel_lvds_pps *pps) 159 { 160 u32 val; 161 162 pps->powerdown_on_reset = intel_de_read(dev_priv, 163 PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET; 164 165 val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); 166 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 167 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 168 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 169 170 val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); 171 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 172 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 173 174 val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); 175 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 176 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 177 /* 178 * Remove the BSpec specified +1 (100ms) offset that accounts for a 179 * too short power-cycle delay due to the asynchronous programming of 180 * the register. 181 */ 182 if (val) 183 val--; 184 /* Convert from 100ms to 100us units */ 185 pps->delays.power_cycle = val * 1000; 186 187 if (DISPLAY_VER(dev_priv) < 5 && 188 pps->delays.power_up == 0 && 189 pps->delays.backlight_on == 0 && 190 pps->delays.power_down == 0 && 191 pps->delays.backlight_off == 0) { 192 drm_dbg_kms(&dev_priv->drm, 193 "Panel power timings uninitialized, " 194 "setting defaults\n"); 195 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 196 pps->delays.power_up = 40 * 10; 197 pps->delays.backlight_on = 200 * 10; 198 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 199 pps->delays.power_down = 35 * 10; 200 pps->delays.backlight_off = 200 * 10; 201 } 202 203 drm_dbg(&dev_priv->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d " 204 "divider %d port %d powerdown_on_reset %d\n", 205 pps->delays.power_up, pps->delays.power_down, 206 pps->delays.power_cycle, pps->delays.backlight_on, 207 pps->delays.backlight_off, pps->divider, 208 pps->port, pps->powerdown_on_reset); 209 } 210 211 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 212 struct intel_lvds_pps *pps) 213 { 214 u32 val; 215 216 val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)); 217 drm_WARN_ON(&dev_priv->drm, 218 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 219 if (pps->powerdown_on_reset) 220 val |= PANEL_POWER_RESET; 221 intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val); 222 223 intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0), 224 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | 225 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) | 226 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on)); 227 228 intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0), 229 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) | 230 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off)); 231 232 intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0), 233 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | 234 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, 235 DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1)); 236 } 237 238 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 239 struct intel_encoder *encoder, 240 const struct intel_crtc_state *crtc_state, 241 const struct drm_connector_state *conn_state) 242 { 243 struct intel_display *display = to_intel_display(state); 244 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 245 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 246 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 247 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 248 enum pipe pipe = crtc->pipe; 249 u32 temp; 250 251 if (HAS_PCH_SPLIT(i915)) { 252 assert_fdi_rx_pll_disabled(display, pipe); 253 assert_shared_dpll_disabled(display, crtc_state->shared_dpll); 254 } else { 255 assert_pll_disabled(display, pipe); 256 } 257 258 intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps); 259 260 temp = lvds_encoder->init_lvds_val; 261 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 262 263 if (HAS_PCH_CPT(i915)) { 264 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 265 temp |= LVDS_PIPE_SEL_CPT(pipe); 266 } else { 267 temp &= ~LVDS_PIPE_SEL_MASK; 268 temp |= LVDS_PIPE_SEL(pipe); 269 } 270 271 /* set the corresponding LVDS_BORDER bit */ 272 temp &= ~LVDS_BORDER_ENABLE; 273 temp |= crtc_state->gmch_pfit.lvds_border_bits; 274 275 /* 276 * Set the B0-B3 data pairs corresponding to whether we're going to 277 * set the DPLLs for dual-channel mode or not. 278 */ 279 if (lvds_encoder->is_dual_link) 280 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 281 else 282 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 283 284 /* 285 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 286 * appropriately here, but we need to look more thoroughly into how 287 * panels behave in the two modes. For now, let's just maintain the 288 * value we got from the BIOS. 289 */ 290 temp &= ~LVDS_A3_POWER_MASK; 291 temp |= lvds_encoder->a3_power; 292 293 /* 294 * Set the dithering flag on LVDS as needed, note that there is no 295 * special lvds dither control bit on pch-split platforms, dithering is 296 * only controlled through the TRANSCONF reg. 297 */ 298 if (DISPLAY_VER(i915) == 4) { 299 /* 300 * Bspec wording suggests that LVDS port dithering only exists 301 * for 18bpp panels. 302 */ 303 if (crtc_state->dither && crtc_state->pipe_bpp == 18) 304 temp |= LVDS_ENABLE_DITHER; 305 else 306 temp &= ~LVDS_ENABLE_DITHER; 307 } 308 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 309 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 310 temp |= LVDS_HSYNC_POLARITY; 311 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 312 temp |= LVDS_VSYNC_POLARITY; 313 314 intel_de_write(i915, lvds_encoder->reg, temp); 315 } 316 317 /* 318 * Sets the power state for the panel. 319 */ 320 static void intel_enable_lvds(struct intel_atomic_state *state, 321 struct intel_encoder *encoder, 322 const struct intel_crtc_state *crtc_state, 323 const struct drm_connector_state *conn_state) 324 { 325 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 327 328 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); 329 330 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON); 331 intel_de_posting_read(dev_priv, lvds_encoder->reg); 332 333 if (intel_de_wait_for_set(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 5000)) 334 drm_err(&dev_priv->drm, 335 "timed out waiting for panel to power on\n"); 336 337 intel_backlight_enable(crtc_state, conn_state); 338 } 339 340 static void intel_disable_lvds(struct intel_atomic_state *state, 341 struct intel_encoder *encoder, 342 const struct intel_crtc_state *old_crtc_state, 343 const struct drm_connector_state *old_conn_state) 344 { 345 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 346 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 347 348 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0); 349 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 1000)) 350 drm_err(&dev_priv->drm, 351 "timed out waiting for panel to power off\n"); 352 353 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); 354 intel_de_posting_read(dev_priv, lvds_encoder->reg); 355 } 356 357 static void gmch_disable_lvds(struct intel_atomic_state *state, 358 struct intel_encoder *encoder, 359 const struct intel_crtc_state *old_crtc_state, 360 const struct drm_connector_state *old_conn_state) 361 362 { 363 intel_backlight_disable(old_conn_state); 364 365 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 366 } 367 368 static void pch_disable_lvds(struct intel_atomic_state *state, 369 struct intel_encoder *encoder, 370 const struct intel_crtc_state *old_crtc_state, 371 const struct drm_connector_state *old_conn_state) 372 { 373 intel_backlight_disable(old_conn_state); 374 } 375 376 static void pch_post_disable_lvds(struct intel_atomic_state *state, 377 struct intel_encoder *encoder, 378 const struct intel_crtc_state *old_crtc_state, 379 const struct drm_connector_state *old_conn_state) 380 { 381 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 382 } 383 384 static void intel_lvds_shutdown(struct intel_encoder *encoder) 385 { 386 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 387 388 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_CYCLE_DELAY_ACTIVE, 5000)) 389 drm_err(&dev_priv->drm, 390 "timed out waiting for panel power cycle delay\n"); 391 } 392 393 static enum drm_mode_status 394 intel_lvds_mode_valid(struct drm_connector *_connector, 395 const struct drm_display_mode *mode) 396 { 397 struct intel_display *display = to_intel_display(_connector->dev); 398 struct intel_connector *connector = to_intel_connector(_connector); 399 const struct drm_display_mode *fixed_mode = 400 intel_panel_fixed_mode(connector, mode); 401 int max_pixclk = display->cdclk.max_dotclk_freq; 402 enum drm_mode_status status; 403 404 status = intel_cpu_transcoder_mode_valid(display, mode); 405 if (status != MODE_OK) 406 return status; 407 408 status = intel_panel_mode_valid(connector, mode); 409 if (status != MODE_OK) 410 return status; 411 412 if (fixed_mode->clock > max_pixclk) 413 return MODE_CLOCK_HIGH; 414 415 return MODE_OK; 416 } 417 418 static int intel_lvds_compute_config(struct intel_encoder *encoder, 419 struct intel_crtc_state *crtc_state, 420 struct drm_connector_state *conn_state) 421 { 422 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 423 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 424 struct intel_connector *connector = lvds_encoder->attached_connector; 425 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 426 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 427 unsigned int lvds_bpp; 428 int ret; 429 430 /* Should never happen!! */ 431 if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) { 432 drm_err(&i915->drm, "Can't support LVDS on pipe A\n"); 433 return -EINVAL; 434 } 435 436 if (HAS_PCH_SPLIT(i915)) { 437 crtc_state->has_pch_encoder = true; 438 if (!intel_fdi_compute_pipe_bpp(crtc_state)) 439 return -EINVAL; 440 } 441 442 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 443 lvds_bpp = 8*3; 444 else 445 lvds_bpp = 6*3; 446 447 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ 448 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { 449 drm_dbg_kms(&i915->drm, 450 "forcing display bpp (was %d) to LVDS (%d)\n", 451 crtc_state->pipe_bpp, lvds_bpp); 452 crtc_state->pipe_bpp = lvds_bpp; 453 } 454 455 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 456 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 457 458 /* 459 * We have timings from the BIOS for the panel, put them in 460 * to the adjusted mode. The CRTC will be set up for this mode, 461 * with the panel scaling set up to source from the H/VDisplay 462 * of the original mode. 463 */ 464 ret = intel_panel_compute_config(connector, adjusted_mode); 465 if (ret) 466 return ret; 467 468 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 469 return -EINVAL; 470 471 ret = intel_panel_fitting(crtc_state, conn_state); 472 if (ret) 473 return ret; 474 475 /* 476 * XXX: It would be nice to support lower refresh rates on the 477 * panels to reduce power consumption, and perhaps match the 478 * user's requested refresh rate. 479 */ 480 481 return 0; 482 } 483 484 /* 485 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 486 */ 487 static int intel_lvds_get_modes(struct drm_connector *_connector) 488 { 489 struct intel_connector *connector = to_intel_connector(_connector); 490 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 491 492 /* Use panel fixed edid if we have one */ 493 if (!IS_ERR_OR_NULL(fixed_edid)) { 494 drm_edid_connector_update(&connector->base, fixed_edid); 495 496 return drm_edid_connector_add_modes(&connector->base); 497 } 498 499 return intel_panel_get_modes(connector); 500 } 501 502 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 503 .get_modes = intel_lvds_get_modes, 504 .mode_valid = intel_lvds_mode_valid, 505 .atomic_check = intel_digital_connector_atomic_check, 506 }; 507 508 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 509 .detect = intel_panel_detect, 510 .fill_modes = drm_helper_probe_single_connector_modes, 511 .atomic_get_property = intel_digital_connector_atomic_get_property, 512 .atomic_set_property = intel_digital_connector_atomic_set_property, 513 .late_register = intel_connector_register, 514 .early_unregister = intel_connector_unregister, 515 .destroy = intel_connector_destroy, 516 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 517 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 518 }; 519 520 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 521 .destroy = intel_encoder_destroy, 522 }; 523 524 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 525 { 526 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 527 return 1; 528 } 529 530 /* These systems claim to have LVDS, but really don't */ 531 static const struct dmi_system_id intel_no_lvds[] = { 532 { 533 .callback = intel_no_lvds_dmi_callback, 534 .ident = "Apple Mac Mini (Core series)", 535 .matches = { 536 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 537 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 538 }, 539 }, 540 { 541 .callback = intel_no_lvds_dmi_callback, 542 .ident = "Apple Mac Mini (Core 2 series)", 543 .matches = { 544 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 545 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 546 }, 547 }, 548 { 549 .callback = intel_no_lvds_dmi_callback, 550 .ident = "MSI IM-945GSE-A", 551 .matches = { 552 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 553 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 554 }, 555 }, 556 { 557 .callback = intel_no_lvds_dmi_callback, 558 .ident = "Dell Studio Hybrid", 559 .matches = { 560 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 561 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 562 }, 563 }, 564 { 565 .callback = intel_no_lvds_dmi_callback, 566 .ident = "Dell OptiPlex FX170", 567 .matches = { 568 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 569 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 570 }, 571 }, 572 { 573 .callback = intel_no_lvds_dmi_callback, 574 .ident = "AOpen Mini PC", 575 .matches = { 576 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 577 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 578 }, 579 }, 580 { 581 .callback = intel_no_lvds_dmi_callback, 582 .ident = "AOpen Mini PC MP915", 583 .matches = { 584 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 585 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 586 }, 587 }, 588 { 589 .callback = intel_no_lvds_dmi_callback, 590 .ident = "AOpen i915GMm-HFS", 591 .matches = { 592 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 593 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 594 }, 595 }, 596 { 597 .callback = intel_no_lvds_dmi_callback, 598 .ident = "AOpen i45GMx-I", 599 .matches = { 600 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 601 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 602 }, 603 }, 604 { 605 .callback = intel_no_lvds_dmi_callback, 606 .ident = "Aopen i945GTt-VFA", 607 .matches = { 608 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 609 }, 610 }, 611 { 612 .callback = intel_no_lvds_dmi_callback, 613 .ident = "Clientron U800", 614 .matches = { 615 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 616 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 617 }, 618 }, 619 { 620 .callback = intel_no_lvds_dmi_callback, 621 .ident = "Clientron E830", 622 .matches = { 623 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 624 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 625 }, 626 }, 627 { 628 .callback = intel_no_lvds_dmi_callback, 629 .ident = "Asus EeeBox PC EB1007", 630 .matches = { 631 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 632 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 633 }, 634 }, 635 { 636 .callback = intel_no_lvds_dmi_callback, 637 .ident = "Asus AT5NM10T-I", 638 .matches = { 639 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 640 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 641 }, 642 }, 643 { 644 .callback = intel_no_lvds_dmi_callback, 645 .ident = "Hewlett-Packard HP t5740", 646 .matches = { 647 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 648 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 649 }, 650 }, 651 { 652 .callback = intel_no_lvds_dmi_callback, 653 .ident = "Hewlett-Packard t5745", 654 .matches = { 655 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 656 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 657 }, 658 }, 659 { 660 .callback = intel_no_lvds_dmi_callback, 661 .ident = "Hewlett-Packard st5747", 662 .matches = { 663 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 664 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 665 }, 666 }, 667 { 668 .callback = intel_no_lvds_dmi_callback, 669 .ident = "MSI Wind Box DC500", 670 .matches = { 671 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 672 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 673 }, 674 }, 675 { 676 .callback = intel_no_lvds_dmi_callback, 677 .ident = "Gigabyte GA-D525TUD", 678 .matches = { 679 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 680 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 681 }, 682 }, 683 { 684 .callback = intel_no_lvds_dmi_callback, 685 .ident = "Supermicro X7SPA-H", 686 .matches = { 687 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 688 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 689 }, 690 }, 691 { 692 .callback = intel_no_lvds_dmi_callback, 693 .ident = "Fujitsu Esprimo Q900", 694 .matches = { 695 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 696 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 697 }, 698 }, 699 { 700 .callback = intel_no_lvds_dmi_callback, 701 .ident = "Intel D410PT", 702 .matches = { 703 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 704 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 705 }, 706 }, 707 { 708 .callback = intel_no_lvds_dmi_callback, 709 .ident = "Intel D425KT", 710 .matches = { 711 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 712 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 713 }, 714 }, 715 { 716 .callback = intel_no_lvds_dmi_callback, 717 .ident = "Intel D510MO", 718 .matches = { 719 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 720 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 721 }, 722 }, 723 { 724 .callback = intel_no_lvds_dmi_callback, 725 .ident = "Intel D525MW", 726 .matches = { 727 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 728 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 729 }, 730 }, 731 { 732 .callback = intel_no_lvds_dmi_callback, 733 .ident = "Radiant P845", 734 .matches = { 735 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 736 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 737 }, 738 }, 739 740 { } /* terminating entry */ 741 }; 742 743 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 744 { 745 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 746 return 1; 747 } 748 749 static const struct dmi_system_id intel_dual_link_lvds[] = { 750 { 751 .callback = intel_dual_link_lvds_callback, 752 .ident = "Apple MacBook Pro 15\" (2010)", 753 .matches = { 754 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 755 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 756 }, 757 }, 758 { 759 .callback = intel_dual_link_lvds_callback, 760 .ident = "Apple MacBook Pro 15\" (2011)", 761 .matches = { 762 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 763 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 764 }, 765 }, 766 { 767 .callback = intel_dual_link_lvds_callback, 768 .ident = "Apple MacBook Pro 15\" (2012)", 769 .matches = { 770 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 771 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 772 }, 773 }, 774 { } /* terminating entry */ 775 }; 776 777 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915) 778 { 779 struct intel_encoder *encoder; 780 781 for_each_intel_encoder(&i915->drm, encoder) { 782 if (encoder->type == INTEL_OUTPUT_LVDS) 783 return encoder; 784 } 785 786 return NULL; 787 } 788 789 bool intel_is_dual_link_lvds(struct drm_i915_private *i915) 790 { 791 struct intel_encoder *encoder = intel_get_lvds_encoder(i915); 792 793 return encoder && to_lvds_encoder(encoder)->is_dual_link; 794 } 795 796 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 797 { 798 struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev); 799 struct intel_connector *connector = lvds_encoder->attached_connector; 800 const struct drm_display_mode *fixed_mode = 801 intel_panel_preferred_fixed_mode(connector); 802 unsigned int val; 803 804 /* use the module option value if specified */ 805 if (i915->display.params.lvds_channel_mode > 0) 806 return i915->display.params.lvds_channel_mode == 2; 807 808 /* single channel LVDS is limited to 112 MHz */ 809 if (fixed_mode->clock > 112999) 810 return true; 811 812 if (dmi_check_system(intel_dual_link_lvds)) 813 return true; 814 815 /* 816 * BIOS should set the proper LVDS register value at boot, but 817 * in reality, it doesn't set the value when the lid is closed; 818 * we need to check "the value to be set" in VBT when LVDS 819 * register is uninitialized. 820 */ 821 val = intel_de_read(i915, lvds_encoder->reg); 822 if (HAS_PCH_CPT(i915)) 823 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 824 else 825 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 826 if (val == 0) 827 val = connector->panel.vbt.bios_lvds_val; 828 829 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 830 } 831 832 static void intel_lvds_add_properties(struct drm_connector *connector) 833 { 834 intel_attach_scaling_mode_property(connector); 835 } 836 837 /** 838 * intel_lvds_init - setup LVDS connectors on this device 839 * @i915: i915 device 840 * 841 * Create the connector, register the LVDS DDC bus, and try to figure out what 842 * modes we can display on the LVDS panel (if present). 843 */ 844 void intel_lvds_init(struct drm_i915_private *i915) 845 { 846 struct intel_display *display = &i915->display; 847 struct intel_lvds_encoder *lvds_encoder; 848 struct intel_connector *connector; 849 const struct drm_edid *drm_edid; 850 struct intel_encoder *encoder; 851 i915_reg_t lvds_reg; 852 u32 lvds; 853 u8 ddc_pin; 854 855 /* Skip init on machines we know falsely report LVDS */ 856 if (dmi_check_system(intel_no_lvds)) { 857 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support, 858 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 859 return; 860 } 861 862 if (!i915->display.vbt.int_lvds_support) { 863 drm_dbg_kms(&i915->drm, 864 "Internal LVDS support disabled by VBT\n"); 865 return; 866 } 867 868 if (HAS_PCH_SPLIT(i915)) 869 lvds_reg = PCH_LVDS; 870 else 871 lvds_reg = LVDS; 872 873 lvds = intel_de_read(i915, lvds_reg); 874 875 if (HAS_PCH_SPLIT(i915)) { 876 if ((lvds & LVDS_DETECTED) == 0) 877 return; 878 } 879 880 ddc_pin = GMBUS_PIN_PANEL; 881 if (!intel_bios_is_lvds_present(display, &ddc_pin)) { 882 if ((lvds & LVDS_PORT_EN) == 0) { 883 drm_dbg_kms(&i915->drm, 884 "LVDS is not present in VBT\n"); 885 return; 886 } 887 drm_dbg_kms(&i915->drm, 888 "LVDS is not present in VBT, but enabled anyway\n"); 889 } 890 891 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 892 if (!lvds_encoder) 893 return; 894 895 connector = intel_connector_alloc(); 896 if (!connector) { 897 kfree(lvds_encoder); 898 return; 899 } 900 901 lvds_encoder->attached_connector = connector; 902 encoder = &lvds_encoder->base; 903 904 drm_connector_init_with_ddc(&i915->drm, &connector->base, 905 &intel_lvds_connector_funcs, 906 DRM_MODE_CONNECTOR_LVDS, 907 intel_gmbus_get_adapter(display, ddc_pin)); 908 909 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs, 910 DRM_MODE_ENCODER_LVDS, "LVDS"); 911 912 encoder->enable = intel_enable_lvds; 913 encoder->pre_enable = intel_pre_enable_lvds; 914 encoder->compute_config = intel_lvds_compute_config; 915 if (HAS_PCH_SPLIT(i915)) { 916 encoder->disable = pch_disable_lvds; 917 encoder->post_disable = pch_post_disable_lvds; 918 } else { 919 encoder->disable = gmch_disable_lvds; 920 } 921 encoder->get_hw_state = intel_lvds_get_hw_state; 922 encoder->get_config = intel_lvds_get_config; 923 encoder->update_pipe = intel_backlight_update; 924 encoder->shutdown = intel_lvds_shutdown; 925 connector->get_hw_state = intel_connector_get_hw_state; 926 927 intel_connector_attach_encoder(connector, encoder); 928 929 encoder->type = INTEL_OUTPUT_LVDS; 930 encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 931 encoder->port = PORT_NONE; 932 encoder->cloneable = 0; 933 if (DISPLAY_VER(i915) < 4) 934 encoder->pipe_mask = BIT(PIPE_B); 935 else 936 encoder->pipe_mask = ~0; 937 938 drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs); 939 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; 940 941 lvds_encoder->reg = lvds_reg; 942 943 intel_lvds_add_properties(&connector->base); 944 945 intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps); 946 lvds_encoder->init_lvds_val = lvds; 947 948 /* 949 * LVDS discovery: 950 * 1) check for EDID on DDC 951 * 2) check for VBT data 952 * 3) check to see if LVDS is already on 953 * if none of the above, no panel 954 */ 955 956 /* 957 * Attempt to get the fixed panel mode from DDC. Assume that the 958 * preferred mode is the right one. 959 */ 960 mutex_lock(&i915->drm.mode_config.mutex); 961 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 962 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc); 963 else 964 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 965 if (drm_edid) { 966 if (drm_edid_connector_update(&connector->base, drm_edid) || 967 !drm_edid_connector_add_modes(&connector->base)) { 968 drm_edid_connector_update(&connector->base, NULL); 969 drm_edid_free(drm_edid); 970 drm_edid = ERR_PTR(-EINVAL); 971 } 972 } else { 973 drm_edid = ERR_PTR(-ENOENT); 974 } 975 intel_bios_init_panel_late(display, &connector->panel, NULL, 976 IS_ERR(drm_edid) ? NULL : drm_edid); 977 978 /* Try EDID first */ 979 intel_panel_add_edid_fixed_modes(connector, true); 980 981 /* Failed to get EDID, what about VBT? */ 982 if (!intel_panel_preferred_fixed_mode(connector)) 983 intel_panel_add_vbt_lfp_fixed_mode(connector); 984 985 /* 986 * If we didn't get a fixed mode from EDID or VBT, try checking 987 * if the panel is already turned on. If so, assume that 988 * whatever is currently programmed is the correct mode. 989 */ 990 if (!intel_panel_preferred_fixed_mode(connector)) 991 intel_panel_add_encoder_fixed_mode(connector, encoder); 992 993 mutex_unlock(&i915->drm.mode_config.mutex); 994 995 /* If we still don't have a mode after all that, give up. */ 996 if (!intel_panel_preferred_fixed_mode(connector)) 997 goto failed; 998 999 intel_panel_init(connector, drm_edid); 1000 1001 intel_backlight_setup(connector, INVALID_PIPE); 1002 1003 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1004 drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n", 1005 lvds_encoder->is_dual_link ? "dual" : "single"); 1006 1007 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1008 1009 return; 1010 1011 failed: 1012 drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n"); 1013 drm_connector_cleanup(&connector->base); 1014 drm_encoder_cleanup(&encoder->base); 1015 kfree(lvds_encoder); 1016 intel_connector_free(connector); 1017 return; 1018 } 1019