1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/drm_fixed.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "intel_atomic.h" 13 #include "intel_crtc.h" 14 #include "intel_ddi.h" 15 #include "intel_de.h" 16 #include "intel_dp.h" 17 #include "intel_display_types.h" 18 #include "intel_fdi.h" 19 #include "intel_fdi_regs.h" 20 #include "intel_link_bw.h" 21 22 struct intel_fdi_funcs { 23 void (*fdi_link_train)(struct intel_crtc *crtc, 24 const struct intel_crtc_state *crtc_state); 25 }; 26 27 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 28 enum pipe pipe, bool state) 29 { 30 struct intel_display *display = &dev_priv->display; 31 bool cur_state; 32 33 if (HAS_DDI(display)) { 34 /* 35 * DDI does not have a specific FDI_TX register. 36 * 37 * FDI is never fed from EDP transcoder 38 * so pipe->transcoder cast is fine here. 39 */ 40 enum transcoder cpu_transcoder = (enum transcoder)pipe; 41 cur_state = intel_de_read(display, 42 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; 43 } else { 44 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; 45 } 46 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 47 "FDI TX state assertion failure (expected %s, current %s)\n", 48 str_on_off(state), str_on_off(cur_state)); 49 } 50 51 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe) 52 { 53 assert_fdi_tx(i915, pipe, true); 54 } 55 56 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe) 57 { 58 assert_fdi_tx(i915, pipe, false); 59 } 60 61 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 62 enum pipe pipe, bool state) 63 { 64 struct intel_display *display = &dev_priv->display; 65 bool cur_state; 66 67 cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; 68 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 69 "FDI RX state assertion failure (expected %s, current %s)\n", 70 str_on_off(state), str_on_off(cur_state)); 71 } 72 73 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe) 74 { 75 assert_fdi_rx(i915, pipe, true); 76 } 77 78 void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe) 79 { 80 assert_fdi_rx(i915, pipe, false); 81 } 82 83 void assert_fdi_tx_pll_enabled(struct intel_display *display, 84 enum pipe pipe) 85 { 86 bool cur_state; 87 88 /* ILK FDI PLL is always enabled */ 89 if (display->platform.ironlake) 90 return; 91 92 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 93 if (HAS_DDI(display)) 94 return; 95 96 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; 97 INTEL_DISPLAY_STATE_WARN(display, !cur_state, 98 "FDI TX PLL assertion failure, should be active but is disabled\n"); 99 } 100 101 static void assert_fdi_rx_pll(struct intel_display *display, 102 enum pipe pipe, bool state) 103 { 104 bool cur_state; 105 106 cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; 107 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 108 "FDI RX PLL assertion failure (expected %s, current %s)\n", 109 str_on_off(state), str_on_off(cur_state)); 110 } 111 112 void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe) 113 { 114 assert_fdi_rx_pll(display, pipe, true); 115 } 116 117 void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe) 118 { 119 assert_fdi_rx_pll(display, pipe, false); 120 } 121 122 void intel_fdi_link_train(struct intel_crtc *crtc, 123 const struct intel_crtc_state *crtc_state) 124 { 125 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 126 127 dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state); 128 } 129 130 /** 131 * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs 132 * @state: intel atomic state 133 * 134 * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is 135 * known to affect the available FDI BW for the former CRTC. In practice this 136 * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by 137 * CRTC C) and CRTC C is getting disabled. 138 * 139 * Returns 0 in case of success, or a negative error code otherwise. 140 */ 141 int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state) 142 { 143 struct intel_display *display = to_intel_display(state); 144 struct drm_i915_private *i915 = to_i915(state->base.dev); 145 const struct intel_crtc_state *old_crtc_state; 146 const struct intel_crtc_state *new_crtc_state; 147 struct intel_crtc *crtc; 148 149 if (!IS_IVYBRIDGE(i915) || INTEL_NUM_PIPES(i915) != 3) 150 return 0; 151 152 crtc = intel_crtc_for_pipe(display, PIPE_C); 153 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 154 if (!new_crtc_state) 155 return 0; 156 157 if (!intel_crtc_needs_modeset(new_crtc_state)) 158 return 0; 159 160 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 161 if (!old_crtc_state->fdi_lanes) 162 return 0; 163 164 crtc = intel_crtc_for_pipe(display, PIPE_B); 165 new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 166 if (IS_ERR(new_crtc_state)) 167 return PTR_ERR(new_crtc_state); 168 169 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 170 if (!old_crtc_state->fdi_lanes) 171 return 0; 172 173 return intel_modeset_pipes_in_mask_early(state, 174 "FDI link BW decrease on pipe C", 175 BIT(PIPE_B)); 176 } 177 178 /* units of 100MHz */ 179 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) 180 { 181 if (crtc_state->hw.enable && crtc_state->has_pch_encoder) 182 return crtc_state->fdi_lanes; 183 184 return 0; 185 } 186 187 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, 188 struct intel_crtc_state *pipe_config, 189 enum pipe *pipe_to_reduce) 190 { 191 struct intel_display *display = to_intel_display(dev); 192 struct drm_i915_private *dev_priv = to_i915(dev); 193 struct drm_atomic_state *state = pipe_config->uapi.state; 194 struct intel_crtc *other_crtc; 195 struct intel_crtc_state *other_crtc_state; 196 197 *pipe_to_reduce = pipe; 198 199 drm_dbg_kms(&dev_priv->drm, 200 "checking fdi config on pipe %c, lanes %i\n", 201 pipe_name(pipe), pipe_config->fdi_lanes); 202 if (pipe_config->fdi_lanes > 4) { 203 drm_dbg_kms(&dev_priv->drm, 204 "invalid fdi lane config on pipe %c: %i lanes\n", 205 pipe_name(pipe), pipe_config->fdi_lanes); 206 return -EINVAL; 207 } 208 209 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 210 if (pipe_config->fdi_lanes > 2) { 211 drm_dbg_kms(&dev_priv->drm, 212 "only 2 lanes on haswell, required: %i lanes\n", 213 pipe_config->fdi_lanes); 214 return -EINVAL; 215 } else { 216 return 0; 217 } 218 } 219 220 if (INTEL_NUM_PIPES(dev_priv) == 2) 221 return 0; 222 223 /* Ivybridge 3 pipe is really complicated */ 224 switch (pipe) { 225 case PIPE_A: 226 return 0; 227 case PIPE_B: 228 if (pipe_config->fdi_lanes <= 2) 229 return 0; 230 231 other_crtc = intel_crtc_for_pipe(display, PIPE_C); 232 other_crtc_state = 233 intel_atomic_get_crtc_state(state, other_crtc); 234 if (IS_ERR(other_crtc_state)) 235 return PTR_ERR(other_crtc_state); 236 237 if (pipe_required_fdi_lanes(other_crtc_state) > 0) { 238 drm_dbg_kms(&dev_priv->drm, 239 "invalid shared fdi lane config on pipe %c: %i lanes\n", 240 pipe_name(pipe), pipe_config->fdi_lanes); 241 return -EINVAL; 242 } 243 return 0; 244 case PIPE_C: 245 if (pipe_config->fdi_lanes > 2) { 246 drm_dbg_kms(&dev_priv->drm, 247 "only 2 lanes on pipe %c: required %i lanes\n", 248 pipe_name(pipe), pipe_config->fdi_lanes); 249 return -EINVAL; 250 } 251 252 other_crtc = intel_crtc_for_pipe(display, PIPE_B); 253 other_crtc_state = 254 intel_atomic_get_crtc_state(state, other_crtc); 255 if (IS_ERR(other_crtc_state)) 256 return PTR_ERR(other_crtc_state); 257 258 if (pipe_required_fdi_lanes(other_crtc_state) > 2) { 259 drm_dbg_kms(&dev_priv->drm, 260 "fdi link B uses too many lanes to enable link C\n"); 261 262 *pipe_to_reduce = PIPE_B; 263 264 return -EINVAL; 265 } 266 return 0; 267 default: 268 MISSING_CASE(pipe); 269 return 0; 270 } 271 } 272 273 void intel_fdi_pll_freq_update(struct drm_i915_private *i915) 274 { 275 if (IS_IRONLAKE(i915)) { 276 u32 fdi_pll_clk = 277 intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; 278 279 i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 10000; 280 } else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) { 281 i915->display.fdi.pll_freq = 270000; 282 } else { 283 return; 284 } 285 286 drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq); 287 } 288 289 int intel_fdi_link_freq(struct drm_i915_private *i915, 290 const struct intel_crtc_state *pipe_config) 291 { 292 if (HAS_DDI(i915)) 293 return pipe_config->port_clock; /* SPLL */ 294 else 295 return i915->display.fdi.pll_freq; 296 } 297 298 /** 299 * intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp 300 * @crtc_state: the crtc state 301 * 302 * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can 303 * call this function during state computation in the simple case where the 304 * link bpp will always match the pipe bpp. This is the case for all non-DP 305 * encoders, while DP encoders will use a link bpp lower than pipe bpp in case 306 * of DSC compression. 307 * 308 * Returns %true in case of success, %false if pipe bpp would need to be 309 * reduced below its valid range. 310 */ 311 bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state) 312 { 313 int pipe_bpp = min(crtc_state->pipe_bpp, 314 fxp_q4_to_int(crtc_state->max_link_bpp_x16)); 315 316 pipe_bpp = rounddown(pipe_bpp, 2 * 3); 317 318 if (pipe_bpp < 6 * 3) 319 return false; 320 321 crtc_state->pipe_bpp = pipe_bpp; 322 323 return true; 324 } 325 326 int ilk_fdi_compute_config(struct intel_crtc *crtc, 327 struct intel_crtc_state *pipe_config) 328 { 329 struct drm_device *dev = crtc->base.dev; 330 struct drm_i915_private *i915 = to_i915(dev); 331 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 332 int lane, link_bw, fdi_dotclock; 333 334 /* FDI is a binary signal running at ~2.7GHz, encoding 335 * each output octet as 10 bits. The actual frequency 336 * is stored as a divider into a 100MHz clock, and the 337 * mode pixel clock is stored in units of 1KHz. 338 * Hence the bw of each lane in terms of the mode signal 339 * is: 340 */ 341 link_bw = intel_fdi_link_freq(i915, pipe_config); 342 343 fdi_dotclock = adjusted_mode->crtc_clock; 344 345 lane = ilk_get_lanes_required(fdi_dotclock, link_bw, 346 pipe_config->pipe_bpp); 347 348 pipe_config->fdi_lanes = lane; 349 350 intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), 351 lane, fdi_dotclock, 352 link_bw, 353 intel_dp_bw_fec_overhead(false), 354 &pipe_config->fdi_m_n); 355 356 return 0; 357 } 358 359 static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state, 360 struct intel_crtc *crtc, 361 struct intel_crtc_state *pipe_config, 362 struct intel_link_bw_limits *limits) 363 { 364 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 365 enum pipe pipe_to_reduce; 366 int ret; 367 368 ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config, 369 &pipe_to_reduce); 370 if (ret != -EINVAL) 371 return ret; 372 373 ret = intel_link_bw_reduce_bpp(state, limits, 374 BIT(pipe_to_reduce), 375 "FDI link BW"); 376 377 return ret ? : -EAGAIN; 378 } 379 380 /** 381 * intel_fdi_atomic_check_link - check all modeset FDI link configuration 382 * @state: intel atomic state 383 * @limits: link BW limits 384 * 385 * Check the link configuration for all modeset FDI outputs. If the 386 * configuration is invalid @limits will be updated if possible to 387 * reduce the total BW, after which the configuration for all CRTCs in 388 * @state must be recomputed with the updated @limits. 389 * 390 * Returns: 391 * - 0 if the configuration is valid 392 * - %-EAGAIN, if the configuration is invalid and @limits got updated 393 * with fallback values with which the configuration of all CRTCs 394 * in @state must be recomputed 395 * - Other negative error, if the configuration is invalid without a 396 * fallback possibility, or the check failed for another reason 397 */ 398 int intel_fdi_atomic_check_link(struct intel_atomic_state *state, 399 struct intel_link_bw_limits *limits) 400 { 401 struct intel_crtc *crtc; 402 struct intel_crtc_state *crtc_state; 403 int i; 404 405 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 406 int ret; 407 408 if (!crtc_state->has_pch_encoder || 409 !intel_crtc_needs_modeset(crtc_state) || 410 !crtc_state->hw.enable) 411 continue; 412 413 ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits); 414 if (ret) 415 return ret; 416 } 417 418 return 0; 419 } 420 421 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) 422 { 423 u32 temp; 424 425 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); 426 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) 427 return; 428 429 drm_WARN_ON(&dev_priv->drm, 430 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & 431 FDI_RX_ENABLE); 432 drm_WARN_ON(&dev_priv->drm, 433 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & 434 FDI_RX_ENABLE); 435 436 temp &= ~FDI_BC_BIFURCATION_SELECT; 437 if (enable) 438 temp |= FDI_BC_BIFURCATION_SELECT; 439 440 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n", 441 enable ? "en" : "dis"); 442 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); 443 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); 444 } 445 446 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) 447 { 448 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 450 451 switch (crtc->pipe) { 452 case PIPE_A: 453 break; 454 case PIPE_B: 455 if (crtc_state->fdi_lanes > 2) 456 cpt_set_fdi_bc_bifurcation(dev_priv, false); 457 else 458 cpt_set_fdi_bc_bifurcation(dev_priv, true); 459 460 break; 461 case PIPE_C: 462 cpt_set_fdi_bc_bifurcation(dev_priv, true); 463 464 break; 465 default: 466 MISSING_CASE(crtc->pipe); 467 } 468 } 469 470 void intel_fdi_normal_train(struct intel_crtc *crtc) 471 { 472 struct drm_device *dev = crtc->base.dev; 473 struct drm_i915_private *dev_priv = to_i915(dev); 474 enum pipe pipe = crtc->pipe; 475 i915_reg_t reg; 476 u32 temp; 477 478 /* enable normal train */ 479 reg = FDI_TX_CTL(pipe); 480 temp = intel_de_read(dev_priv, reg); 481 if (IS_IVYBRIDGE(dev_priv)) { 482 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 483 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 484 } else { 485 temp &= ~FDI_LINK_TRAIN_NONE; 486 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 487 } 488 intel_de_write(dev_priv, reg, temp); 489 490 reg = FDI_RX_CTL(pipe); 491 temp = intel_de_read(dev_priv, reg); 492 if (HAS_PCH_CPT(dev_priv)) { 493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 494 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 495 } else { 496 temp &= ~FDI_LINK_TRAIN_NONE; 497 temp |= FDI_LINK_TRAIN_NONE; 498 } 499 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 500 501 /* wait one idle pattern time */ 502 intel_de_posting_read(dev_priv, reg); 503 udelay(1000); 504 505 /* IVB wants error correction enabled */ 506 if (IS_IVYBRIDGE(dev_priv)) 507 intel_de_rmw(dev_priv, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); 508 } 509 510 /* The FDI link training functions for ILK/Ibexpeak. */ 511 static void ilk_fdi_link_train(struct intel_crtc *crtc, 512 const struct intel_crtc_state *crtc_state) 513 { 514 struct intel_display *display = to_intel_display(crtc); 515 struct drm_device *dev = crtc->base.dev; 516 struct drm_i915_private *dev_priv = to_i915(dev); 517 enum pipe pipe = crtc->pipe; 518 i915_reg_t reg; 519 u32 temp, tries; 520 521 /* 522 * Write the TU size bits before fdi link training, so that error 523 * detection works. 524 */ 525 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), 526 intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); 527 528 /* FDI needs bits from pipe first */ 529 assert_transcoder_enabled(display, crtc_state->cpu_transcoder); 530 531 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 532 for train result */ 533 reg = FDI_RX_IMR(pipe); 534 temp = intel_de_read(dev_priv, reg); 535 temp &= ~FDI_RX_SYMBOL_LOCK; 536 temp &= ~FDI_RX_BIT_LOCK; 537 intel_de_write(dev_priv, reg, temp); 538 intel_de_read(dev_priv, reg); 539 udelay(150); 540 541 /* enable CPU FDI TX and PCH FDI RX */ 542 reg = FDI_TX_CTL(pipe); 543 temp = intel_de_read(dev_priv, reg); 544 temp &= ~FDI_DP_PORT_WIDTH_MASK; 545 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 546 temp &= ~FDI_LINK_TRAIN_NONE; 547 temp |= FDI_LINK_TRAIN_PATTERN_1; 548 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); 549 550 reg = FDI_RX_CTL(pipe); 551 temp = intel_de_read(dev_priv, reg); 552 temp &= ~FDI_LINK_TRAIN_NONE; 553 temp |= FDI_LINK_TRAIN_PATTERN_1; 554 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); 555 556 intel_de_posting_read(dev_priv, reg); 557 udelay(150); 558 559 /* Ironlake workaround, enable clock pointer after FDI enable*/ 560 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 561 FDI_RX_PHASE_SYNC_POINTER_OVR); 562 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 563 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); 564 565 reg = FDI_RX_IIR(pipe); 566 for (tries = 0; tries < 5; tries++) { 567 temp = intel_de_read(dev_priv, reg); 568 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 569 570 if ((temp & FDI_RX_BIT_LOCK)) { 571 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); 572 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); 573 break; 574 } 575 } 576 if (tries == 5) 577 drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); 578 579 /* Train 2 */ 580 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 581 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2); 582 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), 583 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2); 584 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); 585 udelay(150); 586 587 reg = FDI_RX_IIR(pipe); 588 for (tries = 0; tries < 5; tries++) { 589 temp = intel_de_read(dev_priv, reg); 590 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 591 592 if (temp & FDI_RX_SYMBOL_LOCK) { 593 intel_de_write(dev_priv, reg, 594 temp | FDI_RX_SYMBOL_LOCK); 595 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); 596 break; 597 } 598 } 599 if (tries == 5) 600 drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); 601 602 drm_dbg_kms(&dev_priv->drm, "FDI train done\n"); 603 604 } 605 606 static const int snb_b_fdi_train_param[] = { 607 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 608 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 609 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 610 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 611 }; 612 613 /* The FDI link training functions for SNB/Cougarpoint. */ 614 static void gen6_fdi_link_train(struct intel_crtc *crtc, 615 const struct intel_crtc_state *crtc_state) 616 { 617 struct drm_device *dev = crtc->base.dev; 618 struct drm_i915_private *dev_priv = to_i915(dev); 619 enum pipe pipe = crtc->pipe; 620 i915_reg_t reg; 621 u32 temp, i, retry; 622 623 /* 624 * Write the TU size bits before fdi link training, so that error 625 * detection works. 626 */ 627 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), 628 intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); 629 630 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 631 for train result */ 632 reg = FDI_RX_IMR(pipe); 633 temp = intel_de_read(dev_priv, reg); 634 temp &= ~FDI_RX_SYMBOL_LOCK; 635 temp &= ~FDI_RX_BIT_LOCK; 636 intel_de_write(dev_priv, reg, temp); 637 638 intel_de_posting_read(dev_priv, reg); 639 udelay(150); 640 641 /* enable CPU FDI TX and PCH FDI RX */ 642 reg = FDI_TX_CTL(pipe); 643 temp = intel_de_read(dev_priv, reg); 644 temp &= ~FDI_DP_PORT_WIDTH_MASK; 645 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 646 temp &= ~FDI_LINK_TRAIN_NONE; 647 temp |= FDI_LINK_TRAIN_PATTERN_1; 648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 649 /* SNB-B */ 650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 651 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); 652 653 intel_de_write(dev_priv, FDI_RX_MISC(pipe), 654 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 655 656 reg = FDI_RX_CTL(pipe); 657 temp = intel_de_read(dev_priv, reg); 658 if (HAS_PCH_CPT(dev_priv)) { 659 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 660 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 661 } else { 662 temp &= ~FDI_LINK_TRAIN_NONE; 663 temp |= FDI_LINK_TRAIN_PATTERN_1; 664 } 665 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); 666 667 intel_de_posting_read(dev_priv, reg); 668 udelay(150); 669 670 for (i = 0; i < 4; i++) { 671 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 672 FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]); 673 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 674 udelay(500); 675 676 for (retry = 0; retry < 5; retry++) { 677 reg = FDI_RX_IIR(pipe); 678 temp = intel_de_read(dev_priv, reg); 679 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 680 if (temp & FDI_RX_BIT_LOCK) { 681 intel_de_write(dev_priv, reg, 682 temp | FDI_RX_BIT_LOCK); 683 drm_dbg_kms(&dev_priv->drm, 684 "FDI train 1 done.\n"); 685 break; 686 } 687 udelay(50); 688 } 689 if (retry < 5) 690 break; 691 } 692 if (i == 4) 693 drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); 694 695 /* Train 2 */ 696 reg = FDI_TX_CTL(pipe); 697 temp = intel_de_read(dev_priv, reg); 698 temp &= ~FDI_LINK_TRAIN_NONE; 699 temp |= FDI_LINK_TRAIN_PATTERN_2; 700 if (IS_SANDYBRIDGE(dev_priv)) { 701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 702 /* SNB-B */ 703 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 704 } 705 intel_de_write(dev_priv, reg, temp); 706 707 reg = FDI_RX_CTL(pipe); 708 temp = intel_de_read(dev_priv, reg); 709 if (HAS_PCH_CPT(dev_priv)) { 710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 711 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 712 } else { 713 temp &= ~FDI_LINK_TRAIN_NONE; 714 temp |= FDI_LINK_TRAIN_PATTERN_2; 715 } 716 intel_de_write(dev_priv, reg, temp); 717 718 intel_de_posting_read(dev_priv, reg); 719 udelay(150); 720 721 for (i = 0; i < 4; i++) { 722 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 723 FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]); 724 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 725 udelay(500); 726 727 for (retry = 0; retry < 5; retry++) { 728 reg = FDI_RX_IIR(pipe); 729 temp = intel_de_read(dev_priv, reg); 730 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 731 if (temp & FDI_RX_SYMBOL_LOCK) { 732 intel_de_write(dev_priv, reg, 733 temp | FDI_RX_SYMBOL_LOCK); 734 drm_dbg_kms(&dev_priv->drm, 735 "FDI train 2 done.\n"); 736 break; 737 } 738 udelay(50); 739 } 740 if (retry < 5) 741 break; 742 } 743 if (i == 4) 744 drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); 745 746 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); 747 } 748 749 /* Manual link training for Ivy Bridge A0 parts */ 750 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, 751 const struct intel_crtc_state *crtc_state) 752 { 753 struct drm_device *dev = crtc->base.dev; 754 struct drm_i915_private *dev_priv = to_i915(dev); 755 enum pipe pipe = crtc->pipe; 756 i915_reg_t reg; 757 u32 temp, i, j; 758 759 ivb_update_fdi_bc_bifurcation(crtc_state); 760 761 /* 762 * Write the TU size bits before fdi link training, so that error 763 * detection works. 764 */ 765 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), 766 intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); 767 768 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 769 for train result */ 770 reg = FDI_RX_IMR(pipe); 771 temp = intel_de_read(dev_priv, reg); 772 temp &= ~FDI_RX_SYMBOL_LOCK; 773 temp &= ~FDI_RX_BIT_LOCK; 774 intel_de_write(dev_priv, reg, temp); 775 776 intel_de_posting_read(dev_priv, reg); 777 udelay(150); 778 779 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", 780 intel_de_read(dev_priv, FDI_RX_IIR(pipe))); 781 782 /* Try each vswing and preemphasis setting twice before moving on */ 783 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { 784 /* disable first in case we need to retry */ 785 reg = FDI_TX_CTL(pipe); 786 temp = intel_de_read(dev_priv, reg); 787 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 788 temp &= ~FDI_TX_ENABLE; 789 intel_de_write(dev_priv, reg, temp); 790 791 reg = FDI_RX_CTL(pipe); 792 temp = intel_de_read(dev_priv, reg); 793 temp &= ~FDI_LINK_TRAIN_AUTO; 794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 795 temp &= ~FDI_RX_ENABLE; 796 intel_de_write(dev_priv, reg, temp); 797 798 /* enable CPU FDI TX and PCH FDI RX */ 799 reg = FDI_TX_CTL(pipe); 800 temp = intel_de_read(dev_priv, reg); 801 temp &= ~FDI_DP_PORT_WIDTH_MASK; 802 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 803 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 804 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 805 temp |= snb_b_fdi_train_param[j/2]; 806 temp |= FDI_COMPOSITE_SYNC; 807 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); 808 809 intel_de_write(dev_priv, FDI_RX_MISC(pipe), 810 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 811 812 reg = FDI_RX_CTL(pipe); 813 temp = intel_de_read(dev_priv, reg); 814 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 815 temp |= FDI_COMPOSITE_SYNC; 816 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); 817 818 intel_de_posting_read(dev_priv, reg); 819 udelay(1); /* should be 0.5us */ 820 821 for (i = 0; i < 4; i++) { 822 reg = FDI_RX_IIR(pipe); 823 temp = intel_de_read(dev_priv, reg); 824 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 825 826 if (temp & FDI_RX_BIT_LOCK || 827 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) { 828 intel_de_write(dev_priv, reg, 829 temp | FDI_RX_BIT_LOCK); 830 drm_dbg_kms(&dev_priv->drm, 831 "FDI train 1 done, level %i.\n", 832 i); 833 break; 834 } 835 udelay(1); /* should be 0.5us */ 836 } 837 if (i == 4) { 838 drm_dbg_kms(&dev_priv->drm, 839 "FDI train 1 fail on vswing %d\n", j / 2); 840 continue; 841 } 842 843 /* Train 2 */ 844 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 845 FDI_LINK_TRAIN_NONE_IVB, 846 FDI_LINK_TRAIN_PATTERN_2_IVB); 847 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), 848 FDI_LINK_TRAIN_PATTERN_MASK_CPT, 849 FDI_LINK_TRAIN_PATTERN_2_CPT); 850 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); 851 udelay(2); /* should be 1.5us */ 852 853 for (i = 0; i < 4; i++) { 854 reg = FDI_RX_IIR(pipe); 855 temp = intel_de_read(dev_priv, reg); 856 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 857 858 if (temp & FDI_RX_SYMBOL_LOCK || 859 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) { 860 intel_de_write(dev_priv, reg, 861 temp | FDI_RX_SYMBOL_LOCK); 862 drm_dbg_kms(&dev_priv->drm, 863 "FDI train 2 done, level %i.\n", 864 i); 865 goto train_done; 866 } 867 udelay(2); /* should be 1.5us */ 868 } 869 if (i == 4) 870 drm_dbg_kms(&dev_priv->drm, 871 "FDI train 2 fail on vswing %d\n", j / 2); 872 } 873 874 train_done: 875 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); 876 } 877 878 /* Starting with Haswell, different DDI ports can work in FDI mode for 879 * connection to the PCH-located connectors. For this, it is necessary to train 880 * both the DDI port and PCH receiver for the desired DDI buffer settings. 881 * 882 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 883 * please note that when FDI mode is active on DDI E, it shares 2 lines with 884 * DDI A (which is used for eDP) 885 */ 886 void hsw_fdi_link_train(struct intel_encoder *encoder, 887 const struct intel_crtc_state *crtc_state) 888 { 889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 890 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 891 u32 temp, i, rx_ctl_val; 892 int n_entries; 893 894 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 895 896 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 897 898 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 899 * mode set "sequence for CRT port" document: 900 * - TP1 to TP2 time with the default value 901 * - FDI delay to 90h 902 * 903 * WaFDIAutoLinkSetTimingOverrride:hsw 904 */ 905 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 906 FDI_RX_PWRDN_LANE1_VAL(2) | 907 FDI_RX_PWRDN_LANE0_VAL(2) | 908 FDI_RX_TP1_TO_TP2_48 | 909 FDI_RX_FDI_DELAY_90); 910 911 /* Enable the PCH Receiver FDI PLL */ 912 rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 913 FDI_RX_PLL_ENABLE | 914 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 915 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 916 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 917 udelay(220); 918 919 /* Switch from Rawclk to PCDclk */ 920 rx_ctl_val |= FDI_PCDCLK; 921 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 922 923 /* Configure Port Clock Select */ 924 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); 925 intel_ddi_enable_clock(encoder, crtc_state); 926 927 /* Start the training iterating through available voltages and emphasis, 928 * testing each value twice. */ 929 for (i = 0; i < n_entries * 2; i++) { 930 /* Configure DP_TP_CTL with auto-training */ 931 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 932 DP_TP_CTL_FDI_AUTOTRAIN | 933 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 934 DP_TP_CTL_LINK_TRAIN_PAT1 | 935 DP_TP_CTL_ENABLE); 936 937 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 938 * DDI E does not support port reversal, the functionality is 939 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 940 * port reversal bit */ 941 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 942 DDI_BUF_CTL_ENABLE | 943 ((crtc_state->fdi_lanes - 1) << 1) | 944 DDI_BUF_TRANS_SELECT(i / 2)); 945 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 946 947 udelay(600); 948 949 /* Program PCH FDI Receiver TU */ 950 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 951 952 /* Enable PCH FDI Receiver with auto-training */ 953 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 954 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 955 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 956 957 /* Wait for FDI receiver lane calibration */ 958 udelay(30); 959 960 /* Unset FDI_RX_MISC pwrdn lanes */ 961 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), 962 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0); 963 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 964 965 /* Wait for FDI auto training time */ 966 udelay(5); 967 968 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 969 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 970 drm_dbg_kms(&dev_priv->drm, 971 "FDI link training done on step %d\n", i); 972 break; 973 } 974 975 /* 976 * Leave things enabled even if we failed to train FDI. 977 * Results in less fireworks from the state checker. 978 */ 979 if (i == n_entries * 2 - 1) { 980 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 981 break; 982 } 983 984 rx_ctl_val &= ~FDI_RX_ENABLE; 985 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 986 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 987 988 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); 989 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 990 991 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 992 intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); 993 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 994 995 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 996 997 /* Reset FDI_RX_MISC pwrdn lanes */ 998 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), 999 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 1000 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2)); 1001 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1002 } 1003 1004 /* Enable normal pixel sending for FDI */ 1005 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1006 DP_TP_CTL_FDI_AUTOTRAIN | 1007 DP_TP_CTL_LINK_TRAIN_NORMAL | 1008 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1009 DP_TP_CTL_ENABLE); 1010 } 1011 1012 void hsw_fdi_disable(struct intel_encoder *encoder) 1013 { 1014 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1015 1016 /* 1017 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 1018 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 1019 * step 13 is the correct place for it. Step 18 is where it was 1020 * originally before the BUN. 1021 */ 1022 intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0); 1023 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); 1024 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1025 intel_ddi_disable_clock(encoder); 1026 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), 1027 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 1028 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2)); 1029 intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0); 1030 intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0); 1031 } 1032 1033 void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) 1034 { 1035 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1037 enum pipe pipe = crtc->pipe; 1038 i915_reg_t reg; 1039 u32 temp; 1040 1041 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1042 reg = FDI_RX_CTL(pipe); 1043 temp = intel_de_read(dev_priv, reg); 1044 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); 1045 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1046 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; 1047 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); 1048 1049 intel_de_posting_read(dev_priv, reg); 1050 udelay(200); 1051 1052 /* Switch from Rawclk to PCDclk */ 1053 intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK); 1054 intel_de_posting_read(dev_priv, reg); 1055 udelay(200); 1056 1057 /* Enable CPU FDI TX PLL, always on for Ironlake */ 1058 reg = FDI_TX_CTL(pipe); 1059 temp = intel_de_read(dev_priv, reg); 1060 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 1061 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE); 1062 1063 intel_de_posting_read(dev_priv, reg); 1064 udelay(100); 1065 } 1066 } 1067 1068 void ilk_fdi_pll_disable(struct intel_crtc *crtc) 1069 { 1070 struct drm_device *dev = crtc->base.dev; 1071 struct drm_i915_private *dev_priv = to_i915(dev); 1072 enum pipe pipe = crtc->pipe; 1073 1074 /* Switch from PCDclk to Rawclk */ 1075 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0); 1076 1077 /* Disable CPU FDI TX PLL */ 1078 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0); 1079 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 1080 udelay(100); 1081 1082 /* Wait for the clocks to turn off. */ 1083 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0); 1084 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); 1085 udelay(100); 1086 } 1087 1088 void ilk_fdi_disable(struct intel_crtc *crtc) 1089 { 1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1091 enum pipe pipe = crtc->pipe; 1092 i915_reg_t reg; 1093 u32 temp; 1094 1095 /* disable CPU FDI tx and PCH FDI rx */ 1096 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0); 1097 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 1098 1099 reg = FDI_RX_CTL(pipe); 1100 temp = intel_de_read(dev_priv, reg); 1101 temp &= ~(0x7 << 16); 1102 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; 1103 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE); 1104 1105 intel_de_posting_read(dev_priv, reg); 1106 udelay(100); 1107 1108 /* Ironlake workaround, disable clock pointer after downing FDI */ 1109 if (HAS_PCH_IBX(dev_priv)) 1110 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 1111 FDI_RX_PHASE_SYNC_POINTER_OVR); 1112 1113 /* still set train pattern 1 */ 1114 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 1115 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1); 1116 1117 reg = FDI_RX_CTL(pipe); 1118 temp = intel_de_read(dev_priv, reg); 1119 if (HAS_PCH_CPT(dev_priv)) { 1120 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 1121 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 1122 } else { 1123 temp &= ~FDI_LINK_TRAIN_NONE; 1124 temp |= FDI_LINK_TRAIN_PATTERN_1; 1125 } 1126 /* BPC in FDI rx is consistent with that in TRANSCONF */ 1127 temp &= ~(0x07 << 16); 1128 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; 1129 intel_de_write(dev_priv, reg, temp); 1130 1131 intel_de_posting_read(dev_priv, reg); 1132 udelay(100); 1133 } 1134 1135 static const struct intel_fdi_funcs ilk_funcs = { 1136 .fdi_link_train = ilk_fdi_link_train, 1137 }; 1138 1139 static const struct intel_fdi_funcs gen6_funcs = { 1140 .fdi_link_train = gen6_fdi_link_train, 1141 }; 1142 1143 static const struct intel_fdi_funcs ivb_funcs = { 1144 .fdi_link_train = ivb_manual_fdi_link_train, 1145 }; 1146 1147 void 1148 intel_fdi_init_hook(struct drm_i915_private *dev_priv) 1149 { 1150 if (IS_IRONLAKE(dev_priv)) { 1151 dev_priv->display.funcs.fdi = &ilk_funcs; 1152 } else if (IS_SANDYBRIDGE(dev_priv)) { 1153 dev_priv->display.funcs.fdi = &gen6_funcs; 1154 } else if (IS_IVYBRIDGE(dev_priv)) { 1155 /* FIXME: detect B0+ stepping and use auto training */ 1156 dev_priv->display.funcs.fdi = &ivb_funcs; 1157 } 1158 } 1159