1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /** 7 * DOC: display pinning helpers 8 */ 9 10 #include "gem/i915_gem_domain.h" 11 #include "gem/i915_gem_object.h" 12 13 #include "i915_drv.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_display_types.h" 16 #include "intel_dpt.h" 17 #include "intel_fb.h" 18 #include "intel_fb_pin.h" 19 20 static struct i915_vma * 21 intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, 22 const struct i915_gtt_view *view, 23 unsigned int alignment, 24 unsigned long *out_flags, 25 struct i915_address_space *vm) 26 { 27 struct drm_device *dev = fb->dev; 28 struct drm_i915_private *dev_priv = to_i915(dev); 29 struct drm_gem_object *_obj = intel_fb_bo(fb); 30 struct drm_i915_gem_object *obj = to_intel_bo(_obj); 31 struct i915_gem_ww_ctx ww; 32 struct i915_vma *vma; 33 int ret; 34 35 /* 36 * We are not syncing against the binding (and potential migrations) 37 * below, so this vm must never be async. 38 */ 39 if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags)) 40 return ERR_PTR(-EINVAL); 41 42 if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) 43 return ERR_PTR(-EINVAL); 44 45 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 46 47 for_i915_gem_ww(&ww, ret, true) { 48 ret = i915_gem_object_lock(obj, &ww); 49 if (ret) 50 continue; 51 52 if (HAS_LMEM(dev_priv)) { 53 unsigned int flags = obj->flags; 54 55 /* 56 * For this type of buffer we need to able to read from the CPU 57 * the clear color value found in the buffer, hence we need to 58 * ensure it is always in the mappable part of lmem, if this is 59 * a small-bar device. 60 */ 61 if (intel_fb_rc_ccs_cc_plane(fb) >= 0) 62 flags &= ~I915_BO_ALLOC_GPU_ONLY; 63 ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0, 64 flags); 65 if (ret) 66 continue; 67 } 68 69 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); 70 if (ret) 71 continue; 72 73 vma = i915_vma_instance(obj, vm, view); 74 if (IS_ERR(vma)) { 75 ret = PTR_ERR(vma); 76 continue; 77 } 78 79 if (i915_vma_misplaced(vma, 0, alignment, 0)) { 80 ret = i915_vma_unbind(vma); 81 if (ret) 82 continue; 83 } 84 85 ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL); 86 if (ret) 87 continue; 88 } 89 if (ret) { 90 vma = ERR_PTR(ret); 91 goto err; 92 } 93 94 vma->display_alignment = max(vma->display_alignment, alignment); 95 96 i915_gem_object_flush_if_display(obj); 97 98 i915_vma_get(vma); 99 err: 100 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 101 102 return vma; 103 } 104 105 struct i915_vma * 106 intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, 107 const struct i915_gtt_view *view, 108 unsigned int alignment, 109 unsigned int phys_alignment, 110 unsigned int vtd_guard, 111 bool uses_fence, 112 unsigned long *out_flags) 113 { 114 struct drm_device *dev = fb->dev; 115 struct drm_i915_private *dev_priv = to_i915(dev); 116 struct drm_gem_object *_obj = intel_fb_bo(fb); 117 struct drm_i915_gem_object *obj = to_intel_bo(_obj); 118 intel_wakeref_t wakeref; 119 struct i915_gem_ww_ctx ww; 120 struct i915_vma *vma; 121 unsigned int pinctl; 122 int ret; 123 124 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) 125 return ERR_PTR(-EINVAL); 126 127 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) 128 return ERR_PTR(-EINVAL); 129 130 /* 131 * Global gtt pte registers are special registers which actually forward 132 * writes to a chunk of system memory. Which means that there is no risk 133 * that the register values disappear as soon as we call 134 * intel_runtime_pm_put(), so it is correct to wrap only the 135 * pin/unpin/fence and not more. 136 */ 137 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 138 139 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 140 141 /* 142 * Valleyview is definitely limited to scanning out the first 143 * 512MiB. Lets presume this behaviour was inherited from the 144 * g4x display engine and that all earlier gen are similarly 145 * limited. Testing suggests that it is a little more 146 * complicated than this. For example, Cherryview appears quite 147 * happy to scanout from anywhere within its global aperture. 148 */ 149 pinctl = 0; 150 if (HAS_GMCH(dev_priv)) 151 pinctl |= PIN_MAPPABLE; 152 153 i915_gem_ww_ctx_init(&ww, true); 154 retry: 155 ret = i915_gem_object_lock(obj, &ww); 156 if (!ret && phys_alignment) 157 ret = i915_gem_object_attach_phys(obj, phys_alignment); 158 else if (!ret && HAS_LMEM(dev_priv)) 159 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); 160 if (!ret) 161 ret = i915_gem_object_pin_pages(obj); 162 if (ret) 163 goto err; 164 165 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, 166 vtd_guard, view, pinctl); 167 if (IS_ERR(vma)) { 168 ret = PTR_ERR(vma); 169 goto err_unpin; 170 } 171 172 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { 173 /* 174 * Install a fence for tiled scan-out. Pre-i965 always needs a 175 * fence, whereas 965+ only requires a fence if using 176 * framebuffer compression. For simplicity, we always, when 177 * possible, install a fence as the cost is not that onerous. 178 * 179 * If we fail to fence the tiled scanout, then either the 180 * modeset will reject the change (which is highly unlikely as 181 * the affected systems, all but one, do not have unmappable 182 * space) or we will not be able to enable full powersaving 183 * techniques (also likely not to apply due to various limits 184 * FBC and the like impose on the size of the buffer, which 185 * presumably we violated anyway with this unmappable buffer). 186 * Anyway, it is presumably better to stumble onwards with 187 * something and try to run the system in a "less than optimal" 188 * mode that matches the user configuration. 189 */ 190 ret = i915_vma_pin_fence(vma); 191 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) { 192 i915_vma_unpin(vma); 193 goto err_unpin; 194 } 195 ret = 0; 196 197 if (vma->fence) 198 *out_flags |= PLANE_HAS_FENCE; 199 } 200 201 i915_vma_get(vma); 202 203 err_unpin: 204 i915_gem_object_unpin_pages(obj); 205 err: 206 if (ret == -EDEADLK) { 207 ret = i915_gem_ww_ctx_backoff(&ww); 208 if (!ret) 209 goto retry; 210 } 211 i915_gem_ww_ctx_fini(&ww); 212 if (ret) 213 vma = ERR_PTR(ret); 214 215 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 216 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 217 return vma; 218 } 219 220 void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) 221 { 222 if (flags & PLANE_HAS_FENCE) 223 i915_vma_unpin_fence(vma); 224 i915_vma_unpin(vma); 225 i915_vma_put(vma); 226 } 227 228 static unsigned int 229 intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) 230 { 231 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 232 233 return fb->min_alignment; 234 } 235 236 static unsigned int 237 intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) 238 { 239 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 240 const struct drm_framebuffer *fb = plane_state->hw.fb; 241 242 if (!intel_plane_needs_physical(plane)) 243 return 0; 244 245 return plane->min_alignment(plane, fb, 0); 246 } 247 248 static unsigned int 249 intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) 250 { 251 return intel_fb_view_vtd_guard(plane_state->hw.fb, 252 &plane_state->view, 253 plane_state->hw.rotation); 254 } 255 256 int intel_plane_pin_fb(struct intel_plane_state *plane_state, 257 const struct intel_plane_state *old_plane_state) 258 { 259 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 260 const struct intel_framebuffer *fb = 261 to_intel_framebuffer(plane_state->hw.fb); 262 struct i915_vma *vma; 263 264 if (!intel_fb_uses_dpt(&fb->base)) { 265 vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, 266 intel_plane_fb_min_alignment(plane_state), 267 intel_plane_fb_min_phys_alignment(plane_state), 268 intel_plane_fb_vtd_guard(plane_state), 269 intel_plane_uses_fence(plane_state), 270 &plane_state->flags); 271 if (IS_ERR(vma)) 272 return PTR_ERR(vma); 273 274 plane_state->ggtt_vma = vma; 275 276 /* 277 * Pre-populate the dma address before we enter the vblank 278 * evade critical section as i915_gem_object_get_dma_address() 279 * will trigger might_sleep() even if it won't actually sleep, 280 * which is the case when the fb has already been pinned. 281 */ 282 if (intel_plane_needs_physical(plane)) { 283 struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); 284 285 plane_state->phys_dma_addr = i915_gem_object_get_dma_address(obj, 0); 286 } 287 } else { 288 unsigned int alignment = intel_plane_fb_min_alignment(plane_state); 289 290 vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512); 291 if (IS_ERR(vma)) 292 return PTR_ERR(vma); 293 294 plane_state->ggtt_vma = vma; 295 296 vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt, 297 alignment, &plane_state->flags, 298 fb->dpt_vm); 299 if (IS_ERR(vma)) { 300 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 301 plane_state->ggtt_vma = NULL; 302 return PTR_ERR(vma); 303 } 304 305 plane_state->dpt_vma = vma; 306 307 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); 308 } 309 310 return 0; 311 } 312 313 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) 314 { 315 const struct intel_framebuffer *fb = 316 to_intel_framebuffer(old_plane_state->hw.fb); 317 struct i915_vma *vma; 318 319 if (!intel_fb_uses_dpt(&fb->base)) { 320 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 321 if (vma) 322 intel_fb_unpin_vma(vma, old_plane_state->flags); 323 } else { 324 vma = fetch_and_zero(&old_plane_state->dpt_vma); 325 if (vma) 326 intel_fb_unpin_vma(vma, old_plane_state->flags); 327 328 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 329 if (vma) 330 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 331 } 332 } 333