1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <[email protected]> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/seq_buf.h> 32 #include <linux/slab.h> 33 #include <linux/sort.h> 34 #include <linux/string_helpers.h> 35 #include <linux/timekeeping.h> 36 #include <linux/types.h> 37 38 #include <asm/byteorder.h> 39 40 #include <drm/display/drm_dp_helper.h> 41 #include <drm/display/drm_dp_tunnel.h> 42 #include <drm/display/drm_dsc_helper.h> 43 #include <drm/display/drm_hdmi_helper.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_crtc.h> 46 #include <drm/drm_edid.h> 47 #include <drm/drm_fixed.h> 48 #include <drm/drm_probe_helper.h> 49 50 #include "g4x_dp.h" 51 #include "i915_drv.h" 52 #include "i915_irq.h" 53 #include "i915_reg.h" 54 #include "intel_alpm.h" 55 #include "intel_atomic.h" 56 #include "intel_audio.h" 57 #include "intel_backlight.h" 58 #include "intel_combo_phy_regs.h" 59 #include "intel_connector.h" 60 #include "intel_crtc.h" 61 #include "intel_cx0_phy.h" 62 #include "intel_ddi.h" 63 #include "intel_de.h" 64 #include "intel_display_driver.h" 65 #include "intel_display_types.h" 66 #include "intel_dp.h" 67 #include "intel_dp_aux.h" 68 #include "intel_dp_hdcp.h" 69 #include "intel_dp_link_training.h" 70 #include "intel_dp_mst.h" 71 #include "intel_dp_test.h" 72 #include "intel_dp_tunnel.h" 73 #include "intel_dpio_phy.h" 74 #include "intel_dpll.h" 75 #include "intel_drrs.h" 76 #include "intel_encoder.h" 77 #include "intel_fifo_underrun.h" 78 #include "intel_hdcp.h" 79 #include "intel_hdmi.h" 80 #include "intel_hotplug.h" 81 #include "intel_hotplug_irq.h" 82 #include "intel_lspcon.h" 83 #include "intel_lvds.h" 84 #include "intel_modeset_lock.h" 85 #include "intel_panel.h" 86 #include "intel_pch_display.h" 87 #include "intel_pfit.h" 88 #include "intel_pps.h" 89 #include "intel_psr.h" 90 #include "intel_runtime_pm.h" 91 #include "intel_quirks.h" 92 #include "intel_tc.h" 93 #include "intel_vdsc.h" 94 #include "intel_vrr.h" 95 #include "intel_crtc_state_dump.h" 96 97 /* DP DSC throughput values used for slice count calculations KPixels/s */ 98 #define DP_DSC_PEAK_PIXEL_RATE 2720000 99 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 100 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 101 102 /* Max DSC line buffer depth supported by HW. */ 103 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 104 105 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ 106 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 107 108 /* Constants for DP DSC configurations */ 109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 110 111 /* 112 * With Single pipe configuration, HW is capable of supporting maximum of: 113 * 2 slices per line for ICL, BMG 114 * 4 slices per line for other platforms. 115 * For now consider a max of 2 slices per line, which works for all platforms. 116 * With this we can have max of 4 DSC Slices per pipe. 117 * 118 * For higher resolutions where 12 slice support is required with 119 * ultrajoiner, only then each pipe can support 3 slices. 120 * 121 * #TODO Split this better to use 4 slices/dsc engine where supported. 122 */ 123 static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; 124 125 /** 126 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 127 * @intel_dp: DP struct 128 * 129 * If a CPU or PCH DP output is attached to an eDP panel, this function 130 * will return true, and false otherwise. 131 * 132 * This function is not safe to use prior to encoder type being set. 133 */ 134 bool intel_dp_is_edp(struct intel_dp *intel_dp) 135 { 136 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 137 138 return dig_port->base.type == INTEL_OUTPUT_EDP; 139 } 140 141 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 142 143 /* Is link rate UHBR and thus 128b/132b? */ 144 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 145 { 146 return drm_dp_is_uhbr_rate(crtc_state->port_clock); 147 } 148 149 /** 150 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 151 * @rate: link rate in 10kbit/s units 152 * 153 * Returns the link symbol size in bits/symbol units depending on the link 154 * rate -> channel coding. 155 */ 156 int intel_dp_link_symbol_size(int rate) 157 { 158 return drm_dp_is_uhbr_rate(rate) ? 32 : 10; 159 } 160 161 /** 162 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 163 * @rate: link rate in 10kbit/s units 164 * 165 * Returns the link symbol clock frequency in kHz units depending on the 166 * link rate and channel coding. 167 */ 168 int intel_dp_link_symbol_clock(int rate) 169 { 170 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); 171 } 172 173 static int max_dprx_rate(struct intel_dp *intel_dp) 174 { 175 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 176 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); 177 178 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 179 } 180 181 static int max_dprx_lane_count(struct intel_dp *intel_dp) 182 { 183 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 184 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); 185 186 return drm_dp_max_lane_count(intel_dp->dpcd); 187 } 188 189 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 190 { 191 intel_dp->sink_rates[0] = 162000; 192 intel_dp->num_sink_rates = 1; 193 } 194 195 /* update sink rates from dpcd */ 196 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 197 { 198 static const int dp_rates[] = { 199 162000, 270000, 540000, 810000 200 }; 201 int i, max_rate; 202 int max_lttpr_rate; 203 204 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 205 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 206 static const int quirk_rates[] = { 162000, 270000, 324000 }; 207 208 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 209 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 210 211 return; 212 } 213 214 /* 215 * Sink rates for 8b/10b. 216 */ 217 max_rate = max_dprx_rate(intel_dp); 218 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 219 if (max_lttpr_rate) 220 max_rate = min(max_rate, max_lttpr_rate); 221 222 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 223 if (dp_rates[i] > max_rate) 224 break; 225 intel_dp->sink_rates[i] = dp_rates[i]; 226 } 227 228 /* 229 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 230 * rates and 10 Gbps. 231 */ 232 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { 233 u8 uhbr_rates = 0; 234 235 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 236 237 drm_dp_dpcd_readb(&intel_dp->aux, 238 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 239 240 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 241 /* We have a repeater */ 242 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 243 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 244 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 245 DP_PHY_REPEATER_128B132B_SUPPORTED) { 246 /* Repeater supports 128b/132b, valid UHBR rates */ 247 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 248 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 249 } else { 250 /* Does not support 128b/132b */ 251 uhbr_rates = 0; 252 } 253 } 254 255 if (uhbr_rates & DP_UHBR10) 256 intel_dp->sink_rates[i++] = 1000000; 257 if (uhbr_rates & DP_UHBR13_5) 258 intel_dp->sink_rates[i++] = 1350000; 259 if (uhbr_rates & DP_UHBR20) 260 intel_dp->sink_rates[i++] = 2000000; 261 } 262 263 intel_dp->num_sink_rates = i; 264 } 265 266 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 267 { 268 struct intel_display *display = to_intel_display(intel_dp); 269 struct intel_connector *connector = intel_dp->attached_connector; 270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 271 struct intel_encoder *encoder = &intel_dig_port->base; 272 273 intel_dp_set_dpcd_sink_rates(intel_dp); 274 275 if (intel_dp->num_sink_rates) 276 return; 277 278 drm_err(display->drm, 279 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 280 connector->base.base.id, connector->base.name, 281 encoder->base.base.id, encoder->base.name); 282 283 intel_dp_set_default_sink_rates(intel_dp); 284 } 285 286 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 287 { 288 intel_dp->max_sink_lane_count = 1; 289 } 290 291 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 292 { 293 struct intel_display *display = to_intel_display(intel_dp); 294 struct intel_connector *connector = intel_dp->attached_connector; 295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 296 struct intel_encoder *encoder = &intel_dig_port->base; 297 298 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); 299 300 switch (intel_dp->max_sink_lane_count) { 301 case 1: 302 case 2: 303 case 4: 304 return; 305 } 306 307 drm_err(display->drm, 308 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 309 connector->base.base.id, connector->base.name, 310 encoder->base.base.id, encoder->base.name, 311 intel_dp->max_sink_lane_count); 312 313 intel_dp_set_default_max_sink_lane_count(intel_dp); 314 } 315 316 /* Get length of rates array potentially limited by max_rate. */ 317 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 318 { 319 int i; 320 321 /* Limit results by potentially reduced max rate */ 322 for (i = 0; i < len; i++) { 323 if (rates[len - i - 1] <= max_rate) 324 return len - i; 325 } 326 327 return 0; 328 } 329 330 /* Get length of common rates array potentially limited by max_rate. */ 331 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 332 int max_rate) 333 { 334 return intel_dp_rate_limit_len(intel_dp->common_rates, 335 intel_dp->num_common_rates, max_rate); 336 } 337 338 int intel_dp_common_rate(struct intel_dp *intel_dp, int index) 339 { 340 struct intel_display *display = to_intel_display(intel_dp); 341 342 if (drm_WARN_ON(display->drm, 343 index < 0 || index >= intel_dp->num_common_rates)) 344 return 162000; 345 346 return intel_dp->common_rates[index]; 347 } 348 349 /* Theoretical max between source and sink */ 350 int intel_dp_max_common_rate(struct intel_dp *intel_dp) 351 { 352 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); 353 } 354 355 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 356 { 357 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 358 int max_lanes = dig_port->max_lanes; 359 360 if (vbt_max_lanes) 361 max_lanes = min(max_lanes, vbt_max_lanes); 362 363 return max_lanes; 364 } 365 366 /* Theoretical max between source and sink */ 367 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 368 { 369 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 370 int source_max = intel_dp_max_source_lane_count(dig_port); 371 int sink_max = intel_dp->max_sink_lane_count; 372 int lane_max = intel_tc_port_max_lane_count(dig_port); 373 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 374 375 if (lttpr_max) 376 sink_max = min(sink_max, lttpr_max); 377 378 return min3(source_max, sink_max, lane_max); 379 } 380 381 static int forced_lane_count(struct intel_dp *intel_dp) 382 { 383 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); 384 } 385 386 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 387 { 388 int lane_count; 389 390 if (intel_dp->link.force_lane_count) 391 lane_count = forced_lane_count(intel_dp); 392 else 393 lane_count = intel_dp->link.max_lane_count; 394 395 switch (lane_count) { 396 case 1: 397 case 2: 398 case 4: 399 return lane_count; 400 default: 401 MISSING_CASE(lane_count); 402 return 1; 403 } 404 } 405 406 static int intel_dp_min_lane_count(struct intel_dp *intel_dp) 407 { 408 if (intel_dp->link.force_lane_count) 409 return forced_lane_count(intel_dp); 410 411 return 1; 412 } 413 414 /* 415 * The required data bandwidth for a mode with given pixel clock and bpp. This 416 * is the required net bandwidth independent of the data bandwidth efficiency. 417 * 418 * TODO: check if callers of this functions should use 419 * intel_dp_effective_data_rate() instead. 420 */ 421 int 422 intel_dp_link_required(int pixel_clock, int bpp) 423 { 424 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 425 return DIV_ROUND_UP(pixel_clock * bpp, 8); 426 } 427 428 /** 429 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead 430 * @pixel_clock: pixel clock in kHz 431 * @bpp_x16: bits per pixel .4 fixed point format 432 * @bw_overhead: BW allocation overhead in 1ppm units 433 * 434 * Return the effective pixel data rate in kB/sec units taking into account 435 * the provided SSC, FEC, DSC BW allocation overhead. 436 */ 437 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 438 int bw_overhead) 439 { 440 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 441 1000000 * 16 * 8); 442 } 443 444 /** 445 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params 446 * @intel_dp: Intel DP object 447 * @max_dprx_rate: Maximum data rate of the DPRX 448 * @max_dprx_lanes: Maximum lane count of the DPRX 449 * 450 * Calculate the maximum data rate for the provided link parameters taking into 451 * account any BW limitations by a DP tunnel attached to @intel_dp. 452 * 453 * Returns the maximum data rate in kBps units. 454 */ 455 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 456 int max_dprx_rate, int max_dprx_lanes) 457 { 458 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); 459 460 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 461 max_rate = min(max_rate, 462 drm_dp_tunnel_available_bw(intel_dp->tunnel)); 463 464 return max_rate; 465 } 466 467 bool intel_dp_has_joiner(struct intel_dp *intel_dp) 468 { 469 struct intel_display *display = to_intel_display(intel_dp); 470 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 471 struct intel_encoder *encoder = &intel_dig_port->base; 472 473 /* eDP MSO is not compatible with joiner */ 474 if (intel_dp->mso_link_count) 475 return false; 476 477 return DISPLAY_VER(display) >= 12 || 478 (DISPLAY_VER(display) == 11 && 479 encoder->port != PORT_A); 480 } 481 482 static int dg2_max_source_rate(struct intel_dp *intel_dp) 483 { 484 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 485 } 486 487 static int icl_max_source_rate(struct intel_dp *intel_dp) 488 { 489 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 490 491 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) 492 return 540000; 493 494 return 810000; 495 } 496 497 static int ehl_max_source_rate(struct intel_dp *intel_dp) 498 { 499 if (intel_dp_is_edp(intel_dp)) 500 return 540000; 501 502 return 810000; 503 } 504 505 static int mtl_max_source_rate(struct intel_dp *intel_dp) 506 { 507 struct intel_display *display = to_intel_display(intel_dp); 508 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 509 510 if (intel_encoder_is_c10phy(encoder)) 511 return 810000; 512 513 if (DISPLAY_VERx100(display) == 1401) 514 return 1350000; 515 516 return 2000000; 517 } 518 519 static int vbt_max_link_rate(struct intel_dp *intel_dp) 520 { 521 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 522 int max_rate; 523 524 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 525 526 if (intel_dp_is_edp(intel_dp)) { 527 struct intel_connector *connector = intel_dp->attached_connector; 528 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 529 530 if (max_rate && edp_max_rate) 531 max_rate = min(max_rate, edp_max_rate); 532 else if (edp_max_rate) 533 max_rate = edp_max_rate; 534 } 535 536 return max_rate; 537 } 538 539 static void 540 intel_dp_set_source_rates(struct intel_dp *intel_dp) 541 { 542 /* The values must be in increasing order */ 543 static const int bmg_rates[] = { 544 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 545 810000, 1000000, 1350000, 546 }; 547 static const int mtl_rates[] = { 548 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 549 810000, 1000000, 2000000, 550 }; 551 static const int icl_rates[] = { 552 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 553 1000000, 1350000, 554 }; 555 static const int bxt_rates[] = { 556 162000, 216000, 243000, 270000, 324000, 432000, 540000 557 }; 558 static const int skl_rates[] = { 559 162000, 216000, 270000, 324000, 432000, 540000 560 }; 561 static const int hsw_rates[] = { 562 162000, 270000, 540000 563 }; 564 static const int g4x_rates[] = { 565 162000, 270000 566 }; 567 struct intel_display *display = to_intel_display(intel_dp); 568 const int *source_rates; 569 int size, max_rate = 0, vbt_max_rate; 570 571 /* This should only be done once */ 572 drm_WARN_ON(display->drm, 573 intel_dp->source_rates || intel_dp->num_source_rates); 574 575 if (DISPLAY_VER(display) >= 14) { 576 if (display->platform.battlemage) { 577 source_rates = bmg_rates; 578 size = ARRAY_SIZE(bmg_rates); 579 } else { 580 source_rates = mtl_rates; 581 size = ARRAY_SIZE(mtl_rates); 582 } 583 max_rate = mtl_max_source_rate(intel_dp); 584 } else if (DISPLAY_VER(display) >= 11) { 585 source_rates = icl_rates; 586 size = ARRAY_SIZE(icl_rates); 587 if (display->platform.dg2) 588 max_rate = dg2_max_source_rate(intel_dp); 589 else if (display->platform.alderlake_p || display->platform.alderlake_s || 590 display->platform.dg1 || display->platform.rocketlake) 591 max_rate = 810000; 592 else if (display->platform.jasperlake || display->platform.elkhartlake) 593 max_rate = ehl_max_source_rate(intel_dp); 594 else 595 max_rate = icl_max_source_rate(intel_dp); 596 } else if (display->platform.geminilake || display->platform.broxton) { 597 source_rates = bxt_rates; 598 size = ARRAY_SIZE(bxt_rates); 599 } else if (DISPLAY_VER(display) == 9) { 600 source_rates = skl_rates; 601 size = ARRAY_SIZE(skl_rates); 602 } else if ((display->platform.haswell && !display->platform.haswell_ulx) || 603 display->platform.broadwell) { 604 source_rates = hsw_rates; 605 size = ARRAY_SIZE(hsw_rates); 606 } else { 607 source_rates = g4x_rates; 608 size = ARRAY_SIZE(g4x_rates); 609 } 610 611 vbt_max_rate = vbt_max_link_rate(intel_dp); 612 if (max_rate && vbt_max_rate) 613 max_rate = min(max_rate, vbt_max_rate); 614 else if (vbt_max_rate) 615 max_rate = vbt_max_rate; 616 617 if (max_rate) 618 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 619 620 intel_dp->source_rates = source_rates; 621 intel_dp->num_source_rates = size; 622 } 623 624 static int intersect_rates(const int *source_rates, int source_len, 625 const int *sink_rates, int sink_len, 626 int *common_rates) 627 { 628 int i = 0, j = 0, k = 0; 629 630 while (i < source_len && j < sink_len) { 631 if (source_rates[i] == sink_rates[j]) { 632 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 633 return k; 634 common_rates[k] = source_rates[i]; 635 ++k; 636 ++i; 637 ++j; 638 } else if (source_rates[i] < sink_rates[j]) { 639 ++i; 640 } else { 641 ++j; 642 } 643 } 644 return k; 645 } 646 647 /* return index of rate in rates array, or -1 if not found */ 648 int intel_dp_rate_index(const int *rates, int len, int rate) 649 { 650 int i; 651 652 for (i = 0; i < len; i++) 653 if (rate == rates[i]) 654 return i; 655 656 return -1; 657 } 658 659 static int intel_dp_link_config_rate(struct intel_dp *intel_dp, 660 const struct intel_dp_link_config *lc) 661 { 662 return intel_dp_common_rate(intel_dp, lc->link_rate_idx); 663 } 664 665 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) 666 { 667 return 1 << lc->lane_count_exp; 668 } 669 670 static int intel_dp_link_config_bw(struct intel_dp *intel_dp, 671 const struct intel_dp_link_config *lc) 672 { 673 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), 674 intel_dp_link_config_lane_count(lc)); 675 } 676 677 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) 678 { 679 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ 680 const struct intel_dp_link_config *lc_a = a; 681 const struct intel_dp_link_config *lc_b = b; 682 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); 683 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); 684 685 if (bw_a != bw_b) 686 return bw_a - bw_b; 687 688 return intel_dp_link_config_rate(intel_dp, lc_a) - 689 intel_dp_link_config_rate(intel_dp, lc_b); 690 } 691 692 static void intel_dp_link_config_init(struct intel_dp *intel_dp) 693 { 694 struct intel_display *display = to_intel_display(intel_dp); 695 struct intel_dp_link_config *lc; 696 int num_common_lane_configs; 697 int i; 698 int j; 699 700 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) 701 return; 702 703 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; 704 705 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs > 706 ARRAY_SIZE(intel_dp->link.configs))) 707 return; 708 709 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs; 710 711 lc = &intel_dp->link.configs[0]; 712 for (i = 0; i < intel_dp->num_common_rates; i++) { 713 for (j = 0; j < num_common_lane_configs; j++) { 714 lc->lane_count_exp = j; 715 lc->link_rate_idx = i; 716 717 lc++; 718 } 719 } 720 721 sort_r(intel_dp->link.configs, intel_dp->link.num_configs, 722 sizeof(intel_dp->link.configs[0]), 723 link_config_cmp_by_bw, NULL, 724 intel_dp); 725 } 726 727 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) 728 { 729 struct intel_display *display = to_intel_display(intel_dp); 730 const struct intel_dp_link_config *lc; 731 732 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs)) 733 idx = 0; 734 735 lc = &intel_dp->link.configs[idx]; 736 737 *link_rate = intel_dp_link_config_rate(intel_dp, lc); 738 *lane_count = intel_dp_link_config_lane_count(lc); 739 } 740 741 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) 742 { 743 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, 744 link_rate); 745 int lane_count_exp = ilog2(lane_count); 746 int i; 747 748 for (i = 0; i < intel_dp->link.num_configs; i++) { 749 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; 750 751 if (lc->lane_count_exp == lane_count_exp && 752 lc->link_rate_idx == link_rate_idx) 753 return i; 754 } 755 756 return -1; 757 } 758 759 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 760 { 761 struct intel_display *display = to_intel_display(intel_dp); 762 763 drm_WARN_ON(display->drm, 764 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 765 766 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 767 intel_dp->num_source_rates, 768 intel_dp->sink_rates, 769 intel_dp->num_sink_rates, 770 intel_dp->common_rates); 771 772 /* Paranoia, there should always be something in common. */ 773 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) { 774 intel_dp->common_rates[0] = 162000; 775 intel_dp->num_common_rates = 1; 776 } 777 778 intel_dp_link_config_init(intel_dp); 779 } 780 781 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 782 u8 lane_count) 783 { 784 /* 785 * FIXME: we need to synchronize the current link parameters with 786 * hardware readout. Currently fast link training doesn't work on 787 * boot-up. 788 */ 789 if (link_rate == 0 || 790 link_rate > intel_dp->link.max_rate) 791 return false; 792 793 if (lane_count == 0 || 794 lane_count > intel_dp_max_lane_count(intel_dp)) 795 return false; 796 797 return true; 798 } 799 800 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 801 { 802 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), 803 1000000U); 804 } 805 806 int intel_dp_bw_fec_overhead(bool fec_enabled) 807 { 808 /* 809 * TODO: Calculate the actual overhead for a given mode. 810 * The hard-coded 1/0.972261=2.853% overhead factor 811 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + 812 * 0.453% DSC overhead. This is enough for a 3840 width mode, 813 * which has a DSC overhead of up to ~0.2%, but may not be 814 * enough for a 1024 width mode where this is ~0.8% (on a 4 815 * lane DP link, with 2 DSC slices and 8 bpp color depth). 816 */ 817 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; 818 } 819 820 static int 821 small_joiner_ram_size_bits(struct intel_display *display) 822 { 823 if (DISPLAY_VER(display) >= 13) 824 return 17280 * 8; 825 else if (DISPLAY_VER(display) >= 11) 826 return 7680 * 8; 827 else 828 return 6144 * 8; 829 } 830 831 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) 832 { 833 u32 bits_per_pixel = bpp; 834 int i; 835 836 /* Error out if the max bpp is less than smallest allowed valid bpp */ 837 if (bits_per_pixel < valid_dsc_bpp[0]) { 838 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n", 839 bits_per_pixel, valid_dsc_bpp[0]); 840 return 0; 841 } 842 843 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 844 if (DISPLAY_VER(display) >= 13) { 845 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 846 847 /* 848 * According to BSpec, 27 is the max DSC output bpp, 849 * 8 is the min DSC output bpp. 850 * While we can still clamp higher bpp values to 27, saving bandwidth, 851 * if it is required to oompress up to bpp < 8, means we can't do 852 * that and probably means we can't fit the required mode, even with 853 * DSC enabled. 854 */ 855 if (bits_per_pixel < 8) { 856 drm_dbg_kms(display->drm, 857 "Unsupported BPP %u, min 8\n", 858 bits_per_pixel); 859 return 0; 860 } 861 bits_per_pixel = min_t(u32, bits_per_pixel, 27); 862 } else { 863 /* Find the nearest match in the array of known BPPs from VESA */ 864 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 865 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 866 break; 867 } 868 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n", 869 bits_per_pixel, valid_dsc_bpp[i]); 870 871 bits_per_pixel = valid_dsc_bpp[i]; 872 } 873 874 return bits_per_pixel; 875 } 876 877 static int bigjoiner_interface_bits(struct intel_display *display) 878 { 879 return DISPLAY_VER(display) >= 14 ? 36 : 24; 880 } 881 882 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock, 883 int num_joined_pipes) 884 { 885 u32 max_bpp; 886 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 887 int ppc = 2; 888 int num_big_joiners = num_joined_pipes / 2; 889 890 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / 891 intel_dp_mode_to_fec_clock(mode_clock); 892 893 max_bpp *= num_big_joiners; 894 895 return max_bpp; 896 897 } 898 899 static u32 small_joiner_ram_max_bpp(struct intel_display *display, 900 u32 mode_hdisplay, 901 int num_joined_pipes) 902 { 903 u32 max_bpp; 904 905 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 906 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay; 907 908 max_bpp *= num_joined_pipes; 909 910 return max_bpp; 911 } 912 913 static int ultrajoiner_ram_bits(void) 914 { 915 return 4 * 72 * 512; 916 } 917 918 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay) 919 { 920 return ultrajoiner_ram_bits() / mode_hdisplay; 921 } 922 923 static 924 u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, 925 u32 mode_clock, u32 mode_hdisplay, 926 int num_joined_pipes) 927 { 928 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes); 929 930 if (num_joined_pipes > 1) 931 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock, 932 num_joined_pipes)); 933 if (num_joined_pipes == 4) 934 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay)); 935 936 return max_bpp; 937 } 938 939 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, 940 u32 link_clock, u32 lane_count, 941 u32 mode_clock, u32 mode_hdisplay, 942 int num_joined_pipes, 943 enum intel_output_format output_format, 944 u32 pipe_bpp, 945 u32 timeslots) 946 { 947 u32 bits_per_pixel, joiner_max_bpp; 948 949 /* 950 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 951 * (LinkSymbolClock)* 8 * (TimeSlots / 64) 952 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) 953 * for MST -> TimeSlots has to be calculated, based on mode requirements 954 * 955 * Due to FEC overhead, the available bw is reduced to 97.2261%. 956 * To support the given mode: 957 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead 958 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead 959 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock 960 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / 961 * (ModeClock / FEC Overhead) 962 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / 963 * (ModeClock / FEC Overhead * 8) 964 */ 965 bits_per_pixel = ((link_clock * lane_count) * timeslots) / 966 (intel_dp_mode_to_fec_clock(mode_clock) * 8); 967 968 /* Bandwidth required for 420 is half, that of 444 format */ 969 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 970 bits_per_pixel *= 2; 971 972 /* 973 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum 974 * supported PPS value can be 63.9375 and with the further 975 * mention that for 420, 422 formats, bpp should be programmed double 976 * the target bpp restricting our target bpp to be 31.9375 at max. 977 */ 978 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 979 bits_per_pixel = min_t(u32, bits_per_pixel, 31); 980 981 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots " 982 "total bw %u pixel clock %u\n", 983 bits_per_pixel, timeslots, 984 (link_clock * lane_count * 8), 985 intel_dp_mode_to_fec_clock(mode_clock)); 986 987 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock, 988 mode_hdisplay, num_joined_pipes); 989 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); 990 991 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp); 992 993 return bits_per_pixel; 994 } 995 996 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 997 int mode_clock, int mode_hdisplay, 998 int num_joined_pipes) 999 { 1000 struct intel_display *display = to_intel_display(connector); 1001 u8 min_slice_count, i; 1002 int max_slice_width; 1003 1004 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 1005 min_slice_count = DIV_ROUND_UP(mode_clock, 1006 DP_DSC_MAX_ENC_THROUGHPUT_0); 1007 else 1008 min_slice_count = DIV_ROUND_UP(mode_clock, 1009 DP_DSC_MAX_ENC_THROUGHPUT_1); 1010 1011 /* 1012 * Due to some DSC engine BW limitations, we need to enable second 1013 * slice and VDSC engine, whenever we approach close enough to max CDCLK 1014 */ 1015 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) 1016 min_slice_count = max_t(u8, min_slice_count, 2); 1017 1018 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 1019 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 1020 drm_dbg_kms(display->drm, 1021 "Unsupported slice width %d by DP DSC Sink device\n", 1022 max_slice_width); 1023 return 0; 1024 } 1025 /* Also take into account max slice width */ 1026 min_slice_count = max_t(u8, min_slice_count, 1027 DIV_ROUND_UP(mode_hdisplay, 1028 max_slice_width)); 1029 1030 /* Find the closest match to the valid slice count values */ 1031 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 1032 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; 1033 1034 /* 1035 * 3 DSC Slices per pipe need 3 DSC engines, 1036 * which is supported only with Ultrajoiner. 1037 */ 1038 if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4) 1039 continue; 1040 1041 if (test_slice_count > 1042 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 1043 break; 1044 1045 /* 1046 * Bigjoiner needs small joiner to be enabled. 1047 * So there should be at least 2 dsc slices per pipe, 1048 * whenever bigjoiner is enabled. 1049 */ 1050 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) 1051 continue; 1052 1053 if (mode_hdisplay % test_slice_count) 1054 continue; 1055 1056 if (min_slice_count <= test_slice_count) 1057 return test_slice_count; 1058 } 1059 1060 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n", 1061 min_slice_count); 1062 return 0; 1063 } 1064 1065 static bool source_can_output(struct intel_dp *intel_dp, 1066 enum intel_output_format format) 1067 { 1068 struct intel_display *display = to_intel_display(intel_dp); 1069 1070 switch (format) { 1071 case INTEL_OUTPUT_FORMAT_RGB: 1072 return true; 1073 1074 case INTEL_OUTPUT_FORMAT_YCBCR444: 1075 /* 1076 * No YCbCr output support on gmch platforms. 1077 * Also, ILK doesn't seem capable of DP YCbCr output. 1078 * The displayed image is severely corrupted. SNB+ is fine. 1079 */ 1080 return !HAS_GMCH(display) && !display->platform.ironlake; 1081 1082 case INTEL_OUTPUT_FORMAT_YCBCR420: 1083 /* Platform < Gen 11 cannot output YCbCr420 format */ 1084 return DISPLAY_VER(display) >= 11; 1085 1086 default: 1087 MISSING_CASE(format); 1088 return false; 1089 } 1090 } 1091 1092 static bool 1093 dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 1094 enum intel_output_format sink_format) 1095 { 1096 if (!drm_dp_is_branch(intel_dp->dpcd)) 1097 return false; 1098 1099 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1100 return intel_dp->dfp.rgb_to_ycbcr; 1101 1102 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1103 return intel_dp->dfp.rgb_to_ycbcr && 1104 intel_dp->dfp.ycbcr_444_to_420; 1105 1106 return false; 1107 } 1108 1109 static bool 1110 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 1111 enum intel_output_format sink_format) 1112 { 1113 if (!drm_dp_is_branch(intel_dp->dpcd)) 1114 return false; 1115 1116 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1117 return intel_dp->dfp.ycbcr_444_to_420; 1118 1119 return false; 1120 } 1121 1122 static bool 1123 dfp_can_convert(struct intel_dp *intel_dp, 1124 enum intel_output_format output_format, 1125 enum intel_output_format sink_format) 1126 { 1127 switch (output_format) { 1128 case INTEL_OUTPUT_FORMAT_RGB: 1129 return dfp_can_convert_from_rgb(intel_dp, sink_format); 1130 case INTEL_OUTPUT_FORMAT_YCBCR444: 1131 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 1132 default: 1133 MISSING_CASE(output_format); 1134 return false; 1135 } 1136 1137 return false; 1138 } 1139 1140 static enum intel_output_format 1141 intel_dp_output_format(struct intel_connector *connector, 1142 enum intel_output_format sink_format) 1143 { 1144 struct intel_display *display = to_intel_display(connector); 1145 struct intel_dp *intel_dp = intel_attached_dp(connector); 1146 enum intel_output_format force_dsc_output_format = 1147 intel_dp->force_dsc_output_format; 1148 enum intel_output_format output_format; 1149 if (force_dsc_output_format) { 1150 if (source_can_output(intel_dp, force_dsc_output_format) && 1151 (!drm_dp_is_branch(intel_dp->dpcd) || 1152 sink_format != force_dsc_output_format || 1153 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 1154 return force_dsc_output_format; 1155 1156 drm_dbg_kms(display->drm, "Cannot force DSC output format\n"); 1157 } 1158 1159 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 1160 dfp_can_convert_from_rgb(intel_dp, sink_format)) 1161 output_format = INTEL_OUTPUT_FORMAT_RGB; 1162 1163 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 1164 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 1165 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 1166 1167 else 1168 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1169 1170 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format)); 1171 1172 return output_format; 1173 } 1174 1175 int intel_dp_min_bpp(enum intel_output_format output_format) 1176 { 1177 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 1178 return 6 * 3; 1179 else 1180 return 8 * 3; 1181 } 1182 1183 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1184 { 1185 /* 1186 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1187 * format of the number of bytes per pixel will be half the number 1188 * of bytes of RGB pixel. 1189 */ 1190 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1191 bpp /= 2; 1192 1193 return bpp; 1194 } 1195 1196 static enum intel_output_format 1197 intel_dp_sink_format(struct intel_connector *connector, 1198 const struct drm_display_mode *mode) 1199 { 1200 const struct drm_display_info *info = &connector->base.display_info; 1201 1202 if (drm_mode_is_420_only(info, mode)) 1203 return INTEL_OUTPUT_FORMAT_YCBCR420; 1204 1205 return INTEL_OUTPUT_FORMAT_RGB; 1206 } 1207 1208 static int 1209 intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1210 const struct drm_display_mode *mode) 1211 { 1212 enum intel_output_format output_format, sink_format; 1213 1214 sink_format = intel_dp_sink_format(connector, mode); 1215 1216 output_format = intel_dp_output_format(connector, sink_format); 1217 1218 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1219 } 1220 1221 static bool intel_dp_hdisplay_bad(struct intel_display *display, 1222 int hdisplay) 1223 { 1224 /* 1225 * Older platforms don't like hdisplay==4096 with DP. 1226 * 1227 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1228 * and frame counter increment), but we don't get vblank interrupts, 1229 * and the pipe underruns immediately. The link also doesn't seem 1230 * to get trained properly. 1231 * 1232 * On CHV the vblank interrupts don't seem to disappear but 1233 * otherwise the symptoms are similar. 1234 * 1235 * TODO: confirm the behaviour on HSW+ 1236 */ 1237 return hdisplay == 4096 && !HAS_DDI(display); 1238 } 1239 1240 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1241 { 1242 struct intel_connector *connector = intel_dp->attached_connector; 1243 const struct drm_display_info *info = &connector->base.display_info; 1244 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1245 1246 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1247 if (max_tmds_clock && info->max_tmds_clock) 1248 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1249 1250 return max_tmds_clock; 1251 } 1252 1253 static enum drm_mode_status 1254 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1255 int clock, int bpc, 1256 enum intel_output_format sink_format, 1257 bool respect_downstream_limits) 1258 { 1259 int tmds_clock, min_tmds_clock, max_tmds_clock; 1260 1261 if (!respect_downstream_limits) 1262 return MODE_OK; 1263 1264 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1265 1266 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1267 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1268 1269 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1270 return MODE_CLOCK_LOW; 1271 1272 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1273 return MODE_CLOCK_HIGH; 1274 1275 return MODE_OK; 1276 } 1277 1278 static enum drm_mode_status 1279 intel_dp_mode_valid_downstream(struct intel_connector *connector, 1280 const struct drm_display_mode *mode, 1281 int target_clock) 1282 { 1283 struct intel_dp *intel_dp = intel_attached_dp(connector); 1284 const struct drm_display_info *info = &connector->base.display_info; 1285 enum drm_mode_status status; 1286 enum intel_output_format sink_format; 1287 1288 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1289 if (intel_dp->dfp.pcon_max_frl_bw) { 1290 int target_bw; 1291 int max_frl_bw; 1292 int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1293 1294 target_bw = bpp * target_clock; 1295 1296 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1297 1298 /* converting bw from Gbps to Kbps*/ 1299 max_frl_bw = max_frl_bw * 1000000; 1300 1301 if (target_bw > max_frl_bw) 1302 return MODE_CLOCK_HIGH; 1303 1304 return MODE_OK; 1305 } 1306 1307 if (intel_dp->dfp.max_dotclock && 1308 target_clock > intel_dp->dfp.max_dotclock) 1309 return MODE_CLOCK_HIGH; 1310 1311 sink_format = intel_dp_sink_format(connector, mode); 1312 1313 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1314 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1315 8, sink_format, true); 1316 1317 if (status != MODE_OK) { 1318 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 1319 !connector->base.ycbcr_420_allowed || 1320 !drm_mode_is_420_also(info, mode)) 1321 return status; 1322 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1323 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1324 8, sink_format, true); 1325 if (status != MODE_OK) 1326 return status; 1327 } 1328 1329 return MODE_OK; 1330 } 1331 1332 static 1333 bool intel_dp_needs_joiner(struct intel_dp *intel_dp, 1334 struct intel_connector *connector, 1335 int hdisplay, int clock, 1336 int num_joined_pipes) 1337 { 1338 struct intel_display *display = to_intel_display(intel_dp); 1339 int hdisplay_limit; 1340 1341 if (!intel_dp_has_joiner(intel_dp)) 1342 return false; 1343 1344 num_joined_pipes /= 2; 1345 1346 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120; 1347 1348 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || 1349 hdisplay > num_joined_pipes * hdisplay_limit; 1350 } 1351 1352 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, 1353 struct intel_connector *connector, 1354 int hdisplay, int clock) 1355 { 1356 struct intel_display *display = to_intel_display(intel_dp); 1357 1358 if (connector->force_joined_pipes) 1359 return connector->force_joined_pipes; 1360 1361 if (HAS_ULTRAJOINER(display) && 1362 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4)) 1363 return 4; 1364 1365 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) && 1366 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2)) 1367 return 2; 1368 1369 return 1; 1370 } 1371 1372 bool intel_dp_has_dsc(const struct intel_connector *connector) 1373 { 1374 struct intel_display *display = to_intel_display(connector); 1375 1376 if (!HAS_DSC(display)) 1377 return false; 1378 1379 if (connector->mst_port && !HAS_DSC_MST(display)) 1380 return false; 1381 1382 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && 1383 connector->panel.vbt.edp.dsc_disable) 1384 return false; 1385 1386 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) 1387 return false; 1388 1389 return true; 1390 } 1391 1392 static enum drm_mode_status 1393 intel_dp_mode_valid(struct drm_connector *_connector, 1394 const struct drm_display_mode *mode) 1395 { 1396 struct intel_display *display = to_intel_display(_connector->dev); 1397 struct intel_connector *connector = to_intel_connector(_connector); 1398 struct intel_dp *intel_dp = intel_attached_dp(connector); 1399 const struct drm_display_mode *fixed_mode; 1400 int target_clock = mode->clock; 1401 int max_rate, mode_rate, max_lanes, max_link_clock; 1402 int max_dotclk = display->cdclk.max_dotclk_freq; 1403 u16 dsc_max_compressed_bpp = 0; 1404 u8 dsc_slice_count = 0; 1405 enum drm_mode_status status; 1406 bool dsc = false; 1407 int num_joined_pipes; 1408 1409 status = intel_cpu_transcoder_mode_valid(display, mode); 1410 if (status != MODE_OK) 1411 return status; 1412 1413 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1414 return MODE_H_ILLEGAL; 1415 1416 if (mode->clock < 10000) 1417 return MODE_CLOCK_LOW; 1418 1419 fixed_mode = intel_panel_fixed_mode(connector, mode); 1420 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 1421 status = intel_panel_mode_valid(connector, mode); 1422 if (status != MODE_OK) 1423 return status; 1424 1425 target_clock = fixed_mode->clock; 1426 } 1427 1428 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 1429 mode->hdisplay, target_clock); 1430 max_dotclk *= num_joined_pipes; 1431 1432 if (target_clock > max_dotclk) 1433 return MODE_CLOCK_HIGH; 1434 1435 if (intel_dp_hdisplay_bad(display, mode->hdisplay)) 1436 return MODE_H_ILLEGAL; 1437 1438 max_link_clock = intel_dp_max_link_rate(intel_dp); 1439 max_lanes = intel_dp_max_lane_count(intel_dp); 1440 1441 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1442 1443 mode_rate = intel_dp_link_required(target_clock, 1444 intel_dp_mode_min_output_bpp(connector, mode)); 1445 1446 if (intel_dp_has_dsc(connector)) { 1447 enum intel_output_format sink_format, output_format; 1448 int pipe_bpp; 1449 1450 sink_format = intel_dp_sink_format(connector, mode); 1451 output_format = intel_dp_output_format(connector, sink_format); 1452 /* 1453 * TBD pass the connector BPC, 1454 * for now U8_MAX so that max BPC on that platform would be picked 1455 */ 1456 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1457 1458 /* 1459 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1460 * integer value since we support only integer values of bpp. 1461 */ 1462 if (intel_dp_is_edp(intel_dp)) { 1463 dsc_max_compressed_bpp = 1464 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1465 dsc_slice_count = 1466 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 1467 true); 1468 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1469 dsc_max_compressed_bpp = 1470 intel_dp_dsc_get_max_compressed_bpp(display, 1471 max_link_clock, 1472 max_lanes, 1473 target_clock, 1474 mode->hdisplay, 1475 num_joined_pipes, 1476 output_format, 1477 pipe_bpp, 64); 1478 dsc_slice_count = 1479 intel_dp_dsc_get_slice_count(connector, 1480 target_clock, 1481 mode->hdisplay, 1482 num_joined_pipes); 1483 } 1484 1485 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1486 } 1487 1488 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) 1489 return MODE_CLOCK_HIGH; 1490 1491 if (mode_rate > max_rate && !dsc) 1492 return MODE_CLOCK_HIGH; 1493 1494 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); 1495 if (status != MODE_OK) 1496 return status; 1497 1498 return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); 1499 } 1500 1501 bool intel_dp_source_supports_tps3(struct intel_display *display) 1502 { 1503 return DISPLAY_VER(display) >= 9 || 1504 display->platform.broadwell || display->platform.haswell; 1505 } 1506 1507 bool intel_dp_source_supports_tps4(struct intel_display *display) 1508 { 1509 return DISPLAY_VER(display) >= 10; 1510 } 1511 1512 static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem) 1513 { 1514 int i; 1515 1516 for (i = 0; i < nelem; i++) 1517 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]); 1518 } 1519 1520 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1521 { 1522 struct intel_display *display = to_intel_display(intel_dp); 1523 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */ 1524 1525 if (!drm_debug_enabled(DRM_UT_KMS)) 1526 return; 1527 1528 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates); 1529 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s)); 1530 1531 seq_buf_clear(&s); 1532 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates); 1533 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s)); 1534 1535 seq_buf_clear(&s); 1536 seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates); 1537 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s)); 1538 } 1539 1540 static int forced_link_rate(struct intel_dp *intel_dp) 1541 { 1542 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate); 1543 1544 if (len == 0) 1545 return intel_dp_common_rate(intel_dp, 0); 1546 1547 return intel_dp_common_rate(intel_dp, len - 1); 1548 } 1549 1550 int 1551 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1552 { 1553 int len; 1554 1555 if (intel_dp->link.force_rate) 1556 return forced_link_rate(intel_dp); 1557 1558 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); 1559 1560 return intel_dp_common_rate(intel_dp, len - 1); 1561 } 1562 1563 static int 1564 intel_dp_min_link_rate(struct intel_dp *intel_dp) 1565 { 1566 if (intel_dp->link.force_rate) 1567 return forced_link_rate(intel_dp); 1568 1569 return intel_dp_common_rate(intel_dp, 0); 1570 } 1571 1572 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1573 { 1574 struct intel_display *display = to_intel_display(intel_dp); 1575 int i = intel_dp_rate_index(intel_dp->sink_rates, 1576 intel_dp->num_sink_rates, rate); 1577 1578 if (drm_WARN_ON(display->drm, i < 0)) 1579 i = 0; 1580 1581 return i; 1582 } 1583 1584 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1585 u8 *link_bw, u8 *rate_select) 1586 { 1587 /* eDP 1.4 rate select method. */ 1588 if (intel_dp->use_rate_select) { 1589 *link_bw = 0; 1590 *rate_select = 1591 intel_dp_rate_select(intel_dp, port_clock); 1592 } else { 1593 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1594 *rate_select = 0; 1595 } 1596 } 1597 1598 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1599 { 1600 struct intel_connector *connector = intel_dp->attached_connector; 1601 1602 return connector->base.display_info.is_hdmi; 1603 } 1604 1605 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1606 const struct intel_crtc_state *pipe_config) 1607 { 1608 struct intel_display *display = to_intel_display(intel_dp); 1609 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1610 1611 if (DISPLAY_VER(display) >= 12) 1612 return true; 1613 1614 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A && 1615 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) 1616 return true; 1617 1618 return false; 1619 } 1620 1621 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1622 const struct intel_connector *connector, 1623 const struct intel_crtc_state *pipe_config) 1624 { 1625 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1626 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1627 } 1628 1629 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 1630 const struct intel_connector *connector, 1631 const struct intel_crtc_state *crtc_state) 1632 { 1633 if (!intel_dp_has_dsc(connector)) 1634 return false; 1635 1636 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 1637 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) 1638 return false; 1639 1640 return intel_dsc_source_support(crtc_state); 1641 } 1642 1643 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1644 const struct intel_crtc_state *crtc_state, 1645 int bpc, bool respect_downstream_limits) 1646 { 1647 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1648 1649 /* 1650 * Current bpc could already be below 8bpc due to 1651 * FDI bandwidth constraints or other limits. 1652 * HDMI minimum is 8bpc however. 1653 */ 1654 bpc = max(bpc, 8); 1655 1656 /* 1657 * We will never exceed downstream TMDS clock limits while 1658 * attempting deep color. If the user insists on forcing an 1659 * out of spec mode they will have to be satisfied with 8bpc. 1660 */ 1661 if (!respect_downstream_limits) 1662 bpc = 8; 1663 1664 for (; bpc >= 8; bpc -= 2) { 1665 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1666 intel_dp_has_hdmi_sink(intel_dp)) && 1667 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1668 respect_downstream_limits) == MODE_OK) 1669 return bpc; 1670 } 1671 1672 return -EINVAL; 1673 } 1674 1675 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1676 const struct intel_crtc_state *crtc_state, 1677 bool respect_downstream_limits) 1678 { 1679 struct intel_display *display = to_intel_display(intel_dp); 1680 struct intel_connector *connector = intel_dp->attached_connector; 1681 int bpp, bpc; 1682 1683 bpc = crtc_state->pipe_bpp / 3; 1684 1685 if (intel_dp->dfp.max_bpc) 1686 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1687 1688 if (intel_dp->dfp.min_tmds_clock) { 1689 int max_hdmi_bpc; 1690 1691 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1692 respect_downstream_limits); 1693 if (max_hdmi_bpc < 0) 1694 return 0; 1695 1696 bpc = min(bpc, max_hdmi_bpc); 1697 } 1698 1699 bpp = bpc * 3; 1700 if (intel_dp_is_edp(intel_dp)) { 1701 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1702 if (connector->base.display_info.bpc == 0 && 1703 connector->panel.vbt.edp.bpp && 1704 connector->panel.vbt.edp.bpp < bpp) { 1705 drm_dbg_kms(display->drm, 1706 "clamping bpp for eDP panel to BIOS-provided %i\n", 1707 connector->panel.vbt.edp.bpp); 1708 bpp = connector->panel.vbt.edp.bpp; 1709 } 1710 } 1711 1712 return bpp; 1713 } 1714 1715 static bool has_seamless_m_n(struct intel_connector *connector) 1716 { 1717 struct intel_display *display = to_intel_display(connector); 1718 1719 /* 1720 * Seamless M/N reprogramming only implemented 1721 * for BDW+ double buffered M/N registers so far. 1722 */ 1723 return HAS_DOUBLE_BUFFERED_M_N(display) && 1724 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1725 } 1726 1727 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1728 const struct drm_connector_state *conn_state) 1729 { 1730 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1731 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1732 1733 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1734 if (has_seamless_m_n(connector)) 1735 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1736 else 1737 return adjusted_mode->crtc_clock; 1738 } 1739 1740 /* Optimize link config in order: max bpp, min clock, min lanes */ 1741 static int 1742 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1743 struct intel_crtc_state *pipe_config, 1744 const struct drm_connector_state *conn_state, 1745 const struct link_config_limits *limits) 1746 { 1747 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1748 int mode_rate, link_rate, link_avail; 1749 1750 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1751 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1752 bpp -= 2 * 3) { 1753 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1754 1755 mode_rate = intel_dp_link_required(clock, link_bpp); 1756 1757 for (i = 0; i < intel_dp->num_common_rates; i++) { 1758 link_rate = intel_dp_common_rate(intel_dp, i); 1759 if (link_rate < limits->min_rate || 1760 link_rate > limits->max_rate) 1761 continue; 1762 1763 for (lane_count = limits->min_lane_count; 1764 lane_count <= limits->max_lane_count; 1765 lane_count <<= 1) { 1766 link_avail = intel_dp_max_link_data_rate(intel_dp, 1767 link_rate, 1768 lane_count); 1769 1770 1771 if (mode_rate <= link_avail) { 1772 pipe_config->lane_count = lane_count; 1773 pipe_config->pipe_bpp = bpp; 1774 pipe_config->port_clock = link_rate; 1775 1776 return 0; 1777 } 1778 } 1779 } 1780 } 1781 1782 return -EINVAL; 1783 } 1784 1785 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) 1786 { 1787 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1788 if (DISPLAY_VER(display) >= 12) 1789 return 12; 1790 if (DISPLAY_VER(display) == 11) 1791 return 10; 1792 1793 return intel_dp_dsc_min_src_input_bpc(); 1794 } 1795 1796 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1797 u8 max_req_bpc) 1798 { 1799 struct intel_display *display = to_intel_display(connector); 1800 int i, num_bpc; 1801 u8 dsc_bpc[3] = {}; 1802 int dsc_max_bpc; 1803 1804 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 1805 1806 if (!dsc_max_bpc) 1807 return dsc_max_bpc; 1808 1809 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc); 1810 1811 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1812 dsc_bpc); 1813 for (i = 0; i < num_bpc; i++) { 1814 if (dsc_max_bpc >= dsc_bpc[i]) 1815 return dsc_bpc[i] * 3; 1816 } 1817 1818 return 0; 1819 } 1820 1821 static int intel_dp_source_dsc_version_minor(struct intel_display *display) 1822 { 1823 return DISPLAY_VER(display) >= 14 ? 2 : 1; 1824 } 1825 1826 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1827 { 1828 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1829 DP_DSC_MINOR_SHIFT; 1830 } 1831 1832 static int intel_dp_get_slice_height(int vactive) 1833 { 1834 int slice_height; 1835 1836 /* 1837 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1838 * lines is an optimal slice height, but any size can be used as long as 1839 * vertical active integer multiple and maximum vertical slice count 1840 * requirements are met. 1841 */ 1842 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1843 if (vactive % slice_height == 0) 1844 return slice_height; 1845 1846 /* 1847 * Highly unlikely we reach here as most of the resolutions will end up 1848 * finding appropriate slice_height in above loop but returning 1849 * slice_height as 2 here as it should work with all resolutions. 1850 */ 1851 return 2; 1852 } 1853 1854 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1855 struct intel_crtc_state *crtc_state) 1856 { 1857 struct intel_display *display = to_intel_display(connector); 1858 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1859 int ret; 1860 1861 /* 1862 * RC_MODEL_SIZE is currently a constant across all configurations. 1863 * 1864 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1865 * DP_DSC_RC_BUF_SIZE for this. 1866 */ 1867 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1868 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1869 1870 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1871 1872 ret = intel_dsc_compute_params(crtc_state); 1873 if (ret) 1874 return ret; 1875 1876 vdsc_cfg->dsc_version_major = 1877 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1878 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1879 vdsc_cfg->dsc_version_minor = 1880 min(intel_dp_source_dsc_version_minor(display), 1881 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1882 if (vdsc_cfg->convert_rgb) 1883 vdsc_cfg->convert_rgb = 1884 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1885 DP_DSC_RGB; 1886 1887 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, 1888 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); 1889 if (!vdsc_cfg->line_buf_depth) { 1890 drm_dbg_kms(display->drm, 1891 "DSC Sink Line Buffer Depth invalid\n"); 1892 return -EINVAL; 1893 } 1894 1895 vdsc_cfg->block_pred_enable = 1896 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1897 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1898 1899 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1900 } 1901 1902 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1903 enum intel_output_format output_format) 1904 { 1905 struct intel_display *display = to_intel_display(connector); 1906 u8 sink_dsc_format; 1907 1908 switch (output_format) { 1909 case INTEL_OUTPUT_FORMAT_RGB: 1910 sink_dsc_format = DP_DSC_RGB; 1911 break; 1912 case INTEL_OUTPUT_FORMAT_YCBCR444: 1913 sink_dsc_format = DP_DSC_YCbCr444; 1914 break; 1915 case INTEL_OUTPUT_FORMAT_YCBCR420: 1916 if (min(intel_dp_source_dsc_version_minor(display), 1917 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1918 return false; 1919 sink_dsc_format = DP_DSC_YCbCr420_Native; 1920 break; 1921 default: 1922 return false; 1923 } 1924 1925 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1926 } 1927 1928 static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, 1929 u32 lane_count, u32 mode_clock, 1930 enum intel_output_format output_format, 1931 int timeslots) 1932 { 1933 u32 available_bw, required_bw; 1934 1935 available_bw = (link_clock * lane_count * timeslots * 16) / 8; 1936 required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); 1937 1938 return available_bw > required_bw; 1939 } 1940 1941 static int dsc_compute_link_config(struct intel_dp *intel_dp, 1942 struct intel_crtc_state *pipe_config, 1943 struct drm_connector_state *conn_state, 1944 const struct link_config_limits *limits, 1945 int dsc_bpp_x16, 1946 int timeslots) 1947 { 1948 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1949 int link_rate, lane_count; 1950 int i; 1951 1952 for (i = 0; i < intel_dp->num_common_rates; i++) { 1953 link_rate = intel_dp_common_rate(intel_dp, i); 1954 if (link_rate < limits->min_rate || link_rate > limits->max_rate) 1955 continue; 1956 1957 for (lane_count = limits->min_lane_count; 1958 lane_count <= limits->max_lane_count; 1959 lane_count <<= 1) { 1960 1961 /* 1962 * FIXME: intel_dp_mtp_tu_compute_config() requires 1963 * ->lane_count and ->port_clock set before we know 1964 * they'll work. If we end up failing altogether, 1965 * they'll remain in crtc state. This shouldn't matter, 1966 * as we'd then bail out from compute config, but it's 1967 * just ugly. 1968 */ 1969 pipe_config->lane_count = lane_count; 1970 pipe_config->port_clock = link_rate; 1971 1972 if (drm_dp_is_uhbr_rate(link_rate)) { 1973 int ret; 1974 1975 ret = intel_dp_mtp_tu_compute_config(intel_dp, 1976 pipe_config, 1977 conn_state, 1978 dsc_bpp_x16, 1979 dsc_bpp_x16, 1980 0, true); 1981 if (ret) 1982 continue; 1983 } else { 1984 if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, 1985 lane_count, adjusted_mode->clock, 1986 pipe_config->output_format, 1987 timeslots)) 1988 continue; 1989 } 1990 1991 return 0; 1992 } 1993 } 1994 1995 return -EINVAL; 1996 } 1997 1998 static 1999 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 2000 const struct intel_crtc_state *pipe_config, 2001 int bpc) 2002 { 2003 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 2004 2005 if (max_bppx16) 2006 return max_bppx16; 2007 /* 2008 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 2009 * values as given in spec Table 2-157 DP v2.0 2010 */ 2011 switch (pipe_config->output_format) { 2012 case INTEL_OUTPUT_FORMAT_RGB: 2013 case INTEL_OUTPUT_FORMAT_YCBCR444: 2014 return (3 * bpc) << 4; 2015 case INTEL_OUTPUT_FORMAT_YCBCR420: 2016 return (3 * (bpc / 2)) << 4; 2017 default: 2018 MISSING_CASE(pipe_config->output_format); 2019 break; 2020 } 2021 2022 return 0; 2023 } 2024 2025 int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config) 2026 { 2027 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 2028 switch (pipe_config->output_format) { 2029 case INTEL_OUTPUT_FORMAT_RGB: 2030 case INTEL_OUTPUT_FORMAT_YCBCR444: 2031 return 8; 2032 case INTEL_OUTPUT_FORMAT_YCBCR420: 2033 return 6; 2034 default: 2035 MISSING_CASE(pipe_config->output_format); 2036 break; 2037 } 2038 2039 return 0; 2040 } 2041 2042 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 2043 const struct intel_crtc_state *pipe_config, 2044 int bpc) 2045 { 2046 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 2047 pipe_config, bpc) >> 4; 2048 } 2049 2050 static int dsc_src_min_compressed_bpp(void) 2051 { 2052 /* Min Compressed bpp supported by source is 8 */ 2053 return 8; 2054 } 2055 2056 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 2057 { 2058 struct intel_display *display = to_intel_display(intel_dp); 2059 2060 /* 2061 * Forcing DSC and using the platform's max compressed bpp is seen to cause 2062 * underruns. Since DSC isn't needed in these cases, limit the 2063 * max compressed bpp to 18, which is a safe value across platforms with different 2064 * pipe bpps. 2065 */ 2066 if (intel_dp->force_dsc_en) 2067 return 18; 2068 2069 /* 2070 * Max Compressed bpp for Gen 13+ is 27bpp. 2071 * For earlier platform is 23bpp. (Bspec:49259). 2072 */ 2073 if (DISPLAY_VER(display) < 13) 2074 return 23; 2075 else 2076 return 27; 2077 } 2078 2079 /* 2080 * Note: for pre-13 display you still need to check the validity of each step. 2081 */ 2082 static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) 2083 { 2084 struct intel_display *display = to_intel_display(connector); 2085 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); 2086 2087 if (DISPLAY_VER(display) < 14 || !incr) 2088 return fxp_q4_from_int(1); 2089 2090 /* fxp q4 */ 2091 return fxp_q4_from_int(1) / incr; 2092 } 2093 2094 /* Note: This is not universally usable! */ 2095 static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16) 2096 { 2097 struct intel_display *display = to_intel_display(intel_dp); 2098 int i; 2099 2100 if (DISPLAY_VER(display) >= 13) { 2101 if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) 2102 return false; 2103 2104 return true; 2105 } 2106 2107 if (fxp_q4_to_frac(bpp_x16)) 2108 return false; 2109 2110 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 2111 if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) 2112 return true; 2113 } 2114 2115 return false; 2116 } 2117 2118 /* 2119 * Find the max compressed BPP we can find a link configuration for. The BPPs to 2120 * try depend on the source (platform) and sink. 2121 */ 2122 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 2123 struct intel_crtc_state *pipe_config, 2124 struct drm_connector_state *conn_state, 2125 const struct link_config_limits *limits, 2126 int pipe_bpp, 2127 int timeslots) 2128 { 2129 struct intel_display *display = to_intel_display(intel_dp); 2130 const struct intel_connector *connector = to_intel_connector(conn_state->connector); 2131 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2132 int output_bpp; 2133 int dsc_min_bpp; 2134 int dsc_max_bpp; 2135 int min_bpp_x16, max_bpp_x16, bpp_step_x16; 2136 int dsc_joiner_max_bpp; 2137 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2138 int bpp_x16; 2139 int ret; 2140 2141 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2142 2143 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, 2144 adjusted_mode->hdisplay, 2145 num_joined_pipes); 2146 dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2147 2148 /* FIXME: remove the round trip via integers */ 2149 min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2150 max_bpp_x16 = fxp_q4_from_int(dsc_max_bpp); 2151 2152 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2153 2154 /* Compressed BPP should be less than the Input DSC bpp */ 2155 output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); 2156 max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); 2157 2158 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { 2159 if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16)) 2160 continue; 2161 2162 ret = dsc_compute_link_config(intel_dp, 2163 pipe_config, 2164 conn_state, 2165 limits, 2166 bpp_x16, 2167 timeslots); 2168 if (ret == 0) { 2169 pipe_config->dsc.compressed_bpp_x16 = bpp_x16; 2170 if (intel_dp->force_dsc_fractional_bpp_en && 2171 fxp_q4_to_frac(bpp_x16)) 2172 drm_dbg_kms(display->drm, 2173 "Forcing DSC fractional bpp\n"); 2174 2175 return 0; 2176 } 2177 } 2178 2179 return -EINVAL; 2180 } 2181 2182 int intel_dp_dsc_min_src_input_bpc(void) 2183 { 2184 /* Min DSC Input BPC for ICL+ is 8 */ 2185 return 8; 2186 } 2187 2188 static 2189 bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits, 2190 int pipe_bpp) 2191 { 2192 return pipe_bpp >= limits->pipe.min_bpp && 2193 pipe_bpp <= limits->pipe.max_bpp; 2194 } 2195 2196 static 2197 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 2198 const struct link_config_limits *limits) 2199 { 2200 struct intel_display *display = to_intel_display(intel_dp); 2201 int forced_bpp; 2202 2203 if (!intel_dp->force_dsc_bpc) 2204 return 0; 2205 2206 forced_bpp = intel_dp->force_dsc_bpc * 3; 2207 2208 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) { 2209 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n", 2210 intel_dp->force_dsc_bpc); 2211 return forced_bpp; 2212 } 2213 2214 drm_dbg_kms(display->drm, 2215 "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 2216 intel_dp->force_dsc_bpc); 2217 2218 return 0; 2219 } 2220 2221 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2222 struct intel_crtc_state *pipe_config, 2223 struct drm_connector_state *conn_state, 2224 const struct link_config_limits *limits, 2225 int timeslots) 2226 { 2227 const struct intel_connector *connector = 2228 to_intel_connector(conn_state->connector); 2229 u8 dsc_bpc[3] = {}; 2230 int forced_bpp, pipe_bpp; 2231 int num_bpc, i, ret; 2232 2233 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2234 2235 if (forced_bpp) { 2236 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2237 limits, forced_bpp, timeslots); 2238 if (ret == 0) { 2239 pipe_config->pipe_bpp = forced_bpp; 2240 return 0; 2241 } 2242 } 2243 2244 /* 2245 * Get the maximum DSC bpc that will be supported by any valid 2246 * link configuration and compressed bpp. 2247 */ 2248 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); 2249 for (i = 0; i < num_bpc; i++) { 2250 pipe_bpp = dsc_bpc[i] * 3; 2251 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) 2252 continue; 2253 2254 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2255 limits, pipe_bpp, timeslots); 2256 if (ret == 0) { 2257 pipe_config->pipe_bpp = pipe_bpp; 2258 return 0; 2259 } 2260 } 2261 2262 return -EINVAL; 2263 } 2264 2265 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2266 struct intel_crtc_state *pipe_config, 2267 struct drm_connector_state *conn_state, 2268 const struct link_config_limits *limits) 2269 { 2270 struct intel_display *display = to_intel_display(intel_dp); 2271 struct intel_connector *connector = 2272 to_intel_connector(conn_state->connector); 2273 int pipe_bpp, forced_bpp; 2274 int dsc_min_bpp; 2275 int dsc_max_bpp; 2276 2277 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2278 2279 if (forced_bpp) { 2280 pipe_bpp = forced_bpp; 2281 } else { 2282 int max_bpc = limits->pipe.max_bpp / 3; 2283 2284 /* For eDP use max bpp that can be supported with DSC. */ 2285 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); 2286 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { 2287 drm_dbg_kms(display->drm, 2288 "Computed BPC is not in DSC BPC limits\n"); 2289 return -EINVAL; 2290 } 2291 } 2292 pipe_config->port_clock = limits->max_rate; 2293 pipe_config->lane_count = limits->max_lane_count; 2294 2295 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2296 2297 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 2298 2299 /* Compressed BPP should be less than the Input DSC bpp */ 2300 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2301 2302 pipe_config->dsc.compressed_bpp_x16 = 2303 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); 2304 2305 pipe_config->pipe_bpp = pipe_bpp; 2306 2307 return 0; 2308 } 2309 2310 static void intel_dp_fec_compute_config(struct intel_dp *intel_dp, 2311 struct intel_crtc_state *crtc_state) 2312 { 2313 if (crtc_state->fec_enable) 2314 return; 2315 2316 /* 2317 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. 2318 * Since, FEC is a bandwidth overhead, continue to not enable it for 2319 * eDP. Until, there is a good reason to do so. 2320 */ 2321 if (intel_dp_is_edp(intel_dp)) 2322 return; 2323 2324 if (intel_dp_is_uhbr(crtc_state)) 2325 return; 2326 2327 crtc_state->fec_enable = true; 2328 } 2329 2330 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2331 struct intel_crtc_state *pipe_config, 2332 struct drm_connector_state *conn_state, 2333 const struct link_config_limits *limits, 2334 int timeslots) 2335 { 2336 struct intel_display *display = to_intel_display(intel_dp); 2337 const struct intel_connector *connector = 2338 to_intel_connector(conn_state->connector); 2339 const struct drm_display_mode *adjusted_mode = 2340 &pipe_config->hw.adjusted_mode; 2341 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2342 bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); 2343 int ret; 2344 2345 intel_dp_fec_compute_config(intel_dp, pipe_config); 2346 2347 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2348 return -EINVAL; 2349 2350 /* 2351 * Link parameters, pipe bpp and compressed bpp have already been 2352 * figured out for DP MST DSC. 2353 */ 2354 if (!is_mst) { 2355 if (intel_dp_is_edp(intel_dp)) 2356 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2357 conn_state, limits); 2358 else 2359 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2360 conn_state, limits, timeslots); 2361 if (ret) { 2362 drm_dbg_kms(display->drm, 2363 "No Valid pipe bpp for given mode ret = %d\n", ret); 2364 return ret; 2365 } 2366 } 2367 2368 /* Calculate Slice count */ 2369 if (intel_dp_is_edp(intel_dp)) { 2370 pipe_config->dsc.slice_count = 2371 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 2372 true); 2373 if (!pipe_config->dsc.slice_count) { 2374 drm_dbg_kms(display->drm, 2375 "Unsupported Slice Count %d\n", 2376 pipe_config->dsc.slice_count); 2377 return -EINVAL; 2378 } 2379 } else { 2380 u8 dsc_dp_slice_count; 2381 2382 dsc_dp_slice_count = 2383 intel_dp_dsc_get_slice_count(connector, 2384 adjusted_mode->crtc_clock, 2385 adjusted_mode->crtc_hdisplay, 2386 num_joined_pipes); 2387 if (!dsc_dp_slice_count) { 2388 drm_dbg_kms(display->drm, 2389 "Compressed Slice Count not supported\n"); 2390 return -EINVAL; 2391 } 2392 2393 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2394 } 2395 /* 2396 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2397 * is greater than the maximum Cdclock and if slice count is even 2398 * then we need to use 2 VDSC instances. 2399 * In case of Ultrajoiner along with 12 slices we need to use 3 2400 * VDSC instances. 2401 */ 2402 if (pipe_config->joiner_pipes && num_joined_pipes == 4 && 2403 pipe_config->dsc.slice_count == 12) 2404 pipe_config->dsc.num_streams = 3; 2405 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2406 pipe_config->dsc.num_streams = 2; 2407 else 2408 pipe_config->dsc.num_streams = 1; 2409 2410 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2411 if (ret < 0) { 2412 drm_dbg_kms(display->drm, 2413 "Cannot compute valid DSC parameters for Input Bpp = %d" 2414 "Compressed BPP = " FXP_Q4_FMT "\n", 2415 pipe_config->pipe_bpp, 2416 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2417 return ret; 2418 } 2419 2420 pipe_config->dsc.compression_enable = true; 2421 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d " 2422 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2423 pipe_config->pipe_bpp, 2424 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2425 pipe_config->dsc.slice_count); 2426 2427 return 0; 2428 } 2429 2430 /* 2431 * Calculate the output link min, max bpp values in limits based on the pipe bpp 2432 * range, crtc_state and dsc mode. Return true on success. 2433 */ 2434 static bool 2435 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 2436 const struct intel_connector *connector, 2437 const struct intel_crtc_state *crtc_state, 2438 bool dsc, 2439 struct link_config_limits *limits) 2440 { 2441 struct intel_display *display = to_intel_display(intel_dp); 2442 const struct drm_display_mode *adjusted_mode = 2443 &crtc_state->hw.adjusted_mode; 2444 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2445 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2446 int max_link_bpp_x16; 2447 2448 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2449 fxp_q4_from_int(limits->pipe.max_bpp)); 2450 2451 if (!dsc) { 2452 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2453 2454 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2455 return false; 2456 2457 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2458 } else { 2459 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2460 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2461 2462 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2463 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); 2464 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2465 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2466 2467 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2468 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2469 crtc_state, 2470 limits->pipe.max_bpp / 3); 2471 dsc_max_bpp = dsc_sink_max_bpp ? 2472 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2473 2474 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); 2475 } 2476 2477 limits->link.max_bpp_x16 = max_link_bpp_x16; 2478 2479 drm_dbg_kms(display->drm, 2480 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2481 encoder->base.base.id, encoder->base.name, 2482 crtc->base.base.id, crtc->base.name, 2483 adjusted_mode->crtc_clock, 2484 str_on_off(dsc), 2485 limits->max_lane_count, 2486 limits->max_rate, 2487 limits->pipe.max_bpp, 2488 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2489 2490 return true; 2491 } 2492 2493 static void 2494 intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp, 2495 struct link_config_limits *limits) 2496 { 2497 struct intel_display *display = to_intel_display(intel_dp); 2498 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); 2499 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 2500 2501 limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2502 limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2503 } 2504 2505 bool 2506 intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2507 struct intel_crtc_state *crtc_state, 2508 bool respect_downstream_limits, 2509 bool dsc, 2510 struct link_config_limits *limits) 2511 { 2512 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2513 2514 limits->min_rate = intel_dp_min_link_rate(intel_dp); 2515 limits->max_rate = intel_dp_max_link_rate(intel_dp); 2516 2517 limits->min_rate = min(limits->min_rate, limits->max_rate); 2518 2519 limits->min_lane_count = intel_dp_min_lane_count(intel_dp); 2520 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2521 2522 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2523 if (is_mst) { 2524 /* 2525 * FIXME: If all the streams can't fit into the link with their 2526 * current pipe_bpp we should reduce pipe_bpp across the board 2527 * until things start to fit. Until then we limit to <= 8bpc 2528 * since that's what was hardcoded for all MST streams 2529 * previously. This hack should be removed once we have the 2530 * proper retry logic in place. 2531 */ 2532 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24); 2533 } else { 2534 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2535 respect_downstream_limits); 2536 } 2537 2538 if (dsc) 2539 intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits); 2540 2541 if (is_mst || intel_dp->use_max_params) { 2542 /* 2543 * For MST we always configure max link bw - the spec doesn't 2544 * seem to suggest we should do otherwise. 2545 * 2546 * Use the maximum clock and number of lanes the eDP panel 2547 * advertizes being capable of in case the initial fast 2548 * optimal params failed us. The panels are generally 2549 * designed to support only a single clock and lane 2550 * configuration, and typically on older panels these 2551 * values correspond to the native resolution of the panel. 2552 */ 2553 limits->min_lane_count = limits->max_lane_count; 2554 limits->min_rate = limits->max_rate; 2555 } 2556 2557 intel_dp_test_compute_config(intel_dp, crtc_state, limits); 2558 2559 return intel_dp_compute_config_link_bpp_limits(intel_dp, 2560 intel_dp->attached_connector, 2561 crtc_state, 2562 dsc, 2563 limits); 2564 } 2565 2566 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) 2567 { 2568 const struct drm_display_mode *adjusted_mode = 2569 &crtc_state->hw.adjusted_mode; 2570 int bpp = crtc_state->dsc.compression_enable ? 2571 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2572 crtc_state->pipe_bpp; 2573 2574 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2575 } 2576 2577 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 2578 int num_joined_pipes) 2579 { 2580 /* 2581 * Pipe joiner needs compression up to display 12 due to bandwidth 2582 * limitation. DG2 onwards pipe joiner can be enabled without 2583 * compression. 2584 * Ultrajoiner always needs compression. 2585 */ 2586 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) || 2587 num_joined_pipes == 4; 2588 } 2589 2590 static int 2591 intel_dp_compute_link_config(struct intel_encoder *encoder, 2592 struct intel_crtc_state *pipe_config, 2593 struct drm_connector_state *conn_state, 2594 bool respect_downstream_limits) 2595 { 2596 struct intel_display *display = to_intel_display(encoder); 2597 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2598 struct intel_connector *connector = 2599 to_intel_connector(conn_state->connector); 2600 const struct drm_display_mode *adjusted_mode = 2601 &pipe_config->hw.adjusted_mode; 2602 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2603 struct link_config_limits limits; 2604 bool dsc_needed, joiner_needs_dsc; 2605 int num_joined_pipes; 2606 int ret = 0; 2607 2608 if (pipe_config->fec_enable && 2609 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) 2610 return -EINVAL; 2611 2612 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 2613 adjusted_mode->crtc_hdisplay, 2614 adjusted_mode->crtc_clock); 2615 if (num_joined_pipes > 1) 2616 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe); 2617 2618 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); 2619 2620 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2621 !intel_dp_compute_config_limits(intel_dp, pipe_config, 2622 respect_downstream_limits, 2623 false, 2624 &limits); 2625 2626 if (!dsc_needed) { 2627 /* 2628 * Optimize for slow and wide for everything, because there are some 2629 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2630 */ 2631 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2632 conn_state, &limits); 2633 if (!ret && intel_dp_is_uhbr(pipe_config)) 2634 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2635 pipe_config, 2636 conn_state, 2637 fxp_q4_from_int(pipe_config->pipe_bpp), 2638 fxp_q4_from_int(pipe_config->pipe_bpp), 2639 0, false); 2640 if (ret) 2641 dsc_needed = true; 2642 } 2643 2644 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) { 2645 drm_dbg_kms(display->drm, "DSC required but not available\n"); 2646 return -EINVAL; 2647 } 2648 2649 if (dsc_needed) { 2650 drm_dbg_kms(display->drm, 2651 "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2652 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2653 str_yes_no(intel_dp->force_dsc_en)); 2654 2655 if (!intel_dp_compute_config_limits(intel_dp, pipe_config, 2656 respect_downstream_limits, 2657 true, 2658 &limits)) 2659 return -EINVAL; 2660 2661 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2662 conn_state, &limits, 64); 2663 if (ret < 0) 2664 return ret; 2665 } 2666 2667 drm_dbg_kms(display->drm, 2668 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", 2669 pipe_config->lane_count, pipe_config->port_clock, 2670 pipe_config->pipe_bpp, 2671 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2672 intel_dp_config_required_rate(pipe_config), 2673 intel_dp_max_link_data_rate(intel_dp, 2674 pipe_config->port_clock, 2675 pipe_config->lane_count)); 2676 2677 return 0; 2678 } 2679 2680 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2681 const struct drm_connector_state *conn_state) 2682 { 2683 const struct intel_digital_connector_state *intel_conn_state = 2684 to_intel_digital_connector_state(conn_state); 2685 const struct drm_display_mode *adjusted_mode = 2686 &crtc_state->hw.adjusted_mode; 2687 2688 /* 2689 * Our YCbCr output is always limited range. 2690 * crtc_state->limited_color_range only applies to RGB, 2691 * and it must never be set for YCbCr or we risk setting 2692 * some conflicting bits in TRANSCONF which will mess up 2693 * the colors on the monitor. 2694 */ 2695 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2696 return false; 2697 2698 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2699 /* 2700 * See: 2701 * CEA-861-E - 5.1 Default Encoding Parameters 2702 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2703 */ 2704 return crtc_state->pipe_bpp != 18 && 2705 drm_default_rgb_quant_range(adjusted_mode) == 2706 HDMI_QUANTIZATION_RANGE_LIMITED; 2707 } else { 2708 return intel_conn_state->broadcast_rgb == 2709 INTEL_BROADCAST_RGB_LIMITED; 2710 } 2711 } 2712 2713 static bool intel_dp_port_has_audio(struct intel_display *display, enum port port) 2714 { 2715 if (display->platform.g4x) 2716 return false; 2717 if (DISPLAY_VER(display) < 12 && port == PORT_A) 2718 return false; 2719 2720 return true; 2721 } 2722 2723 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2724 const struct drm_connector_state *conn_state, 2725 struct drm_dp_vsc_sdp *vsc) 2726 { 2727 struct intel_display *display = to_intel_display(crtc_state); 2728 2729 if (crtc_state->has_panel_replay) { 2730 /* 2731 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2732 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel 2733 * Encoding/Colorimetry Format indication. 2734 */ 2735 vsc->revision = 0x7; 2736 } else { 2737 /* 2738 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2739 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2740 * Colorimetry Format indication. 2741 */ 2742 vsc->revision = 0x5; 2743 } 2744 2745 vsc->length = 0x13; 2746 2747 /* DP 1.4a spec, Table 2-120 */ 2748 switch (crtc_state->output_format) { 2749 case INTEL_OUTPUT_FORMAT_YCBCR444: 2750 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2751 break; 2752 case INTEL_OUTPUT_FORMAT_YCBCR420: 2753 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2754 break; 2755 case INTEL_OUTPUT_FORMAT_RGB: 2756 default: 2757 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2758 } 2759 2760 switch (conn_state->colorspace) { 2761 case DRM_MODE_COLORIMETRY_BT709_YCC: 2762 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2763 break; 2764 case DRM_MODE_COLORIMETRY_XVYCC_601: 2765 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2766 break; 2767 case DRM_MODE_COLORIMETRY_XVYCC_709: 2768 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2769 break; 2770 case DRM_MODE_COLORIMETRY_SYCC_601: 2771 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2772 break; 2773 case DRM_MODE_COLORIMETRY_OPYCC_601: 2774 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2775 break; 2776 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2777 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2778 break; 2779 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2780 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2781 break; 2782 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2783 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2784 break; 2785 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2786 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2787 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2788 break; 2789 default: 2790 /* 2791 * RGB->YCBCR color conversion uses the BT.709 2792 * color space. 2793 */ 2794 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2795 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2796 else 2797 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2798 break; 2799 } 2800 2801 vsc->bpc = crtc_state->pipe_bpp / 3; 2802 2803 /* only RGB pixelformat supports 6 bpc */ 2804 drm_WARN_ON(display->drm, 2805 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2806 2807 /* all YCbCr are always limited range */ 2808 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2809 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2810 } 2811 2812 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, 2813 struct intel_crtc_state *crtc_state) 2814 { 2815 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; 2816 const struct drm_display_mode *adjusted_mode = 2817 &crtc_state->hw.adjusted_mode; 2818 2819 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) 2820 return; 2821 2822 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 2823 2824 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; 2825 as_sdp->length = 0x9; 2826 as_sdp->duration_incr_ms = 0; 2827 as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state); 2828 2829 if (crtc_state->cmrr.enable) { 2830 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; 2831 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); 2832 as_sdp->target_rr_divider = true; 2833 } else { 2834 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL; 2835 as_sdp->target_rr = 0; 2836 } 2837 } 2838 2839 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2840 struct intel_crtc_state *crtc_state, 2841 const struct drm_connector_state *conn_state) 2842 { 2843 struct drm_dp_vsc_sdp *vsc; 2844 2845 if ((!intel_dp->colorimetry_support || 2846 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && 2847 !crtc_state->has_psr) 2848 return; 2849 2850 vsc = &crtc_state->infoframes.vsc; 2851 2852 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2853 vsc->sdp_type = DP_SDP_VSC; 2854 2855 /* Needs colorimetry */ 2856 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 2857 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2858 vsc); 2859 } else if (crtc_state->has_panel_replay) { 2860 /* 2861 * [Panel Replay without colorimetry info] 2862 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2863 * VSC SDP supporting 3D stereo + Panel Replay. 2864 */ 2865 vsc->revision = 0x6; 2866 vsc->length = 0x10; 2867 } else if (crtc_state->has_sel_update) { 2868 /* 2869 * [PSR2 without colorimetry] 2870 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 2871 * 3D stereo + PSR/PSR2 + Y-coordinate. 2872 */ 2873 vsc->revision = 0x4; 2874 vsc->length = 0xe; 2875 } else { 2876 /* 2877 * [PSR1] 2878 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2879 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 2880 * higher). 2881 */ 2882 vsc->revision = 0x2; 2883 vsc->length = 0x8; 2884 } 2885 } 2886 2887 static void 2888 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 2889 struct intel_crtc_state *crtc_state, 2890 const struct drm_connector_state *conn_state) 2891 { 2892 struct intel_display *display = to_intel_display(intel_dp); 2893 int ret; 2894 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 2895 2896 if (!conn_state->hdr_output_metadata) 2897 return; 2898 2899 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 2900 2901 if (ret) { 2902 drm_dbg_kms(display->drm, 2903 "couldn't set HDR metadata in infoframe\n"); 2904 return; 2905 } 2906 2907 crtc_state->infoframes.enable |= 2908 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2909 } 2910 2911 static bool can_enable_drrs(struct intel_connector *connector, 2912 const struct intel_crtc_state *pipe_config, 2913 const struct drm_display_mode *downclock_mode) 2914 { 2915 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2916 2917 if (pipe_config->vrr.enable) 2918 return false; 2919 2920 /* 2921 * DRRS and PSR can't be enable together, so giving preference to PSR 2922 * as it allows more power-savings by complete shutting down display, 2923 * so to guarantee this, intel_drrs_compute_config() must be called 2924 * after intel_psr_compute_config(). 2925 */ 2926 if (pipe_config->has_psr) 2927 return false; 2928 2929 /* FIXME missing FDI M2/N2 etc. */ 2930 if (pipe_config->has_pch_encoder) 2931 return false; 2932 2933 if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) 2934 return false; 2935 2936 return downclock_mode && 2937 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 2938 } 2939 2940 static void 2941 intel_dp_drrs_compute_config(struct intel_connector *connector, 2942 struct intel_crtc_state *pipe_config, 2943 int link_bpp_x16) 2944 { 2945 struct intel_display *display = to_intel_display(connector); 2946 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2947 const struct drm_display_mode *downclock_mode = 2948 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 2949 int pixel_clock; 2950 2951 /* 2952 * FIXME all joined pipes share the same transcoder. 2953 * Need to account for that when updating M/N live. 2954 */ 2955 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) 2956 pipe_config->update_m_n = true; 2957 2958 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 2959 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 2960 intel_zero_m_n(&pipe_config->dp_m2_n2); 2961 return; 2962 } 2963 2964 if (display->platform.ironlake || display->platform.sandybridge || 2965 display->platform.ivybridge) 2966 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 2967 2968 pipe_config->has_drrs = true; 2969 2970 pixel_clock = downclock_mode->clock; 2971 if (pipe_config->splitter.enable) 2972 pixel_clock /= pipe_config->splitter.link_count; 2973 2974 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, 2975 pipe_config->port_clock, 2976 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 2977 &pipe_config->dp_m2_n2); 2978 2979 /* FIXME: abstract this better */ 2980 if (pipe_config->splitter.enable) 2981 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 2982 } 2983 2984 static bool intel_dp_has_audio(struct intel_encoder *encoder, 2985 const struct drm_connector_state *conn_state) 2986 { 2987 struct intel_display *display = to_intel_display(encoder); 2988 const struct intel_digital_connector_state *intel_conn_state = 2989 to_intel_digital_connector_state(conn_state); 2990 struct intel_connector *connector = 2991 to_intel_connector(conn_state->connector); 2992 2993 if (!intel_dp_port_has_audio(display, encoder->port)) 2994 return false; 2995 2996 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2997 return connector->base.display_info.has_audio; 2998 else 2999 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 3000 } 3001 3002 static int 3003 intel_dp_compute_output_format(struct intel_encoder *encoder, 3004 struct intel_crtc_state *crtc_state, 3005 struct drm_connector_state *conn_state, 3006 bool respect_downstream_limits) 3007 { 3008 struct intel_display *display = to_intel_display(encoder); 3009 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3010 struct intel_connector *connector = intel_dp->attached_connector; 3011 const struct drm_display_info *info = &connector->base.display_info; 3012 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3013 bool ycbcr_420_only; 3014 int ret; 3015 3016 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 3017 3018 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { 3019 drm_dbg_kms(display->drm, 3020 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 3021 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 3022 } else { 3023 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); 3024 } 3025 3026 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 3027 3028 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3029 respect_downstream_limits); 3030 if (ret) { 3031 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3032 !connector->base.ycbcr_420_allowed || 3033 !drm_mode_is_420_also(info, adjusted_mode)) 3034 return ret; 3035 3036 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 3037 crtc_state->output_format = intel_dp_output_format(connector, 3038 crtc_state->sink_format); 3039 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3040 respect_downstream_limits); 3041 } 3042 3043 return ret; 3044 } 3045 3046 void 3047 intel_dp_audio_compute_config(struct intel_encoder *encoder, 3048 struct intel_crtc_state *pipe_config, 3049 struct drm_connector_state *conn_state) 3050 { 3051 pipe_config->has_audio = 3052 intel_dp_has_audio(encoder, conn_state) && 3053 intel_audio_compute_config(encoder, pipe_config, conn_state); 3054 3055 pipe_config->sdp_split_enable = pipe_config->has_audio && 3056 intel_dp_is_uhbr(pipe_config); 3057 } 3058 3059 void 3060 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 3061 struct intel_encoder *encoder, 3062 const struct intel_crtc_state *crtc_state) 3063 { 3064 struct intel_connector *connector; 3065 struct intel_digital_connector_state *conn_state; 3066 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3067 int i; 3068 3069 if (intel_dp->needs_modeset_retry) 3070 return; 3071 3072 intel_dp->needs_modeset_retry = true; 3073 3074 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3075 intel_connector_queue_modeset_retry_work(intel_dp->attached_connector); 3076 3077 return; 3078 } 3079 3080 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 3081 if (!conn_state->base.crtc) 3082 continue; 3083 3084 if (connector->mst_port == intel_dp) 3085 intel_connector_queue_modeset_retry_work(connector); 3086 } 3087 } 3088 3089 int 3090 intel_dp_compute_config(struct intel_encoder *encoder, 3091 struct intel_crtc_state *pipe_config, 3092 struct drm_connector_state *conn_state) 3093 { 3094 struct intel_display *display = to_intel_display(encoder); 3095 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 3096 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 3097 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3098 const struct drm_display_mode *fixed_mode; 3099 struct intel_connector *connector = intel_dp->attached_connector; 3100 int ret = 0, link_bpp_x16; 3101 3102 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 3103 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 3104 ret = intel_panel_compute_config(connector, adjusted_mode); 3105 if (ret) 3106 return ret; 3107 } 3108 3109 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 3110 return -EINVAL; 3111 3112 if (!connector->base.interlace_allowed && 3113 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 3114 return -EINVAL; 3115 3116 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 3117 return -EINVAL; 3118 3119 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay)) 3120 return -EINVAL; 3121 3122 /* 3123 * Try to respect downstream TMDS clock limits first, if 3124 * that fails assume the user might know something we don't. 3125 */ 3126 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); 3127 if (ret) 3128 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); 3129 if (ret) 3130 return ret; 3131 3132 if ((intel_dp_is_edp(intel_dp) && fixed_mode) || 3133 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3134 ret = intel_panel_fitting(pipe_config, conn_state); 3135 if (ret) 3136 return ret; 3137 } 3138 3139 pipe_config->limited_color_range = 3140 intel_dp_limited_color_range(pipe_config, conn_state); 3141 3142 if (intel_dp_is_uhbr(pipe_config)) { 3143 /* 128b/132b SST also needs this */ 3144 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder; 3145 } else { 3146 pipe_config->enhanced_framing = 3147 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3148 } 3149 3150 if (pipe_config->dsc.compression_enable) 3151 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3152 else 3153 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3154 pipe_config->pipe_bpp)); 3155 3156 if (intel_dp->mso_link_count) { 3157 int n = intel_dp->mso_link_count; 3158 int overlap = intel_dp->mso_pixel_overlap; 3159 3160 pipe_config->splitter.enable = true; 3161 pipe_config->splitter.link_count = n; 3162 pipe_config->splitter.pixel_overlap = overlap; 3163 3164 drm_dbg_kms(display->drm, 3165 "MSO link count %d, pixel overlap %d\n", 3166 n, overlap); 3167 3168 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 3169 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 3170 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 3171 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 3172 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 3173 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 3174 adjusted_mode->crtc_clock /= n; 3175 } 3176 3177 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 3178 3179 if (!intel_dp_is_uhbr(pipe_config)) { 3180 intel_link_compute_m_n(link_bpp_x16, 3181 pipe_config->lane_count, 3182 adjusted_mode->crtc_clock, 3183 pipe_config->port_clock, 3184 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3185 &pipe_config->dp_m_n); 3186 } 3187 3188 /* FIXME: abstract this better */ 3189 if (pipe_config->splitter.enable) 3190 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3191 3192 intel_vrr_compute_config(pipe_config, conn_state); 3193 intel_dp_compute_as_sdp(intel_dp, pipe_config); 3194 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 3195 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); 3196 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); 3197 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 3198 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 3199 3200 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, 3201 pipe_config); 3202 } 3203 3204 void intel_dp_set_link_params(struct intel_dp *intel_dp, 3205 int link_rate, int lane_count) 3206 { 3207 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3208 intel_dp->link_trained = false; 3209 intel_dp->needs_modeset_retry = false; 3210 intel_dp->link_rate = link_rate; 3211 intel_dp->lane_count = lane_count; 3212 } 3213 3214 void intel_dp_reset_link_params(struct intel_dp *intel_dp) 3215 { 3216 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); 3217 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); 3218 intel_dp->link.mst_probed_lane_count = 0; 3219 intel_dp->link.mst_probed_rate = 0; 3220 intel_dp->link.retrain_disabled = false; 3221 intel_dp->link.seq_train_failures = 0; 3222 } 3223 3224 /* Enable backlight PWM and backlight PP control. */ 3225 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3226 const struct drm_connector_state *conn_state) 3227 { 3228 struct intel_display *display = to_intel_display(crtc_state); 3229 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3230 3231 if (!intel_dp_is_edp(intel_dp)) 3232 return; 3233 3234 drm_dbg_kms(display->drm, "\n"); 3235 3236 intel_backlight_enable(crtc_state, conn_state); 3237 intel_pps_backlight_on(intel_dp); 3238 } 3239 3240 /* Disable backlight PP control and backlight PWM. */ 3241 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3242 { 3243 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3244 struct intel_display *display = to_intel_display(intel_dp); 3245 3246 if (!intel_dp_is_edp(intel_dp)) 3247 return; 3248 3249 drm_dbg_kms(display->drm, "\n"); 3250 3251 intel_pps_backlight_off(intel_dp); 3252 intel_backlight_disable(old_conn_state); 3253 } 3254 3255 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3256 { 3257 /* 3258 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3259 * be capable of signalling downstream hpd with a long pulse. 3260 * Whether or not that means D3 is safe to use is not clear, 3261 * but let's assume so until proven otherwise. 3262 * 3263 * FIXME should really check all downstream ports... 3264 */ 3265 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3266 drm_dp_is_branch(intel_dp->dpcd) && 3267 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3268 } 3269 3270 static int 3271 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) 3272 { 3273 int err; 3274 u8 val; 3275 3276 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); 3277 if (err < 0) 3278 return err; 3279 3280 if (set) 3281 val |= flag; 3282 else 3283 val &= ~flag; 3284 3285 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); 3286 } 3287 3288 static void 3289 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, 3290 bool enable) 3291 { 3292 struct intel_display *display = to_intel_display(connector); 3293 3294 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, 3295 DP_DECOMPRESSION_EN, enable) < 0) 3296 drm_dbg_kms(display->drm, 3297 "Failed to %s sink decompression state\n", 3298 str_enable_disable(enable)); 3299 } 3300 3301 static void 3302 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, 3303 bool enable) 3304 { 3305 struct intel_display *display = to_intel_display(connector); 3306 struct drm_dp_aux *aux = connector->port ? 3307 connector->port->passthrough_aux : NULL; 3308 3309 if (!aux) 3310 return; 3311 3312 if (write_dsc_decompression_flag(aux, 3313 DP_DSC_PASSTHROUGH_EN, enable) < 0) 3314 drm_dbg_kms(display->drm, 3315 "Failed to %s sink compression passthrough state\n", 3316 str_enable_disable(enable)); 3317 } 3318 3319 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, 3320 const struct intel_connector *connector, 3321 bool for_get_ref) 3322 { 3323 struct intel_display *display = to_intel_display(state); 3324 struct drm_connector *_connector_iter; 3325 struct drm_connector_state *old_conn_state; 3326 struct drm_connector_state *new_conn_state; 3327 int ref_count = 0; 3328 int i; 3329 3330 /* 3331 * On SST the decompression AUX device won't be shared, each connector 3332 * uses for this its own AUX targeting the sink device. 3333 */ 3334 if (!connector->mst_port) 3335 return connector->dp.dsc_decompression_enabled ? 1 : 0; 3336 3337 for_each_oldnew_connector_in_state(&state->base, _connector_iter, 3338 old_conn_state, new_conn_state, i) { 3339 const struct intel_connector * 3340 connector_iter = to_intel_connector(_connector_iter); 3341 3342 if (connector_iter->mst_port != connector->mst_port) 3343 continue; 3344 3345 if (!connector_iter->dp.dsc_decompression_enabled) 3346 continue; 3347 3348 drm_WARN_ON(display->drm, 3349 (for_get_ref && !new_conn_state->crtc) || 3350 (!for_get_ref && !old_conn_state->crtc)); 3351 3352 if (connector_iter->dp.dsc_decompression_aux == 3353 connector->dp.dsc_decompression_aux) 3354 ref_count++; 3355 } 3356 3357 return ref_count; 3358 } 3359 3360 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, 3361 struct intel_connector *connector) 3362 { 3363 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; 3364 3365 connector->dp.dsc_decompression_enabled = true; 3366 3367 return ret; 3368 } 3369 3370 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, 3371 struct intel_connector *connector) 3372 { 3373 connector->dp.dsc_decompression_enabled = false; 3374 3375 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; 3376 } 3377 3378 /** 3379 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device 3380 * @state: atomic state 3381 * @connector: connector to enable the decompression for 3382 * @new_crtc_state: new state for the CRTC driving @connector 3383 * 3384 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3385 * register of the appropriate sink/branch device. On SST this is always the 3386 * sink device, whereas on MST based on each device's DSC capabilities it's 3387 * either the last branch device (enabling decompression in it) or both the 3388 * last branch device (enabling passthrough in it) and the sink device 3389 * (enabling decompression in it). 3390 */ 3391 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 3392 struct intel_connector *connector, 3393 const struct intel_crtc_state *new_crtc_state) 3394 { 3395 struct intel_display *display = to_intel_display(state); 3396 3397 if (!new_crtc_state->dsc.compression_enable) 3398 return; 3399 3400 if (drm_WARN_ON(display->drm, 3401 !connector->dp.dsc_decompression_aux || 3402 connector->dp.dsc_decompression_enabled)) 3403 return; 3404 3405 if (!intel_dp_dsc_aux_get_ref(state, connector)) 3406 return; 3407 3408 intel_dp_sink_set_dsc_passthrough(connector, true); 3409 intel_dp_sink_set_dsc_decompression(connector, true); 3410 } 3411 3412 /** 3413 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device 3414 * @state: atomic state 3415 * @connector: connector to disable the decompression for 3416 * @old_crtc_state: old state for the CRTC driving @connector 3417 * 3418 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3419 * register of the appropriate sink/branch device, corresponding to the 3420 * sequence in intel_dp_sink_enable_decompression(). 3421 */ 3422 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 3423 struct intel_connector *connector, 3424 const struct intel_crtc_state *old_crtc_state) 3425 { 3426 struct intel_display *display = to_intel_display(state); 3427 3428 if (!old_crtc_state->dsc.compression_enable) 3429 return; 3430 3431 if (drm_WARN_ON(display->drm, 3432 !connector->dp.dsc_decompression_aux || 3433 !connector->dp.dsc_decompression_enabled)) 3434 return; 3435 3436 if (!intel_dp_dsc_aux_put_ref(state, connector)) 3437 return; 3438 3439 intel_dp_sink_set_dsc_decompression(connector, false); 3440 intel_dp_sink_set_dsc_passthrough(connector, false); 3441 } 3442 3443 static void 3444 intel_dp_init_source_oui(struct intel_dp *intel_dp) 3445 { 3446 struct intel_display *display = to_intel_display(intel_dp); 3447 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3448 u8 buf[3] = {}; 3449 3450 if (READ_ONCE(intel_dp->oui_valid)) 3451 return; 3452 3453 WRITE_ONCE(intel_dp->oui_valid, true); 3454 3455 /* 3456 * During driver init, we want to be careful and avoid changing the source OUI if it's 3457 * already set to what we want, so as to avoid clearing any state by accident 3458 */ 3459 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3460 drm_dbg_kms(display->drm, "Failed to read source OUI\n"); 3461 3462 if (memcmp(oui, buf, sizeof(oui)) == 0) { 3463 /* Assume the OUI was written now. */ 3464 intel_dp->last_oui_write = jiffies; 3465 return; 3466 } 3467 3468 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { 3469 drm_dbg_kms(display->drm, "Failed to write source OUI\n"); 3470 WRITE_ONCE(intel_dp->oui_valid, false); 3471 } 3472 3473 intel_dp->last_oui_write = jiffies; 3474 } 3475 3476 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) 3477 { 3478 WRITE_ONCE(intel_dp->oui_valid, false); 3479 } 3480 3481 void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 3482 { 3483 struct intel_display *display = to_intel_display(intel_dp); 3484 struct intel_connector *connector = intel_dp->attached_connector; 3485 3486 drm_dbg_kms(display->drm, 3487 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 3488 connector->base.base.id, connector->base.name, 3489 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3490 3491 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 3492 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3493 } 3494 3495 /* If the device supports it, try to set the power state appropriately */ 3496 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3497 { 3498 struct intel_display *display = to_intel_display(intel_dp); 3499 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3500 int ret, i; 3501 3502 /* Should have a valid DPCD by this point */ 3503 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3504 return; 3505 3506 if (mode != DP_SET_POWER_D0) { 3507 if (downstream_hpd_needs_d0(intel_dp)) 3508 return; 3509 3510 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3511 } else { 3512 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3513 3514 intel_lspcon_resume(dig_port); 3515 3516 /* Write the source OUI as early as possible */ 3517 intel_dp_init_source_oui(intel_dp); 3518 3519 /* 3520 * When turning on, we need to retry for 1ms to give the sink 3521 * time to wake up. 3522 */ 3523 for (i = 0; i < 3; i++) { 3524 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3525 if (ret == 1) 3526 break; 3527 msleep(1); 3528 } 3529 3530 if (ret == 1 && intel_lspcon_active(dig_port)) 3531 intel_lspcon_wait_pcon_mode(dig_port); 3532 } 3533 3534 if (ret != 1) 3535 drm_dbg_kms(display->drm, 3536 "[ENCODER:%d:%s] Set power to %s failed\n", 3537 encoder->base.base.id, encoder->base.name, 3538 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3539 } 3540 3541 static bool 3542 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3543 3544 /** 3545 * intel_dp_sync_state - sync the encoder state during init/resume 3546 * @encoder: intel encoder to sync 3547 * @crtc_state: state for the CRTC connected to the encoder 3548 * 3549 * Sync any state stored in the encoder wrt. HW state during driver init 3550 * and system resume. 3551 */ 3552 void intel_dp_sync_state(struct intel_encoder *encoder, 3553 const struct intel_crtc_state *crtc_state) 3554 { 3555 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3556 bool dpcd_updated = false; 3557 3558 /* 3559 * Don't clobber DPCD if it's been already read out during output 3560 * setup (eDP) or detect. 3561 */ 3562 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { 3563 intel_dp_get_dpcd(intel_dp); 3564 dpcd_updated = true; 3565 } 3566 3567 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3568 3569 if (crtc_state) { 3570 intel_dp_reset_link_params(intel_dp); 3571 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3572 intel_dp->link_trained = true; 3573 } 3574 } 3575 3576 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3577 struct intel_crtc_state *crtc_state) 3578 { 3579 struct intel_display *display = to_intel_display(encoder); 3580 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3581 bool fastset = true; 3582 3583 /* 3584 * If BIOS has set an unsupported or non-standard link rate for some 3585 * reason force an encoder recompute and full modeset. 3586 */ 3587 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3588 crtc_state->port_clock) < 0) { 3589 drm_dbg_kms(display->drm, 3590 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3591 encoder->base.base.id, encoder->base.name); 3592 crtc_state->uapi.connectors_changed = true; 3593 fastset = false; 3594 } 3595 3596 /* 3597 * FIXME hack to force full modeset when DSC is being used. 3598 * 3599 * As long as we do not have full state readout and config comparison 3600 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3601 * Remove once we have readout for DSC. 3602 */ 3603 if (crtc_state->dsc.compression_enable) { 3604 drm_dbg_kms(display->drm, 3605 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3606 encoder->base.base.id, encoder->base.name); 3607 crtc_state->uapi.mode_changed = true; 3608 fastset = false; 3609 } 3610 3611 if (CAN_PANEL_REPLAY(intel_dp)) { 3612 drm_dbg_kms(display->drm, 3613 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n", 3614 encoder->base.base.id, encoder->base.name); 3615 crtc_state->uapi.mode_changed = true; 3616 fastset = false; 3617 } 3618 3619 return fastset; 3620 } 3621 3622 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3623 { 3624 struct intel_display *display = to_intel_display(intel_dp); 3625 3626 /* Clear the cached register set to avoid using stale values */ 3627 3628 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 3629 3630 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 3631 intel_dp->pcon_dsc_dpcd, 3632 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 3633 drm_err(display->drm, "Failed to read DPCD register 0x%x\n", 3634 DP_PCON_DSC_ENCODER); 3635 3636 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n", 3637 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 3638 } 3639 3640 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3641 { 3642 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3643 int i; 3644 3645 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 3646 if (frl_bw_mask & (1 << i)) 3647 return bw_gbps[i]; 3648 } 3649 return 0; 3650 } 3651 3652 static int intel_dp_pcon_set_frl_mask(int max_frl) 3653 { 3654 switch (max_frl) { 3655 case 48: 3656 return DP_PCON_FRL_BW_MASK_48GBPS; 3657 case 40: 3658 return DP_PCON_FRL_BW_MASK_40GBPS; 3659 case 32: 3660 return DP_PCON_FRL_BW_MASK_32GBPS; 3661 case 24: 3662 return DP_PCON_FRL_BW_MASK_24GBPS; 3663 case 18: 3664 return DP_PCON_FRL_BW_MASK_18GBPS; 3665 case 9: 3666 return DP_PCON_FRL_BW_MASK_9GBPS; 3667 } 3668 3669 return 0; 3670 } 3671 3672 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 3673 { 3674 struct intel_connector *connector = intel_dp->attached_connector; 3675 const struct drm_display_info *info = &connector->base.display_info; 3676 int max_frl_rate; 3677 int max_lanes, rate_per_lane; 3678 int max_dsc_lanes, dsc_rate_per_lane; 3679 3680 max_lanes = info->hdmi.max_lanes; 3681 rate_per_lane = info->hdmi.max_frl_rate_per_lane; 3682 max_frl_rate = max_lanes * rate_per_lane; 3683 3684 if (info->hdmi.dsc_cap.v_1p2) { 3685 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes; 3686 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane; 3687 if (max_dsc_lanes && dsc_rate_per_lane) 3688 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 3689 } 3690 3691 return max_frl_rate; 3692 } 3693 3694 static bool 3695 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 3696 u8 max_frl_bw_mask, u8 *frl_trained_mask) 3697 { 3698 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 3699 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 3700 *frl_trained_mask >= max_frl_bw_mask) 3701 return true; 3702 3703 return false; 3704 } 3705 3706 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 3707 { 3708 struct intel_display *display = to_intel_display(intel_dp); 3709 #define TIMEOUT_FRL_READY_MS 500 3710 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 3711 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 3712 u8 max_frl_bw_mask = 0, frl_trained_mask; 3713 bool is_active; 3714 3715 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 3716 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 3717 3718 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 3719 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n", 3720 max_edid_frl_bw); 3721 3722 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 3723 3724 if (max_frl_bw <= 0) 3725 return -EINVAL; 3726 3727 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 3728 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 3729 3730 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 3731 goto frl_trained; 3732 3733 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 3734 if (ret < 0) 3735 return ret; 3736 /* Wait for PCON to be FRL Ready */ 3737 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); 3738 3739 if (!is_active) 3740 return -ETIMEDOUT; 3741 3742 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 3743 DP_PCON_ENABLE_SEQUENTIAL_LINK); 3744 if (ret < 0) 3745 return ret; 3746 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 3747 DP_PCON_FRL_LINK_TRAIN_NORMAL); 3748 if (ret < 0) 3749 return ret; 3750 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 3751 if (ret < 0) 3752 return ret; 3753 /* 3754 * Wait for FRL to be completed 3755 * Check if the HDMI Link is up and active. 3756 */ 3757 wait_for(is_active = 3758 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 3759 TIMEOUT_HDMI_LINK_ACTIVE_MS); 3760 3761 if (!is_active) 3762 return -ETIMEDOUT; 3763 3764 frl_trained: 3765 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 3766 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 3767 intel_dp->frl.is_trained = true; 3768 drm_dbg(display->drm, "FRL trained with : %d Gbps\n", 3769 intel_dp->frl.trained_rate_gbps); 3770 3771 return 0; 3772 } 3773 3774 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 3775 { 3776 if (drm_dp_is_branch(intel_dp->dpcd) && 3777 intel_dp_has_hdmi_sink(intel_dp) && 3778 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 3779 return true; 3780 3781 return false; 3782 } 3783 3784 static 3785 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 3786 { 3787 int ret; 3788 u8 buf = 0; 3789 3790 /* Set PCON source control mode */ 3791 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 3792 3793 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3794 if (ret < 0) 3795 return ret; 3796 3797 /* Set HDMI LINK ENABLE */ 3798 buf |= DP_PCON_ENABLE_HDMI_LINK; 3799 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3800 if (ret < 0) 3801 return ret; 3802 3803 return 0; 3804 } 3805 3806 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 3807 { 3808 struct intel_display *display = to_intel_display(intel_dp); 3809 3810 /* 3811 * Always go for FRL training if: 3812 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 3813 * -sink is HDMI2.1 3814 */ 3815 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 3816 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 3817 intel_dp->frl.is_trained) 3818 return; 3819 3820 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 3821 int ret, mode; 3822 3823 drm_dbg(display->drm, 3824 "Couldn't set FRL mode, continuing with TMDS mode\n"); 3825 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 3826 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 3827 3828 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 3829 drm_dbg(display->drm, 3830 "Issue with PCON, cannot set TMDS mode\n"); 3831 } else { 3832 drm_dbg(display->drm, "FRL training Completed\n"); 3833 } 3834 } 3835 3836 static int 3837 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 3838 { 3839 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 3840 3841 return intel_hdmi_dsc_get_slice_height(vactive); 3842 } 3843 3844 static int 3845 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 3846 const struct intel_crtc_state *crtc_state) 3847 { 3848 struct intel_connector *connector = intel_dp->attached_connector; 3849 const struct drm_display_info *info = &connector->base.display_info; 3850 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice; 3851 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices; 3852 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 3853 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 3854 3855 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 3856 pcon_max_slice_width, 3857 hdmi_max_slices, hdmi_throughput); 3858 } 3859 3860 static int 3861 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 3862 const struct intel_crtc_state *crtc_state, 3863 int num_slices, int slice_width) 3864 { 3865 struct intel_connector *connector = intel_dp->attached_connector; 3866 const struct drm_display_info *info = &connector->base.display_info; 3867 int output_format = crtc_state->output_format; 3868 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp; 3869 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 3870 int hdmi_max_chunk_bytes = 3871 info->hdmi.dsc_cap.total_chunk_kbytes * 1024; 3872 3873 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 3874 num_slices, output_format, hdmi_all_bpp, 3875 hdmi_max_chunk_bytes); 3876 } 3877 3878 void 3879 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 3880 const struct intel_crtc_state *crtc_state) 3881 { 3882 struct intel_display *display = to_intel_display(intel_dp); 3883 struct intel_connector *connector = intel_dp->attached_connector; 3884 const struct drm_display_info *info; 3885 u8 pps_param[6]; 3886 int slice_height; 3887 int slice_width; 3888 int num_slices; 3889 int bits_per_pixel; 3890 int ret; 3891 bool hdmi_is_dsc_1_2; 3892 3893 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 3894 return; 3895 3896 if (!connector) 3897 return; 3898 3899 info = &connector->base.display_info; 3900 3901 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2; 3902 3903 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 3904 !hdmi_is_dsc_1_2) 3905 return; 3906 3907 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 3908 if (!slice_height) 3909 return; 3910 3911 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 3912 if (!num_slices) 3913 return; 3914 3915 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 3916 num_slices); 3917 3918 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 3919 num_slices, slice_width); 3920 if (!bits_per_pixel) 3921 return; 3922 3923 pps_param[0] = slice_height & 0xFF; 3924 pps_param[1] = slice_height >> 8; 3925 pps_param[2] = slice_width & 0xFF; 3926 pps_param[3] = slice_width >> 8; 3927 pps_param[4] = bits_per_pixel & 0xFF; 3928 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 3929 3930 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 3931 if (ret < 0) 3932 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n"); 3933 } 3934 3935 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 3936 const struct intel_crtc_state *crtc_state) 3937 { 3938 struct intel_display *display = to_intel_display(intel_dp); 3939 bool ycbcr444_to_420 = false; 3940 bool rgb_to_ycbcr = false; 3941 u8 tmp; 3942 3943 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 3944 return; 3945 3946 if (!drm_dp_is_branch(intel_dp->dpcd)) 3947 return; 3948 3949 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 3950 3951 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3952 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 3953 drm_dbg_kms(display->drm, 3954 "Failed to %s protocol converter HDMI mode\n", 3955 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 3956 3957 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3958 switch (crtc_state->output_format) { 3959 case INTEL_OUTPUT_FORMAT_YCBCR420: 3960 break; 3961 case INTEL_OUTPUT_FORMAT_YCBCR444: 3962 ycbcr444_to_420 = true; 3963 break; 3964 case INTEL_OUTPUT_FORMAT_RGB: 3965 rgb_to_ycbcr = true; 3966 ycbcr444_to_420 = true; 3967 break; 3968 default: 3969 MISSING_CASE(crtc_state->output_format); 3970 break; 3971 } 3972 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 3973 switch (crtc_state->output_format) { 3974 case INTEL_OUTPUT_FORMAT_YCBCR444: 3975 break; 3976 case INTEL_OUTPUT_FORMAT_RGB: 3977 rgb_to_ycbcr = true; 3978 break; 3979 default: 3980 MISSING_CASE(crtc_state->output_format); 3981 break; 3982 } 3983 } 3984 3985 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 3986 3987 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3988 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 3989 drm_dbg_kms(display->drm, 3990 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 3991 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 3992 3993 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 3994 3995 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 3996 drm_dbg_kms(display->drm, 3997 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 3998 str_enable_disable(tmp)); 3999 } 4000 4001 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4002 { 4003 u8 dprx = 0; 4004 4005 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4006 &dprx) != 1) 4007 return false; 4008 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4009 } 4010 4011 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 4012 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 4013 { 4014 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, 4015 DP_DSC_RECEIVER_CAP_SIZE) < 0) { 4016 drm_err(aux->drm_dev, 4017 "Failed to read DPCD register 0x%x\n", 4018 DP_DSC_SUPPORT); 4019 return; 4020 } 4021 4022 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 4023 DP_DSC_RECEIVER_CAP_SIZE, 4024 dsc_dpcd); 4025 } 4026 4027 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) 4028 { 4029 struct intel_display *display = to_intel_display(connector); 4030 4031 /* 4032 * Clear the cached register set to avoid using stale values 4033 * for the sinks that do not support DSC. 4034 */ 4035 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 4036 4037 /* Clear fec_capable to avoid using stale values */ 4038 connector->dp.fec_capability = 0; 4039 4040 if (dpcd_rev < DP_DPCD_REV_14) 4041 return; 4042 4043 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 4044 connector->dp.dsc_dpcd); 4045 4046 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 4047 &connector->dp.fec_capability) < 0) { 4048 drm_err(display->drm, "Failed to read FEC DPCD register\n"); 4049 return; 4050 } 4051 4052 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n", 4053 connector->dp.fec_capability); 4054 } 4055 4056 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 4057 { 4058 if (edp_dpcd_rev < DP_EDP_14) 4059 return; 4060 4061 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); 4062 } 4063 4064 static void 4065 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 4066 { 4067 struct intel_display *display = to_intel_display(intel_dp); 4068 4069 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 4070 if (!HAS_DSC(display)) 4071 return; 4072 4073 if (intel_dp_is_edp(intel_dp)) 4074 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 4075 connector); 4076 else 4077 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 4078 connector); 4079 } 4080 4081 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 4082 struct drm_display_mode *mode) 4083 { 4084 struct intel_display *display = to_intel_display(connector); 4085 struct intel_dp *intel_dp = intel_attached_dp(connector); 4086 int n = intel_dp->mso_link_count; 4087 int overlap = intel_dp->mso_pixel_overlap; 4088 4089 if (!mode || !n) 4090 return; 4091 4092 mode->hdisplay = (mode->hdisplay - overlap) * n; 4093 mode->hsync_start = (mode->hsync_start - overlap) * n; 4094 mode->hsync_end = (mode->hsync_end - overlap) * n; 4095 mode->htotal = (mode->htotal - overlap) * n; 4096 mode->clock *= n; 4097 4098 drm_mode_set_name(mode); 4099 4100 drm_dbg_kms(display->drm, 4101 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 4102 connector->base.base.id, connector->base.name, 4103 DRM_MODE_ARG(mode)); 4104 } 4105 4106 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 4107 { 4108 struct intel_display *display = to_intel_display(encoder); 4109 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4110 struct intel_connector *connector = intel_dp->attached_connector; 4111 4112 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 4113 /* 4114 * This is a big fat ugly hack. 4115 * 4116 * Some machines in UEFI boot mode provide us a VBT that has 18 4117 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4118 * unknown we fail to light up. Yet the same BIOS boots up with 4119 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4120 * max, not what it tells us to use. 4121 * 4122 * Note: This will still be broken if the eDP panel is not lit 4123 * up by the BIOS, and thus we can't get the mode at module 4124 * load. 4125 */ 4126 drm_dbg_kms(display->drm, 4127 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4128 pipe_bpp, connector->panel.vbt.edp.bpp); 4129 connector->panel.vbt.edp.bpp = pipe_bpp; 4130 } 4131 } 4132 4133 static void intel_edp_mso_init(struct intel_dp *intel_dp) 4134 { 4135 struct intel_display *display = to_intel_display(intel_dp); 4136 struct intel_connector *connector = intel_dp->attached_connector; 4137 struct drm_display_info *info = &connector->base.display_info; 4138 u8 mso; 4139 4140 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 4141 return; 4142 4143 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 4144 drm_err(display->drm, "Failed to read MSO cap\n"); 4145 return; 4146 } 4147 4148 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 4149 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 4150 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 4151 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso); 4152 mso = 0; 4153 } 4154 4155 if (mso) { 4156 drm_dbg_kms(display->drm, 4157 "Sink MSO %ux%u configuration, pixel overlap %u\n", 4158 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 4159 info->mso_pixel_overlap); 4160 if (!HAS_MSO(display)) { 4161 drm_err(display->drm, 4162 "No source MSO support, disabling\n"); 4163 mso = 0; 4164 } 4165 } 4166 4167 intel_dp->mso_link_count = mso; 4168 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 4169 } 4170 4171 static void 4172 intel_edp_set_sink_rates(struct intel_dp *intel_dp) 4173 { 4174 intel_dp->num_sink_rates = 0; 4175 4176 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4177 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4178 int i; 4179 4180 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4181 sink_rates, sizeof(sink_rates)); 4182 4183 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4184 int val = le16_to_cpu(sink_rates[i]); 4185 4186 if (val == 0) 4187 break; 4188 4189 /* Value read multiplied by 200kHz gives the per-lane 4190 * link rate in kHz. The source rates are, however, 4191 * stored in terms of LS_Clk kHz. The full conversion 4192 * back to symbols is 4193 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4194 */ 4195 intel_dp->sink_rates[i] = (val * 200) / 10; 4196 } 4197 intel_dp->num_sink_rates = i; 4198 } 4199 4200 /* 4201 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4202 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4203 */ 4204 if (intel_dp->num_sink_rates) 4205 intel_dp->use_rate_select = true; 4206 else 4207 intel_dp_set_sink_rates(intel_dp); 4208 } 4209 4210 static bool 4211 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 4212 { 4213 struct intel_display *display = to_intel_display(intel_dp); 4214 4215 /* this function is meant to be called only once */ 4216 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4217 4218 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4219 return false; 4220 4221 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4222 drm_dp_is_branch(intel_dp->dpcd)); 4223 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4224 4225 intel_dp->colorimetry_support = 4226 intel_dp_get_colorimetry_status(intel_dp); 4227 4228 /* 4229 * Read the eDP display control registers. 4230 * 4231 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4232 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4233 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4234 * method). The display control registers should read zero if they're 4235 * not supported anyway. 4236 */ 4237 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4238 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4239 sizeof(intel_dp->edp_dpcd)) { 4240 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n", 4241 (int)sizeof(intel_dp->edp_dpcd), 4242 intel_dp->edp_dpcd); 4243 4244 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 4245 } 4246 4247 /* 4248 * If needed, program our source OUI so we can make various Intel-specific AUX services 4249 * available (such as HDR backlight controls) 4250 */ 4251 intel_dp_init_source_oui(intel_dp); 4252 4253 /* 4254 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4255 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4256 */ 4257 intel_psr_init_dpcd(intel_dp); 4258 4259 intel_edp_set_sink_rates(intel_dp); 4260 intel_dp_set_max_sink_lane_count(intel_dp); 4261 4262 /* Read the eDP DSC DPCD registers */ 4263 intel_dp_detect_dsc_caps(intel_dp, connector); 4264 4265 return true; 4266 } 4267 4268 static bool 4269 intel_dp_has_sink_count(struct intel_dp *intel_dp) 4270 { 4271 if (!intel_dp->attached_connector) 4272 return false; 4273 4274 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4275 intel_dp->dpcd, 4276 &intel_dp->desc); 4277 } 4278 4279 void intel_dp_update_sink_caps(struct intel_dp *intel_dp) 4280 { 4281 intel_dp_set_sink_rates(intel_dp); 4282 intel_dp_set_max_sink_lane_count(intel_dp); 4283 intel_dp_set_common_rates(intel_dp); 4284 } 4285 4286 static bool 4287 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4288 { 4289 int ret; 4290 4291 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 4292 return false; 4293 4294 /* 4295 * Don't clobber cached eDP rates. Also skip re-reading 4296 * the OUI/ID since we know it won't change. 4297 */ 4298 if (!intel_dp_is_edp(intel_dp)) { 4299 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4300 drm_dp_is_branch(intel_dp->dpcd)); 4301 4302 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4303 4304 intel_dp->colorimetry_support = 4305 intel_dp_get_colorimetry_status(intel_dp); 4306 4307 intel_dp_update_sink_caps(intel_dp); 4308 } 4309 4310 if (intel_dp_has_sink_count(intel_dp)) { 4311 ret = drm_dp_read_sink_count(&intel_dp->aux); 4312 if (ret < 0) 4313 return false; 4314 4315 /* 4316 * Sink count can change between short pulse hpd hence 4317 * a member variable in intel_dp will track any changes 4318 * between short pulse interrupts. 4319 */ 4320 intel_dp->sink_count = ret; 4321 4322 /* 4323 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4324 * a dongle is present but no display. Unless we require to know 4325 * if a dongle is present or not, we don't need to update 4326 * downstream port information. So, an early return here saves 4327 * time from performing other operations which are not required. 4328 */ 4329 if (!intel_dp->sink_count) 4330 return false; 4331 } 4332 4333 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4334 intel_dp->downstream_ports) == 0; 4335 } 4336 4337 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) 4338 { 4339 if (mst_mode == DRM_DP_MST) 4340 return "MST"; 4341 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) 4342 return "SST w/ sideband messaging"; 4343 else 4344 return "SST"; 4345 } 4346 4347 static enum drm_dp_mst_mode 4348 intel_dp_mst_mode_choose(struct intel_dp *intel_dp, 4349 enum drm_dp_mst_mode sink_mst_mode) 4350 { 4351 struct intel_display *display = to_intel_display(intel_dp); 4352 4353 if (!display->params.enable_dp_mst) 4354 return DRM_DP_SST; 4355 4356 if (!intel_dp_mst_source_support(intel_dp)) 4357 return DRM_DP_SST; 4358 4359 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && 4360 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) 4361 return DRM_DP_SST; 4362 4363 return sink_mst_mode; 4364 } 4365 4366 static enum drm_dp_mst_mode 4367 intel_dp_mst_detect(struct intel_dp *intel_dp) 4368 { 4369 struct intel_display *display = to_intel_display(intel_dp); 4370 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4371 enum drm_dp_mst_mode sink_mst_mode; 4372 enum drm_dp_mst_mode mst_detect; 4373 4374 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4375 4376 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); 4377 4378 drm_dbg_kms(display->drm, 4379 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", 4380 encoder->base.base.id, encoder->base.name, 4381 str_yes_no(intel_dp_mst_source_support(intel_dp)), 4382 intel_dp_mst_mode_str(sink_mst_mode), 4383 str_yes_no(display->params.enable_dp_mst), 4384 intel_dp_mst_mode_str(mst_detect)); 4385 4386 return mst_detect; 4387 } 4388 4389 static void 4390 intel_dp_mst_configure(struct intel_dp *intel_dp) 4391 { 4392 if (!intel_dp_mst_source_support(intel_dp)) 4393 return; 4394 4395 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4396 4397 if (intel_dp->is_mst) 4398 intel_dp_mst_prepare_probe(intel_dp); 4399 4400 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4401 4402 /* Avoid stale info on the next detect cycle. */ 4403 intel_dp->mst_detect = DRM_DP_SST; 4404 } 4405 4406 static void 4407 intel_dp_mst_disconnect(struct intel_dp *intel_dp) 4408 { 4409 struct intel_display *display = to_intel_display(intel_dp); 4410 4411 if (!intel_dp->is_mst) 4412 return; 4413 4414 drm_dbg_kms(display->drm, 4415 "MST device may have disappeared %d vs %d\n", 4416 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4417 intel_dp->is_mst = false; 4418 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4419 } 4420 4421 static bool 4422 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 4423 { 4424 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 4425 } 4426 4427 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 4428 { 4429 int retry; 4430 4431 for (retry = 0; retry < 3; retry++) { 4432 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 4433 &esi[1], 3) == 3) 4434 return true; 4435 } 4436 4437 return false; 4438 } 4439 4440 bool 4441 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 4442 const struct drm_connector_state *conn_state) 4443 { 4444 /* 4445 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 4446 * of Color Encoding Format and Content Color Gamut], in order to 4447 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 4448 */ 4449 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 4450 return true; 4451 4452 switch (conn_state->colorspace) { 4453 case DRM_MODE_COLORIMETRY_SYCC_601: 4454 case DRM_MODE_COLORIMETRY_OPYCC_601: 4455 case DRM_MODE_COLORIMETRY_BT2020_YCC: 4456 case DRM_MODE_COLORIMETRY_BT2020_RGB: 4457 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 4458 return true; 4459 default: 4460 break; 4461 } 4462 4463 return false; 4464 } 4465 4466 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, 4467 struct dp_sdp *sdp, size_t size) 4468 { 4469 size_t length = sizeof(struct dp_sdp); 4470 4471 if (size < length) 4472 return -ENOSPC; 4473 4474 memset(sdp, 0, size); 4475 4476 /* Prepare AS (Adaptive Sync) SDP Header */ 4477 sdp->sdp_header.HB0 = 0; 4478 sdp->sdp_header.HB1 = as_sdp->sdp_type; 4479 sdp->sdp_header.HB2 = 0x02; 4480 sdp->sdp_header.HB3 = as_sdp->length; 4481 4482 /* Fill AS (Adaptive Sync) SDP Payload */ 4483 sdp->db[0] = as_sdp->mode; 4484 sdp->db[1] = as_sdp->vtotal & 0xFF; 4485 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; 4486 sdp->db[3] = as_sdp->target_rr & 0xFF; 4487 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; 4488 4489 if (as_sdp->target_rr_divider) 4490 sdp->db[4] |= 0x20; 4491 4492 return length; 4493 } 4494 4495 static ssize_t 4496 intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display, 4497 const struct hdmi_drm_infoframe *drm_infoframe, 4498 struct dp_sdp *sdp, 4499 size_t size) 4500 { 4501 size_t length = sizeof(struct dp_sdp); 4502 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 4503 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 4504 ssize_t len; 4505 4506 if (size < length) 4507 return -ENOSPC; 4508 4509 memset(sdp, 0, size); 4510 4511 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 4512 if (len < 0) { 4513 drm_dbg_kms(display->drm, 4514 "buffer size is smaller than hdr metadata infoframe\n"); 4515 return -ENOSPC; 4516 } 4517 4518 if (len != infoframe_size) { 4519 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n"); 4520 return -ENOSPC; 4521 } 4522 4523 /* 4524 * Set up the infoframe sdp packet for HDR static metadata. 4525 * Prepare VSC Header for SU as per DP 1.4a spec, 4526 * Table 2-100 and Table 2-101 4527 */ 4528 4529 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 4530 sdp->sdp_header.HB0 = 0; 4531 /* 4532 * Packet Type 80h + Non-audio INFOFRAME Type value 4533 * HDMI_INFOFRAME_TYPE_DRM: 0x87 4534 * - 80h + Non-audio INFOFRAME Type value 4535 * - InfoFrame Type: 0x07 4536 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 4537 */ 4538 sdp->sdp_header.HB1 = drm_infoframe->type; 4539 /* 4540 * Least Significant Eight Bits of (Data Byte Count – 1) 4541 * infoframe_size - 1 4542 */ 4543 sdp->sdp_header.HB2 = 0x1D; 4544 /* INFOFRAME SDP Version Number */ 4545 sdp->sdp_header.HB3 = (0x13 << 2); 4546 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4547 sdp->db[0] = drm_infoframe->version; 4548 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4549 sdp->db[1] = drm_infoframe->length; 4550 /* 4551 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 4552 * HDMI_INFOFRAME_HEADER_SIZE 4553 */ 4554 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 4555 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 4556 HDMI_DRM_INFOFRAME_SIZE); 4557 4558 /* 4559 * Size of DP infoframe sdp packet for HDR static metadata consists of 4560 * - DP SDP Header(struct dp_sdp_header): 4 bytes 4561 * - Two Data Blocks: 2 bytes 4562 * CTA Header Byte2 (INFOFRAME Version Number) 4563 * CTA Header Byte3 (Length of INFOFRAME) 4564 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 4565 * 4566 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 4567 * infoframe size. But GEN11+ has larger than that size, write_infoframe 4568 * will pad rest of the size. 4569 */ 4570 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 4571 } 4572 4573 static void intel_write_dp_sdp(struct intel_encoder *encoder, 4574 const struct intel_crtc_state *crtc_state, 4575 unsigned int type) 4576 { 4577 struct intel_display *display = to_intel_display(encoder); 4578 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4579 struct dp_sdp sdp = {}; 4580 ssize_t len; 4581 4582 if ((crtc_state->infoframes.enable & 4583 intel_hdmi_infoframe_enable(type)) == 0) 4584 return; 4585 4586 switch (type) { 4587 case DP_SDP_VSC: 4588 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp); 4589 break; 4590 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4591 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display, 4592 &crtc_state->infoframes.drm.drm, 4593 &sdp, sizeof(sdp)); 4594 break; 4595 case DP_SDP_ADAPTIVE_SYNC: 4596 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, 4597 sizeof(sdp)); 4598 break; 4599 default: 4600 MISSING_CASE(type); 4601 return; 4602 } 4603 4604 if (drm_WARN_ON(display->drm, len < 0)) 4605 return; 4606 4607 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 4608 } 4609 4610 void intel_dp_set_infoframes(struct intel_encoder *encoder, 4611 bool enable, 4612 const struct intel_crtc_state *crtc_state, 4613 const struct drm_connector_state *conn_state) 4614 { 4615 struct intel_display *display = to_intel_display(encoder); 4616 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); 4617 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 4618 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 4619 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 4620 4621 if (HAS_AS_SDP(display)) 4622 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; 4623 4624 u32 val = intel_de_read(display, reg) & ~dip_enable; 4625 4626 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ 4627 if (!enable && HAS_DSC(display)) 4628 val &= ~VDIP_ENABLE_PPS; 4629 4630 /* 4631 * This routine disables VSC DIP if the function is called 4632 * to disable SDP or if it does not have PSR 4633 */ 4634 if (!enable || !crtc_state->has_psr) 4635 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4636 4637 intel_de_write(display, reg, val); 4638 intel_de_posting_read(display, reg); 4639 4640 if (!enable) 4641 return; 4642 4643 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 4644 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); 4645 4646 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 4647 } 4648 4649 static 4650 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, 4651 const void *buffer, size_t size) 4652 { 4653 const struct dp_sdp *sdp = buffer; 4654 4655 if (size < sizeof(struct dp_sdp)) 4656 return -EINVAL; 4657 4658 memset(as_sdp, 0, sizeof(*as_sdp)); 4659 4660 if (sdp->sdp_header.HB0 != 0) 4661 return -EINVAL; 4662 4663 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) 4664 return -EINVAL; 4665 4666 if (sdp->sdp_header.HB2 != 0x02) 4667 return -EINVAL; 4668 4669 if ((sdp->sdp_header.HB3 & 0x3F) != 9) 4670 return -EINVAL; 4671 4672 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; 4673 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; 4674 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; 4675 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); 4676 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; 4677 4678 return 0; 4679 } 4680 4681 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 4682 const void *buffer, size_t size) 4683 { 4684 const struct dp_sdp *sdp = buffer; 4685 4686 if (size < sizeof(struct dp_sdp)) 4687 return -EINVAL; 4688 4689 memset(vsc, 0, sizeof(*vsc)); 4690 4691 if (sdp->sdp_header.HB0 != 0) 4692 return -EINVAL; 4693 4694 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 4695 return -EINVAL; 4696 4697 vsc->sdp_type = sdp->sdp_header.HB1; 4698 vsc->revision = sdp->sdp_header.HB2; 4699 vsc->length = sdp->sdp_header.HB3; 4700 4701 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 4702 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || 4703 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { 4704 /* 4705 * - HB2 = 0x2, HB3 = 0x8 4706 * VSC SDP supporting 3D stereo + PSR 4707 * - HB2 = 0x4, HB3 = 0xe 4708 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 4709 * first scan line of the SU region (applies to eDP v1.4b 4710 * and higher). 4711 * - HB2 = 0x6, HB3 = 0x10 4712 * VSC SDP supporting 3D stereo + Panel Replay. 4713 */ 4714 return 0; 4715 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 4716 /* 4717 * - HB2 = 0x5, HB3 = 0x13 4718 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 4719 * Format. 4720 */ 4721 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 4722 vsc->colorimetry = sdp->db[16] & 0xf; 4723 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 4724 4725 switch (sdp->db[17] & 0x7) { 4726 case 0x0: 4727 vsc->bpc = 6; 4728 break; 4729 case 0x1: 4730 vsc->bpc = 8; 4731 break; 4732 case 0x2: 4733 vsc->bpc = 10; 4734 break; 4735 case 0x3: 4736 vsc->bpc = 12; 4737 break; 4738 case 0x4: 4739 vsc->bpc = 16; 4740 break; 4741 default: 4742 MISSING_CASE(sdp->db[17] & 0x7); 4743 return -EINVAL; 4744 } 4745 4746 vsc->content_type = sdp->db[18] & 0x7; 4747 } else { 4748 return -EINVAL; 4749 } 4750 4751 return 0; 4752 } 4753 4754 static void 4755 intel_read_dp_as_sdp(struct intel_encoder *encoder, 4756 struct intel_crtc_state *crtc_state, 4757 struct drm_dp_as_sdp *as_sdp) 4758 { 4759 struct intel_display *display = to_intel_display(encoder); 4760 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4761 unsigned int type = DP_SDP_ADAPTIVE_SYNC; 4762 struct dp_sdp sdp = {}; 4763 int ret; 4764 4765 if ((crtc_state->infoframes.enable & 4766 intel_hdmi_infoframe_enable(type)) == 0) 4767 return; 4768 4769 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4770 sizeof(sdp)); 4771 4772 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); 4773 if (ret) 4774 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n"); 4775 } 4776 4777 static int 4778 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 4779 const void *buffer, size_t size) 4780 { 4781 int ret; 4782 4783 const struct dp_sdp *sdp = buffer; 4784 4785 if (size < sizeof(struct dp_sdp)) 4786 return -EINVAL; 4787 4788 if (sdp->sdp_header.HB0 != 0) 4789 return -EINVAL; 4790 4791 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 4792 return -EINVAL; 4793 4794 /* 4795 * Least Significant Eight Bits of (Data Byte Count – 1) 4796 * 1Dh (i.e., Data Byte Count = 30 bytes). 4797 */ 4798 if (sdp->sdp_header.HB2 != 0x1D) 4799 return -EINVAL; 4800 4801 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 4802 if ((sdp->sdp_header.HB3 & 0x3) != 0) 4803 return -EINVAL; 4804 4805 /* INFOFRAME SDP Version Number */ 4806 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 4807 return -EINVAL; 4808 4809 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4810 if (sdp->db[0] != 1) 4811 return -EINVAL; 4812 4813 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4814 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 4815 return -EINVAL; 4816 4817 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 4818 HDMI_DRM_INFOFRAME_SIZE); 4819 4820 return ret; 4821 } 4822 4823 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 4824 struct intel_crtc_state *crtc_state, 4825 struct drm_dp_vsc_sdp *vsc) 4826 { 4827 struct intel_display *display = to_intel_display(encoder); 4828 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4829 unsigned int type = DP_SDP_VSC; 4830 struct dp_sdp sdp = {}; 4831 int ret; 4832 4833 if ((crtc_state->infoframes.enable & 4834 intel_hdmi_infoframe_enable(type)) == 0) 4835 return; 4836 4837 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 4838 4839 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 4840 4841 if (ret) 4842 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n"); 4843 } 4844 4845 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 4846 struct intel_crtc_state *crtc_state, 4847 struct hdmi_drm_infoframe *drm_infoframe) 4848 { 4849 struct intel_display *display = to_intel_display(encoder); 4850 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4851 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 4852 struct dp_sdp sdp = {}; 4853 int ret; 4854 4855 if ((crtc_state->infoframes.enable & 4856 intel_hdmi_infoframe_enable(type)) == 0) 4857 return; 4858 4859 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4860 sizeof(sdp)); 4861 4862 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 4863 sizeof(sdp)); 4864 4865 if (ret) 4866 drm_dbg_kms(display->drm, 4867 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 4868 } 4869 4870 void intel_read_dp_sdp(struct intel_encoder *encoder, 4871 struct intel_crtc_state *crtc_state, 4872 unsigned int type) 4873 { 4874 switch (type) { 4875 case DP_SDP_VSC: 4876 intel_read_dp_vsc_sdp(encoder, crtc_state, 4877 &crtc_state->infoframes.vsc); 4878 break; 4879 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4880 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 4881 &crtc_state->infoframes.drm.drm); 4882 break; 4883 case DP_SDP_ADAPTIVE_SYNC: 4884 intel_read_dp_as_sdp(encoder, crtc_state, 4885 &crtc_state->infoframes.as_sdp); 4886 break; 4887 default: 4888 MISSING_CASE(type); 4889 break; 4890 } 4891 } 4892 4893 static bool intel_dp_link_ok(struct intel_dp *intel_dp, 4894 u8 link_status[DP_LINK_STATUS_SIZE]) 4895 { 4896 struct intel_display *display = to_intel_display(intel_dp); 4897 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4898 bool uhbr = intel_dp->link_rate >= 1000000; 4899 bool ok; 4900 4901 if (uhbr) 4902 ok = drm_dp_128b132b_lane_channel_eq_done(link_status, 4903 intel_dp->lane_count); 4904 else 4905 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 4906 4907 if (ok) 4908 return true; 4909 4910 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 4911 drm_dbg_kms(display->drm, 4912 "[ENCODER:%d:%s] %s link not ok, retraining\n", 4913 encoder->base.base.id, encoder->base.name, 4914 uhbr ? "128b/132b" : "8b/10b"); 4915 4916 return false; 4917 } 4918 4919 static void 4920 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 4921 { 4922 bool handled = false; 4923 4924 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled); 4925 4926 if (esi[1] & DP_CP_IRQ) { 4927 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 4928 ack[1] |= DP_CP_IRQ; 4929 } 4930 } 4931 4932 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) 4933 { 4934 struct intel_display *display = to_intel_display(intel_dp); 4935 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4936 u8 link_status[DP_LINK_STATUS_SIZE] = {}; 4937 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; 4938 4939 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, 4940 esi_link_status_size) != esi_link_status_size) { 4941 drm_err(display->drm, 4942 "[ENCODER:%d:%s] Failed to read link status\n", 4943 encoder->base.base.id, encoder->base.name); 4944 return false; 4945 } 4946 4947 return intel_dp_link_ok(intel_dp, link_status); 4948 } 4949 4950 /** 4951 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 4952 * @intel_dp: Intel DP struct 4953 * 4954 * Read any pending MST interrupts, call MST core to handle these and ack the 4955 * interrupts. Check if the main and AUX link state is ok. 4956 * 4957 * Returns: 4958 * - %true if pending interrupts were serviced (or no interrupts were 4959 * pending) w/o detecting an error condition. 4960 * - %false if an error condition - like AUX failure or a loss of link - is 4961 * detected, or another condition - like a DP tunnel BW state change - needs 4962 * servicing from the hotplug work. 4963 */ 4964 static bool 4965 intel_dp_check_mst_status(struct intel_dp *intel_dp) 4966 { 4967 struct intel_display *display = to_intel_display(intel_dp); 4968 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4969 struct intel_encoder *encoder = &dig_port->base; 4970 bool link_ok = true; 4971 bool reprobe_needed = false; 4972 4973 drm_WARN_ON_ONCE(display->drm, intel_dp->active_mst_links < 0); 4974 4975 for (;;) { 4976 u8 esi[4] = {}; 4977 u8 ack[4] = {}; 4978 4979 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 4980 drm_dbg_kms(display->drm, 4981 "failed to get ESI - device may have failed\n"); 4982 link_ok = false; 4983 4984 break; 4985 } 4986 4987 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi); 4988 4989 if (intel_dp->active_mst_links > 0 && link_ok && 4990 esi[3] & LINK_STATUS_CHANGED) { 4991 if (!intel_dp_mst_link_status(intel_dp)) 4992 link_ok = false; 4993 ack[3] |= LINK_STATUS_CHANGED; 4994 } 4995 4996 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 4997 4998 if (esi[3] & DP_TUNNELING_IRQ) { 4999 if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5000 &intel_dp->aux)) 5001 reprobe_needed = true; 5002 ack[3] |= DP_TUNNELING_IRQ; 5003 } 5004 5005 if (mem_is_zero(ack, sizeof(ack))) 5006 break; 5007 5008 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) 5009 drm_dbg_kms(display->drm, "Failed to ack ESI\n"); 5010 5011 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 5012 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); 5013 } 5014 5015 if (!link_ok || intel_dp->link.force_retrain) 5016 intel_encoder_link_check_queue_work(encoder, 0); 5017 5018 return !reprobe_needed; 5019 } 5020 5021 static void 5022 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 5023 { 5024 bool is_active; 5025 u8 buf = 0; 5026 5027 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 5028 if (intel_dp->frl.is_trained && !is_active) { 5029 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 5030 return; 5031 5032 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 5033 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 5034 return; 5035 5036 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 5037 5038 intel_dp->frl.is_trained = false; 5039 5040 /* Restart FRL training or fall back to TMDS mode */ 5041 intel_dp_check_frl_training(intel_dp); 5042 } 5043 } 5044 5045 static bool 5046 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 5047 { 5048 u8 link_status[DP_LINK_STATUS_SIZE]; 5049 5050 if (!intel_dp->link_trained) 5051 return false; 5052 5053 /* 5054 * While PSR source HW is enabled, it will control main-link sending 5055 * frames, enabling and disabling it so trying to do a retrain will fail 5056 * as the link would or not be on or it could mix training patterns 5057 * and frame data at the same time causing retrain to fail. 5058 * Also when exiting PSR, HW will retrain the link anyways fixing 5059 * any link status error. 5060 */ 5061 if (intel_psr_enabled(intel_dp)) 5062 return false; 5063 5064 if (intel_dp->link.force_retrain) 5065 return true; 5066 5067 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5068 link_status) < 0) 5069 return false; 5070 5071 /* 5072 * Validate the cached values of intel_dp->link_rate and 5073 * intel_dp->lane_count before attempting to retrain. 5074 * 5075 * FIXME would be nice to user the crtc state here, but since 5076 * we need to call this from the short HPD handler that seems 5077 * a bit hard. 5078 */ 5079 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 5080 intel_dp->lane_count)) 5081 return false; 5082 5083 if (intel_dp->link.retrain_disabled) 5084 return false; 5085 5086 if (intel_dp->link.seq_train_failures) 5087 return true; 5088 5089 /* Retrain if link not ok */ 5090 return !intel_dp_link_ok(intel_dp, link_status) && 5091 !intel_psr_link_ok(intel_dp); 5092 } 5093 5094 bool intel_dp_has_connector(struct intel_dp *intel_dp, 5095 const struct drm_connector_state *conn_state) 5096 { 5097 struct intel_display *display = to_intel_display(intel_dp); 5098 struct intel_encoder *encoder; 5099 enum pipe pipe; 5100 5101 if (!conn_state->best_encoder) 5102 return false; 5103 5104 /* SST */ 5105 encoder = &dp_to_dig_port(intel_dp)->base; 5106 if (conn_state->best_encoder == &encoder->base) 5107 return true; 5108 5109 /* MST */ 5110 for_each_pipe(display, pipe) { 5111 encoder = &intel_dp->mst_encoders[pipe]->base; 5112 if (conn_state->best_encoder == &encoder->base) 5113 return true; 5114 } 5115 5116 return false; 5117 } 5118 5119 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state) 5120 { 5121 struct intel_connector *connector = to_intel_connector(conn_state->connector); 5122 struct intel_display *display = to_intel_display(connector); 5123 5124 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 5125 5126 if (!conn_state->commit) 5127 return; 5128 5129 drm_WARN_ON(display->drm, 5130 !wait_for_completion_timeout(&conn_state->commit->hw_done, 5131 msecs_to_jiffies(5000))); 5132 } 5133 5134 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 5135 struct drm_modeset_acquire_ctx *ctx, 5136 u8 *pipe_mask) 5137 { 5138 struct intel_display *display = to_intel_display(intel_dp); 5139 struct drm_connector_list_iter conn_iter; 5140 struct intel_connector *connector; 5141 int ret = 0; 5142 5143 *pipe_mask = 0; 5144 5145 drm_connector_list_iter_begin(display->drm, &conn_iter); 5146 for_each_intel_connector_iter(connector, &conn_iter) { 5147 struct drm_connector_state *conn_state = 5148 connector->base.state; 5149 struct intel_crtc_state *crtc_state; 5150 struct intel_crtc *crtc; 5151 5152 if (!intel_dp_has_connector(intel_dp, conn_state)) 5153 continue; 5154 5155 crtc = to_intel_crtc(conn_state->crtc); 5156 if (!crtc) 5157 continue; 5158 5159 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5160 if (ret) 5161 break; 5162 5163 crtc_state = to_intel_crtc_state(crtc->base.state); 5164 5165 drm_WARN_ON(display->drm, 5166 !intel_crtc_has_dp_encoder(crtc_state)); 5167 5168 if (!crtc_state->hw.active) 5169 continue; 5170 5171 wait_for_connector_hw_done(conn_state); 5172 5173 *pipe_mask |= BIT(crtc->pipe); 5174 } 5175 drm_connector_list_iter_end(&conn_iter); 5176 5177 return ret; 5178 } 5179 5180 void intel_dp_flush_connector_commits(struct intel_connector *connector) 5181 { 5182 wait_for_connector_hw_done(connector->base.state); 5183 } 5184 5185 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 5186 { 5187 struct intel_connector *connector = intel_dp->attached_connector; 5188 5189 return connector->base.status == connector_status_connected || 5190 intel_dp->is_mst; 5191 } 5192 5193 static int intel_dp_retrain_link(struct intel_encoder *encoder, 5194 struct drm_modeset_acquire_ctx *ctx) 5195 { 5196 struct intel_display *display = to_intel_display(encoder); 5197 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5198 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5199 u8 pipe_mask; 5200 int ret; 5201 5202 if (!intel_dp_is_connected(intel_dp)) 5203 return 0; 5204 5205 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 5206 ctx); 5207 if (ret) 5208 return ret; 5209 5210 if (!intel_dp_needs_link_retrain(intel_dp)) 5211 return 0; 5212 5213 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); 5214 if (ret) 5215 return ret; 5216 5217 if (pipe_mask == 0) 5218 return 0; 5219 5220 if (!intel_dp_needs_link_retrain(intel_dp)) 5221 return 0; 5222 5223 drm_dbg_kms(display->drm, 5224 "[ENCODER:%d:%s] retraining link (forced %s)\n", 5225 encoder->base.base.id, encoder->base.name, 5226 str_yes_no(intel_dp->link.force_retrain)); 5227 5228 ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); 5229 if (ret == -EDEADLK) 5230 return ret; 5231 5232 intel_dp->link.force_retrain = false; 5233 5234 if (ret) 5235 drm_dbg_kms(display->drm, 5236 "[ENCODER:%d:%s] link retraining failed: %pe\n", 5237 encoder->base.base.id, encoder->base.name, 5238 ERR_PTR(ret)); 5239 5240 return ret; 5241 } 5242 5243 void intel_dp_link_check(struct intel_encoder *encoder) 5244 { 5245 struct drm_modeset_acquire_ctx ctx; 5246 int ret; 5247 5248 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 5249 ret = intel_dp_retrain_link(encoder, &ctx); 5250 } 5251 5252 void intel_dp_check_link_state(struct intel_dp *intel_dp) 5253 { 5254 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5255 struct intel_encoder *encoder = &dig_port->base; 5256 5257 if (!intel_dp_is_connected(intel_dp)) 5258 return; 5259 5260 if (!intel_dp_needs_link_retrain(intel_dp)) 5261 return; 5262 5263 intel_encoder_link_check_queue_work(encoder, 0); 5264 } 5265 5266 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 5267 { 5268 struct intel_display *display = to_intel_display(intel_dp); 5269 u8 val; 5270 5271 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5272 return; 5273 5274 if (drm_dp_dpcd_readb(&intel_dp->aux, 5275 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 5276 return; 5277 5278 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 5279 5280 if (val & DP_AUTOMATED_TEST_REQUEST) 5281 intel_dp_test_request(intel_dp); 5282 5283 if (val & DP_CP_IRQ) 5284 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5285 5286 if (val & DP_SINK_SPECIFIC_IRQ) 5287 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n"); 5288 } 5289 5290 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 5291 { 5292 struct intel_display *display = to_intel_display(intel_dp); 5293 bool reprobe_needed = false; 5294 u8 val; 5295 5296 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5297 return false; 5298 5299 if (drm_dp_dpcd_readb(&intel_dp->aux, 5300 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 5301 return false; 5302 5303 if ((val & DP_TUNNELING_IRQ) && 5304 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5305 &intel_dp->aux)) 5306 reprobe_needed = true; 5307 5308 if (drm_dp_dpcd_writeb(&intel_dp->aux, 5309 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 5310 return reprobe_needed; 5311 5312 if (val & HDMI_LINK_STATUS_CHANGED) 5313 intel_dp_handle_hdmi_link_status_change(intel_dp); 5314 5315 return reprobe_needed; 5316 } 5317 5318 /* 5319 * According to DP spec 5320 * 5.1.2: 5321 * 1. Read DPCD 5322 * 2. Configure link according to Receiver Capabilities 5323 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5324 * 4. Check link status on receipt of hot-plug interrupt 5325 * 5326 * intel_dp_short_pulse - handles short pulse interrupts 5327 * when full detection is not required. 5328 * Returns %true if short pulse is handled and full detection 5329 * is NOT required and %false otherwise. 5330 */ 5331 static bool 5332 intel_dp_short_pulse(struct intel_dp *intel_dp) 5333 { 5334 u8 old_sink_count = intel_dp->sink_count; 5335 bool reprobe_needed = false; 5336 bool ret; 5337 5338 intel_dp_test_reset(intel_dp); 5339 5340 /* 5341 * Now read the DPCD to see if it's actually running 5342 * If the current value of sink count doesn't match with 5343 * the value that was stored earlier or dpcd read failed 5344 * we need to do full detection 5345 */ 5346 ret = intel_dp_get_dpcd(intel_dp); 5347 5348 if ((old_sink_count != intel_dp->sink_count) || !ret) { 5349 /* No need to proceed if we are going to do full detect */ 5350 return false; 5351 } 5352 5353 intel_dp_check_device_service_irq(intel_dp); 5354 reprobe_needed = intel_dp_check_link_service_irq(intel_dp); 5355 5356 /* Handle CEC interrupts, if any */ 5357 drm_dp_cec_irq(&intel_dp->aux); 5358 5359 intel_dp_check_link_state(intel_dp); 5360 5361 intel_psr_short_pulse(intel_dp); 5362 5363 if (intel_dp_test_short_pulse(intel_dp)) 5364 reprobe_needed = true; 5365 5366 return !reprobe_needed; 5367 } 5368 5369 /* XXX this is probably wrong for multiple downstream ports */ 5370 static enum drm_connector_status 5371 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5372 { 5373 struct intel_display *display = to_intel_display(intel_dp); 5374 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5375 u8 *dpcd = intel_dp->dpcd; 5376 u8 type; 5377 5378 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp))) 5379 return connector_status_connected; 5380 5381 intel_lspcon_resume(dig_port); 5382 5383 if (!intel_dp_get_dpcd(intel_dp)) 5384 return connector_status_disconnected; 5385 5386 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); 5387 5388 /* if there's no downstream port, we're done */ 5389 if (!drm_dp_is_branch(dpcd)) 5390 return connector_status_connected; 5391 5392 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5393 if (intel_dp_has_sink_count(intel_dp) && 5394 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5395 return intel_dp->sink_count ? 5396 connector_status_connected : connector_status_disconnected; 5397 } 5398 5399 if (intel_dp->mst_detect == DRM_DP_MST) 5400 return connector_status_connected; 5401 5402 /* If no HPD, poke DDC gently */ 5403 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5404 return connector_status_connected; 5405 5406 /* Well we tried, say unknown for unreliable port types */ 5407 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5408 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5409 if (type == DP_DS_PORT_TYPE_VGA || 5410 type == DP_DS_PORT_TYPE_NON_EDID) 5411 return connector_status_unknown; 5412 } else { 5413 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5414 DP_DWN_STRM_PORT_TYPE_MASK; 5415 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5416 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5417 return connector_status_unknown; 5418 } 5419 5420 /* Anything else is out of spec, warn and ignore */ 5421 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n"); 5422 return connector_status_disconnected; 5423 } 5424 5425 static enum drm_connector_status 5426 edp_detect(struct intel_dp *intel_dp) 5427 { 5428 return connector_status_connected; 5429 } 5430 5431 void intel_digital_port_lock(struct intel_encoder *encoder) 5432 { 5433 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5434 5435 if (dig_port->lock) 5436 dig_port->lock(dig_port); 5437 } 5438 5439 void intel_digital_port_unlock(struct intel_encoder *encoder) 5440 { 5441 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5442 5443 if (dig_port->unlock) 5444 dig_port->unlock(dig_port); 5445 } 5446 5447 /* 5448 * intel_digital_port_connected_locked - is the specified port connected? 5449 * @encoder: intel_encoder 5450 * 5451 * In cases where there's a connector physically connected but it can't be used 5452 * by our hardware we also return false, since the rest of the driver should 5453 * pretty much treat the port as disconnected. This is relevant for type-C 5454 * (starting on ICL) where there's ownership involved. 5455 * 5456 * The caller must hold the lock acquired by calling intel_digital_port_lock() 5457 * when calling this function. 5458 * 5459 * Return %true if port is connected, %false otherwise. 5460 */ 5461 bool intel_digital_port_connected_locked(struct intel_encoder *encoder) 5462 { 5463 struct intel_display *display = to_intel_display(encoder); 5464 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5465 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5466 bool is_connected = false; 5467 intel_wakeref_t wakeref; 5468 5469 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 5470 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); 5471 5472 do { 5473 is_connected = dig_port->connected(encoder); 5474 if (is_connected || is_glitch_free) 5475 break; 5476 usleep_range(10, 30); 5477 } while (time_before(jiffies, wait_expires)); 5478 } 5479 5480 return is_connected; 5481 } 5482 5483 bool intel_digital_port_connected(struct intel_encoder *encoder) 5484 { 5485 bool ret; 5486 5487 intel_digital_port_lock(encoder); 5488 ret = intel_digital_port_connected_locked(encoder); 5489 intel_digital_port_unlock(encoder); 5490 5491 return ret; 5492 } 5493 5494 static const struct drm_edid * 5495 intel_dp_get_edid(struct intel_dp *intel_dp) 5496 { 5497 struct intel_connector *connector = intel_dp->attached_connector; 5498 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5499 5500 /* Use panel fixed edid if we have one */ 5501 if (fixed_edid) { 5502 /* invalid edid */ 5503 if (IS_ERR(fixed_edid)) 5504 return NULL; 5505 5506 return drm_edid_dup(fixed_edid); 5507 } 5508 5509 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5510 } 5511 5512 static void 5513 intel_dp_update_dfp(struct intel_dp *intel_dp, 5514 const struct drm_edid *drm_edid) 5515 { 5516 struct intel_display *display = to_intel_display(intel_dp); 5517 struct intel_connector *connector = intel_dp->attached_connector; 5518 5519 intel_dp->dfp.max_bpc = 5520 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5521 intel_dp->downstream_ports, drm_edid); 5522 5523 intel_dp->dfp.max_dotclock = 5524 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5525 intel_dp->downstream_ports); 5526 5527 intel_dp->dfp.min_tmds_clock = 5528 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5529 intel_dp->downstream_ports, 5530 drm_edid); 5531 intel_dp->dfp.max_tmds_clock = 5532 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5533 intel_dp->downstream_ports, 5534 drm_edid); 5535 5536 intel_dp->dfp.pcon_max_frl_bw = 5537 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5538 intel_dp->downstream_ports); 5539 5540 drm_dbg_kms(display->drm, 5541 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5542 connector->base.base.id, connector->base.name, 5543 intel_dp->dfp.max_bpc, 5544 intel_dp->dfp.max_dotclock, 5545 intel_dp->dfp.min_tmds_clock, 5546 intel_dp->dfp.max_tmds_clock, 5547 intel_dp->dfp.pcon_max_frl_bw); 5548 5549 intel_dp_get_pcon_dsc_cap(intel_dp); 5550 } 5551 5552 static bool 5553 intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 5554 { 5555 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 5556 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 5557 return true; 5558 5559 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 5560 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5561 return true; 5562 5563 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 5564 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5565 return true; 5566 5567 return false; 5568 } 5569 5570 static void 5571 intel_dp_update_420(struct intel_dp *intel_dp) 5572 { 5573 struct intel_display *display = to_intel_display(intel_dp); 5574 struct intel_connector *connector = intel_dp->attached_connector; 5575 5576 intel_dp->dfp.ycbcr420_passthrough = 5577 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 5578 intel_dp->downstream_ports); 5579 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 5580 intel_dp->dfp.ycbcr_444_to_420 = 5581 intel_lspcon_active(dp_to_dig_port(intel_dp)) || 5582 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 5583 intel_dp->downstream_ports); 5584 intel_dp->dfp.rgb_to_ycbcr = 5585 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 5586 intel_dp->downstream_ports, 5587 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 5588 5589 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 5590 5591 drm_dbg_kms(display->drm, 5592 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 5593 connector->base.base.id, connector->base.name, 5594 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 5595 str_yes_no(connector->base.ycbcr_420_allowed), 5596 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 5597 } 5598 5599 static void 5600 intel_dp_set_edid(struct intel_dp *intel_dp) 5601 { 5602 struct intel_display *display = to_intel_display(intel_dp); 5603 struct intel_connector *connector = intel_dp->attached_connector; 5604 const struct drm_edid *drm_edid; 5605 bool vrr_capable; 5606 5607 intel_dp_unset_edid(intel_dp); 5608 drm_edid = intel_dp_get_edid(intel_dp); 5609 connector->detect_edid = drm_edid; 5610 5611 /* Below we depend on display info having been updated */ 5612 drm_edid_connector_update(&connector->base, drm_edid); 5613 5614 vrr_capable = intel_vrr_is_capable(connector); 5615 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 5616 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 5617 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 5618 5619 intel_dp_update_dfp(intel_dp, drm_edid); 5620 intel_dp_update_420(intel_dp); 5621 5622 drm_dp_cec_attach(&intel_dp->aux, 5623 connector->base.display_info.source_physical_address); 5624 } 5625 5626 static void 5627 intel_dp_unset_edid(struct intel_dp *intel_dp) 5628 { 5629 struct intel_connector *connector = intel_dp->attached_connector; 5630 5631 drm_dp_cec_unset_edid(&intel_dp->aux); 5632 drm_edid_free(connector->detect_edid); 5633 connector->detect_edid = NULL; 5634 5635 intel_dp->dfp.max_bpc = 0; 5636 intel_dp->dfp.max_dotclock = 0; 5637 intel_dp->dfp.min_tmds_clock = 0; 5638 intel_dp->dfp.max_tmds_clock = 0; 5639 5640 intel_dp->dfp.pcon_max_frl_bw = 0; 5641 5642 intel_dp->dfp.ycbcr_444_to_420 = false; 5643 connector->base.ycbcr_420_allowed = false; 5644 5645 drm_connector_set_vrr_capable_property(&connector->base, 5646 false); 5647 } 5648 5649 static void 5650 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 5651 { 5652 struct intel_display *display = to_intel_display(intel_dp); 5653 5654 intel_dp->as_sdp_supported = HAS_AS_SDP(display) && 5655 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 5656 } 5657 5658 static int 5659 intel_dp_detect(struct drm_connector *_connector, 5660 struct drm_modeset_acquire_ctx *ctx, 5661 bool force) 5662 { 5663 struct intel_display *display = to_intel_display(_connector->dev); 5664 struct intel_connector *connector = to_intel_connector(_connector); 5665 struct intel_dp *intel_dp = intel_attached_dp(connector); 5666 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5667 struct intel_encoder *encoder = &dig_port->base; 5668 enum drm_connector_status status; 5669 int ret; 5670 5671 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5672 connector->base.base.id, connector->base.name); 5673 drm_WARN_ON(display->drm, 5674 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 5675 5676 if (!intel_display_device_enabled(display)) 5677 return connector_status_disconnected; 5678 5679 if (!intel_display_driver_check_access(display)) 5680 return connector->base.status; 5681 5682 intel_dp_flush_connector_commits(connector); 5683 5684 intel_pps_vdd_on(intel_dp); 5685 5686 /* Can't disconnect eDP */ 5687 if (intel_dp_is_edp(intel_dp)) 5688 status = edp_detect(intel_dp); 5689 else if (intel_digital_port_connected(encoder)) 5690 status = intel_dp_detect_dpcd(intel_dp); 5691 else 5692 status = connector_status_disconnected; 5693 5694 if (status != connector_status_disconnected && 5695 !intel_dp_mst_verify_dpcd_state(intel_dp)) 5696 /* 5697 * This requires retrying detection for instance to re-enable 5698 * the MST mode that got reset via a long HPD pulse. The retry 5699 * will happen either via the hotplug handler's retry logic, 5700 * ensured by setting the connector here to SST/disconnected, 5701 * or via a userspace connector probing in response to the 5702 * hotplug uevent sent when removing the MST connectors. 5703 */ 5704 status = connector_status_disconnected; 5705 5706 if (status == connector_status_disconnected) { 5707 intel_dp_test_reset(intel_dp); 5708 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 5709 intel_dp->psr.sink_panel_replay_support = false; 5710 intel_dp->psr.sink_panel_replay_su_support = false; 5711 5712 intel_dp_mst_disconnect(intel_dp); 5713 5714 intel_dp_tunnel_disconnect(intel_dp); 5715 5716 goto out_unset_edid; 5717 } 5718 5719 intel_dp_init_source_oui(intel_dp); 5720 5721 ret = intel_dp_tunnel_detect(intel_dp, ctx); 5722 if (ret == -EDEADLK) { 5723 status = ret; 5724 5725 goto out_vdd_off; 5726 } 5727 5728 if (ret == 1) 5729 connector->base.epoch_counter++; 5730 5731 if (!intel_dp_is_edp(intel_dp)) 5732 intel_psr_init_dpcd(intel_dp); 5733 5734 intel_dp_detect_dsc_caps(intel_dp, connector); 5735 5736 intel_dp_detect_sdp_caps(intel_dp); 5737 5738 if (intel_dp->reset_link_params) { 5739 intel_dp_reset_link_params(intel_dp); 5740 intel_dp->reset_link_params = false; 5741 } 5742 5743 intel_dp_mst_configure(intel_dp); 5744 5745 intel_dp_print_rates(intel_dp); 5746 5747 if (intel_dp->is_mst) { 5748 /* 5749 * If we are in MST mode then this connector 5750 * won't appear connected or have anything 5751 * with EDID on it 5752 */ 5753 status = connector_status_disconnected; 5754 goto out_unset_edid; 5755 } 5756 5757 /* 5758 * Some external monitors do not signal loss of link synchronization 5759 * with an IRQ_HPD, so force a link status check. 5760 * 5761 * TODO: this probably became redundant, so remove it: the link state 5762 * is rechecked/recovered now after modesets, where the loss of 5763 * synchronization tends to occur. 5764 */ 5765 if (!intel_dp_is_edp(intel_dp)) 5766 intel_dp_check_link_state(intel_dp); 5767 5768 /* 5769 * Clearing NACK and defer counts to get their exact values 5770 * while reading EDID which are required by Compliance tests 5771 * 4.2.2.4 and 4.2.2.5 5772 */ 5773 intel_dp->aux.i2c_nack_count = 0; 5774 intel_dp->aux.i2c_defer_count = 0; 5775 5776 intel_dp_set_edid(intel_dp); 5777 if (intel_dp_is_edp(intel_dp) || connector->detect_edid) 5778 status = connector_status_connected; 5779 5780 intel_dp_check_device_service_irq(intel_dp); 5781 5782 out_unset_edid: 5783 if (status != connector_status_connected && !intel_dp->is_mst) 5784 intel_dp_unset_edid(intel_dp); 5785 5786 if (!intel_dp_is_edp(intel_dp)) 5787 drm_dp_set_subconnector_property(&connector->base, 5788 status, 5789 intel_dp->dpcd, 5790 intel_dp->downstream_ports); 5791 out_vdd_off: 5792 intel_pps_vdd_off(intel_dp); 5793 5794 return status; 5795 } 5796 5797 static void 5798 intel_dp_force(struct drm_connector *connector) 5799 { 5800 struct intel_display *display = to_intel_display(connector->dev); 5801 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5802 5803 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5804 connector->base.id, connector->name); 5805 5806 if (!intel_display_driver_check_access(display)) 5807 return; 5808 5809 intel_dp_unset_edid(intel_dp); 5810 5811 if (connector->status != connector_status_connected) 5812 return; 5813 5814 intel_dp_set_edid(intel_dp); 5815 } 5816 5817 static int intel_dp_get_modes(struct drm_connector *_connector) 5818 { 5819 struct intel_display *display = to_intel_display(_connector->dev); 5820 struct intel_connector *connector = to_intel_connector(_connector); 5821 struct intel_dp *intel_dp = intel_attached_dp(connector); 5822 int num_modes; 5823 5824 /* drm_edid_connector_update() done in ->detect() or ->force() */ 5825 num_modes = drm_edid_connector_add_modes(&connector->base); 5826 5827 /* Also add fixed mode, which may or may not be present in EDID */ 5828 if (intel_dp_is_edp(intel_dp)) 5829 num_modes += intel_panel_get_modes(connector); 5830 5831 if (num_modes) 5832 return num_modes; 5833 5834 if (!connector->detect_edid) { 5835 struct drm_display_mode *mode; 5836 5837 mode = drm_dp_downstream_mode(display->drm, 5838 intel_dp->dpcd, 5839 intel_dp->downstream_ports); 5840 if (mode) { 5841 drm_mode_probed_add(&connector->base, mode); 5842 num_modes++; 5843 } 5844 } 5845 5846 return num_modes; 5847 } 5848 5849 static int 5850 intel_dp_connector_register(struct drm_connector *connector) 5851 { 5852 struct intel_display *display = to_intel_display(connector->dev); 5853 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5854 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5855 int ret; 5856 5857 ret = intel_connector_register(connector); 5858 if (ret) 5859 return ret; 5860 5861 drm_dbg_kms(display->drm, "registering %s bus for %s\n", 5862 intel_dp->aux.name, connector->kdev->kobj.name); 5863 5864 intel_dp->aux.dev = connector->kdev; 5865 ret = drm_dp_aux_register(&intel_dp->aux); 5866 if (!ret) 5867 drm_dp_cec_register_connector(&intel_dp->aux, connector); 5868 5869 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 5870 return ret; 5871 5872 /* 5873 * ToDo: Clean this up to handle lspcon init and resume more 5874 * efficiently and streamlined. 5875 */ 5876 if (intel_lspcon_init(dig_port)) { 5877 if (intel_lspcon_detect_hdr_capability(dig_port)) 5878 drm_connector_attach_hdr_output_metadata_property(connector); 5879 } 5880 5881 return ret; 5882 } 5883 5884 static void 5885 intel_dp_connector_unregister(struct drm_connector *connector) 5886 { 5887 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5888 5889 drm_dp_cec_unregister_connector(&intel_dp->aux); 5890 drm_dp_aux_unregister(&intel_dp->aux); 5891 intel_connector_unregister(connector); 5892 } 5893 5894 void intel_dp_connector_sync_state(struct intel_connector *connector, 5895 const struct intel_crtc_state *crtc_state) 5896 { 5897 struct intel_display *display = to_intel_display(connector); 5898 5899 if (crtc_state && crtc_state->dsc.compression_enable) { 5900 drm_WARN_ON(display->drm, 5901 !connector->dp.dsc_decompression_aux); 5902 connector->dp.dsc_decompression_enabled = true; 5903 } else { 5904 connector->dp.dsc_decompression_enabled = false; 5905 } 5906 } 5907 5908 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) 5909 { 5910 struct intel_encoder *encoder = to_intel_encoder(_encoder); 5911 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5912 struct intel_dp *intel_dp = &dig_port->dp; 5913 5914 intel_encoder_link_check_flush_work(encoder); 5915 5916 intel_dp_mst_encoder_cleanup(dig_port); 5917 5918 intel_dp_tunnel_destroy(intel_dp); 5919 5920 intel_pps_vdd_off_sync(intel_dp); 5921 5922 /* 5923 * Ensure power off delay is respected on module remove, so that we can 5924 * reduce delays at driver probe. See pps_init_timestamps(). 5925 */ 5926 intel_pps_wait_power_cycle(intel_dp); 5927 5928 intel_dp_aux_fini(intel_dp); 5929 } 5930 5931 void intel_dp_encoder_suspend(struct intel_encoder *encoder) 5932 { 5933 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5934 5935 intel_pps_vdd_off_sync(intel_dp); 5936 5937 intel_dp_tunnel_suspend(intel_dp); 5938 } 5939 5940 void intel_dp_encoder_shutdown(struct intel_encoder *encoder) 5941 { 5942 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5943 5944 intel_pps_wait_power_cycle(intel_dp); 5945 } 5946 5947 static int intel_modeset_tile_group(struct intel_atomic_state *state, 5948 int tile_group_id) 5949 { 5950 struct intel_display *display = to_intel_display(state); 5951 struct drm_connector_list_iter conn_iter; 5952 struct drm_connector *connector; 5953 int ret = 0; 5954 5955 drm_connector_list_iter_begin(display->drm, &conn_iter); 5956 drm_for_each_connector_iter(connector, &conn_iter) { 5957 struct drm_connector_state *conn_state; 5958 struct intel_crtc_state *crtc_state; 5959 struct intel_crtc *crtc; 5960 5961 if (!connector->has_tile || 5962 connector->tile_group->id != tile_group_id) 5963 continue; 5964 5965 conn_state = drm_atomic_get_connector_state(&state->base, 5966 connector); 5967 if (IS_ERR(conn_state)) { 5968 ret = PTR_ERR(conn_state); 5969 break; 5970 } 5971 5972 crtc = to_intel_crtc(conn_state->crtc); 5973 5974 if (!crtc) 5975 continue; 5976 5977 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5978 crtc_state->uapi.mode_changed = true; 5979 5980 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 5981 if (ret) 5982 break; 5983 } 5984 drm_connector_list_iter_end(&conn_iter); 5985 5986 return ret; 5987 } 5988 5989 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 5990 { 5991 struct intel_display *display = to_intel_display(state); 5992 struct intel_crtc *crtc; 5993 5994 if (transcoders == 0) 5995 return 0; 5996 5997 for_each_intel_crtc(display->drm, crtc) { 5998 struct intel_crtc_state *crtc_state; 5999 int ret; 6000 6001 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6002 if (IS_ERR(crtc_state)) 6003 return PTR_ERR(crtc_state); 6004 6005 if (!crtc_state->hw.enable) 6006 continue; 6007 6008 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6009 continue; 6010 6011 crtc_state->uapi.mode_changed = true; 6012 6013 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6014 if (ret) 6015 return ret; 6016 6017 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6018 if (ret) 6019 return ret; 6020 6021 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6022 } 6023 6024 drm_WARN_ON(display->drm, transcoders != 0); 6025 6026 return 0; 6027 } 6028 6029 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6030 struct drm_connector *connector) 6031 { 6032 const struct drm_connector_state *old_conn_state = 6033 drm_atomic_get_old_connector_state(&state->base, connector); 6034 const struct intel_crtc_state *old_crtc_state; 6035 struct intel_crtc *crtc; 6036 u8 transcoders; 6037 6038 crtc = to_intel_crtc(old_conn_state->crtc); 6039 if (!crtc) 6040 return 0; 6041 6042 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6043 6044 if (!old_crtc_state->hw.active) 6045 return 0; 6046 6047 transcoders = old_crtc_state->sync_mode_slaves_mask; 6048 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 6049 transcoders |= BIT(old_crtc_state->master_transcoder); 6050 6051 return intel_modeset_affected_transcoders(state, 6052 transcoders); 6053 } 6054 6055 static int intel_dp_connector_atomic_check(struct drm_connector *conn, 6056 struct drm_atomic_state *_state) 6057 { 6058 struct intel_display *display = to_intel_display(conn->dev); 6059 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6060 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn); 6061 struct intel_connector *intel_conn = to_intel_connector(conn); 6062 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); 6063 int ret; 6064 6065 ret = intel_digital_connector_atomic_check(conn, &state->base); 6066 if (ret) 6067 return ret; 6068 6069 if (intel_dp_mst_source_support(intel_dp)) { 6070 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); 6071 if (ret) 6072 return ret; 6073 } 6074 6075 if (!intel_connector_needs_modeset(state, conn)) 6076 return 0; 6077 6078 ret = intel_dp_tunnel_atomic_check_state(state, 6079 intel_dp, 6080 intel_conn); 6081 if (ret) 6082 return ret; 6083 6084 /* 6085 * We don't enable port sync on BDW due to missing w/as and 6086 * due to not having adjusted the modeset sequence appropriately. 6087 */ 6088 if (DISPLAY_VER(display) < 9) 6089 return 0; 6090 6091 if (conn->has_tile) { 6092 ret = intel_modeset_tile_group(state, conn->tile_group->id); 6093 if (ret) 6094 return ret; 6095 } 6096 6097 return intel_modeset_synced_crtcs(state, conn); 6098 } 6099 6100 static void intel_dp_oob_hotplug_event(struct drm_connector *connector, 6101 enum drm_connector_status hpd_state) 6102 { 6103 struct intel_display *display = to_intel_display(connector->dev); 6104 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 6105 struct drm_i915_private *i915 = to_i915(connector->dev); 6106 bool hpd_high = hpd_state == connector_status_connected; 6107 unsigned int hpd_pin = encoder->hpd_pin; 6108 bool need_work = false; 6109 6110 spin_lock_irq(&i915->irq_lock); 6111 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) { 6112 display->hotplug.event_bits |= BIT(hpd_pin); 6113 6114 __assign_bit(hpd_pin, 6115 &display->hotplug.oob_hotplug_last_state, 6116 hpd_high); 6117 need_work = true; 6118 } 6119 spin_unlock_irq(&i915->irq_lock); 6120 6121 if (need_work) 6122 intel_hpd_schedule_detection(i915); 6123 } 6124 6125 static const struct drm_connector_funcs intel_dp_connector_funcs = { 6126 .force = intel_dp_force, 6127 .fill_modes = drm_helper_probe_single_connector_modes, 6128 .atomic_get_property = intel_digital_connector_atomic_get_property, 6129 .atomic_set_property = intel_digital_connector_atomic_set_property, 6130 .late_register = intel_dp_connector_register, 6131 .early_unregister = intel_dp_connector_unregister, 6132 .destroy = intel_connector_destroy, 6133 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6134 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6135 .oob_hotplug_event = intel_dp_oob_hotplug_event, 6136 }; 6137 6138 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6139 .detect_ctx = intel_dp_detect, 6140 .get_modes = intel_dp_get_modes, 6141 .mode_valid = intel_dp_mode_valid, 6142 .atomic_check = intel_dp_connector_atomic_check, 6143 }; 6144 6145 enum irqreturn 6146 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 6147 { 6148 struct intel_display *display = to_intel_display(dig_port); 6149 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 6150 struct intel_dp *intel_dp = &dig_port->dp; 6151 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 6152 6153 if (dig_port->base.type == INTEL_OUTPUT_EDP && 6154 (long_hpd || 6155 intel_runtime_pm_suspended(&i915->runtime_pm) || 6156 !intel_pps_have_panel_power_or_vdd(intel_dp))) { 6157 /* 6158 * vdd off can generate a long/short pulse on eDP which 6159 * would require vdd on to handle it, and thus we 6160 * would end up in an endless cycle of 6161 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 6162 */ 6163 drm_dbg_kms(display->drm, 6164 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 6165 long_hpd ? "long" : "short", 6166 dig_port->base.base.base.id, 6167 dig_port->base.base.name); 6168 return IRQ_HANDLED; 6169 } 6170 6171 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 6172 dig_port->base.base.base.id, 6173 dig_port->base.base.name, 6174 long_hpd ? "long" : "short"); 6175 6176 /* 6177 * TBT DP tunnels require the GFX driver to read out the DPRX caps in 6178 * response to long HPD pulses. The DP hotplug handler does that, 6179 * however the hotplug handler may be blocked by another 6180 * connector's/encoder's hotplug handler. Since the TBT CM may not 6181 * complete the DP tunnel BW request for the latter connector/encoder 6182 * waiting for this encoder's DPRX read, perform a dummy read here. 6183 */ 6184 if (long_hpd) 6185 intel_dp_read_dprx_caps(intel_dp, dpcd); 6186 6187 if (long_hpd) { 6188 intel_dp->reset_link_params = true; 6189 intel_dp_invalidate_source_oui(intel_dp); 6190 6191 return IRQ_NONE; 6192 } 6193 6194 if (intel_dp->is_mst) { 6195 if (!intel_dp_check_mst_status(intel_dp)) 6196 return IRQ_NONE; 6197 } else if (!intel_dp_short_pulse(intel_dp)) { 6198 return IRQ_NONE; 6199 } 6200 6201 return IRQ_HANDLED; 6202 } 6203 6204 static bool _intel_dp_is_port_edp(struct intel_display *display, 6205 const struct intel_bios_encoder_data *devdata, 6206 enum port port) 6207 { 6208 /* 6209 * eDP not supported on g4x. so bail out early just 6210 * for a bit extra safety in case the VBT is bonkers. 6211 */ 6212 if (DISPLAY_VER(display) < 5) 6213 return false; 6214 6215 if (DISPLAY_VER(display) < 9 && port == PORT_A) 6216 return true; 6217 6218 return devdata && intel_bios_encoder_supports_edp(devdata); 6219 } 6220 6221 bool intel_dp_is_port_edp(struct intel_display *display, enum port port) 6222 { 6223 const struct intel_bios_encoder_data *devdata = 6224 intel_bios_encoder_data_lookup(display, port); 6225 6226 return _intel_dp_is_port_edp(display, devdata, port); 6227 } 6228 6229 bool 6230 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) 6231 { 6232 struct intel_display *display = to_intel_display(encoder); 6233 enum port port = encoder->port; 6234 6235 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 6236 return false; 6237 6238 if (DISPLAY_VER(display) >= 11) 6239 return true; 6240 6241 if (port == PORT_A) 6242 return false; 6243 6244 if (display->platform.haswell || display->platform.broadwell || 6245 DISPLAY_VER(display) >= 9) 6246 return true; 6247 6248 return false; 6249 } 6250 6251 static void 6252 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 6253 { 6254 struct intel_display *display = to_intel_display(intel_dp); 6255 enum port port = dp_to_dig_port(intel_dp)->base.port; 6256 6257 if (!intel_dp_is_edp(intel_dp)) 6258 drm_connector_attach_dp_subconnector_property(connector); 6259 6260 if (!display->platform.g4x && port != PORT_A) 6261 intel_attach_force_audio_property(connector); 6262 6263 intel_attach_broadcast_rgb_property(connector); 6264 if (HAS_GMCH(display)) 6265 drm_connector_attach_max_bpc_property(connector, 6, 10); 6266 else if (DISPLAY_VER(display) >= 5) 6267 drm_connector_attach_max_bpc_property(connector, 6, 12); 6268 6269 /* Register HDMI colorspace for case of lspcon */ 6270 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 6271 drm_connector_attach_content_type_property(connector); 6272 intel_attach_hdmi_colorspace_property(connector); 6273 } else { 6274 intel_attach_dp_colorspace_property(connector); 6275 } 6276 6277 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 6278 drm_connector_attach_hdr_output_metadata_property(connector); 6279 6280 if (HAS_VRR(display)) 6281 drm_connector_attach_vrr_capable_property(connector); 6282 } 6283 6284 static void 6285 intel_edp_add_properties(struct intel_dp *intel_dp) 6286 { 6287 struct intel_display *display = to_intel_display(intel_dp); 6288 struct intel_connector *connector = intel_dp->attached_connector; 6289 const struct drm_display_mode *fixed_mode = 6290 intel_panel_preferred_fixed_mode(connector); 6291 6292 intel_attach_scaling_mode_property(&connector->base); 6293 6294 drm_connector_set_panel_orientation_with_quirk(&connector->base, 6295 display->vbt.orientation, 6296 fixed_mode->hdisplay, 6297 fixed_mode->vdisplay); 6298 } 6299 6300 static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 6301 struct intel_connector *connector) 6302 { 6303 struct intel_display *display = to_intel_display(intel_dp); 6304 enum pipe pipe = INVALID_PIPE; 6305 6306 if (display->platform.valleyview || display->platform.cherryview) 6307 pipe = vlv_pps_backlight_initial_pipe(intel_dp); 6308 6309 intel_backlight_setup(connector, pipe); 6310 } 6311 6312 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6313 struct intel_connector *connector) 6314 { 6315 struct intel_display *display = to_intel_display(intel_dp); 6316 struct drm_i915_private *dev_priv = to_i915(display->drm); 6317 struct drm_display_mode *fixed_mode; 6318 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6319 bool has_dpcd; 6320 const struct drm_edid *drm_edid; 6321 6322 if (!intel_dp_is_edp(intel_dp)) 6323 return true; 6324 6325 /* 6326 * On IBX/CPT we may get here with LVDS already registered. Since the 6327 * driver uses the only internal power sequencer available for both 6328 * eDP and LVDS bail out early in this case to prevent interfering 6329 * with an already powered-on LVDS power sequencer. 6330 */ 6331 if (intel_get_lvds_encoder(dev_priv)) { 6332 drm_WARN_ON(display->drm, 6333 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 6334 drm_info(display->drm, 6335 "LVDS was detected, not registering eDP\n"); 6336 6337 return false; 6338 } 6339 6340 intel_bios_init_panel_early(display, &connector->panel, 6341 encoder->devdata); 6342 6343 if (!intel_pps_init(intel_dp)) { 6344 drm_info(display->drm, 6345 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6346 encoder->base.base.id, encoder->base.name); 6347 /* 6348 * The BIOS may have still enabled VDD on the PPS even 6349 * though it's unusable. Make sure we turn it back off 6350 * and to release the power domain references/etc. 6351 */ 6352 goto out_vdd_off; 6353 } 6354 6355 /* 6356 * Enable HPD sense for live status check. 6357 * intel_hpd_irq_setup() will turn it off again 6358 * if it's no longer needed later. 6359 * 6360 * The DPCD probe below will make sure VDD is on. 6361 */ 6362 intel_hpd_enable_detection(encoder); 6363 6364 intel_alpm_init_dpcd(intel_dp); 6365 6366 /* Cache DPCD and EDID for edp. */ 6367 has_dpcd = intel_edp_init_dpcd(intel_dp, connector); 6368 6369 if (!has_dpcd) { 6370 /* if this fails, presume the device is a ghost */ 6371 drm_info(display->drm, 6372 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6373 encoder->base.base.id, encoder->base.name); 6374 goto out_vdd_off; 6375 } 6376 6377 /* 6378 * VBT and straps are liars. Also check HPD as that seems 6379 * to be the most reliable piece of information available. 6380 * 6381 * ... expect on devices that forgot to hook HPD up for eDP 6382 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6383 * ports are attempting to use the same AUX CH, according to VBT. 6384 */ 6385 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6386 /* 6387 * If this fails, presume the DPCD answer came 6388 * from some other port using the same AUX CH. 6389 * 6390 * FIXME maybe cleaner to check this before the 6391 * DPCD read? Would need sort out the VDD handling... 6392 */ 6393 if (!intel_digital_port_connected(encoder)) { 6394 drm_info(display->drm, 6395 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6396 encoder->base.base.id, encoder->base.name); 6397 goto out_vdd_off; 6398 } 6399 6400 /* 6401 * Unfortunately even the HPD based detection fails on 6402 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6403 * back to checking for a VGA branch device. Only do this 6404 * on known affected platforms to minimize false positives. 6405 */ 6406 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6407 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6408 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6409 drm_info(display->drm, 6410 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6411 encoder->base.base.id, encoder->base.name); 6412 goto out_vdd_off; 6413 } 6414 } 6415 6416 mutex_lock(&display->drm->mode_config.mutex); 6417 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 6418 if (!drm_edid) { 6419 /* Fallback to EDID from ACPI OpRegion, if any */ 6420 drm_edid = intel_opregion_get_edid(connector); 6421 if (drm_edid) 6422 drm_dbg_kms(display->drm, 6423 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6424 connector->base.base.id, connector->base.name); 6425 } 6426 if (drm_edid) { 6427 if (drm_edid_connector_update(&connector->base, drm_edid) || 6428 !drm_edid_connector_add_modes(&connector->base)) { 6429 drm_edid_connector_update(&connector->base, NULL); 6430 drm_edid_free(drm_edid); 6431 drm_edid = ERR_PTR(-EINVAL); 6432 } 6433 } else { 6434 drm_edid = ERR_PTR(-ENOENT); 6435 } 6436 6437 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata, 6438 IS_ERR(drm_edid) ? NULL : drm_edid); 6439 6440 intel_panel_add_edid_fixed_modes(connector, true); 6441 6442 /* MSO requires information from the EDID */ 6443 intel_edp_mso_init(intel_dp); 6444 6445 /* multiply the mode clock and horizontal timings for MSO */ 6446 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 6447 intel_edp_mso_mode_fixup(connector, fixed_mode); 6448 6449 /* fallback to VBT if available for eDP */ 6450 if (!intel_panel_preferred_fixed_mode(connector)) 6451 intel_panel_add_vbt_lfp_fixed_mode(connector); 6452 6453 mutex_unlock(&display->drm->mode_config.mutex); 6454 6455 if (!intel_panel_preferred_fixed_mode(connector)) { 6456 drm_info(display->drm, 6457 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6458 encoder->base.base.id, encoder->base.name); 6459 goto out_vdd_off; 6460 } 6461 6462 intel_panel_init(connector, drm_edid); 6463 6464 intel_edp_backlight_setup(intel_dp, connector); 6465 6466 intel_edp_add_properties(intel_dp); 6467 6468 intel_pps_init_late(intel_dp); 6469 6470 return true; 6471 6472 out_vdd_off: 6473 intel_pps_vdd_off_sync(intel_dp); 6474 intel_bios_fini_panel(&connector->panel); 6475 6476 return false; 6477 } 6478 6479 bool 6480 intel_dp_init_connector(struct intel_digital_port *dig_port, 6481 struct intel_connector *connector) 6482 { 6483 struct intel_display *display = to_intel_display(dig_port); 6484 struct intel_dp *intel_dp = &dig_port->dp; 6485 struct intel_encoder *encoder = &dig_port->base; 6486 struct drm_device *dev = encoder->base.dev; 6487 enum port port = encoder->port; 6488 int type; 6489 6490 if (drm_WARN(dev, dig_port->max_lanes < 1, 6491 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 6492 dig_port->max_lanes, encoder->base.base.id, 6493 encoder->base.name)) 6494 return false; 6495 6496 intel_dp->reset_link_params = true; 6497 6498 /* Preserve the current hw state. */ 6499 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 6500 intel_dp->attached_connector = connector; 6501 6502 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) { 6503 /* 6504 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, 6505 * although in theory it could work on TypeC legacy ports. 6506 */ 6507 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) && 6508 DISPLAY_VER(display) < 30); 6509 type = DRM_MODE_CONNECTOR_eDP; 6510 encoder->type = INTEL_OUTPUT_EDP; 6511 6512 /* eDP only on port B and/or C on vlv/chv */ 6513 if (drm_WARN_ON(dev, (display->platform.valleyview || 6514 display->platform.cherryview) && 6515 port != PORT_B && port != PORT_C)) 6516 return false; 6517 } else { 6518 type = DRM_MODE_CONNECTOR_DisplayPort; 6519 } 6520 6521 intel_dp_set_default_sink_rates(intel_dp); 6522 intel_dp_set_default_max_sink_lane_count(intel_dp); 6523 6524 if (display->platform.valleyview || display->platform.cherryview) 6525 vlv_pps_pipe_init(intel_dp); 6526 6527 intel_dp_aux_init(intel_dp); 6528 connector->dp.dsc_decompression_aux = &intel_dp->aux; 6529 6530 drm_dbg_kms(display->drm, 6531 "Adding %s connector on [ENCODER:%d:%s]\n", 6532 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 6533 encoder->base.base.id, encoder->base.name); 6534 6535 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs, 6536 type, &intel_dp->aux.ddc); 6537 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs); 6538 6539 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12) 6540 connector->base.interlace_allowed = true; 6541 6542 if (type != DRM_MODE_CONNECTOR_eDP) 6543 connector->polled = DRM_CONNECTOR_POLL_HPD; 6544 connector->base.polled = connector->polled; 6545 6546 intel_connector_attach_encoder(connector, encoder); 6547 6548 if (HAS_DDI(display)) 6549 connector->get_hw_state = intel_ddi_connector_get_hw_state; 6550 else 6551 connector->get_hw_state = intel_connector_get_hw_state; 6552 connector->sync_state = intel_dp_connector_sync_state; 6553 6554 if (!intel_edp_init_connector(intel_dp, connector)) { 6555 intel_dp_aux_fini(intel_dp); 6556 goto fail; 6557 } 6558 6559 intel_dp_set_source_rates(intel_dp); 6560 intel_dp_set_common_rates(intel_dp); 6561 intel_dp_reset_link_params(intel_dp); 6562 6563 /* init MST on ports that can support it */ 6564 intel_dp_mst_encoder_init(dig_port, connector->base.base.id); 6565 6566 intel_dp_add_properties(intel_dp, &connector->base); 6567 6568 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) { 6569 int ret = intel_dp_hdcp_init(dig_port, connector); 6570 if (ret) 6571 drm_dbg_kms(display->drm, 6572 "HDCP init failed, skipping.\n"); 6573 } 6574 6575 intel_dp->frl.is_trained = false; 6576 intel_dp->frl.trained_rate_gbps = 0; 6577 6578 intel_psr_init(intel_dp); 6579 6580 return true; 6581 6582 fail: 6583 intel_display_power_flush_work(display); 6584 drm_connector_cleanup(&connector->base); 6585 6586 return false; 6587 } 6588 6589 void intel_dp_mst_suspend(struct intel_display *display) 6590 { 6591 struct intel_encoder *encoder; 6592 6593 if (!HAS_DISPLAY(display)) 6594 return; 6595 6596 for_each_intel_encoder(display->drm, encoder) { 6597 struct intel_dp *intel_dp; 6598 6599 if (encoder->type != INTEL_OUTPUT_DDI) 6600 continue; 6601 6602 intel_dp = enc_to_intel_dp(encoder); 6603 6604 if (!intel_dp_mst_source_support(intel_dp)) 6605 continue; 6606 6607 if (intel_dp->is_mst) 6608 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); 6609 } 6610 } 6611 6612 void intel_dp_mst_resume(struct intel_display *display) 6613 { 6614 struct intel_encoder *encoder; 6615 6616 if (!HAS_DISPLAY(display)) 6617 return; 6618 6619 for_each_intel_encoder(display->drm, encoder) { 6620 struct intel_dp *intel_dp; 6621 int ret; 6622 6623 if (encoder->type != INTEL_OUTPUT_DDI) 6624 continue; 6625 6626 intel_dp = enc_to_intel_dp(encoder); 6627 6628 if (!intel_dp_mst_source_support(intel_dp)) 6629 continue; 6630 6631 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, 6632 true); 6633 if (ret) { 6634 intel_dp->is_mst = false; 6635 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 6636 false); 6637 } 6638 } 6639 } 6640