1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_de.h" 31 #include "intel_dmc.h" 32 #include "intel_dmc_regs.h" 33 34 /** 35 * DOC: DMC Firmware Support 36 * 37 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 38 * engine to save and restore the state of display engine when it enter into 39 * low-power state and comes back to normal. 40 */ 41 42 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 43 44 enum intel_dmc_id { 45 DMC_FW_MAIN = 0, 46 DMC_FW_PIPEA, 47 DMC_FW_PIPEB, 48 DMC_FW_PIPEC, 49 DMC_FW_PIPED, 50 DMC_FW_MAX 51 }; 52 53 struct intel_dmc { 54 struct drm_i915_private *i915; 55 struct work_struct work; 56 const char *fw_path; 57 u32 max_fw_size; /* bytes */ 58 u32 version; 59 struct dmc_fw_info { 60 u32 mmio_count; 61 i915_reg_t mmioaddr[20]; 62 u32 mmiodata[20]; 63 u32 dmc_offset; 64 u32 start_mmioaddr; 65 u32 dmc_fw_size; /*dwords */ 66 u32 *payload; 67 bool present; 68 } dmc_info[DMC_FW_MAX]; 69 }; 70 71 /* Note: This may be NULL. */ 72 static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915) 73 { 74 return i915->display.dmc.dmc; 75 } 76 77 static const char *dmc_firmware_param(struct drm_i915_private *i915) 78 { 79 const char *p = i915->display.params.dmc_firmware_path; 80 81 return p && *p ? p : NULL; 82 } 83 84 static bool dmc_firmware_param_disabled(struct drm_i915_private *i915) 85 { 86 const char *p = dmc_firmware_param(i915); 87 88 /* Magic path to indicate disabled */ 89 return p && !strcmp(p, "/dev/null"); 90 } 91 92 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 93 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 94 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 95 96 #define DMC_PATH(platform) \ 97 "i915/" __stringify(platform) "_dmc.bin" 98 99 /* 100 * New DMC additions should not use this. This is used solely to remain 101 * compatible with systems that have not yet updated DMC blobs to use 102 * unversioned file names. 103 */ 104 #define DMC_LEGACY_PATH(platform, major, minor) \ 105 "i915/" \ 106 __stringify(platform) "_dmc_ver" \ 107 __stringify(major) "_" \ 108 __stringify(minor) ".bin" 109 110 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 111 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 112 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 113 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 114 115 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 116 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 117 118 #define BMG_DMC_PATH DMC_PATH(bmg) 119 MODULE_FIRMWARE(BMG_DMC_PATH); 120 121 #define MTL_DMC_PATH DMC_PATH(mtl) 122 MODULE_FIRMWARE(MTL_DMC_PATH); 123 124 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 125 MODULE_FIRMWARE(DG2_DMC_PATH); 126 127 #define ADLP_DMC_PATH DMC_PATH(adlp) 128 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 129 MODULE_FIRMWARE(ADLP_DMC_PATH); 130 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 131 132 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 133 MODULE_FIRMWARE(ADLS_DMC_PATH); 134 135 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 136 MODULE_FIRMWARE(DG1_DMC_PATH); 137 138 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 139 MODULE_FIRMWARE(RKL_DMC_PATH); 140 141 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 142 MODULE_FIRMWARE(TGL_DMC_PATH); 143 144 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 145 #define ICL_DMC_MAX_FW_SIZE 0x6000 146 MODULE_FIRMWARE(ICL_DMC_PATH); 147 148 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 149 #define GLK_DMC_MAX_FW_SIZE 0x4000 150 MODULE_FIRMWARE(GLK_DMC_PATH); 151 152 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 153 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 154 MODULE_FIRMWARE(KBL_DMC_PATH); 155 156 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 157 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 158 MODULE_FIRMWARE(SKL_DMC_PATH); 159 160 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 161 #define BXT_DMC_MAX_FW_SIZE 0x3000 162 MODULE_FIRMWARE(BXT_DMC_PATH); 163 164 static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size) 165 { 166 const char *fw_path = NULL; 167 u32 max_fw_size = 0; 168 169 if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) { 170 fw_path = XE2LPD_DMC_PATH; 171 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 172 } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) { 173 fw_path = BMG_DMC_PATH; 174 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 175 } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { 176 fw_path = MTL_DMC_PATH; 177 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 178 } else if (IS_DG2(i915)) { 179 fw_path = DG2_DMC_PATH; 180 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 181 } else if (IS_ALDERLAKE_P(i915)) { 182 fw_path = ADLP_DMC_PATH; 183 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 184 } else if (IS_ALDERLAKE_S(i915)) { 185 fw_path = ADLS_DMC_PATH; 186 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 187 } else if (IS_DG1(i915)) { 188 fw_path = DG1_DMC_PATH; 189 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 190 } else if (IS_ROCKETLAKE(i915)) { 191 fw_path = RKL_DMC_PATH; 192 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 193 } else if (IS_TIGERLAKE(i915)) { 194 fw_path = TGL_DMC_PATH; 195 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 196 } else if (DISPLAY_VER(i915) == 11) { 197 fw_path = ICL_DMC_PATH; 198 max_fw_size = ICL_DMC_MAX_FW_SIZE; 199 } else if (IS_GEMINILAKE(i915)) { 200 fw_path = GLK_DMC_PATH; 201 max_fw_size = GLK_DMC_MAX_FW_SIZE; 202 } else if (IS_KABYLAKE(i915) || 203 IS_COFFEELAKE(i915) || 204 IS_COMETLAKE(i915)) { 205 fw_path = KBL_DMC_PATH; 206 max_fw_size = KBL_DMC_MAX_FW_SIZE; 207 } else if (IS_SKYLAKE(i915)) { 208 fw_path = SKL_DMC_PATH; 209 max_fw_size = SKL_DMC_MAX_FW_SIZE; 210 } else if (IS_BROXTON(i915)) { 211 fw_path = BXT_DMC_PATH; 212 max_fw_size = BXT_DMC_MAX_FW_SIZE; 213 } 214 215 *size = max_fw_size; 216 217 return fw_path; 218 } 219 220 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 221 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 222 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 223 #define DMC_V1_MAX_MMIO_COUNT 8 224 #define DMC_V3_MAX_MMIO_COUNT 20 225 #define DMC_V1_MMIO_START_RANGE 0x80000 226 227 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 228 229 struct intel_css_header { 230 /* 0x09 for DMC */ 231 u32 module_type; 232 233 /* Includes the DMC specific header in dwords */ 234 u32 header_len; 235 236 /* always value would be 0x10000 */ 237 u32 header_ver; 238 239 /* Not used */ 240 u32 module_id; 241 242 /* Not used */ 243 u32 module_vendor; 244 245 /* in YYYYMMDD format */ 246 u32 date; 247 248 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 249 u32 size; 250 251 /* Not used */ 252 u32 key_size; 253 254 /* Not used */ 255 u32 modulus_size; 256 257 /* Not used */ 258 u32 exponent_size; 259 260 /* Not used */ 261 u32 reserved1[12]; 262 263 /* Major Minor */ 264 u32 version; 265 266 /* Not used */ 267 u32 reserved2[8]; 268 269 /* Not used */ 270 u32 kernel_header_info; 271 } __packed; 272 273 struct intel_fw_info { 274 u8 reserved1; 275 276 /* reserved on package_header version 1, must be 0 on version 2 */ 277 u8 dmc_id; 278 279 /* Stepping (A, B, C, ..., *). * is a wildcard */ 280 char stepping; 281 282 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 283 char substepping; 284 285 u32 offset; 286 u32 reserved2; 287 } __packed; 288 289 struct intel_package_header { 290 /* DMC container header length in dwords */ 291 u8 header_len; 292 293 /* 0x01, 0x02 */ 294 u8 header_ver; 295 296 u8 reserved[10]; 297 298 /* Number of valid entries in the FWInfo array below */ 299 u32 num_entries; 300 } __packed; 301 302 struct intel_dmc_header_base { 303 /* always value would be 0x40403E3E */ 304 u32 signature; 305 306 /* DMC binary header length */ 307 u8 header_len; 308 309 /* 0x01 */ 310 u8 header_ver; 311 312 /* Reserved */ 313 u16 dmcc_ver; 314 315 /* Major, Minor */ 316 u32 project; 317 318 /* Firmware program size (excluding header) in dwords */ 319 u32 fw_size; 320 321 /* Major Minor version */ 322 u32 fw_version; 323 } __packed; 324 325 struct intel_dmc_header_v1 { 326 struct intel_dmc_header_base base; 327 328 /* Number of valid MMIO cycles present. */ 329 u32 mmio_count; 330 331 /* MMIO address */ 332 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 333 334 /* MMIO data */ 335 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 336 337 /* FW filename */ 338 char dfile[32]; 339 340 u32 reserved1[2]; 341 } __packed; 342 343 struct intel_dmc_header_v3 { 344 struct intel_dmc_header_base base; 345 346 /* DMC RAM start MMIO address */ 347 u32 start_mmioaddr; 348 349 u32 reserved[9]; 350 351 /* FW filename */ 352 char dfile[32]; 353 354 /* Number of valid MMIO cycles present. */ 355 u32 mmio_count; 356 357 /* MMIO address */ 358 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 359 360 /* MMIO data */ 361 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 362 } __packed; 363 364 struct stepping_info { 365 char stepping; 366 char substepping; 367 }; 368 369 #define for_each_dmc_id(__dmc_id) \ 370 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 371 372 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 373 { 374 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 375 } 376 377 static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id) 378 { 379 struct intel_dmc *dmc = i915_to_dmc(i915); 380 381 return dmc && dmc->dmc_info[dmc_id].payload; 382 } 383 384 bool intel_dmc_has_payload(struct drm_i915_private *i915) 385 { 386 return has_dmc_id_fw(i915, DMC_FW_MAIN); 387 } 388 389 static const struct stepping_info * 390 intel_get_stepping_info(struct drm_i915_private *i915, 391 struct stepping_info *si) 392 { 393 const char *step_name = intel_display_step_name(i915); 394 395 si->stepping = step_name[0]; 396 si->substepping = step_name[1]; 397 return si; 398 } 399 400 static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915) 401 { 402 /* The below bit doesn't need to be cleared ever afterwards */ 403 intel_de_rmw(i915, DC_STATE_DEBUG, 0, 404 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 405 intel_de_posting_read(i915, DC_STATE_DEBUG); 406 } 407 408 static void disable_event_handler(struct drm_i915_private *i915, 409 i915_reg_t ctl_reg, i915_reg_t htp_reg) 410 { 411 intel_de_write(i915, ctl_reg, 412 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 413 DMC_EVT_CTL_TYPE_EDGE_0_1) | 414 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 415 DMC_EVT_CTL_EVENT_ID_FALSE)); 416 intel_de_write(i915, htp_reg, 0); 417 } 418 419 static void disable_all_event_handlers(struct drm_i915_private *i915) 420 { 421 enum intel_dmc_id dmc_id; 422 423 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 424 if (DISPLAY_VER(i915) < 12) 425 return; 426 427 for_each_dmc_id(dmc_id) { 428 int handler; 429 430 if (!has_dmc_id_fw(i915, dmc_id)) 431 continue; 432 433 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 434 disable_event_handler(i915, 435 DMC_EVT_CTL(i915, dmc_id, handler), 436 DMC_EVT_HTP(i915, dmc_id, handler)); 437 } 438 } 439 440 static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 441 { 442 enum pipe pipe; 443 444 /* 445 * Wa_16015201720:adl-p,dg2 446 * The WA requires clock gating to be disabled all the time 447 * for pipe A and B. 448 * For pipe C and D clock gating needs to be disabled only 449 * during initializing the firmware. 450 */ 451 if (enable) 452 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 453 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 454 0, PIPEDMC_GATING_DIS); 455 else 456 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 457 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 458 PIPEDMC_GATING_DIS, 0); 459 } 460 461 static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) 462 { 463 /* 464 * Wa_16015201720 465 * The WA requires clock gating to be disabled all the time 466 * for pipe A and B. 467 */ 468 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, 469 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 470 } 471 472 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 473 { 474 if (DISPLAY_VER(i915) >= 14 && enable) 475 mtl_pipedmc_clock_gating_wa(i915); 476 else if (DISPLAY_VER(i915) == 13) 477 adlp_pipedmc_clock_gating_wa(i915, enable); 478 } 479 480 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) 481 { 482 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 483 484 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 485 return; 486 487 if (DISPLAY_VER(i915) >= 14) 488 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 489 else 490 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 491 } 492 493 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) 494 { 495 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 496 497 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 498 return; 499 500 if (DISPLAY_VER(i915) >= 14) 501 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 502 else 503 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 504 } 505 506 static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915, 507 enum intel_dmc_id dmc_id, i915_reg_t reg) 508 { 509 u32 offset = i915_mmio_reg_offset(reg); 510 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0)); 511 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 512 513 return offset >= start && offset < end; 514 } 515 516 static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915, 517 enum intel_dmc_id dmc_id, i915_reg_t reg) 518 { 519 u32 offset = i915_mmio_reg_offset(reg); 520 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0)); 521 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 522 523 return offset >= start && offset < end; 524 } 525 526 static bool disable_dmc_evt(struct drm_i915_private *i915, 527 enum intel_dmc_id dmc_id, 528 i915_reg_t reg, u32 data) 529 { 530 if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg)) 531 return false; 532 533 /* keep all pipe DMC events disabled by default */ 534 if (dmc_id != DMC_FW_MAIN) 535 return true; 536 537 /* also disable the flip queue event on the main DMC on TGL */ 538 if (IS_TIGERLAKE(i915) && 539 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) 540 return true; 541 542 /* also disable the HRR event on the main DMC on TGL/ADLS */ 543 if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) && 544 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) 545 return true; 546 547 return false; 548 } 549 550 static u32 dmc_mmiodata(struct drm_i915_private *i915, 551 struct intel_dmc *dmc, 552 enum intel_dmc_id dmc_id, int i) 553 { 554 if (disable_dmc_evt(i915, dmc_id, 555 dmc->dmc_info[dmc_id].mmioaddr[i], 556 dmc->dmc_info[dmc_id].mmiodata[i])) 557 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 558 DMC_EVT_CTL_TYPE_EDGE_0_1) | 559 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 560 DMC_EVT_CTL_EVENT_ID_FALSE); 561 else 562 return dmc->dmc_info[dmc_id].mmiodata[i]; 563 } 564 565 /** 566 * intel_dmc_load_program() - write the firmware from memory to register. 567 * @i915: i915 drm device. 568 * 569 * DMC firmware is read from a .bin file and kept in internal memory one time. 570 * Everytime display comes back from low power state this function is called to 571 * copy the firmware from internal memory to registers. 572 */ 573 void intel_dmc_load_program(struct drm_i915_private *i915) 574 { 575 struct i915_power_domains *power_domains = &i915->display.power.domains; 576 struct intel_dmc *dmc = i915_to_dmc(i915); 577 enum intel_dmc_id dmc_id; 578 u32 i; 579 580 if (!intel_dmc_has_payload(i915)) 581 return; 582 583 pipedmc_clock_gating_wa(i915, true); 584 585 disable_all_event_handlers(i915); 586 587 assert_rpm_wakelock_held(&i915->runtime_pm); 588 589 preempt_disable(); 590 591 for_each_dmc_id(dmc_id) { 592 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 593 intel_de_write_fw(i915, 594 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 595 dmc->dmc_info[dmc_id].payload[i]); 596 } 597 } 598 599 preempt_enable(); 600 601 for_each_dmc_id(dmc_id) { 602 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 603 intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], 604 dmc_mmiodata(i915, dmc, dmc_id, i)); 605 } 606 } 607 608 power_domains->dc_state = 0; 609 610 gen9_set_dc_state_debugmask(i915); 611 612 pipedmc_clock_gating_wa(i915, false); 613 } 614 615 /** 616 * intel_dmc_disable_program() - disable the firmware 617 * @i915: i915 drm device 618 * 619 * Disable all event handlers in the firmware, making sure the firmware is 620 * inactive after the display is uninitialized. 621 */ 622 void intel_dmc_disable_program(struct drm_i915_private *i915) 623 { 624 if (!intel_dmc_has_payload(i915)) 625 return; 626 627 pipedmc_clock_gating_wa(i915, true); 628 disable_all_event_handlers(i915); 629 pipedmc_clock_gating_wa(i915, false); 630 631 intel_dmc_wl_disable(&i915->display); 632 } 633 634 void assert_dmc_loaded(struct drm_i915_private *i915) 635 { 636 struct intel_dmc *dmc = i915_to_dmc(i915); 637 638 drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n"); 639 drm_WARN_ONCE(&i915->drm, dmc && 640 !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 641 "DMC program storage start is NULL\n"); 642 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 643 "DMC SSP Base Not fine\n"); 644 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 645 "DMC HTP Not fine\n"); 646 } 647 648 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 649 const struct stepping_info *si) 650 { 651 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 652 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 653 /* 654 * If we don't find a more specific one from above two checks, we 655 * then check for the generic one to be sure to work even with 656 * "broken firmware" 657 */ 658 (si->stepping == '*' && si->substepping == fw_info->substepping) || 659 (fw_info->stepping == '*' && fw_info->substepping == '*')) 660 return true; 661 662 return false; 663 } 664 665 /* 666 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 667 * already sanitized. 668 */ 669 static void dmc_set_fw_offset(struct intel_dmc *dmc, 670 const struct intel_fw_info *fw_info, 671 unsigned int num_entries, 672 const struct stepping_info *si, 673 u8 package_ver) 674 { 675 struct drm_i915_private *i915 = dmc->i915; 676 enum intel_dmc_id dmc_id; 677 unsigned int i; 678 679 for (i = 0; i < num_entries; i++) { 680 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 681 682 if (!is_valid_dmc_id(dmc_id)) { 683 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id); 684 continue; 685 } 686 687 /* More specific versions come first, so we don't even have to 688 * check for the stepping since we already found a previous FW 689 * for this id. 690 */ 691 if (dmc->dmc_info[dmc_id].present) 692 continue; 693 694 if (fw_info_matches_stepping(&fw_info[i], si)) { 695 dmc->dmc_info[dmc_id].present = true; 696 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 697 } 698 } 699 } 700 701 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 702 const u32 *mmioaddr, u32 mmio_count, 703 int header_ver, enum intel_dmc_id dmc_id) 704 { 705 struct drm_i915_private *i915 = dmc->i915; 706 u32 start_range, end_range; 707 int i; 708 709 if (header_ver == 1) { 710 start_range = DMC_MMIO_START_RANGE; 711 end_range = DMC_MMIO_END_RANGE; 712 } else if (dmc_id == DMC_FW_MAIN) { 713 start_range = TGL_MAIN_MMIO_START; 714 end_range = TGL_MAIN_MMIO_END; 715 } else if (DISPLAY_VER(i915) >= 13) { 716 start_range = ADLP_PIPE_MMIO_START; 717 end_range = ADLP_PIPE_MMIO_END; 718 } else if (DISPLAY_VER(i915) >= 12) { 719 start_range = TGL_PIPE_MMIO_START(dmc_id); 720 end_range = TGL_PIPE_MMIO_END(dmc_id); 721 } else { 722 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 723 return false; 724 } 725 726 for (i = 0; i < mmio_count; i++) { 727 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 728 return false; 729 } 730 731 return true; 732 } 733 734 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 735 const struct intel_dmc_header_base *dmc_header, 736 size_t rem_size, enum intel_dmc_id dmc_id) 737 { 738 struct drm_i915_private *i915 = dmc->i915; 739 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 740 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 741 const u32 *mmioaddr, *mmiodata; 742 u32 mmio_count, mmio_count_max, start_mmioaddr; 743 u8 *payload; 744 745 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 746 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 747 748 /* 749 * Check if we can access common fields, we will checkc again below 750 * after we have read the version 751 */ 752 if (rem_size < sizeof(struct intel_dmc_header_base)) 753 goto error_truncated; 754 755 /* Cope with small differences between v1 and v3 */ 756 if (dmc_header->header_ver == 3) { 757 const struct intel_dmc_header_v3 *v3 = 758 (const struct intel_dmc_header_v3 *)dmc_header; 759 760 if (rem_size < sizeof(struct intel_dmc_header_v3)) 761 goto error_truncated; 762 763 mmioaddr = v3->mmioaddr; 764 mmiodata = v3->mmiodata; 765 mmio_count = v3->mmio_count; 766 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 767 /* header_len is in dwords */ 768 header_len_bytes = dmc_header->header_len * 4; 769 start_mmioaddr = v3->start_mmioaddr; 770 dmc_header_size = sizeof(*v3); 771 } else if (dmc_header->header_ver == 1) { 772 const struct intel_dmc_header_v1 *v1 = 773 (const struct intel_dmc_header_v1 *)dmc_header; 774 775 if (rem_size < sizeof(struct intel_dmc_header_v1)) 776 goto error_truncated; 777 778 mmioaddr = v1->mmioaddr; 779 mmiodata = v1->mmiodata; 780 mmio_count = v1->mmio_count; 781 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 782 header_len_bytes = dmc_header->header_len; 783 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 784 dmc_header_size = sizeof(*v1); 785 } else { 786 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 787 dmc_header->header_ver); 788 return 0; 789 } 790 791 if (header_len_bytes != dmc_header_size) { 792 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 793 "(%u bytes)\n", header_len_bytes); 794 return 0; 795 } 796 797 /* Cache the dmc header info. */ 798 if (mmio_count > mmio_count_max) { 799 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 800 return 0; 801 } 802 803 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 804 dmc_header->header_ver, dmc_id)) { 805 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 806 return 0; 807 } 808 809 drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id); 810 for (i = 0; i < mmio_count; i++) { 811 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 812 dmc_info->mmiodata[i] = mmiodata[i]; 813 814 drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 815 i, mmioaddr[i], mmiodata[i], 816 is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 817 is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 818 disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i], 819 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 820 } 821 dmc_info->mmio_count = mmio_count; 822 dmc_info->start_mmioaddr = start_mmioaddr; 823 824 rem_size -= header_len_bytes; 825 826 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 827 payload_size = dmc_header->fw_size * 4; 828 if (rem_size < payload_size) 829 goto error_truncated; 830 831 if (payload_size > dmc->max_fw_size) { 832 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 833 return 0; 834 } 835 dmc_info->dmc_fw_size = dmc_header->fw_size; 836 837 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 838 if (!dmc_info->payload) 839 return 0; 840 841 payload = (u8 *)(dmc_header) + header_len_bytes; 842 memcpy(dmc_info->payload, payload, payload_size); 843 844 return header_len_bytes + payload_size; 845 846 error_truncated: 847 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 848 return 0; 849 } 850 851 static u32 852 parse_dmc_fw_package(struct intel_dmc *dmc, 853 const struct intel_package_header *package_header, 854 const struct stepping_info *si, 855 size_t rem_size) 856 { 857 struct drm_i915_private *i915 = dmc->i915; 858 u32 package_size = sizeof(struct intel_package_header); 859 u32 num_entries, max_entries; 860 const struct intel_fw_info *fw_info; 861 862 if (rem_size < package_size) 863 goto error_truncated; 864 865 if (package_header->header_ver == 1) { 866 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 867 } else if (package_header->header_ver == 2) { 868 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 869 } else { 870 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 871 package_header->header_ver); 872 return 0; 873 } 874 875 /* 876 * We should always have space for max_entries, 877 * even if not all are used 878 */ 879 package_size += max_entries * sizeof(struct intel_fw_info); 880 if (rem_size < package_size) 881 goto error_truncated; 882 883 if (package_header->header_len * 4 != package_size) { 884 drm_err(&i915->drm, "DMC firmware has wrong package header length " 885 "(%u bytes)\n", package_size); 886 return 0; 887 } 888 889 num_entries = package_header->num_entries; 890 if (WARN_ON(package_header->num_entries > max_entries)) 891 num_entries = max_entries; 892 893 fw_info = (const struct intel_fw_info *) 894 ((u8 *)package_header + sizeof(*package_header)); 895 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 896 package_header->header_ver); 897 898 /* dmc_offset is in dwords */ 899 return package_size; 900 901 error_truncated: 902 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 903 return 0; 904 } 905 906 /* Return number of bytes parsed or 0 on error */ 907 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 908 struct intel_css_header *css_header, 909 size_t rem_size) 910 { 911 struct drm_i915_private *i915 = dmc->i915; 912 913 if (rem_size < sizeof(struct intel_css_header)) { 914 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 915 return 0; 916 } 917 918 if (sizeof(struct intel_css_header) != 919 (css_header->header_len * 4)) { 920 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 921 "(%u bytes)\n", 922 (css_header->header_len * 4)); 923 return 0; 924 } 925 926 dmc->version = css_header->version; 927 928 return sizeof(struct intel_css_header); 929 } 930 931 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 932 { 933 struct drm_i915_private *i915 = dmc->i915; 934 struct intel_css_header *css_header; 935 struct intel_package_header *package_header; 936 struct intel_dmc_header_base *dmc_header; 937 struct stepping_info display_info = { '*', '*'}; 938 const struct stepping_info *si = intel_get_stepping_info(i915, &display_info); 939 enum intel_dmc_id dmc_id; 940 u32 readcount = 0; 941 u32 r, offset; 942 943 if (!fw) 944 return -EINVAL; 945 946 /* Extract CSS Header information */ 947 css_header = (struct intel_css_header *)fw->data; 948 r = parse_dmc_fw_css(dmc, css_header, fw->size); 949 if (!r) 950 return -EINVAL; 951 952 readcount += r; 953 954 /* Extract Package Header information */ 955 package_header = (struct intel_package_header *)&fw->data[readcount]; 956 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 957 if (!r) 958 return -EINVAL; 959 960 readcount += r; 961 962 for_each_dmc_id(dmc_id) { 963 if (!dmc->dmc_info[dmc_id].present) 964 continue; 965 966 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 967 if (offset > fw->size) { 968 drm_err(&i915->drm, "Reading beyond the fw_size\n"); 969 continue; 970 } 971 972 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 973 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 974 } 975 976 if (!intel_dmc_has_payload(i915)) { 977 drm_err(&i915->drm, "DMC firmware main program not found\n"); 978 return -ENOENT; 979 } 980 981 return 0; 982 } 983 984 static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915) 985 { 986 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 987 i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 988 } 989 990 static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915) 991 { 992 intel_wakeref_t wakeref __maybe_unused = 993 fetch_and_zero(&i915->display.dmc.wakeref); 994 995 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 996 } 997 998 static const char *dmc_fallback_path(struct drm_i915_private *i915) 999 { 1000 if (IS_ALDERLAKE_P(i915)) 1001 return ADLP_DMC_FALLBACK_PATH; 1002 1003 return NULL; 1004 } 1005 1006 static void dmc_load_work_fn(struct work_struct *work) 1007 { 1008 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1009 struct drm_i915_private *i915 = dmc->i915; 1010 const struct firmware *fw = NULL; 1011 const char *fallback_path; 1012 int err; 1013 1014 err = request_firmware(&fw, dmc->fw_path, i915->drm.dev); 1015 1016 if (err == -ENOENT && !dmc_firmware_param(i915)) { 1017 fallback_path = dmc_fallback_path(i915); 1018 if (fallback_path) { 1019 drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n", 1020 dmc->fw_path, fallback_path); 1021 err = request_firmware(&fw, fallback_path, i915->drm.dev); 1022 if (err == 0) 1023 dmc->fw_path = fallback_path; 1024 } 1025 } 1026 1027 if (err) { 1028 drm_notice(&i915->drm, 1029 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1030 dmc->fw_path, ERR_PTR(err)); 1031 drm_notice(&i915->drm, "DMC firmware homepage: %s", 1032 INTEL_DMC_FIRMWARE_URL); 1033 return; 1034 } 1035 1036 err = parse_dmc_fw(dmc, fw); 1037 if (err) { 1038 drm_notice(&i915->drm, 1039 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1040 dmc->fw_path, ERR_PTR(err)); 1041 goto out; 1042 } 1043 1044 intel_dmc_load_program(i915); 1045 intel_dmc_runtime_pm_put(i915); 1046 1047 drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1048 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1049 DMC_VERSION_MINOR(dmc->version)); 1050 1051 out: 1052 release_firmware(fw); 1053 } 1054 1055 /** 1056 * intel_dmc_init() - initialize the firmware loading. 1057 * @i915: i915 drm device. 1058 * 1059 * This function is called at the time of loading the display driver to read 1060 * firmware from a .bin file and copied into a internal memory. 1061 */ 1062 void intel_dmc_init(struct drm_i915_private *i915) 1063 { 1064 struct intel_dmc *dmc; 1065 1066 if (!HAS_DMC(i915)) 1067 return; 1068 1069 /* 1070 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1071 * runtime-suspend. 1072 * 1073 * On error, we return with the rpm wakeref held to prevent runtime 1074 * suspend as runtime suspend *requires* a working DMC for whatever 1075 * reason. 1076 */ 1077 intel_dmc_runtime_pm_get(i915); 1078 1079 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 1080 if (!dmc) 1081 return; 1082 1083 dmc->i915 = i915; 1084 1085 INIT_WORK(&dmc->work, dmc_load_work_fn); 1086 1087 dmc->fw_path = dmc_firmware_default(i915, &dmc->max_fw_size); 1088 1089 if (dmc_firmware_param_disabled(i915)) { 1090 drm_info(&i915->drm, "Disabling DMC firmware and runtime PM\n"); 1091 goto out; 1092 } 1093 1094 if (dmc_firmware_param(i915)) 1095 dmc->fw_path = dmc_firmware_param(i915); 1096 1097 if (!dmc->fw_path) { 1098 drm_dbg_kms(&i915->drm, 1099 "No known DMC firmware for platform, disabling runtime PM\n"); 1100 goto out; 1101 } 1102 1103 i915->display.dmc.dmc = dmc; 1104 1105 drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path); 1106 queue_work(i915->unordered_wq, &dmc->work); 1107 1108 return; 1109 1110 out: 1111 kfree(dmc); 1112 } 1113 1114 /** 1115 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1116 * @i915: i915 drm device 1117 * 1118 * Prepare the DMC firmware before entering system suspend. This includes 1119 * flushing pending work items and releasing any resources acquired during 1120 * init. 1121 */ 1122 void intel_dmc_suspend(struct drm_i915_private *i915) 1123 { 1124 struct intel_dmc *dmc = i915_to_dmc(i915); 1125 1126 if (!HAS_DMC(i915)) 1127 return; 1128 1129 if (dmc) 1130 flush_work(&dmc->work); 1131 1132 intel_dmc_wl_disable(&i915->display); 1133 1134 /* Drop the reference held in case DMC isn't loaded. */ 1135 if (!intel_dmc_has_payload(i915)) 1136 intel_dmc_runtime_pm_put(i915); 1137 } 1138 1139 /** 1140 * intel_dmc_resume() - init DMC firmware during system resume 1141 * @i915: i915 drm device 1142 * 1143 * Reinitialize the DMC firmware during system resume, reacquiring any 1144 * resources released in intel_dmc_suspend(). 1145 */ 1146 void intel_dmc_resume(struct drm_i915_private *i915) 1147 { 1148 if (!HAS_DMC(i915)) 1149 return; 1150 1151 /* 1152 * Reacquire the reference to keep RPM disabled in case DMC isn't 1153 * loaded. 1154 */ 1155 if (!intel_dmc_has_payload(i915)) 1156 intel_dmc_runtime_pm_get(i915); 1157 } 1158 1159 /** 1160 * intel_dmc_fini() - unload the DMC firmware. 1161 * @i915: i915 drm device. 1162 * 1163 * Firmmware unloading includes freeing the internal memory and reset the 1164 * firmware loading status. 1165 */ 1166 void intel_dmc_fini(struct drm_i915_private *i915) 1167 { 1168 struct intel_dmc *dmc = i915_to_dmc(i915); 1169 enum intel_dmc_id dmc_id; 1170 1171 if (!HAS_DMC(i915)) 1172 return; 1173 1174 intel_dmc_suspend(i915); 1175 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 1176 1177 if (dmc) { 1178 for_each_dmc_id(dmc_id) 1179 kfree(dmc->dmc_info[dmc_id].payload); 1180 1181 kfree(dmc); 1182 i915->display.dmc.dmc = NULL; 1183 } 1184 } 1185 1186 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 1187 struct drm_i915_private *i915) 1188 { 1189 struct intel_dmc *dmc = i915_to_dmc(i915); 1190 1191 if (!HAS_DMC(i915)) 1192 return; 1193 1194 i915_error_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1195 i915_error_printf(m, "DMC loaded: %s\n", 1196 str_yes_no(intel_dmc_has_payload(i915))); 1197 if (dmc) 1198 i915_error_printf(m, "DMC fw version: %d.%d\n", 1199 DMC_VERSION_MAJOR(dmc->version), 1200 DMC_VERSION_MINOR(dmc->version)); 1201 } 1202 1203 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1204 { 1205 struct drm_i915_private *i915 = m->private; 1206 struct intel_dmc *dmc = i915_to_dmc(i915); 1207 intel_wakeref_t wakeref; 1208 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1209 1210 if (!HAS_DMC(i915)) 1211 return -ENODEV; 1212 1213 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1214 1215 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1216 seq_printf(m, "fw loaded: %s\n", 1217 str_yes_no(intel_dmc_has_payload(i915))); 1218 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1219 seq_printf(m, "Pipe A fw needed: %s\n", 1220 str_yes_no(DISPLAY_VER(i915) >= 12)); 1221 seq_printf(m, "Pipe A fw loaded: %s\n", 1222 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); 1223 seq_printf(m, "Pipe B fw needed: %s\n", 1224 str_yes_no(IS_ALDERLAKE_P(i915) || 1225 DISPLAY_VER(i915) >= 14)); 1226 seq_printf(m, "Pipe B fw loaded: %s\n", 1227 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); 1228 1229 if (!intel_dmc_has_payload(i915)) 1230 goto out; 1231 1232 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1233 DMC_VERSION_MINOR(dmc->version)); 1234 1235 if (DISPLAY_VER(i915) >= 12) { 1236 i915_reg_t dc3co_reg; 1237 1238 if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { 1239 dc3co_reg = DG1_DMC_DEBUG3; 1240 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1241 } else { 1242 dc3co_reg = TGL_DMC_DEBUG3; 1243 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1244 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1245 } 1246 1247 seq_printf(m, "DC3CO count: %d\n", 1248 intel_de_read(i915, dc3co_reg)); 1249 } else { 1250 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1251 SKL_DMC_DC3_DC5_COUNT; 1252 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1253 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1254 } 1255 1256 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 1257 if (i915_mmio_reg_valid(dc6_reg)) 1258 seq_printf(m, "DC5 -> DC6 count: %d\n", 1259 intel_de_read(i915, dc6_reg)); 1260 1261 seq_printf(m, "program base: 0x%08x\n", 1262 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1263 1264 out: 1265 seq_printf(m, "ssp base: 0x%08x\n", 1266 intel_de_read(i915, DMC_SSP_BASE)); 1267 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 1268 1269 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1270 1271 return 0; 1272 } 1273 1274 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1275 1276 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 1277 { 1278 struct drm_minor *minor = i915->drm.primary; 1279 1280 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1281 i915, &intel_dmc_debugfs_status_fops); 1282 } 1283