1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <[email protected]> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_privacy_screen_consumer.h> 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "icl_dsi.h" 38 #include "intel_audio.h" 39 #include "intel_audio_regs.h" 40 #include "intel_backlight.h" 41 #include "intel_combo_phy.h" 42 #include "intel_combo_phy_regs.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_cx0_phy.h" 46 #include "intel_cx0_phy_regs.h" 47 #include "intel_ddi.h" 48 #include "intel_ddi_buf_trans.h" 49 #include "intel_de.h" 50 #include "intel_display_power.h" 51 #include "intel_display_types.h" 52 #include "intel_dkl_phy.h" 53 #include "intel_dkl_phy_regs.h" 54 #include "intel_dp.h" 55 #include "intel_dp_aux.h" 56 #include "intel_dp_link_training.h" 57 #include "intel_dp_mst.h" 58 #include "intel_dp_test.h" 59 #include "intel_dp_tunnel.h" 60 #include "intel_dpio_phy.h" 61 #include "intel_dsi.h" 62 #include "intel_encoder.h" 63 #include "intel_fdi.h" 64 #include "intel_fifo_underrun.h" 65 #include "intel_gmbus.h" 66 #include "intel_hdcp.h" 67 #include "intel_hdmi.h" 68 #include "intel_hotplug.h" 69 #include "intel_hti.h" 70 #include "intel_lspcon.h" 71 #include "intel_mg_phy_regs.h" 72 #include "intel_modeset_lock.h" 73 #include "intel_pps.h" 74 #include "intel_psr.h" 75 #include "intel_quirks.h" 76 #include "intel_snps_phy.h" 77 #include "intel_tc.h" 78 #include "intel_vdsc.h" 79 #include "intel_vdsc_regs.h" 80 #include "skl_scaler.h" 81 #include "skl_universal_plane.h" 82 83 static const u8 index_to_dp_signal_levels[] = { 84 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 87 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 88 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 91 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 93 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 }; 95 96 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 97 const struct intel_ddi_buf_trans *trans) 98 { 99 int level; 100 101 level = intel_bios_hdmi_level_shift(encoder->devdata); 102 if (level < 0) 103 level = trans->hdmi_default_entry; 104 105 return level; 106 } 107 108 static bool has_buf_trans_select(struct drm_i915_private *i915) 109 { 110 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 111 } 112 113 static bool has_iboost(struct drm_i915_private *i915) 114 { 115 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 116 } 117 118 /* 119 * Starting with Haswell, DDI port buffers must be programmed with correct 120 * values in advance. This function programs the correct values for 121 * DP/eDP/FDI use cases. 122 */ 123 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 124 const struct intel_crtc_state *crtc_state) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 u32 iboost_bit = 0; 128 int i, n_entries; 129 enum port port = encoder->port; 130 const struct intel_ddi_buf_trans *trans; 131 132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 134 return; 135 136 /* If we're boosting the current, set bit 31 of trans1 */ 137 if (has_iboost(dev_priv) && 138 intel_bios_dp_boost_level(encoder->devdata)) 139 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 140 141 for (i = 0; i < n_entries; i++) { 142 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 143 trans->entries[i].hsw.trans1 | iboost_bit); 144 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 145 trans->entries[i].hsw.trans2); 146 } 147 } 148 149 /* 150 * Starting with Haswell, DDI port buffers must be programmed with correct 151 * values in advance. This function programs the correct values for 152 * HDMI/DVI use cases. 153 */ 154 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 155 const struct intel_crtc_state *crtc_state) 156 { 157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 158 int level = intel_ddi_level(encoder, crtc_state, 0); 159 u32 iboost_bit = 0; 160 int n_entries; 161 enum port port = encoder->port; 162 const struct intel_ddi_buf_trans *trans; 163 164 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 165 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 166 return; 167 168 /* If we're boosting the current, set bit 31 of trans1 */ 169 if (has_iboost(dev_priv) && 170 intel_bios_hdmi_boost_level(encoder->devdata)) 171 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 172 173 /* Entry 9 is for HDMI: */ 174 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 175 trans->entries[level].hsw.trans1 | iboost_bit); 176 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 177 trans->entries[level].hsw.trans2); 178 } 179 180 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 181 { 182 struct drm_i915_private *i915 = to_i915(display->drm); 183 184 if (DISPLAY_VER(display) >= 14) 185 return XELPDP_PORT_BUF_CTL1(i915, port); 186 else 187 return DDI_BUF_CTL(port); 188 } 189 190 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 191 enum port port) 192 { 193 struct intel_display *display = &dev_priv->display; 194 195 /* 196 * Bspec's platform specific timeouts: 197 * MTL+ : 100 us 198 * BXT : fixed 16 us 199 * HSW-ADL: 8 us 200 * 201 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 202 */ 203 if (display->platform.broxton) { 204 udelay(16); 205 return; 206 } 207 208 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 209 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 210 DDI_BUF_IS_IDLE, 10)) 211 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 212 port_name(port)); 213 } 214 215 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 216 { 217 struct intel_display *display = to_intel_display(encoder); 218 enum port port = encoder->port; 219 220 /* 221 * Bspec's platform specific timeouts: 222 * MTL+ : 10000 us 223 * DG2 : 1200 us 224 * TGL-ADL combo PHY: 1000 us 225 * TGL-ADL TypeC PHY: 3000 us 226 * HSW-ICL : fixed 518 us 227 */ 228 if (DISPLAY_VER(display) < 10) { 229 usleep_range(518, 1000); 230 return; 231 } 232 233 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 234 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 235 DDI_BUF_IS_IDLE, 10)) 236 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 237 port_name(port)); 238 } 239 240 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 241 { 242 switch (pll->info->id) { 243 case DPLL_ID_WRPLL1: 244 return PORT_CLK_SEL_WRPLL1; 245 case DPLL_ID_WRPLL2: 246 return PORT_CLK_SEL_WRPLL2; 247 case DPLL_ID_SPLL: 248 return PORT_CLK_SEL_SPLL; 249 case DPLL_ID_LCPLL_810: 250 return PORT_CLK_SEL_LCPLL_810; 251 case DPLL_ID_LCPLL_1350: 252 return PORT_CLK_SEL_LCPLL_1350; 253 case DPLL_ID_LCPLL_2700: 254 return PORT_CLK_SEL_LCPLL_2700; 255 default: 256 MISSING_CASE(pll->info->id); 257 return PORT_CLK_SEL_NONE; 258 } 259 } 260 261 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 262 const struct intel_crtc_state *crtc_state) 263 { 264 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 265 int clock = crtc_state->port_clock; 266 const enum intel_dpll_id id = pll->info->id; 267 268 switch (id) { 269 default: 270 /* 271 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 272 * here, so do warn if this get passed in 273 */ 274 MISSING_CASE(id); 275 return DDI_CLK_SEL_NONE; 276 case DPLL_ID_ICL_TBTPLL: 277 switch (clock) { 278 case 162000: 279 return DDI_CLK_SEL_TBT_162; 280 case 270000: 281 return DDI_CLK_SEL_TBT_270; 282 case 540000: 283 return DDI_CLK_SEL_TBT_540; 284 case 810000: 285 return DDI_CLK_SEL_TBT_810; 286 default: 287 MISSING_CASE(clock); 288 return DDI_CLK_SEL_NONE; 289 } 290 case DPLL_ID_ICL_MGPLL1: 291 case DPLL_ID_ICL_MGPLL2: 292 case DPLL_ID_ICL_MGPLL3: 293 case DPLL_ID_ICL_MGPLL4: 294 case DPLL_ID_TGL_MGPLL5: 295 case DPLL_ID_TGL_MGPLL6: 296 return DDI_CLK_SEL_MG; 297 } 298 } 299 300 static u32 ddi_buf_phy_link_rate(int port_clock) 301 { 302 switch (port_clock) { 303 case 162000: 304 return DDI_BUF_PHY_LINK_RATE(0); 305 case 216000: 306 return DDI_BUF_PHY_LINK_RATE(4); 307 case 243000: 308 return DDI_BUF_PHY_LINK_RATE(5); 309 case 270000: 310 return DDI_BUF_PHY_LINK_RATE(1); 311 case 324000: 312 return DDI_BUF_PHY_LINK_RATE(6); 313 case 432000: 314 return DDI_BUF_PHY_LINK_RATE(7); 315 case 540000: 316 return DDI_BUF_PHY_LINK_RATE(2); 317 case 810000: 318 return DDI_BUF_PHY_LINK_RATE(3); 319 default: 320 MISSING_CASE(port_clock); 321 return DDI_BUF_PHY_LINK_RATE(0); 322 } 323 } 324 325 static int dp_phy_lane_stagger_delay(int port_clock) 326 { 327 /* 328 * Return the number of symbol clocks delay used to stagger the 329 * assertion/desassertion of the port lane enables. The target delay 330 * time is 100 ns or greater, return the number of symbols specific to 331 * the provided port_clock (aka link clock) corresponding to this delay 332 * time, i.e. so that 333 * 334 * number_of_symbols * duration_of_one_symbol >= 100 ns 335 * 336 * The delay must be applied only on TypeC DP outputs, for everything else 337 * the delay must be set to 0. 338 * 339 * Return the number of link symbols per 100 ns: 340 * port_clock (10 kHz) -> bits / 100 us 341 * / symbol_size -> symbols / 100 us 342 * / 1000 -> symbols / 100 ns 343 */ 344 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 345 } 346 347 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state) 349 { 350 struct intel_display *display = to_intel_display(encoder); 351 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 352 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 353 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 354 355 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 356 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 357 DDI_BUF_TRANS_SELECT(0); 358 359 if (dig_port->lane_reversal) 360 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 361 if (dig_port->ddi_a_4_lanes) 362 intel_dp->DP |= DDI_A_4_LANES; 363 364 if (DISPLAY_VER(i915) >= 14) { 365 if (intel_dp_is_uhbr(crtc_state)) 366 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 367 else 368 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 369 } 370 371 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 372 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 373 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 374 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 375 } 376 377 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 378 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 379 380 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 381 } 382 } 383 384 static int icl_calc_tbt_pll_link(struct intel_display *display, 385 enum port port) 386 { 387 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 388 389 switch (val) { 390 case DDI_CLK_SEL_NONE: 391 return 0; 392 case DDI_CLK_SEL_TBT_162: 393 return 162000; 394 case DDI_CLK_SEL_TBT_270: 395 return 270000; 396 case DDI_CLK_SEL_TBT_540: 397 return 540000; 398 case DDI_CLK_SEL_TBT_810: 399 return 810000; 400 default: 401 MISSING_CASE(val); 402 return 0; 403 } 404 } 405 406 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 407 { 408 /* CRT dotclock is determined via other means */ 409 if (pipe_config->has_pch_encoder) 410 return; 411 412 pipe_config->hw.adjusted_mode.crtc_clock = 413 intel_crtc_dotclock(pipe_config); 414 } 415 416 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 417 const struct drm_connector_state *conn_state) 418 { 419 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 420 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 421 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 422 u32 temp; 423 424 if (!intel_crtc_has_dp_encoder(crtc_state)) 425 return; 426 427 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 428 429 temp = DP_MSA_MISC_SYNC_CLOCK; 430 431 switch (crtc_state->pipe_bpp) { 432 case 18: 433 temp |= DP_MSA_MISC_6_BPC; 434 break; 435 case 24: 436 temp |= DP_MSA_MISC_8_BPC; 437 break; 438 case 30: 439 temp |= DP_MSA_MISC_10_BPC; 440 break; 441 case 36: 442 temp |= DP_MSA_MISC_12_BPC; 443 break; 444 default: 445 MISSING_CASE(crtc_state->pipe_bpp); 446 break; 447 } 448 449 /* nonsense combination */ 450 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 451 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 452 453 if (crtc_state->limited_color_range) 454 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 455 456 /* 457 * As per DP 1.2 spec section 2.3.4.3 while sending 458 * YCBCR 444 signals we should program MSA MISC1/0 fields with 459 * colorspace information. 460 */ 461 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 462 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 463 464 /* 465 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 466 * of Color Encoding Format and Content Color Gamut] while sending 467 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 468 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 469 */ 470 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 471 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 472 473 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 474 temp); 475 } 476 477 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 478 { 479 if (master_transcoder == TRANSCODER_EDP) 480 return 0; 481 else 482 return master_transcoder + 1; 483 } 484 485 static void 486 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 487 bool enable) 488 { 489 struct intel_display *display = to_intel_display(crtc_state); 490 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 491 u32 val = 0; 492 493 if (!HAS_DP20(display)) 494 return; 495 496 if (enable && intel_dp_is_uhbr(crtc_state)) 497 val = TRANS_DP2_128B132B_CHANNEL_CODING; 498 499 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 500 } 501 502 /* 503 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 504 * 505 * Only intended to be used by intel_ddi_enable_transcoder_func() and 506 * intel_ddi_config_transcoder_func(). 507 */ 508 static u32 509 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 510 const struct intel_crtc_state *crtc_state) 511 { 512 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 513 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 514 enum pipe pipe = crtc->pipe; 515 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 516 enum port port = encoder->port; 517 u32 temp; 518 519 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 520 temp = TRANS_DDI_FUNC_ENABLE; 521 if (DISPLAY_VER(dev_priv) >= 12) 522 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 523 else 524 temp |= TRANS_DDI_SELECT_PORT(port); 525 526 switch (crtc_state->pipe_bpp) { 527 default: 528 MISSING_CASE(crtc_state->pipe_bpp); 529 fallthrough; 530 case 18: 531 temp |= TRANS_DDI_BPC_6; 532 break; 533 case 24: 534 temp |= TRANS_DDI_BPC_8; 535 break; 536 case 30: 537 temp |= TRANS_DDI_BPC_10; 538 break; 539 case 36: 540 temp |= TRANS_DDI_BPC_12; 541 break; 542 } 543 544 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 545 temp |= TRANS_DDI_PVSYNC; 546 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 547 temp |= TRANS_DDI_PHSYNC; 548 549 if (cpu_transcoder == TRANSCODER_EDP) { 550 switch (pipe) { 551 default: 552 MISSING_CASE(pipe); 553 fallthrough; 554 case PIPE_A: 555 /* On Haswell, can only use the always-on power well for 556 * eDP when not using the panel fitter, and when not 557 * using motion blur mitigation (which we don't 558 * support). */ 559 if (crtc_state->pch_pfit.force_thru) 560 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 561 else 562 temp |= TRANS_DDI_EDP_INPUT_A_ON; 563 break; 564 case PIPE_B: 565 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 566 break; 567 case PIPE_C: 568 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 569 break; 570 } 571 } 572 573 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 574 if (crtc_state->has_hdmi_sink) 575 temp |= TRANS_DDI_MODE_SELECT_HDMI; 576 else 577 temp |= TRANS_DDI_MODE_SELECT_DVI; 578 579 if (crtc_state->hdmi_scrambling) 580 temp |= TRANS_DDI_HDMI_SCRAMBLING; 581 if (crtc_state->hdmi_high_tmds_clock_ratio) 582 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 583 if (DISPLAY_VER(dev_priv) >= 14) 584 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 585 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 586 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 587 temp |= (crtc_state->fdi_lanes - 1) << 1; 588 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 589 intel_dp_is_uhbr(crtc_state)) { 590 if (intel_dp_is_uhbr(crtc_state)) 591 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 592 else 593 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 594 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 595 596 if (DISPLAY_VER(dev_priv) >= 12) { 597 enum transcoder master; 598 599 master = crtc_state->mst_master_transcoder; 600 drm_WARN_ON(&dev_priv->drm, 601 master == INVALID_TRANSCODER); 602 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 603 } 604 } else { 605 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 606 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 607 } 608 609 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 610 crtc_state->master_transcoder != INVALID_TRANSCODER) { 611 u8 master_select = 612 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 613 614 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 615 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 616 } 617 618 return temp; 619 } 620 621 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 622 const struct intel_crtc_state *crtc_state) 623 { 624 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 625 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 626 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 627 628 if (DISPLAY_VER(dev_priv) >= 11) { 629 enum transcoder master_transcoder = crtc_state->master_transcoder; 630 u32 ctl2 = 0; 631 632 if (master_transcoder != INVALID_TRANSCODER) { 633 u8 master_select = 634 bdw_trans_port_sync_master_select(master_transcoder); 635 636 ctl2 |= PORT_SYNC_MODE_ENABLE | 637 PORT_SYNC_MODE_MASTER_SELECT(master_select); 638 } 639 640 intel_de_write(dev_priv, 641 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 642 ctl2); 643 } 644 645 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 646 intel_ddi_transcoder_func_reg_val_get(encoder, 647 crtc_state)); 648 } 649 650 /* 651 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 652 * bit for the DDI function and enables the DP2 configuration. Called for all 653 * transcoder types. 654 */ 655 void 656 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 657 const struct intel_crtc_state *crtc_state) 658 { 659 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 660 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 661 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 662 u32 ctl; 663 664 intel_ddi_config_transcoder_dp2(crtc_state, true); 665 666 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 667 ctl &= ~TRANS_DDI_FUNC_ENABLE; 668 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 669 ctl); 670 } 671 672 /* 673 * Disable the DDI function and port syncing. 674 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 675 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 676 * transcoders these are done later in intel_ddi_post_disable_dp(). 677 */ 678 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 679 { 680 struct intel_display *display = to_intel_display(crtc_state); 681 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 682 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 683 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 684 u32 ctl; 685 686 if (DISPLAY_VER(dev_priv) >= 11) 687 intel_de_write(dev_priv, 688 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 689 0); 690 691 ctl = intel_de_read(dev_priv, 692 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 693 694 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 695 696 ctl &= ~TRANS_DDI_FUNC_ENABLE; 697 698 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 699 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 700 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 701 702 if (DISPLAY_VER(dev_priv) >= 12) { 703 if (!intel_dp_mst_is_master_trans(crtc_state)) { 704 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 705 TRANS_DDI_MODE_SELECT_MASK); 706 } 707 } else { 708 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 709 } 710 711 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 712 ctl); 713 714 if (intel_dp_mst_is_slave_trans(crtc_state)) 715 intel_ddi_config_transcoder_dp2(crtc_state, false); 716 717 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 718 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 719 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 720 /* Quirk time at 100ms for reliable operation */ 721 msleep(100); 722 } 723 } 724 725 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 726 enum transcoder cpu_transcoder, 727 bool enable, u32 hdcp_mask) 728 { 729 struct intel_display *display = to_intel_display(intel_encoder); 730 struct drm_device *dev = intel_encoder->base.dev; 731 struct drm_i915_private *dev_priv = to_i915(dev); 732 intel_wakeref_t wakeref; 733 int ret = 0; 734 735 wakeref = intel_display_power_get_if_enabled(display, 736 intel_encoder->power_domain); 737 if (drm_WARN_ON(dev, !wakeref)) 738 return -ENXIO; 739 740 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 741 hdcp_mask, enable ? hdcp_mask : 0); 742 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 743 return ret; 744 } 745 746 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 747 { 748 struct intel_display *display = to_intel_display(intel_connector); 749 struct drm_i915_private *dev_priv = to_i915(display->drm); 750 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 751 int type = intel_connector->base.connector_type; 752 enum port port = encoder->port; 753 enum transcoder cpu_transcoder; 754 intel_wakeref_t wakeref; 755 enum pipe pipe = 0; 756 u32 ddi_mode; 757 bool ret; 758 759 wakeref = intel_display_power_get_if_enabled(display, 760 encoder->power_domain); 761 if (!wakeref) 762 return false; 763 764 /* Note: This returns false for DP MST primary encoders. */ 765 if (!encoder->get_hw_state(encoder, &pipe)) { 766 ret = false; 767 goto out; 768 } 769 770 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 771 cpu_transcoder = TRANSCODER_EDP; 772 else 773 cpu_transcoder = (enum transcoder) pipe; 774 775 ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & 776 TRANS_DDI_MODE_SELECT_MASK; 777 778 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 779 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 780 ret = type == DRM_MODE_CONNECTOR_HDMIA; 781 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 782 ret = type == DRM_MODE_CONNECTOR_VGA; 783 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 784 ret = type == DRM_MODE_CONNECTOR_eDP || 785 type == DRM_MODE_CONNECTOR_DisplayPort; 786 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 787 /* 788 * encoder->get_hw_state() should have bailed out on MST. This 789 * must be SST and non-eDP. 790 */ 791 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 792 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 793 /* encoder->get_hw_state() should have bailed out on MST. */ 794 ret = false; 795 } else { 796 ret = false; 797 } 798 799 out: 800 intel_display_power_put(display, encoder->power_domain, wakeref); 801 802 return ret; 803 } 804 805 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 806 u8 *pipe_mask, bool *is_dp_mst) 807 { 808 struct intel_display *display = to_intel_display(encoder); 809 struct drm_i915_private *dev_priv = to_i915(display->drm); 810 enum port port = encoder->port; 811 intel_wakeref_t wakeref; 812 enum pipe p; 813 u32 tmp; 814 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 815 816 *pipe_mask = 0; 817 *is_dp_mst = false; 818 819 wakeref = intel_display_power_get_if_enabled(display, 820 encoder->power_domain); 821 if (!wakeref) 822 return; 823 824 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 825 if (!(tmp & DDI_BUF_CTL_ENABLE)) 826 goto out; 827 828 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 829 tmp = intel_de_read(dev_priv, 830 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 831 832 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 833 default: 834 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 835 fallthrough; 836 case TRANS_DDI_EDP_INPUT_A_ON: 837 case TRANS_DDI_EDP_INPUT_A_ONOFF: 838 *pipe_mask = BIT(PIPE_A); 839 break; 840 case TRANS_DDI_EDP_INPUT_B_ONOFF: 841 *pipe_mask = BIT(PIPE_B); 842 break; 843 case TRANS_DDI_EDP_INPUT_C_ONOFF: 844 *pipe_mask = BIT(PIPE_C); 845 break; 846 } 847 848 goto out; 849 } 850 851 for_each_pipe(dev_priv, p) { 852 enum transcoder cpu_transcoder = (enum transcoder)p; 853 u32 port_mask, ddi_select, ddi_mode; 854 intel_wakeref_t trans_wakeref; 855 856 trans_wakeref = intel_display_power_get_if_enabled(display, 857 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 858 if (!trans_wakeref) 859 continue; 860 861 if (DISPLAY_VER(dev_priv) >= 12) { 862 port_mask = TGL_TRANS_DDI_PORT_MASK; 863 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 864 } else { 865 port_mask = TRANS_DDI_PORT_MASK; 866 ddi_select = TRANS_DDI_SELECT_PORT(port); 867 } 868 869 tmp = intel_de_read(dev_priv, 870 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 871 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 872 trans_wakeref); 873 874 if ((tmp & port_mask) != ddi_select) 875 continue; 876 877 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 878 879 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 880 mst_pipe_mask |= BIT(p); 881 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 882 dp128b132b_pipe_mask |= BIT(p); 883 884 *pipe_mask |= BIT(p); 885 } 886 887 if (!*pipe_mask) 888 drm_dbg_kms(&dev_priv->drm, 889 "No pipe for [ENCODER:%d:%s] found\n", 890 encoder->base.base.id, encoder->base.name); 891 892 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 893 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 894 895 /* 896 * If we don't have 8b/10b MST, but have more than one 897 * transcoder in 128b/132b mode, we know it must be 128b/132b 898 * MST. 899 * 900 * Otherwise, we fall back to checking the current MST 901 * state. It's not accurate for hardware takeover at probe, but 902 * we don't expect MST to have been enabled at that point, and 903 * can assume it's SST. 904 */ 905 if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst) 906 mst_pipe_mask = dp128b132b_pipe_mask; 907 } 908 909 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 910 drm_dbg_kms(&dev_priv->drm, 911 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 912 encoder->base.base.id, encoder->base.name, 913 *pipe_mask); 914 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 915 } 916 917 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 918 drm_dbg_kms(&dev_priv->drm, 919 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 920 encoder->base.base.id, encoder->base.name, 921 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 922 else 923 *is_dp_mst = mst_pipe_mask; 924 925 out: 926 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 927 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 928 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 929 BXT_PHY_LANE_POWERDOWN_ACK | 930 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 931 drm_err(&dev_priv->drm, 932 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 933 encoder->base.base.id, encoder->base.name, tmp); 934 } 935 936 intel_display_power_put(display, encoder->power_domain, wakeref); 937 } 938 939 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 940 enum pipe *pipe) 941 { 942 u8 pipe_mask; 943 bool is_mst; 944 945 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 946 947 if (is_mst || !pipe_mask) 948 return false; 949 950 *pipe = ffs(pipe_mask) - 1; 951 952 return true; 953 } 954 955 static enum intel_display_power_domain 956 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 957 const struct intel_crtc_state *crtc_state) 958 { 959 struct intel_display *display = to_intel_display(dig_port); 960 961 /* 962 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 963 * DC states enabled at the same time, while for driver initiated AUX 964 * transfers we need the same AUX IOs to be powered but with DC states 965 * disabled. Accordingly use the AUX_IO_<port> power domain here which 966 * leaves DC states enabled. 967 * 968 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 969 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 970 * well, so we can acquire a wider AUX_<port> power domain reference 971 * instead of a specific AUX_IO_<port> reference without powering up any 972 * extra wells. 973 */ 974 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 975 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 976 else if (DISPLAY_VER(display) < 14 && 977 (intel_crtc_has_dp_encoder(crtc_state) || 978 intel_encoder_is_tc(&dig_port->base))) 979 return intel_aux_power_domain(dig_port); 980 else 981 return POWER_DOMAIN_INVALID; 982 } 983 984 static void 985 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 986 const struct intel_crtc_state *crtc_state) 987 { 988 struct intel_display *display = to_intel_display(dig_port); 989 enum intel_display_power_domain domain = 990 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 991 992 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 993 994 if (domain == POWER_DOMAIN_INVALID) 995 return; 996 997 dig_port->aux_wakeref = intel_display_power_get(display, domain); 998 } 999 1000 static void 1001 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 1002 const struct intel_crtc_state *crtc_state) 1003 { 1004 struct intel_display *display = to_intel_display(dig_port); 1005 enum intel_display_power_domain domain = 1006 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1007 intel_wakeref_t wf; 1008 1009 wf = fetch_and_zero(&dig_port->aux_wakeref); 1010 if (!wf) 1011 return; 1012 1013 intel_display_power_put(display, domain, wf); 1014 } 1015 1016 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1017 struct intel_crtc_state *crtc_state) 1018 { 1019 struct intel_display *display = to_intel_display(encoder); 1020 struct intel_digital_port *dig_port; 1021 1022 /* 1023 * TODO: Add support for MST encoders. Atm, the following should never 1024 * happen since fake-MST encoders don't set their get_power_domains() 1025 * hook. 1026 */ 1027 if (drm_WARN_ON(display->drm, 1028 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1029 return; 1030 1031 dig_port = enc_to_dig_port(encoder); 1032 1033 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1034 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1035 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1036 dig_port->ddi_io_power_domain); 1037 } 1038 1039 main_link_aux_power_domain_get(dig_port, crtc_state); 1040 } 1041 1042 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1043 const struct intel_crtc_state *crtc_state) 1044 { 1045 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1046 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1047 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1048 enum phy phy = intel_encoder_to_phy(encoder); 1049 u32 val; 1050 1051 if (cpu_transcoder == TRANSCODER_EDP) 1052 return; 1053 1054 if (DISPLAY_VER(dev_priv) >= 13) 1055 val = TGL_TRANS_CLK_SEL_PORT(phy); 1056 else if (DISPLAY_VER(dev_priv) >= 12) 1057 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1058 else 1059 val = TRANS_CLK_SEL_PORT(encoder->port); 1060 1061 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1062 } 1063 1064 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1065 { 1066 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1067 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1068 u32 val; 1069 1070 if (cpu_transcoder == TRANSCODER_EDP) 1071 return; 1072 1073 if (DISPLAY_VER(dev_priv) >= 12) 1074 val = TGL_TRANS_CLK_SEL_DISABLED; 1075 else 1076 val = TRANS_CLK_SEL_DISABLED; 1077 1078 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1079 } 1080 1081 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1082 enum port port, u8 iboost) 1083 { 1084 u32 tmp; 1085 1086 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1087 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1088 if (iboost) 1089 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1090 else 1091 tmp |= BALANCE_LEG_DISABLE(port); 1092 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1093 } 1094 1095 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1096 const struct intel_crtc_state *crtc_state, 1097 int level) 1098 { 1099 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1101 u8 iboost; 1102 1103 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1104 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1105 else 1106 iboost = intel_bios_dp_boost_level(encoder->devdata); 1107 1108 if (iboost == 0) { 1109 const struct intel_ddi_buf_trans *trans; 1110 int n_entries; 1111 1112 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1113 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1114 return; 1115 1116 iboost = trans->entries[level].hsw.i_boost; 1117 } 1118 1119 /* Make sure that the requested I_boost is valid */ 1120 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1121 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1122 return; 1123 } 1124 1125 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1126 1127 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1128 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1129 } 1130 1131 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1132 const struct intel_crtc_state *crtc_state) 1133 { 1134 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1135 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1136 int n_entries; 1137 1138 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1139 1140 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1141 n_entries = 1; 1142 if (drm_WARN_ON(&dev_priv->drm, 1143 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1144 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1145 1146 return index_to_dp_signal_levels[n_entries - 1] & 1147 DP_TRAIN_VOLTAGE_SWING_MASK; 1148 } 1149 1150 /* 1151 * We assume that the full set of pre-emphasis values can be 1152 * used on all DDI platforms. Should that change we need to 1153 * rethink this code. 1154 */ 1155 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1156 { 1157 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1158 } 1159 1160 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1161 int lane) 1162 { 1163 if (crtc_state->port_clock > 600000) 1164 return 0; 1165 1166 if (crtc_state->lane_count == 4) 1167 return lane >= 1 ? LOADGEN_SELECT : 0; 1168 else 1169 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1170 } 1171 1172 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1173 const struct intel_crtc_state *crtc_state) 1174 { 1175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1176 const struct intel_ddi_buf_trans *trans; 1177 enum phy phy = intel_encoder_to_phy(encoder); 1178 int n_entries, ln; 1179 u32 val; 1180 1181 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1182 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1183 return; 1184 1185 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1186 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1187 1188 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1189 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1190 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1191 intel_dp->hobl_active ? val : 0); 1192 } 1193 1194 /* Set PORT_TX_DW5 */ 1195 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1196 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1197 TAP2_DISABLE | TAP3_DISABLE); 1198 val |= SCALING_MODE_SEL(0x2); 1199 val |= RTERM_SELECT(0x6); 1200 val |= TAP3_DISABLE; 1201 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1202 1203 /* Program PORT_TX_DW2 */ 1204 for (ln = 0; ln < 4; ln++) { 1205 int level = intel_ddi_level(encoder, crtc_state, ln); 1206 1207 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1208 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1209 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1210 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1211 RCOMP_SCALAR(0x98)); 1212 } 1213 1214 /* Program PORT_TX_DW4 */ 1215 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1216 for (ln = 0; ln < 4; ln++) { 1217 int level = intel_ddi_level(encoder, crtc_state, ln); 1218 1219 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1220 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1221 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1222 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1223 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1224 } 1225 1226 /* Program PORT_TX_DW7 */ 1227 for (ln = 0; ln < 4; ln++) { 1228 int level = intel_ddi_level(encoder, crtc_state, ln); 1229 1230 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1231 N_SCALAR_MASK, 1232 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1233 } 1234 } 1235 1236 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1237 const struct intel_crtc_state *crtc_state) 1238 { 1239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1240 enum phy phy = intel_encoder_to_phy(encoder); 1241 u32 val; 1242 int ln; 1243 1244 /* 1245 * 1. If port type is eDP or DP, 1246 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1247 * else clear to 0b. 1248 */ 1249 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1250 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1251 val &= ~COMMON_KEEPER_EN; 1252 else 1253 val |= COMMON_KEEPER_EN; 1254 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1255 1256 /* 2. Program loadgen select */ 1257 /* 1258 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1259 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1260 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1261 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1262 */ 1263 for (ln = 0; ln < 4; ln++) { 1264 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1265 LOADGEN_SELECT, 1266 icl_combo_phy_loadgen_select(crtc_state, ln)); 1267 } 1268 1269 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1270 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1271 0, SUS_CLOCK_CONFIG); 1272 1273 /* 4. Clear training enable to change swing values */ 1274 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1275 val &= ~TX_TRAINING_EN; 1276 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1277 1278 /* 5. Program swing and de-emphasis */ 1279 icl_ddi_combo_vswing_program(encoder, crtc_state); 1280 1281 /* 6. Set training enable to trigger update */ 1282 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1283 val |= TX_TRAINING_EN; 1284 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1285 } 1286 1287 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1288 const struct intel_crtc_state *crtc_state) 1289 { 1290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1291 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1292 const struct intel_ddi_buf_trans *trans; 1293 int n_entries, ln; 1294 1295 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1296 return; 1297 1298 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1299 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1300 return; 1301 1302 for (ln = 0; ln < 2; ln++) { 1303 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1304 CRI_USE_FS32, 0); 1305 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1306 CRI_USE_FS32, 0); 1307 } 1308 1309 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1310 for (ln = 0; ln < 2; ln++) { 1311 int level; 1312 1313 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1314 1315 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1316 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1317 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1318 1319 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1320 1321 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1322 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1323 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1324 } 1325 1326 /* Program MG_TX_DRVCTRL with values from vswing table */ 1327 for (ln = 0; ln < 2; ln++) { 1328 int level; 1329 1330 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1331 1332 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1333 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1334 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1335 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1336 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1337 CRI_TXDEEMPH_OVERRIDE_EN); 1338 1339 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1340 1341 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1342 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1343 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1344 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1345 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1346 CRI_TXDEEMPH_OVERRIDE_EN); 1347 1348 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1349 } 1350 1351 /* 1352 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1353 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1354 * values from table for which TX1 and TX2 enabled. 1355 */ 1356 for (ln = 0; ln < 2; ln++) { 1357 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1358 CFG_LOW_RATE_LKREN_EN, 1359 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1360 } 1361 1362 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1363 for (ln = 0; ln < 2; ln++) { 1364 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1365 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1366 CFG_AMI_CK_DIV_OVERRIDE_EN, 1367 crtc_state->port_clock > 500000 ? 1368 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1369 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1370 1371 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1372 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1373 CFG_AMI_CK_DIV_OVERRIDE_EN, 1374 crtc_state->port_clock > 500000 ? 1375 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1376 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1377 } 1378 1379 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1380 for (ln = 0; ln < 2; ln++) { 1381 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1382 0, CRI_CALCINIT); 1383 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1384 0, CRI_CALCINIT); 1385 } 1386 } 1387 1388 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1389 const struct intel_crtc_state *crtc_state) 1390 { 1391 struct intel_display *display = to_intel_display(encoder); 1392 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1393 const struct intel_ddi_buf_trans *trans; 1394 int n_entries, ln; 1395 1396 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1397 return; 1398 1399 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1400 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1401 return; 1402 1403 for (ln = 0; ln < 2; ln++) { 1404 int level; 1405 1406 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1407 1408 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1409 1410 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1411 DKL_TX_PRESHOOT_COEFF_MASK | 1412 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1413 DKL_TX_VSWING_CONTROL_MASK, 1414 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1415 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1416 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1417 1418 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1419 1420 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1421 DKL_TX_PRESHOOT_COEFF_MASK | 1422 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1423 DKL_TX_VSWING_CONTROL_MASK, 1424 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1425 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1426 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1427 1428 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1429 DKL_TX_DP20BITMODE, 0); 1430 1431 if (display->platform.alderlake_p) { 1432 u32 val; 1433 1434 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1435 if (ln == 0) { 1436 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1437 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1438 } else { 1439 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1440 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1441 } 1442 } else { 1443 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1444 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1445 } 1446 1447 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1448 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1449 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1450 val); 1451 } 1452 } 1453 } 1454 1455 static int translate_signal_level(struct intel_dp *intel_dp, 1456 u8 signal_levels) 1457 { 1458 struct intel_display *display = to_intel_display(intel_dp); 1459 int i; 1460 1461 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1462 if (index_to_dp_signal_levels[i] == signal_levels) 1463 return i; 1464 } 1465 1466 drm_WARN(display->drm, 1, 1467 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1468 signal_levels); 1469 1470 return 0; 1471 } 1472 1473 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1474 const struct intel_crtc_state *crtc_state, 1475 int lane) 1476 { 1477 u8 train_set = intel_dp->train_set[lane]; 1478 1479 if (intel_dp_is_uhbr(crtc_state)) { 1480 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1481 } else { 1482 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1483 DP_TRAIN_PRE_EMPHASIS_MASK); 1484 1485 return translate_signal_level(intel_dp, signal_levels); 1486 } 1487 } 1488 1489 int intel_ddi_level(struct intel_encoder *encoder, 1490 const struct intel_crtc_state *crtc_state, 1491 int lane) 1492 { 1493 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1494 const struct intel_ddi_buf_trans *trans; 1495 int level, n_entries; 1496 1497 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1498 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1499 return 0; 1500 1501 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1502 level = intel_ddi_hdmi_level(encoder, trans); 1503 else 1504 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1505 lane); 1506 1507 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1508 level = n_entries - 1; 1509 1510 return level; 1511 } 1512 1513 static void 1514 hsw_set_signal_levels(struct intel_encoder *encoder, 1515 const struct intel_crtc_state *crtc_state) 1516 { 1517 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1518 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1519 int level = intel_ddi_level(encoder, crtc_state, 0); 1520 enum port port = encoder->port; 1521 u32 signal_levels; 1522 1523 if (has_iboost(dev_priv)) 1524 skl_ddi_set_iboost(encoder, crtc_state, level); 1525 1526 /* HDMI ignores the rest */ 1527 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1528 return; 1529 1530 signal_levels = DDI_BUF_TRANS_SELECT(level); 1531 1532 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1533 signal_levels); 1534 1535 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1536 intel_dp->DP |= signal_levels; 1537 1538 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1539 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1540 } 1541 1542 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1543 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1544 { 1545 mutex_lock(&i915->display.dpll.lock); 1546 1547 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1548 1549 /* 1550 * "This step and the step before must be 1551 * done with separate register writes." 1552 */ 1553 intel_de_rmw(i915, reg, clk_off, 0); 1554 1555 mutex_unlock(&i915->display.dpll.lock); 1556 } 1557 1558 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1559 u32 clk_off) 1560 { 1561 mutex_lock(&i915->display.dpll.lock); 1562 1563 intel_de_rmw(i915, reg, 0, clk_off); 1564 1565 mutex_unlock(&i915->display.dpll.lock); 1566 } 1567 1568 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1569 u32 clk_off) 1570 { 1571 return !(intel_de_read(i915, reg) & clk_off); 1572 } 1573 1574 static struct intel_shared_dpll * 1575 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1576 u32 clk_sel_mask, u32 clk_sel_shift) 1577 { 1578 enum intel_dpll_id id; 1579 1580 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1581 1582 return intel_get_shared_dpll_by_id(display, id); 1583 } 1584 1585 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1586 const struct intel_crtc_state *crtc_state) 1587 { 1588 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1589 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1590 enum phy phy = intel_encoder_to_phy(encoder); 1591 1592 if (drm_WARN_ON(&i915->drm, !pll)) 1593 return; 1594 1595 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1596 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1597 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1598 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1599 } 1600 1601 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1602 { 1603 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1604 enum phy phy = intel_encoder_to_phy(encoder); 1605 1606 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1607 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1608 } 1609 1610 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1611 { 1612 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1613 enum phy phy = intel_encoder_to_phy(encoder); 1614 1615 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1616 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1617 } 1618 1619 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1620 { 1621 struct intel_display *display = to_intel_display(encoder); 1622 enum phy phy = intel_encoder_to_phy(encoder); 1623 1624 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1625 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1626 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1627 } 1628 1629 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1630 const struct intel_crtc_state *crtc_state) 1631 { 1632 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1633 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1634 enum phy phy = intel_encoder_to_phy(encoder); 1635 1636 if (drm_WARN_ON(&i915->drm, !pll)) 1637 return; 1638 1639 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1640 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1641 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1642 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1643 } 1644 1645 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1646 { 1647 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1648 enum phy phy = intel_encoder_to_phy(encoder); 1649 1650 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1651 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1652 } 1653 1654 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1655 { 1656 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1657 enum phy phy = intel_encoder_to_phy(encoder); 1658 1659 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1660 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1661 } 1662 1663 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1664 { 1665 struct intel_display *display = to_intel_display(encoder); 1666 enum phy phy = intel_encoder_to_phy(encoder); 1667 1668 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1669 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1670 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1671 } 1672 1673 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1674 const struct intel_crtc_state *crtc_state) 1675 { 1676 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1677 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1678 enum phy phy = intel_encoder_to_phy(encoder); 1679 1680 if (drm_WARN_ON(&i915->drm, !pll)) 1681 return; 1682 1683 /* 1684 * If we fail this, something went very wrong: first 2 PLLs should be 1685 * used by first 2 phys and last 2 PLLs by last phys 1686 */ 1687 if (drm_WARN_ON(&i915->drm, 1688 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1689 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1690 return; 1691 1692 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1693 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1694 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1695 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1696 } 1697 1698 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1699 { 1700 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1701 enum phy phy = intel_encoder_to_phy(encoder); 1702 1703 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1704 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1705 } 1706 1707 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1708 { 1709 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1710 enum phy phy = intel_encoder_to_phy(encoder); 1711 1712 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1713 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1714 } 1715 1716 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1717 { 1718 struct intel_display *display = to_intel_display(encoder); 1719 enum phy phy = intel_encoder_to_phy(encoder); 1720 enum intel_dpll_id id; 1721 u32 val; 1722 1723 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1724 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1725 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1726 id = val; 1727 1728 /* 1729 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1730 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1731 * bit for phy C and D. 1732 */ 1733 if (phy >= PHY_C) 1734 id += DPLL_ID_DG1_DPLL2; 1735 1736 return intel_get_shared_dpll_by_id(display, id); 1737 } 1738 1739 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1740 const struct intel_crtc_state *crtc_state) 1741 { 1742 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1743 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1744 enum phy phy = intel_encoder_to_phy(encoder); 1745 1746 if (drm_WARN_ON(&i915->drm, !pll)) 1747 return; 1748 1749 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1750 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1751 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1752 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1753 } 1754 1755 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1756 { 1757 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1758 enum phy phy = intel_encoder_to_phy(encoder); 1759 1760 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1761 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1762 } 1763 1764 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1765 { 1766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1767 enum phy phy = intel_encoder_to_phy(encoder); 1768 1769 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1770 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1771 } 1772 1773 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1774 { 1775 struct intel_display *display = to_intel_display(encoder); 1776 enum phy phy = intel_encoder_to_phy(encoder); 1777 1778 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1779 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1780 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1781 } 1782 1783 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1784 const struct intel_crtc_state *crtc_state) 1785 { 1786 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1787 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1788 enum port port = encoder->port; 1789 1790 if (drm_WARN_ON(&i915->drm, !pll)) 1791 return; 1792 1793 /* 1794 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1795 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1796 */ 1797 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1798 1799 icl_ddi_combo_enable_clock(encoder, crtc_state); 1800 } 1801 1802 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1803 { 1804 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1805 enum port port = encoder->port; 1806 1807 icl_ddi_combo_disable_clock(encoder); 1808 1809 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1810 } 1811 1812 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1813 { 1814 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1815 enum port port = encoder->port; 1816 u32 tmp; 1817 1818 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1819 1820 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1821 return false; 1822 1823 return icl_ddi_combo_is_clock_enabled(encoder); 1824 } 1825 1826 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1827 const struct intel_crtc_state *crtc_state) 1828 { 1829 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1830 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1831 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1832 enum port port = encoder->port; 1833 1834 if (drm_WARN_ON(&i915->drm, !pll)) 1835 return; 1836 1837 intel_de_write(i915, DDI_CLK_SEL(port), 1838 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1839 1840 mutex_lock(&i915->display.dpll.lock); 1841 1842 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1843 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1844 1845 mutex_unlock(&i915->display.dpll.lock); 1846 } 1847 1848 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1849 { 1850 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1851 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1852 enum port port = encoder->port; 1853 1854 mutex_lock(&i915->display.dpll.lock); 1855 1856 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1857 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1858 1859 mutex_unlock(&i915->display.dpll.lock); 1860 1861 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1862 } 1863 1864 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1865 { 1866 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1867 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1868 enum port port = encoder->port; 1869 u32 tmp; 1870 1871 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1872 1873 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1874 return false; 1875 1876 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1877 1878 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1879 } 1880 1881 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1882 { 1883 struct intel_display *display = to_intel_display(encoder); 1884 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1885 enum port port = encoder->port; 1886 enum intel_dpll_id id; 1887 u32 tmp; 1888 1889 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1890 1891 switch (tmp & DDI_CLK_SEL_MASK) { 1892 case DDI_CLK_SEL_TBT_162: 1893 case DDI_CLK_SEL_TBT_270: 1894 case DDI_CLK_SEL_TBT_540: 1895 case DDI_CLK_SEL_TBT_810: 1896 id = DPLL_ID_ICL_TBTPLL; 1897 break; 1898 case DDI_CLK_SEL_MG: 1899 id = icl_tc_port_to_pll_id(tc_port); 1900 break; 1901 default: 1902 MISSING_CASE(tmp); 1903 fallthrough; 1904 case DDI_CLK_SEL_NONE: 1905 return NULL; 1906 } 1907 1908 return intel_get_shared_dpll_by_id(display, id); 1909 } 1910 1911 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1912 { 1913 struct intel_display *display = to_intel_display(encoder->base.dev); 1914 enum intel_dpll_id id; 1915 1916 switch (encoder->port) { 1917 case PORT_A: 1918 id = DPLL_ID_SKL_DPLL0; 1919 break; 1920 case PORT_B: 1921 id = DPLL_ID_SKL_DPLL1; 1922 break; 1923 case PORT_C: 1924 id = DPLL_ID_SKL_DPLL2; 1925 break; 1926 default: 1927 MISSING_CASE(encoder->port); 1928 return NULL; 1929 } 1930 1931 return intel_get_shared_dpll_by_id(display, id); 1932 } 1933 1934 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1935 const struct intel_crtc_state *crtc_state) 1936 { 1937 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1938 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1939 enum port port = encoder->port; 1940 1941 if (drm_WARN_ON(&i915->drm, !pll)) 1942 return; 1943 1944 mutex_lock(&i915->display.dpll.lock); 1945 1946 intel_de_rmw(i915, DPLL_CTRL2, 1947 DPLL_CTRL2_DDI_CLK_OFF(port) | 1948 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1949 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1950 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1951 1952 mutex_unlock(&i915->display.dpll.lock); 1953 } 1954 1955 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1956 { 1957 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1958 enum port port = encoder->port; 1959 1960 mutex_lock(&i915->display.dpll.lock); 1961 1962 intel_de_rmw(i915, DPLL_CTRL2, 1963 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1964 1965 mutex_unlock(&i915->display.dpll.lock); 1966 } 1967 1968 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1969 { 1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1971 enum port port = encoder->port; 1972 1973 /* 1974 * FIXME Not sure if the override affects both 1975 * the PLL selection and the CLK_OFF bit. 1976 */ 1977 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1978 } 1979 1980 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1981 { 1982 struct intel_display *display = to_intel_display(encoder); 1983 enum port port = encoder->port; 1984 enum intel_dpll_id id; 1985 u32 tmp; 1986 1987 tmp = intel_de_read(display, DPLL_CTRL2); 1988 1989 /* 1990 * FIXME Not sure if the override affects both 1991 * the PLL selection and the CLK_OFF bit. 1992 */ 1993 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1994 return NULL; 1995 1996 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1997 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1998 1999 return intel_get_shared_dpll_by_id(display, id); 2000 } 2001 2002 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2003 const struct intel_crtc_state *crtc_state) 2004 { 2005 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2006 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2007 enum port port = encoder->port; 2008 2009 if (drm_WARN_ON(&i915->drm, !pll)) 2010 return; 2011 2012 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2013 } 2014 2015 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2016 { 2017 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2018 enum port port = encoder->port; 2019 2020 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2021 } 2022 2023 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2024 { 2025 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2026 enum port port = encoder->port; 2027 2028 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2029 } 2030 2031 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2032 { 2033 struct intel_display *display = to_intel_display(encoder); 2034 enum port port = encoder->port; 2035 enum intel_dpll_id id; 2036 u32 tmp; 2037 2038 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2039 2040 switch (tmp & PORT_CLK_SEL_MASK) { 2041 case PORT_CLK_SEL_WRPLL1: 2042 id = DPLL_ID_WRPLL1; 2043 break; 2044 case PORT_CLK_SEL_WRPLL2: 2045 id = DPLL_ID_WRPLL2; 2046 break; 2047 case PORT_CLK_SEL_SPLL: 2048 id = DPLL_ID_SPLL; 2049 break; 2050 case PORT_CLK_SEL_LCPLL_810: 2051 id = DPLL_ID_LCPLL_810; 2052 break; 2053 case PORT_CLK_SEL_LCPLL_1350: 2054 id = DPLL_ID_LCPLL_1350; 2055 break; 2056 case PORT_CLK_SEL_LCPLL_2700: 2057 id = DPLL_ID_LCPLL_2700; 2058 break; 2059 default: 2060 MISSING_CASE(tmp); 2061 fallthrough; 2062 case PORT_CLK_SEL_NONE: 2063 return NULL; 2064 } 2065 2066 return intel_get_shared_dpll_by_id(display, id); 2067 } 2068 2069 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2070 const struct intel_crtc_state *crtc_state) 2071 { 2072 if (encoder->enable_clock) 2073 encoder->enable_clock(encoder, crtc_state); 2074 } 2075 2076 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2077 { 2078 if (encoder->disable_clock) 2079 encoder->disable_clock(encoder); 2080 } 2081 2082 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2083 { 2084 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2085 u32 port_mask; 2086 bool ddi_clk_needed; 2087 2088 /* 2089 * In case of DP MST, we sanitize the primary encoder only, not the 2090 * virtual ones. 2091 */ 2092 if (encoder->type == INTEL_OUTPUT_DP_MST) 2093 return; 2094 2095 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2096 u8 pipe_mask; 2097 bool is_mst; 2098 2099 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2100 /* 2101 * In the unlikely case that BIOS enables DP in MST mode, just 2102 * warn since our MST HW readout is incomplete. 2103 */ 2104 if (drm_WARN_ON(&i915->drm, is_mst)) 2105 return; 2106 } 2107 2108 port_mask = BIT(encoder->port); 2109 ddi_clk_needed = encoder->base.crtc; 2110 2111 if (encoder->type == INTEL_OUTPUT_DSI) { 2112 struct intel_encoder *other_encoder; 2113 2114 port_mask = intel_dsi_encoder_ports(encoder); 2115 /* 2116 * Sanity check that we haven't incorrectly registered another 2117 * encoder using any of the ports of this DSI encoder. 2118 */ 2119 for_each_intel_encoder(&i915->drm, other_encoder) { 2120 if (other_encoder == encoder) 2121 continue; 2122 2123 if (drm_WARN_ON(&i915->drm, 2124 port_mask & BIT(other_encoder->port))) 2125 return; 2126 } 2127 /* 2128 * For DSI we keep the ddi clocks gated 2129 * except during enable/disable sequence. 2130 */ 2131 ddi_clk_needed = false; 2132 } 2133 2134 if (ddi_clk_needed || !encoder->is_clock_enabled || 2135 !encoder->is_clock_enabled(encoder)) 2136 return; 2137 2138 drm_dbg_kms(&i915->drm, 2139 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2140 encoder->base.base.id, encoder->base.name); 2141 2142 encoder->disable_clock(encoder); 2143 } 2144 2145 static void 2146 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2147 enum tc_port tc_port, u32 ln0, u32 ln1) 2148 { 2149 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2150 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2151 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2152 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2153 } 2154 2155 static void 2156 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2157 const struct intel_crtc_state *crtc_state) 2158 { 2159 struct intel_display *display = to_intel_display(crtc_state); 2160 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2161 u32 ln0, ln1, pin_assignment; 2162 u8 width; 2163 2164 if (DISPLAY_VER(display) >= 14) 2165 return; 2166 2167 if (!intel_encoder_is_tc(&dig_port->base) || 2168 intel_tc_port_in_tbt_alt_mode(dig_port)) 2169 return; 2170 2171 if (DISPLAY_VER(display) >= 12) { 2172 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2173 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2174 } else { 2175 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2176 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2177 } 2178 2179 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2180 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2181 2182 /* DPPATC */ 2183 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2184 width = crtc_state->lane_count; 2185 2186 switch (pin_assignment) { 2187 case 0x0: 2188 drm_WARN_ON(display->drm, 2189 !intel_tc_port_in_legacy_mode(dig_port)); 2190 if (width == 1) { 2191 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2192 } else { 2193 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2194 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2195 } 2196 break; 2197 case 0x1: 2198 if (width == 4) { 2199 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2200 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2201 } 2202 break; 2203 case 0x2: 2204 if (width == 2) { 2205 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2206 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2207 } 2208 break; 2209 case 0x3: 2210 case 0x5: 2211 if (width == 1) { 2212 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2213 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2214 } else { 2215 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2216 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2217 } 2218 break; 2219 case 0x4: 2220 case 0x6: 2221 if (width == 1) { 2222 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2223 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2224 } else { 2225 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2226 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2227 } 2228 break; 2229 default: 2230 MISSING_CASE(pin_assignment); 2231 } 2232 2233 if (DISPLAY_VER(display) >= 12) { 2234 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2235 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2236 /* WA_14018221282 */ 2237 if (IS_DISPLAY_VER(display, 12, 13)) 2238 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2239 2240 } else { 2241 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2242 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2243 } 2244 } 2245 2246 static enum transcoder 2247 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2248 { 2249 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2250 return crtc_state->mst_master_transcoder; 2251 else 2252 return crtc_state->cpu_transcoder; 2253 } 2254 2255 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2256 const struct intel_crtc_state *crtc_state) 2257 { 2258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2259 2260 if (DISPLAY_VER(dev_priv) >= 12) 2261 return TGL_DP_TP_CTL(dev_priv, 2262 tgl_dp_tp_transcoder(crtc_state)); 2263 else 2264 return DP_TP_CTL(encoder->port); 2265 } 2266 2267 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2268 const struct intel_crtc_state *crtc_state) 2269 { 2270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2271 2272 if (DISPLAY_VER(dev_priv) >= 12) 2273 return TGL_DP_TP_STATUS(dev_priv, 2274 tgl_dp_tp_transcoder(crtc_state)); 2275 else 2276 return DP_TP_STATUS(encoder->port); 2277 } 2278 2279 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2280 const struct intel_crtc_state *crtc_state) 2281 { 2282 struct intel_display *display = to_intel_display(encoder); 2283 2284 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2285 DP_TP_STATUS_ACT_SENT); 2286 } 2287 2288 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2289 const struct intel_crtc_state *crtc_state) 2290 { 2291 struct intel_display *display = to_intel_display(encoder); 2292 2293 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2294 DP_TP_STATUS_ACT_SENT, 1)) 2295 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2296 } 2297 2298 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2299 const struct intel_crtc_state *crtc_state, 2300 bool enable) 2301 { 2302 struct intel_display *display = to_intel_display(intel_dp); 2303 2304 if (!crtc_state->vrr.enable) 2305 return; 2306 2307 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2308 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2309 drm_dbg_kms(display->drm, 2310 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2311 str_enable_disable(enable)); 2312 } 2313 2314 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2315 const struct intel_crtc_state *crtc_state, 2316 bool enable) 2317 { 2318 struct intel_display *display = to_intel_display(intel_dp); 2319 2320 if (!crtc_state->fec_enable) 2321 return; 2322 2323 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2324 enable ? DP_FEC_READY : 0) <= 0) 2325 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2326 str_enabled_disabled(enable)); 2327 2328 if (enable && 2329 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2330 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2331 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2332 } 2333 2334 static int read_fec_detected_status(struct drm_dp_aux *aux) 2335 { 2336 int ret; 2337 u8 status; 2338 2339 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2340 if (ret < 0) 2341 return ret; 2342 2343 return status; 2344 } 2345 2346 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2347 { 2348 struct intel_display *display = to_intel_display(aux->drm_dev); 2349 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2350 int status; 2351 int err; 2352 2353 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2354 status & mask || status < 0, 2355 10000, 200000); 2356 2357 if (err || status < 0) { 2358 drm_dbg_kms(display->drm, 2359 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2360 str_enabled_disabled(enabled), err, status); 2361 return err ? err : status; 2362 } 2363 2364 return 0; 2365 } 2366 2367 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2368 const struct intel_crtc_state *crtc_state, 2369 bool enabled) 2370 { 2371 struct intel_display *display = to_intel_display(encoder); 2372 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2373 int ret; 2374 2375 if (!crtc_state->fec_enable) 2376 return 0; 2377 2378 if (enabled) 2379 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2380 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2381 else 2382 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2383 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2384 2385 if (ret) { 2386 drm_err(display->drm, 2387 "Timeout waiting for FEC live state to get %s\n", 2388 str_enabled_disabled(enabled)); 2389 return ret; 2390 } 2391 /* 2392 * At least the Synoptics MST hub doesn't set the detected flag for 2393 * FEC decoding disabling so skip waiting for that. 2394 */ 2395 if (enabled) { 2396 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2397 if (ret) 2398 return ret; 2399 } 2400 2401 return 0; 2402 } 2403 2404 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2405 const struct intel_crtc_state *crtc_state) 2406 { 2407 struct intel_display *display = to_intel_display(encoder); 2408 int i; 2409 int ret; 2410 2411 if (!crtc_state->fec_enable) 2412 return; 2413 2414 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2415 0, DP_TP_CTL_FEC_ENABLE); 2416 2417 if (DISPLAY_VER(display) < 30) 2418 return; 2419 2420 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2421 if (!ret) 2422 return; 2423 2424 for (i = 0; i < 3; i++) { 2425 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2426 2427 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2428 DP_TP_CTL_FEC_ENABLE, 0); 2429 2430 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2431 if (ret) 2432 continue; 2433 2434 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2435 0, DP_TP_CTL_FEC_ENABLE); 2436 2437 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2438 if (!ret) 2439 return; 2440 } 2441 2442 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2443 } 2444 2445 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2446 const struct intel_crtc_state *crtc_state) 2447 { 2448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2449 2450 if (!crtc_state->fec_enable) 2451 return; 2452 2453 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2454 DP_TP_CTL_FEC_ENABLE, 0); 2455 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2456 } 2457 2458 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2459 const struct intel_crtc_state *crtc_state) 2460 { 2461 struct intel_display *display = to_intel_display(encoder); 2462 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2463 2464 if (intel_encoder_is_combo(encoder)) { 2465 enum phy phy = intel_encoder_to_phy(encoder); 2466 2467 intel_combo_phy_power_up_lanes(display, phy, false, 2468 crtc_state->lane_count, 2469 dig_port->lane_reversal); 2470 } 2471 } 2472 2473 /* 2474 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2475 * platforms. 2476 */ 2477 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2478 { 2479 if (DISPLAY_VER(i915) > 20) 2480 return ~0; 2481 else if (IS_ALDERLAKE_P(i915)) 2482 return BIT(PIPE_A) | BIT(PIPE_B); 2483 else 2484 return BIT(PIPE_A); 2485 } 2486 2487 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2488 struct intel_crtc_state *pipe_config) 2489 { 2490 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2491 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2492 enum pipe pipe = crtc->pipe; 2493 u32 dss1; 2494 2495 if (!HAS_MSO(i915)) 2496 return; 2497 2498 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2499 2500 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2501 if (!pipe_config->splitter.enable) 2502 return; 2503 2504 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2505 pipe_config->splitter.enable = false; 2506 return; 2507 } 2508 2509 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2510 default: 2511 drm_WARN(&i915->drm, true, 2512 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2513 fallthrough; 2514 case SPLITTER_CONFIGURATION_2_SEGMENT: 2515 pipe_config->splitter.link_count = 2; 2516 break; 2517 case SPLITTER_CONFIGURATION_4_SEGMENT: 2518 pipe_config->splitter.link_count = 4; 2519 break; 2520 } 2521 2522 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2523 } 2524 2525 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2526 { 2527 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2528 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2529 enum pipe pipe = crtc->pipe; 2530 u32 dss1 = 0; 2531 2532 if (!HAS_MSO(i915)) 2533 return; 2534 2535 if (crtc_state->splitter.enable) { 2536 dss1 |= SPLITTER_ENABLE; 2537 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2538 if (crtc_state->splitter.link_count == 2) 2539 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2540 else 2541 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2542 } 2543 2544 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2545 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2546 OVERLAP_PIXELS_MASK, dss1); 2547 } 2548 2549 static void 2550 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2551 { 2552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2553 enum port port = encoder->port; 2554 i915_reg_t reg; 2555 u32 set_bits, wait_bits; 2556 2557 if (DISPLAY_VER(dev_priv) < 14) 2558 return; 2559 2560 if (DISPLAY_VER(dev_priv) >= 20) { 2561 reg = DDI_BUF_CTL(port); 2562 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2563 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2564 } else { 2565 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2566 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2567 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2568 } 2569 2570 intel_de_rmw(dev_priv, reg, 0, set_bits); 2571 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2572 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2573 port_name(port)); 2574 } 2575 } 2576 2577 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2578 const struct intel_crtc_state *crtc_state) 2579 { 2580 struct intel_display *display = to_intel_display(encoder); 2581 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2582 enum port port = encoder->port; 2583 u32 val = 0; 2584 2585 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2586 2587 if (intel_dp_is_uhbr(crtc_state)) 2588 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2589 else 2590 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2591 2592 if (dig_port->lane_reversal) 2593 val |= XELPDP_PORT_REVERSAL; 2594 2595 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2596 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2597 val); 2598 } 2599 2600 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2601 { 2602 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2604 u32 val; 2605 2606 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2607 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2608 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2609 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2610 } 2611 2612 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2613 struct intel_encoder *encoder, 2614 const struct intel_crtc_state *crtc_state, 2615 const struct drm_connector_state *conn_state) 2616 { 2617 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2618 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2619 bool transparent_mode; 2620 int ret; 2621 2622 intel_dp_set_link_params(intel_dp, 2623 crtc_state->port_clock, 2624 crtc_state->lane_count); 2625 2626 /* 2627 * We only configure what the register value will be here. Actual 2628 * enabling happens during link training farther down. 2629 */ 2630 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2631 2632 /* 2633 * 1. Enable Power Wells 2634 * 2635 * This was handled at the beginning of intel_atomic_commit_tail(), 2636 * before we called down into this function. 2637 */ 2638 2639 /* 2. PMdemand was already set */ 2640 2641 /* 3. Select Thunderbolt */ 2642 mtl_port_buf_ctl_io_selection(encoder); 2643 2644 /* 4. Enable Panel Power if PPS is required */ 2645 intel_pps_on(intel_dp); 2646 2647 /* 5. Enable the port PLL */ 2648 intel_ddi_enable_clock(encoder, crtc_state); 2649 2650 /* 2651 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2652 * Transcoder. 2653 */ 2654 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2655 2656 /* 2657 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2658 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2659 * Transport Select 2660 */ 2661 intel_ddi_config_transcoder_func(encoder, crtc_state); 2662 2663 /* 2664 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2665 */ 2666 intel_ddi_mso_configure(crtc_state); 2667 2668 if (!is_mst) 2669 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2670 2671 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2672 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2673 2674 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2675 if (!is_mst) 2676 intel_dp_sink_enable_decompression(state, 2677 to_intel_connector(conn_state->connector), 2678 crtc_state); 2679 2680 /* 2681 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2682 * in the FEC_CONFIGURATION register to 1 before initiating link 2683 * training 2684 */ 2685 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2686 2687 intel_dp_check_frl_training(intel_dp); 2688 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2689 2690 /* 2691 * 6. The rest of the below are substeps under the bspec's "Enable and 2692 * Train Display Port" step. Note that steps that are specific to 2693 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2694 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2695 * us when active_mst_links==0, so any steps designated for "single 2696 * stream or multi-stream master transcoder" can just be performed 2697 * unconditionally here. 2698 * 2699 * mtl_ddi_prepare_link_retrain() that is called by 2700 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2701 * 6.i and 6.j 2702 * 2703 * 6.k Follow DisplayPort specification training sequence (see notes for 2704 * failure handling) 2705 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2706 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2707 * (timeout after 800 us) 2708 */ 2709 intel_dp_start_link_train(state, intel_dp, crtc_state); 2710 2711 /* 6.n Set DP_TP_CTL link training to Normal */ 2712 if (!is_trans_port_sync_mode(crtc_state)) 2713 intel_dp_stop_link_train(intel_dp, crtc_state); 2714 2715 /* 6.o Configure and enable FEC if needed */ 2716 intel_ddi_enable_fec(encoder, crtc_state); 2717 2718 /* 7.a 128b/132b SST. */ 2719 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2720 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2721 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2722 if (ret < 0) 2723 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2724 } 2725 2726 if (!is_mst) 2727 intel_dsc_dp_pps_write(encoder, crtc_state); 2728 } 2729 2730 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2731 struct intel_encoder *encoder, 2732 const struct intel_crtc_state *crtc_state, 2733 const struct drm_connector_state *conn_state) 2734 { 2735 struct intel_display *display = to_intel_display(encoder); 2736 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2737 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2738 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2739 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2740 int ret; 2741 2742 intel_dp_set_link_params(intel_dp, 2743 crtc_state->port_clock, 2744 crtc_state->lane_count); 2745 2746 /* 2747 * We only configure what the register value will be here. Actual 2748 * enabling happens during link training farther down. 2749 */ 2750 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2751 2752 /* 2753 * 1. Enable Power Wells 2754 * 2755 * This was handled at the beginning of intel_atomic_commit_tail(), 2756 * before we called down into this function. 2757 */ 2758 2759 /* 2. Enable Panel Power if PPS is required */ 2760 intel_pps_on(intel_dp); 2761 2762 /* 2763 * 3. For non-TBT Type-C ports, set FIA lane count 2764 * (DFLEXDPSP.DPX4TXLATC) 2765 * 2766 * This was done before tgl_ddi_pre_enable_dp by 2767 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2768 */ 2769 2770 /* 2771 * 4. Enable the port PLL. 2772 * 2773 * The PLL enabling itself was already done before this function by 2774 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2775 * configure the PLL to port mapping here. 2776 */ 2777 intel_ddi_enable_clock(encoder, crtc_state); 2778 2779 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2780 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2781 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2782 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2783 dig_port->ddi_io_power_domain); 2784 } 2785 2786 /* 6. Program DP_MODE */ 2787 icl_program_mg_dp_mode(dig_port, crtc_state); 2788 2789 /* 2790 * 7. The rest of the below are substeps under the bspec's "Enable and 2791 * Train Display Port" step. Note that steps that are specific to 2792 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2793 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2794 * us when active_mst_links==0, so any steps designated for "single 2795 * stream or multi-stream master transcoder" can just be performed 2796 * unconditionally here. 2797 */ 2798 2799 /* 2800 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2801 * Transcoder. 2802 */ 2803 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2804 2805 /* 2806 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2807 * Transport Select 2808 */ 2809 intel_ddi_config_transcoder_func(encoder, crtc_state); 2810 2811 /* 2812 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2813 * selected 2814 * 2815 * This will be handled by the intel_dp_start_link_train() farther 2816 * down this function. 2817 */ 2818 2819 /* 7.e Configure voltage swing and related IO settings */ 2820 encoder->set_signal_levels(encoder, crtc_state); 2821 2822 /* 2823 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2824 * the used lanes of the DDI. 2825 */ 2826 intel_ddi_power_up_lanes(encoder, crtc_state); 2827 2828 /* 2829 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2830 */ 2831 intel_ddi_mso_configure(crtc_state); 2832 2833 if (!is_mst) 2834 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2835 2836 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2837 if (!is_mst) 2838 intel_dp_sink_enable_decompression(state, 2839 to_intel_connector(conn_state->connector), 2840 crtc_state); 2841 /* 2842 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2843 * in the FEC_CONFIGURATION register to 1 before initiating link 2844 * training 2845 */ 2846 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2847 2848 intel_dp_check_frl_training(intel_dp); 2849 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2850 2851 /* 2852 * 7.i Follow DisplayPort specification training sequence (see notes for 2853 * failure handling) 2854 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2855 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2856 * (timeout after 800 us) 2857 */ 2858 intel_dp_start_link_train(state, intel_dp, crtc_state); 2859 2860 /* 7.k Set DP_TP_CTL link training to Normal */ 2861 if (!is_trans_port_sync_mode(crtc_state)) 2862 intel_dp_stop_link_train(intel_dp, crtc_state); 2863 2864 /* 7.l Configure and enable FEC if needed */ 2865 intel_ddi_enable_fec(encoder, crtc_state); 2866 2867 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2868 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2869 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2870 if (ret < 0) 2871 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2872 } 2873 2874 if (!is_mst) 2875 intel_dsc_dp_pps_write(encoder, crtc_state); 2876 } 2877 2878 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2879 struct intel_encoder *encoder, 2880 const struct intel_crtc_state *crtc_state, 2881 const struct drm_connector_state *conn_state) 2882 { 2883 struct intel_display *display = to_intel_display(encoder); 2884 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2886 enum port port = encoder->port; 2887 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2888 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2889 2890 if (DISPLAY_VER(dev_priv) < 11) 2891 drm_WARN_ON(&dev_priv->drm, 2892 is_mst && (port == PORT_A || port == PORT_E)); 2893 else 2894 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2895 2896 intel_dp_set_link_params(intel_dp, 2897 crtc_state->port_clock, 2898 crtc_state->lane_count); 2899 2900 /* 2901 * We only configure what the register value will be here. Actual 2902 * enabling happens during link training farther down. 2903 */ 2904 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2905 2906 intel_pps_on(intel_dp); 2907 2908 intel_ddi_enable_clock(encoder, crtc_state); 2909 2910 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2911 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2912 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2913 dig_port->ddi_io_power_domain); 2914 } 2915 2916 icl_program_mg_dp_mode(dig_port, crtc_state); 2917 2918 if (has_buf_trans_select(dev_priv)) 2919 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2920 2921 encoder->set_signal_levels(encoder, crtc_state); 2922 2923 intel_ddi_power_up_lanes(encoder, crtc_state); 2924 2925 if (!is_mst) 2926 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2927 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2928 if (!is_mst) 2929 intel_dp_sink_enable_decompression(state, 2930 to_intel_connector(conn_state->connector), 2931 crtc_state); 2932 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2933 intel_dp_start_link_train(state, intel_dp, crtc_state); 2934 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2935 !is_trans_port_sync_mode(crtc_state)) 2936 intel_dp_stop_link_train(intel_dp, crtc_state); 2937 2938 intel_ddi_enable_fec(encoder, crtc_state); 2939 2940 if (!is_mst) { 2941 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2942 intel_dsc_dp_pps_write(encoder, crtc_state); 2943 } 2944 } 2945 2946 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2947 struct intel_encoder *encoder, 2948 const struct intel_crtc_state *crtc_state, 2949 const struct drm_connector_state *conn_state) 2950 { 2951 struct intel_display *display = to_intel_display(encoder); 2952 2953 if (HAS_DP20(display)) 2954 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2955 crtc_state); 2956 2957 /* Panel replay has to be enabled in sink dpcd before link training. */ 2958 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2959 2960 if (DISPLAY_VER(display) >= 14) 2961 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2962 else if (DISPLAY_VER(display) >= 12) 2963 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2964 else 2965 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2966 2967 /* MST will call a setting of MSA after an allocating of Virtual Channel 2968 * from MST encoder pre_enable callback. 2969 */ 2970 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2971 intel_ddi_set_dp_msa(crtc_state, conn_state); 2972 } 2973 2974 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2975 struct intel_encoder *encoder, 2976 const struct intel_crtc_state *crtc_state, 2977 const struct drm_connector_state *conn_state) 2978 { 2979 struct intel_display *display = to_intel_display(encoder); 2980 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2981 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2983 2984 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2985 intel_ddi_enable_clock(encoder, crtc_state); 2986 2987 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2988 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2989 dig_port->ddi_io_power_domain); 2990 2991 icl_program_mg_dp_mode(dig_port, crtc_state); 2992 2993 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2994 2995 dig_port->set_infoframes(encoder, 2996 crtc_state->has_infoframe, 2997 crtc_state, conn_state); 2998 } 2999 3000 /* 3001 * Note: Also called from the ->pre_enable of the first active MST stream 3002 * encoder on its primary encoder. 3003 * 3004 * When called from DP MST code: 3005 * 3006 * - conn_state will be NULL 3007 * 3008 * - encoder will be the primary encoder (i.e. mst->primary) 3009 * 3010 * - the main connector associated with this port won't be active or linked to a 3011 * crtc 3012 * 3013 * - crtc_state will be the state of the first stream to be activated on this 3014 * port, and it may not be the same stream that will be deactivated last, but 3015 * each stream should have a state that is identical when it comes to the DP 3016 * link parameters. 3017 */ 3018 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3019 struct intel_encoder *encoder, 3020 const struct intel_crtc_state *crtc_state, 3021 const struct drm_connector_state *conn_state) 3022 { 3023 struct intel_display *display = to_intel_display(state); 3024 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3025 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3026 enum pipe pipe = crtc->pipe; 3027 3028 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3029 3030 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3031 3032 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3033 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3034 conn_state); 3035 } else { 3036 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3037 3038 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3039 conn_state); 3040 3041 /* FIXME precompute everything properly */ 3042 /* FIXME how do we turn infoframes off again? */ 3043 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3044 dig_port->set_infoframes(encoder, 3045 crtc_state->has_infoframe, 3046 crtc_state, conn_state); 3047 } 3048 } 3049 3050 static void 3051 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3052 { 3053 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3054 enum port port = encoder->port; 3055 i915_reg_t reg; 3056 u32 clr_bits, wait_bits; 3057 3058 if (DISPLAY_VER(dev_priv) < 14) 3059 return; 3060 3061 if (DISPLAY_VER(dev_priv) >= 20) { 3062 reg = DDI_BUF_CTL(port); 3063 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3064 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3065 } else { 3066 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 3067 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3068 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3069 } 3070 3071 intel_de_rmw(dev_priv, reg, clr_bits, 0); 3072 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 3073 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3074 port_name(port)); 3075 } 3076 3077 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3078 { 3079 struct intel_display *display = to_intel_display(encoder); 3080 enum port port = encoder->port; 3081 3082 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3083 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3084 3085 intel_wait_ddi_buf_active(encoder); 3086 } 3087 3088 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3089 const struct intel_crtc_state *crtc_state) 3090 { 3091 struct intel_display *display = to_intel_display(encoder); 3092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3093 enum port port = encoder->port; 3094 3095 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3096 3097 if (DISPLAY_VER(display) >= 14) 3098 intel_wait_ddi_buf_idle(dev_priv, port); 3099 3100 mtl_ddi_disable_d2d(encoder); 3101 3102 if (intel_crtc_has_dp_encoder(crtc_state)) { 3103 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3104 DP_TP_CTL_ENABLE, 0); 3105 } 3106 3107 intel_ddi_disable_fec(encoder, crtc_state); 3108 3109 if (DISPLAY_VER(display) < 14) 3110 intel_wait_ddi_buf_idle(dev_priv, port); 3111 3112 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3113 } 3114 3115 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3116 struct intel_encoder *encoder, 3117 const struct intel_crtc_state *old_crtc_state, 3118 const struct drm_connector_state *old_conn_state) 3119 { 3120 struct intel_display *display = to_intel_display(encoder); 3121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3122 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3123 struct intel_dp *intel_dp = &dig_port->dp; 3124 intel_wakeref_t wakeref; 3125 bool is_mst = intel_crtc_has_type(old_crtc_state, 3126 INTEL_OUTPUT_DP_MST); 3127 3128 if (!is_mst) 3129 intel_dp_set_infoframes(encoder, false, 3130 old_crtc_state, old_conn_state); 3131 3132 /* 3133 * Power down sink before disabling the port, otherwise we end 3134 * up getting interrupts from the sink on detecting link loss. 3135 */ 3136 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3137 3138 if (DISPLAY_VER(dev_priv) >= 12) { 3139 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3140 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3141 3142 intel_de_rmw(dev_priv, 3143 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3144 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3145 0); 3146 } 3147 } else { 3148 if (!is_mst) 3149 intel_ddi_disable_transcoder_clock(old_crtc_state); 3150 } 3151 3152 intel_ddi_buf_disable(encoder, old_crtc_state); 3153 3154 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3155 3156 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3157 3158 /* 3159 * From TGL spec: "If single stream or multi-stream master transcoder: 3160 * Configure Transcoder Clock select to direct no clock to the 3161 * transcoder" 3162 */ 3163 if (DISPLAY_VER(dev_priv) >= 12) 3164 intel_ddi_disable_transcoder_clock(old_crtc_state); 3165 3166 intel_pps_vdd_on(intel_dp); 3167 intel_pps_off(intel_dp); 3168 3169 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3170 3171 if (wakeref) 3172 intel_display_power_put(display, 3173 dig_port->ddi_io_power_domain, 3174 wakeref); 3175 3176 intel_ddi_disable_clock(encoder); 3177 3178 /* De-select Thunderbolt */ 3179 if (DISPLAY_VER(dev_priv) >= 14) 3180 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3181 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3182 } 3183 3184 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3185 struct intel_encoder *encoder, 3186 const struct intel_crtc_state *old_crtc_state, 3187 const struct drm_connector_state *old_conn_state) 3188 { 3189 struct intel_display *display = to_intel_display(encoder); 3190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3191 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3192 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3193 intel_wakeref_t wakeref; 3194 3195 dig_port->set_infoframes(encoder, false, 3196 old_crtc_state, old_conn_state); 3197 3198 if (DISPLAY_VER(dev_priv) < 12) 3199 intel_ddi_disable_transcoder_clock(old_crtc_state); 3200 3201 intel_ddi_buf_disable(encoder, old_crtc_state); 3202 3203 if (DISPLAY_VER(dev_priv) >= 12) 3204 intel_ddi_disable_transcoder_clock(old_crtc_state); 3205 3206 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3207 if (wakeref) 3208 intel_display_power_put(display, 3209 dig_port->ddi_io_power_domain, 3210 wakeref); 3211 3212 intel_ddi_disable_clock(encoder); 3213 3214 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3215 } 3216 3217 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3218 struct intel_encoder *encoder, 3219 const struct intel_crtc_state *old_crtc_state, 3220 const struct drm_connector_state *old_conn_state) 3221 { 3222 struct intel_display *display = to_intel_display(encoder); 3223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3224 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3225 struct intel_crtc *pipe_crtc; 3226 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3227 int i; 3228 3229 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3230 const struct intel_crtc_state *old_pipe_crtc_state = 3231 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3232 3233 intel_crtc_vblank_off(old_pipe_crtc_state); 3234 } 3235 3236 intel_disable_transcoder(old_crtc_state); 3237 3238 /* 128b/132b SST */ 3239 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3240 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3241 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3242 3243 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3244 3245 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3246 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3247 3248 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3249 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3250 } 3251 3252 intel_ddi_disable_transcoder_func(old_crtc_state); 3253 3254 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3255 const struct intel_crtc_state *old_pipe_crtc_state = 3256 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3257 3258 intel_dsc_disable(old_pipe_crtc_state); 3259 3260 if (DISPLAY_VER(dev_priv) >= 9) 3261 skl_scaler_disable(old_pipe_crtc_state); 3262 else 3263 ilk_pfit_disable(old_pipe_crtc_state); 3264 } 3265 } 3266 3267 /* 3268 * Note: Also called from the ->post_disable of the last active MST stream 3269 * encoder on its primary encoder. See also the comment for 3270 * intel_ddi_pre_enable(). 3271 */ 3272 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3273 struct intel_encoder *encoder, 3274 const struct intel_crtc_state *old_crtc_state, 3275 const struct drm_connector_state *old_conn_state) 3276 { 3277 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3278 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3279 old_conn_state); 3280 3281 /* 3282 * When called from DP MST code: 3283 * - old_conn_state will be NULL 3284 * - encoder will be the main encoder (ie. mst->primary) 3285 * - the main connector associated with this port 3286 * won't be active or linked to a crtc 3287 * - old_crtc_state will be the state of the last stream to 3288 * be deactivated on this port, and it may not be the same 3289 * stream that was activated last, but each stream 3290 * should have a state that is identical when it comes to 3291 * the DP link parameters 3292 */ 3293 3294 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3295 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3296 old_conn_state); 3297 else 3298 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3299 old_conn_state); 3300 } 3301 3302 /* 3303 * Note: Also called from the ->post_pll_disable of the last active MST stream 3304 * encoder on its primary encoder. See also the comment for 3305 * intel_ddi_pre_enable(). 3306 */ 3307 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3308 struct intel_encoder *encoder, 3309 const struct intel_crtc_state *old_crtc_state, 3310 const struct drm_connector_state *old_conn_state) 3311 { 3312 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3313 3314 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3315 3316 if (intel_encoder_is_tc(encoder)) 3317 intel_tc_port_put_link(dig_port); 3318 } 3319 3320 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3321 struct intel_encoder *encoder, 3322 const struct intel_crtc_state *crtc_state) 3323 { 3324 const struct drm_connector_state *conn_state; 3325 struct drm_connector *conn; 3326 int i; 3327 3328 if (!crtc_state->sync_mode_slaves_mask) 3329 return; 3330 3331 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3332 struct intel_encoder *slave_encoder = 3333 to_intel_encoder(conn_state->best_encoder); 3334 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3335 const struct intel_crtc_state *slave_crtc_state; 3336 3337 if (!slave_crtc) 3338 continue; 3339 3340 slave_crtc_state = 3341 intel_atomic_get_new_crtc_state(state, slave_crtc); 3342 3343 if (slave_crtc_state->master_transcoder != 3344 crtc_state->cpu_transcoder) 3345 continue; 3346 3347 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3348 slave_crtc_state); 3349 } 3350 3351 usleep_range(200, 400); 3352 3353 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3354 crtc_state); 3355 } 3356 3357 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3358 struct intel_encoder *encoder, 3359 const struct intel_crtc_state *crtc_state, 3360 const struct drm_connector_state *conn_state) 3361 { 3362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3363 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3364 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3365 enum port port = encoder->port; 3366 3367 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3368 intel_dp_stop_link_train(intel_dp, crtc_state); 3369 3370 drm_connector_update_privacy_screen(conn_state); 3371 intel_edp_backlight_on(crtc_state, conn_state); 3372 3373 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3374 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3375 3376 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3377 } 3378 3379 static i915_reg_t 3380 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3381 { 3382 static const enum transcoder trans[] = { 3383 [PORT_A] = TRANSCODER_EDP, 3384 [PORT_B] = TRANSCODER_A, 3385 [PORT_C] = TRANSCODER_B, 3386 [PORT_D] = TRANSCODER_C, 3387 [PORT_E] = TRANSCODER_A, 3388 }; 3389 3390 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3391 3392 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3393 port = PORT_A; 3394 3395 return CHICKEN_TRANS(display, trans[port]); 3396 } 3397 3398 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3399 struct intel_encoder *encoder, 3400 const struct intel_crtc_state *crtc_state, 3401 const struct drm_connector_state *conn_state) 3402 { 3403 struct intel_display *display = to_intel_display(encoder); 3404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3405 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3406 struct drm_connector *connector = conn_state->connector; 3407 enum port port = encoder->port; 3408 u32 buf_ctl = 0; 3409 3410 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3411 crtc_state->hdmi_high_tmds_clock_ratio, 3412 crtc_state->hdmi_scrambling)) 3413 drm_dbg_kms(&dev_priv->drm, 3414 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3415 connector->base.id, connector->name); 3416 3417 if (has_buf_trans_select(dev_priv)) 3418 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3419 3420 /* e. Enable D2D Link for C10/C20 Phy */ 3421 mtl_ddi_enable_d2d(encoder); 3422 3423 encoder->set_signal_levels(encoder, crtc_state); 3424 3425 /* Display WA #1143: skl,kbl,cfl */ 3426 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3427 /* 3428 * For some reason these chicken bits have been 3429 * stuffed into a transcoder register, event though 3430 * the bits affect a specific DDI port rather than 3431 * a specific transcoder. 3432 */ 3433 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3434 u32 val; 3435 3436 val = intel_de_read(dev_priv, reg); 3437 3438 if (port == PORT_E) 3439 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3440 DDIE_TRAINING_OVERRIDE_VALUE; 3441 else 3442 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3443 DDI_TRAINING_OVERRIDE_VALUE; 3444 3445 intel_de_write(dev_priv, reg, val); 3446 intel_de_posting_read(dev_priv, reg); 3447 3448 udelay(1); 3449 3450 if (port == PORT_E) 3451 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3452 DDIE_TRAINING_OVERRIDE_VALUE); 3453 else 3454 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3455 DDI_TRAINING_OVERRIDE_VALUE); 3456 3457 intel_de_write(dev_priv, reg, val); 3458 } 3459 3460 intel_ddi_power_up_lanes(encoder, crtc_state); 3461 3462 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3463 * are ignored so nothing special needs to be done besides 3464 * enabling the port. 3465 * 3466 * On ADL_P the PHY link rate and lane count must be programmed but 3467 * these are both 0 for HDMI. 3468 * 3469 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3470 * is filled with lane count, already set in the crtc_state. 3471 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3472 */ 3473 if (dig_port->lane_reversal) 3474 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3475 if (dig_port->ddi_a_4_lanes) 3476 buf_ctl |= DDI_A_4_LANES; 3477 3478 if (DISPLAY_VER(dev_priv) >= 14) { 3479 u32 port_buf = 0; 3480 3481 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3482 3483 if (dig_port->lane_reversal) 3484 port_buf |= XELPDP_PORT_REVERSAL; 3485 3486 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3487 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3488 3489 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3490 3491 if (DISPLAY_VER(dev_priv) >= 20) 3492 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3493 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3494 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3495 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3496 } 3497 3498 intel_ddi_buf_enable(encoder, buf_ctl); 3499 } 3500 3501 static void intel_ddi_enable(struct intel_atomic_state *state, 3502 struct intel_encoder *encoder, 3503 const struct intel_crtc_state *crtc_state, 3504 const struct drm_connector_state *conn_state) 3505 { 3506 struct intel_display *display = to_intel_display(encoder); 3507 struct intel_crtc *pipe_crtc; 3508 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3509 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3510 int i; 3511 3512 /* 128b/132b SST */ 3513 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3514 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3515 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3516 3517 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3518 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3519 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3520 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3521 } 3522 3523 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3524 3525 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3526 intel_audio_sdp_split_update(crtc_state); 3527 3528 /* 128b/132b SST */ 3529 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3530 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3531 3532 intel_ddi_clear_act_sent(encoder, crtc_state); 3533 3534 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3535 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3536 3537 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3538 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3539 } 3540 3541 intel_enable_transcoder(crtc_state); 3542 3543 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3544 3545 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3546 const struct intel_crtc_state *pipe_crtc_state = 3547 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3548 3549 intel_crtc_vblank_on(pipe_crtc_state); 3550 } 3551 3552 if (is_hdmi) 3553 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3554 else 3555 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3556 3557 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3558 3559 } 3560 3561 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3562 struct intel_encoder *encoder, 3563 const struct intel_crtc_state *old_crtc_state, 3564 const struct drm_connector_state *old_conn_state) 3565 { 3566 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3567 struct intel_connector *connector = 3568 to_intel_connector(old_conn_state->connector); 3569 3570 intel_dp->link_trained = false; 3571 3572 intel_psr_disable(intel_dp, old_crtc_state); 3573 intel_edp_backlight_off(old_conn_state); 3574 /* Disable the decompression in DP Sink */ 3575 intel_dp_sink_disable_decompression(state, 3576 connector, old_crtc_state); 3577 /* Disable Ignore_MSA bit in DP Sink */ 3578 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3579 false); 3580 } 3581 3582 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3583 struct intel_encoder *encoder, 3584 const struct intel_crtc_state *old_crtc_state, 3585 const struct drm_connector_state *old_conn_state) 3586 { 3587 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3588 struct drm_connector *connector = old_conn_state->connector; 3589 3590 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3591 false, false)) 3592 drm_dbg_kms(&i915->drm, 3593 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3594 connector->base.id, connector->name); 3595 } 3596 3597 static void intel_ddi_disable(struct intel_atomic_state *state, 3598 struct intel_encoder *encoder, 3599 const struct intel_crtc_state *old_crtc_state, 3600 const struct drm_connector_state *old_conn_state) 3601 { 3602 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3603 3604 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3605 3606 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3607 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3608 old_conn_state); 3609 else 3610 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3611 old_conn_state); 3612 } 3613 3614 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3615 struct intel_encoder *encoder, 3616 const struct intel_crtc_state *crtc_state, 3617 const struct drm_connector_state *conn_state) 3618 { 3619 intel_ddi_set_dp_msa(crtc_state, conn_state); 3620 3621 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3622 3623 intel_backlight_update(state, encoder, crtc_state, conn_state); 3624 drm_connector_update_privacy_screen(conn_state); 3625 } 3626 3627 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3628 const struct intel_crtc_state *crtc_state, 3629 const struct drm_connector_state *conn_state) 3630 { 3631 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3632 } 3633 3634 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3635 struct intel_encoder *encoder, 3636 const struct intel_crtc_state *crtc_state, 3637 const struct drm_connector_state *conn_state) 3638 { 3639 3640 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3641 !intel_encoder_is_mst(encoder)) 3642 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3643 conn_state); 3644 3645 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3646 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3647 conn_state); 3648 3649 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3650 } 3651 3652 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3653 struct intel_encoder *encoder, 3654 struct intel_crtc *crtc) 3655 { 3656 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3657 const struct intel_crtc_state *crtc_state = 3658 intel_atomic_get_new_crtc_state(state, crtc); 3659 struct intel_crtc *pipe_crtc; 3660 3661 /* FIXME: Add MTL pll_mgr */ 3662 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3663 return; 3664 3665 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3666 intel_crtc_joined_pipe_mask(crtc_state)) 3667 intel_update_active_dpll(state, pipe_crtc, encoder); 3668 } 3669 3670 /* 3671 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3672 * encoder on its primary encoder. See also the comment for 3673 * intel_ddi_pre_enable(). 3674 */ 3675 static void 3676 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3677 struct intel_encoder *encoder, 3678 const struct intel_crtc_state *crtc_state, 3679 const struct drm_connector_state *conn_state) 3680 { 3681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3682 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3683 bool is_tc_port = intel_encoder_is_tc(encoder); 3684 3685 if (is_tc_port) { 3686 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3687 3688 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3689 intel_ddi_update_active_dpll(state, encoder, crtc); 3690 } 3691 3692 main_link_aux_power_domain_get(dig_port, crtc_state); 3693 3694 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3695 /* 3696 * Program the lane count for static/dynamic connections on 3697 * Type-C ports. Skip this step for TBT. 3698 */ 3699 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3700 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3701 bxt_dpio_phy_set_lane_optim_mask(encoder, 3702 crtc_state->lane_lat_optim_mask); 3703 } 3704 3705 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3706 { 3707 struct intel_display *display = to_intel_display(encoder); 3708 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3709 int ln; 3710 3711 for (ln = 0; ln < 2; ln++) 3712 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3713 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3714 } 3715 3716 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3717 const struct intel_crtc_state *crtc_state) 3718 { 3719 struct intel_display *display = to_intel_display(crtc_state); 3720 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3721 struct intel_encoder *encoder = &dig_port->base; 3722 u32 dp_tp_ctl; 3723 3724 /* 3725 * TODO: To train with only a different voltage swing entry is not 3726 * necessary disable and enable port 3727 */ 3728 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3729 3730 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3731 3732 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3733 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3734 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3735 intel_dp_is_uhbr(crtc_state)) { 3736 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3737 } else { 3738 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3739 if (crtc_state->enhanced_framing) 3740 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3741 } 3742 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3743 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3744 3745 /* 6.f Enable D2D Link */ 3746 mtl_ddi_enable_d2d(encoder); 3747 3748 /* 6.g Configure voltage swing and related IO settings */ 3749 encoder->set_signal_levels(encoder, crtc_state); 3750 3751 /* 6.h Configure PORT_BUF_CTL1 */ 3752 mtl_port_buf_ctl_program(encoder, crtc_state); 3753 3754 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3755 if (DISPLAY_VER(display) >= 20) 3756 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3757 3758 intel_ddi_buf_enable(encoder, intel_dp->DP); 3759 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3760 } 3761 3762 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3763 const struct intel_crtc_state *crtc_state) 3764 { 3765 struct intel_display *display = to_intel_display(intel_dp); 3766 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3767 struct intel_encoder *encoder = &dig_port->base; 3768 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3769 u32 dp_tp_ctl; 3770 3771 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3772 3773 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3774 3775 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3776 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3777 intel_dp_is_uhbr(crtc_state)) { 3778 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3779 } else { 3780 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3781 if (crtc_state->enhanced_framing) 3782 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3783 } 3784 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3785 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3786 3787 if (IS_ALDERLAKE_P(dev_priv) && 3788 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3789 adlp_tbt_to_dp_alt_switch_wa(encoder); 3790 3791 intel_ddi_buf_enable(encoder, intel_dp->DP); 3792 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3793 } 3794 3795 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3796 const struct intel_crtc_state *crtc_state, 3797 u8 dp_train_pat) 3798 { 3799 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3801 u32 temp; 3802 3803 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3804 3805 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3806 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3807 case DP_TRAINING_PATTERN_DISABLE: 3808 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3809 break; 3810 case DP_TRAINING_PATTERN_1: 3811 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3812 break; 3813 case DP_TRAINING_PATTERN_2: 3814 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3815 break; 3816 case DP_TRAINING_PATTERN_3: 3817 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3818 break; 3819 case DP_TRAINING_PATTERN_4: 3820 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3821 break; 3822 } 3823 3824 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3825 } 3826 3827 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3828 const struct intel_crtc_state *crtc_state) 3829 { 3830 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3831 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3832 enum port port = encoder->port; 3833 3834 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3835 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3836 3837 /* 3838 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3839 * reason we need to set idle transmission mode is to work around a HW 3840 * issue where we enable the pipe while not in idle link-training mode. 3841 * In this case there is requirement to wait for a minimum number of 3842 * idle patterns to be sent. 3843 */ 3844 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3845 return; 3846 3847 if (intel_de_wait_for_set(dev_priv, 3848 dp_tp_status_reg(encoder, crtc_state), 3849 DP_TP_STATUS_IDLE_DONE, 2)) 3850 drm_err(&dev_priv->drm, 3851 "Timed out waiting for DP idle patterns\n"); 3852 } 3853 3854 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3855 enum transcoder cpu_transcoder) 3856 { 3857 struct intel_display *display = &dev_priv->display; 3858 3859 if (cpu_transcoder == TRANSCODER_EDP) 3860 return false; 3861 3862 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3863 return false; 3864 3865 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3866 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3867 } 3868 3869 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3870 { 3871 if (crtc_state->port_clock > 594000) 3872 return 2; 3873 else 3874 return 0; 3875 } 3876 3877 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3878 { 3879 if (crtc_state->port_clock > 594000) 3880 return 3; 3881 else 3882 return 0; 3883 } 3884 3885 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3886 { 3887 if (crtc_state->port_clock > 594000) 3888 return 1; 3889 else 3890 return 0; 3891 } 3892 3893 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3894 { 3895 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3896 3897 if (DISPLAY_VER(dev_priv) >= 14) 3898 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3899 else if (DISPLAY_VER(dev_priv) >= 12) 3900 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3901 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3902 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3903 else if (DISPLAY_VER(dev_priv) >= 11) 3904 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3905 } 3906 3907 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3908 enum transcoder cpu_transcoder) 3909 { 3910 u32 master_select; 3911 3912 if (DISPLAY_VER(dev_priv) >= 11) { 3913 u32 ctl2 = intel_de_read(dev_priv, 3914 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3915 3916 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3917 return INVALID_TRANSCODER; 3918 3919 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3920 } else { 3921 u32 ctl = intel_de_read(dev_priv, 3922 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3923 3924 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3925 return INVALID_TRANSCODER; 3926 3927 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3928 } 3929 3930 if (master_select == 0) 3931 return TRANSCODER_EDP; 3932 else 3933 return master_select - 1; 3934 } 3935 3936 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3937 { 3938 struct intel_display *display = to_intel_display(crtc_state); 3939 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3940 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3941 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3942 enum transcoder cpu_transcoder; 3943 3944 crtc_state->master_transcoder = 3945 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3946 3947 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3948 enum intel_display_power_domain power_domain; 3949 intel_wakeref_t trans_wakeref; 3950 3951 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3952 trans_wakeref = intel_display_power_get_if_enabled(display, 3953 power_domain); 3954 3955 if (!trans_wakeref) 3956 continue; 3957 3958 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3959 crtc_state->cpu_transcoder) 3960 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3961 3962 intel_display_power_put(display, power_domain, trans_wakeref); 3963 } 3964 3965 drm_WARN_ON(&dev_priv->drm, 3966 crtc_state->master_transcoder != INVALID_TRANSCODER && 3967 crtc_state->sync_mode_slaves_mask); 3968 } 3969 3970 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3971 struct intel_crtc_state *crtc_state, 3972 u32 ddi_func_ctl) 3973 { 3974 struct intel_display *display = to_intel_display(encoder); 3975 3976 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3977 if (DISPLAY_VER(display) >= 14) 3978 crtc_state->lane_count = 3979 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3980 else 3981 crtc_state->lane_count = 4; 3982 } 3983 3984 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3985 struct intel_crtc_state *crtc_state, 3986 u32 ddi_func_ctl) 3987 { 3988 crtc_state->has_hdmi_sink = true; 3989 3990 crtc_state->infoframes.enable |= 3991 intel_hdmi_infoframes_enabled(encoder, crtc_state); 3992 3993 if (crtc_state->infoframes.enable) 3994 crtc_state->has_infoframe = true; 3995 3996 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 3997 crtc_state->hdmi_scrambling = true; 3998 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3999 crtc_state->hdmi_high_tmds_clock_ratio = true; 4000 4001 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4002 } 4003 4004 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4005 struct intel_crtc_state *crtc_state, 4006 u32 ddi_func_ctl) 4007 { 4008 struct intel_display *display = to_intel_display(encoder); 4009 4010 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4011 crtc_state->enhanced_framing = 4012 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4013 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4014 } 4015 4016 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4017 struct intel_crtc_state *crtc_state, 4018 u32 ddi_func_ctl) 4019 { 4020 struct intel_display *display = to_intel_display(encoder); 4021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4022 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4023 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4024 4025 if (encoder->type == INTEL_OUTPUT_EDP) 4026 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4027 else 4028 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4029 crtc_state->lane_count = 4030 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4031 4032 if (DISPLAY_VER(display) >= 12 && 4033 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4034 crtc_state->mst_master_transcoder = 4035 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4036 4037 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4038 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4039 4040 crtc_state->enhanced_framing = 4041 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4042 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4043 4044 if (DISPLAY_VER(display) >= 11) 4045 crtc_state->fec_enable = 4046 intel_de_read(display, 4047 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4048 4049 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4050 crtc_state->infoframes.enable |= 4051 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4052 else 4053 crtc_state->infoframes.enable |= 4054 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4055 } 4056 4057 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4058 struct intel_crtc_state *crtc_state, 4059 u32 ddi_func_ctl) 4060 { 4061 struct intel_display *display = to_intel_display(encoder); 4062 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4063 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4064 4065 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4066 crtc_state->lane_count = 4067 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4068 4069 if (DISPLAY_VER(display) >= 12) 4070 crtc_state->mst_master_transcoder = 4071 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4072 4073 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4074 4075 if (DISPLAY_VER(display) >= 11) 4076 crtc_state->fec_enable = 4077 intel_de_read(display, 4078 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4079 4080 crtc_state->infoframes.enable |= 4081 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4082 } 4083 4084 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4085 struct intel_crtc_state *pipe_config) 4086 { 4087 struct intel_display *display = to_intel_display(encoder); 4088 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4089 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4090 u32 ddi_func_ctl, ddi_mode, flags = 0; 4091 4092 ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 4093 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4094 flags |= DRM_MODE_FLAG_PHSYNC; 4095 else 4096 flags |= DRM_MODE_FLAG_NHSYNC; 4097 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4098 flags |= DRM_MODE_FLAG_PVSYNC; 4099 else 4100 flags |= DRM_MODE_FLAG_NVSYNC; 4101 4102 pipe_config->hw.adjusted_mode.flags |= flags; 4103 4104 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4105 case TRANS_DDI_BPC_6: 4106 pipe_config->pipe_bpp = 18; 4107 break; 4108 case TRANS_DDI_BPC_8: 4109 pipe_config->pipe_bpp = 24; 4110 break; 4111 case TRANS_DDI_BPC_10: 4112 pipe_config->pipe_bpp = 30; 4113 break; 4114 case TRANS_DDI_BPC_12: 4115 pipe_config->pipe_bpp = 36; 4116 break; 4117 default: 4118 break; 4119 } 4120 4121 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4122 4123 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4124 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4125 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4126 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4127 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4128 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4129 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4130 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4131 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4132 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4133 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4134 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4135 4136 /* 4137 * If this is true, we know we're being called from mst stream 4138 * encoder's ->get_config(). 4139 */ 4140 if (intel_dp->is_mst) 4141 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4142 else 4143 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4144 } 4145 } 4146 4147 /* 4148 * Note: Also called from the ->get_config of the MST stream encoders on their 4149 * primary encoder, via the platform specific hooks here. See also the comment 4150 * for intel_ddi_pre_enable(). 4151 */ 4152 static void intel_ddi_get_config(struct intel_encoder *encoder, 4153 struct intel_crtc_state *pipe_config) 4154 { 4155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4156 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4157 4158 /* XXX: DSI transcoder paranoia */ 4159 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4160 return; 4161 4162 intel_ddi_read_func_ctl(encoder, pipe_config); 4163 4164 intel_ddi_mso_get_config(encoder, pipe_config); 4165 4166 pipe_config->has_audio = 4167 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4168 4169 if (encoder->type == INTEL_OUTPUT_EDP) 4170 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4171 4172 ddi_dotclock_get(pipe_config); 4173 4174 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4175 pipe_config->lane_lat_optim_mask = 4176 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4177 4178 intel_ddi_compute_min_voltage_level(pipe_config); 4179 4180 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4181 4182 intel_read_infoframe(encoder, pipe_config, 4183 HDMI_INFOFRAME_TYPE_AVI, 4184 &pipe_config->infoframes.avi); 4185 intel_read_infoframe(encoder, pipe_config, 4186 HDMI_INFOFRAME_TYPE_SPD, 4187 &pipe_config->infoframes.spd); 4188 intel_read_infoframe(encoder, pipe_config, 4189 HDMI_INFOFRAME_TYPE_VENDOR, 4190 &pipe_config->infoframes.hdmi); 4191 intel_read_infoframe(encoder, pipe_config, 4192 HDMI_INFOFRAME_TYPE_DRM, 4193 &pipe_config->infoframes.drm); 4194 4195 if (DISPLAY_VER(dev_priv) >= 8) 4196 bdw_get_trans_port_sync_config(pipe_config); 4197 4198 intel_psr_get_config(encoder, pipe_config); 4199 4200 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4201 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4202 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4203 4204 intel_audio_codec_get_config(encoder, pipe_config); 4205 } 4206 4207 void intel_ddi_get_clock(struct intel_encoder *encoder, 4208 struct intel_crtc_state *crtc_state, 4209 struct intel_shared_dpll *pll) 4210 { 4211 struct intel_display *display = to_intel_display(encoder); 4212 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4213 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4214 bool pll_active; 4215 4216 if (drm_WARN_ON(display->drm, !pll)) 4217 return; 4218 4219 port_dpll->pll = pll; 4220 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4221 drm_WARN_ON(display->drm, !pll_active); 4222 4223 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4224 4225 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, 4226 &crtc_state->dpll_hw_state); 4227 } 4228 4229 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4230 struct intel_crtc_state *crtc_state) 4231 { 4232 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4233 4234 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4235 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4236 else 4237 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4238 4239 intel_ddi_get_config(encoder, crtc_state); 4240 } 4241 4242 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4243 struct intel_crtc_state *crtc_state) 4244 { 4245 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4246 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4247 4248 intel_ddi_get_config(encoder, crtc_state); 4249 } 4250 4251 static void adls_ddi_get_config(struct intel_encoder *encoder, 4252 struct intel_crtc_state *crtc_state) 4253 { 4254 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4255 intel_ddi_get_config(encoder, crtc_state); 4256 } 4257 4258 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4259 struct intel_crtc_state *crtc_state) 4260 { 4261 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4262 intel_ddi_get_config(encoder, crtc_state); 4263 } 4264 4265 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4266 struct intel_crtc_state *crtc_state) 4267 { 4268 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4269 intel_ddi_get_config(encoder, crtc_state); 4270 } 4271 4272 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4273 struct intel_crtc_state *crtc_state) 4274 { 4275 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4276 intel_ddi_get_config(encoder, crtc_state); 4277 } 4278 4279 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4280 { 4281 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4282 } 4283 4284 static enum icl_port_dpll_id 4285 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4286 const struct intel_crtc_state *crtc_state) 4287 { 4288 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4289 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4290 4291 if (drm_WARN_ON(&i915->drm, !pll)) 4292 return ICL_PORT_DPLL_DEFAULT; 4293 4294 if (icl_ddi_tc_pll_is_tbt(pll)) 4295 return ICL_PORT_DPLL_DEFAULT; 4296 else 4297 return ICL_PORT_DPLL_MG_PHY; 4298 } 4299 4300 enum icl_port_dpll_id 4301 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4302 const struct intel_crtc_state *crtc_state) 4303 { 4304 if (!encoder->port_pll_type) 4305 return ICL_PORT_DPLL_DEFAULT; 4306 4307 return encoder->port_pll_type(encoder, crtc_state); 4308 } 4309 4310 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4311 struct intel_crtc_state *crtc_state, 4312 struct intel_shared_dpll *pll) 4313 { 4314 struct intel_display *display = to_intel_display(encoder); 4315 enum icl_port_dpll_id port_dpll_id; 4316 struct icl_port_dpll *port_dpll; 4317 bool pll_active; 4318 4319 if (drm_WARN_ON(display->drm, !pll)) 4320 return; 4321 4322 if (icl_ddi_tc_pll_is_tbt(pll)) 4323 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4324 else 4325 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4326 4327 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4328 4329 port_dpll->pll = pll; 4330 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4331 drm_WARN_ON(display->drm, !pll_active); 4332 4333 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4334 4335 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4336 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4337 else 4338 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, 4339 &crtc_state->dpll_hw_state); 4340 } 4341 4342 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4343 struct intel_crtc_state *crtc_state) 4344 { 4345 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4346 intel_ddi_get_config(encoder, crtc_state); 4347 } 4348 4349 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4350 struct intel_crtc_state *crtc_state) 4351 { 4352 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4353 intel_ddi_get_config(encoder, crtc_state); 4354 } 4355 4356 static void skl_ddi_get_config(struct intel_encoder *encoder, 4357 struct intel_crtc_state *crtc_state) 4358 { 4359 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4360 intel_ddi_get_config(encoder, crtc_state); 4361 } 4362 4363 void hsw_ddi_get_config(struct intel_encoder *encoder, 4364 struct intel_crtc_state *crtc_state) 4365 { 4366 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4367 intel_ddi_get_config(encoder, crtc_state); 4368 } 4369 4370 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4371 const struct intel_crtc_state *crtc_state) 4372 { 4373 if (intel_encoder_is_tc(encoder)) 4374 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4375 crtc_state); 4376 4377 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4378 (!crtc_state && intel_encoder_is_dp(encoder))) 4379 intel_dp_sync_state(encoder, crtc_state); 4380 } 4381 4382 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4383 struct intel_crtc_state *crtc_state) 4384 { 4385 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4386 bool fastset = true; 4387 4388 if (intel_encoder_is_tc(encoder)) { 4389 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4390 encoder->base.base.id, encoder->base.name); 4391 crtc_state->uapi.mode_changed = true; 4392 fastset = false; 4393 } 4394 4395 if (intel_crtc_has_dp_encoder(crtc_state) && 4396 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4397 fastset = false; 4398 4399 return fastset; 4400 } 4401 4402 static enum intel_output_type 4403 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4404 struct intel_crtc_state *crtc_state, 4405 struct drm_connector_state *conn_state) 4406 { 4407 switch (conn_state->connector->connector_type) { 4408 case DRM_MODE_CONNECTOR_HDMIA: 4409 return INTEL_OUTPUT_HDMI; 4410 case DRM_MODE_CONNECTOR_eDP: 4411 return INTEL_OUTPUT_EDP; 4412 case DRM_MODE_CONNECTOR_DisplayPort: 4413 return INTEL_OUTPUT_DP; 4414 default: 4415 MISSING_CASE(conn_state->connector->connector_type); 4416 return INTEL_OUTPUT_UNUSED; 4417 } 4418 } 4419 4420 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4421 struct intel_crtc_state *pipe_config, 4422 struct drm_connector_state *conn_state) 4423 { 4424 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4426 enum port port = encoder->port; 4427 int ret; 4428 4429 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4430 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4431 4432 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4433 pipe_config->has_hdmi_sink = 4434 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4435 4436 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4437 } else { 4438 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4439 } 4440 4441 if (ret) 4442 return ret; 4443 4444 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4445 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4446 pipe_config->pch_pfit.force_thru = 4447 pipe_config->pch_pfit.enabled || 4448 pipe_config->crc_enabled; 4449 4450 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4451 pipe_config->lane_lat_optim_mask = 4452 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4453 4454 intel_ddi_compute_min_voltage_level(pipe_config); 4455 4456 return 0; 4457 } 4458 4459 static bool mode_equal(const struct drm_display_mode *mode1, 4460 const struct drm_display_mode *mode2) 4461 { 4462 return drm_mode_match(mode1, mode2, 4463 DRM_MODE_MATCH_TIMINGS | 4464 DRM_MODE_MATCH_FLAGS | 4465 DRM_MODE_MATCH_3D_FLAGS) && 4466 mode1->clock == mode2->clock; /* we want an exact match */ 4467 } 4468 4469 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4470 const struct intel_link_m_n *m_n_2) 4471 { 4472 return m_n_1->tu == m_n_2->tu && 4473 m_n_1->data_m == m_n_2->data_m && 4474 m_n_1->data_n == m_n_2->data_n && 4475 m_n_1->link_m == m_n_2->link_m && 4476 m_n_1->link_n == m_n_2->link_n; 4477 } 4478 4479 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4480 const struct intel_crtc_state *crtc_state2) 4481 { 4482 /* 4483 * FIXME the modeset sequence is currently wrong and 4484 * can't deal with joiner + port sync at the same time. 4485 */ 4486 return crtc_state1->hw.active && crtc_state2->hw.active && 4487 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4488 crtc_state1->output_types == crtc_state2->output_types && 4489 crtc_state1->output_format == crtc_state2->output_format && 4490 crtc_state1->lane_count == crtc_state2->lane_count && 4491 crtc_state1->port_clock == crtc_state2->port_clock && 4492 mode_equal(&crtc_state1->hw.adjusted_mode, 4493 &crtc_state2->hw.adjusted_mode) && 4494 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4495 } 4496 4497 static u8 4498 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4499 int tile_group_id) 4500 { 4501 struct drm_connector *connector; 4502 const struct drm_connector_state *conn_state; 4503 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4504 struct intel_atomic_state *state = 4505 to_intel_atomic_state(ref_crtc_state->uapi.state); 4506 u8 transcoders = 0; 4507 int i; 4508 4509 /* 4510 * We don't enable port sync on BDW due to missing w/as and 4511 * due to not having adjusted the modeset sequence appropriately. 4512 */ 4513 if (DISPLAY_VER(dev_priv) < 9) 4514 return 0; 4515 4516 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4517 return 0; 4518 4519 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4520 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4521 const struct intel_crtc_state *crtc_state; 4522 4523 if (!crtc) 4524 continue; 4525 4526 if (!connector->has_tile || 4527 connector->tile_group->id != 4528 tile_group_id) 4529 continue; 4530 crtc_state = intel_atomic_get_new_crtc_state(state, 4531 crtc); 4532 if (!crtcs_port_sync_compatible(ref_crtc_state, 4533 crtc_state)) 4534 continue; 4535 transcoders |= BIT(crtc_state->cpu_transcoder); 4536 } 4537 4538 return transcoders; 4539 } 4540 4541 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4542 struct intel_crtc_state *crtc_state, 4543 struct drm_connector_state *conn_state) 4544 { 4545 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4546 struct drm_connector *connector = conn_state->connector; 4547 u8 port_sync_transcoders = 0; 4548 4549 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4550 encoder->base.base.id, encoder->base.name, 4551 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4552 4553 if (connector->has_tile) 4554 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4555 connector->tile_group->id); 4556 4557 /* 4558 * EDP Transcoders cannot be ensalved 4559 * make them a master always when present 4560 */ 4561 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4562 crtc_state->master_transcoder = TRANSCODER_EDP; 4563 else 4564 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4565 4566 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4567 crtc_state->master_transcoder = INVALID_TRANSCODER; 4568 crtc_state->sync_mode_slaves_mask = 4569 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4570 } 4571 4572 return 0; 4573 } 4574 4575 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4576 { 4577 struct intel_display *display = to_intel_display(encoder->dev); 4578 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4579 4580 intel_dp_encoder_flush_work(encoder); 4581 if (intel_encoder_is_tc(&dig_port->base)) 4582 intel_tc_port_cleanup(dig_port); 4583 intel_display_power_flush_work(display); 4584 4585 drm_encoder_cleanup(encoder); 4586 kfree(dig_port->hdcp_port_data.streams); 4587 kfree(dig_port); 4588 } 4589 4590 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4591 { 4592 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4593 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4594 4595 intel_dp->reset_link_params = true; 4596 intel_dp_invalidate_source_oui(intel_dp); 4597 4598 intel_pps_encoder_reset(intel_dp); 4599 4600 if (intel_encoder_is_tc(&dig_port->base)) 4601 intel_tc_port_init_mode(dig_port); 4602 } 4603 4604 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4605 { 4606 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4607 4608 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4609 4610 return 0; 4611 } 4612 4613 static const struct drm_encoder_funcs intel_ddi_funcs = { 4614 .reset = intel_ddi_encoder_reset, 4615 .destroy = intel_ddi_encoder_destroy, 4616 .late_register = intel_ddi_encoder_late_register, 4617 }; 4618 4619 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4620 { 4621 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4622 struct intel_connector *connector; 4623 enum port port = dig_port->base.port; 4624 4625 connector = intel_connector_alloc(); 4626 if (!connector) 4627 return -ENOMEM; 4628 4629 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4630 if (DISPLAY_VER(i915) >= 14) 4631 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4632 else 4633 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4634 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4635 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4636 4637 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4638 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4639 4640 if (!intel_dp_init_connector(dig_port, connector)) { 4641 kfree(connector); 4642 return -EINVAL; 4643 } 4644 4645 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4646 struct drm_device *dev = dig_port->base.base.dev; 4647 struct drm_privacy_screen *privacy_screen; 4648 4649 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4650 if (!IS_ERR(privacy_screen)) { 4651 drm_connector_attach_privacy_screen_provider(&connector->base, 4652 privacy_screen); 4653 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4654 drm_warn(dev, "Error getting privacy-screen\n"); 4655 } 4656 } 4657 4658 return 0; 4659 } 4660 4661 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4662 struct drm_modeset_acquire_ctx *ctx) 4663 { 4664 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4665 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4666 struct intel_connector *connector = hdmi->attached_connector; 4667 struct i2c_adapter *ddc = connector->base.ddc; 4668 struct drm_connector_state *conn_state; 4669 struct intel_crtc_state *crtc_state; 4670 struct intel_crtc *crtc; 4671 u8 config; 4672 int ret; 4673 4674 if (connector->base.status != connector_status_connected) 4675 return 0; 4676 4677 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4678 ctx); 4679 if (ret) 4680 return ret; 4681 4682 conn_state = connector->base.state; 4683 4684 crtc = to_intel_crtc(conn_state->crtc); 4685 if (!crtc) 4686 return 0; 4687 4688 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4689 if (ret) 4690 return ret; 4691 4692 crtc_state = to_intel_crtc_state(crtc->base.state); 4693 4694 drm_WARN_ON(&dev_priv->drm, 4695 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4696 4697 if (!crtc_state->hw.active) 4698 return 0; 4699 4700 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4701 !crtc_state->hdmi_scrambling) 4702 return 0; 4703 4704 if (conn_state->commit && 4705 !try_wait_for_completion(&conn_state->commit->hw_done)) 4706 return 0; 4707 4708 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4709 if (ret < 0) { 4710 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4711 connector->base.base.id, connector->base.name, ret); 4712 return 0; 4713 } 4714 4715 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4716 crtc_state->hdmi_high_tmds_clock_ratio && 4717 !!(config & SCDC_SCRAMBLING_ENABLE) == 4718 crtc_state->hdmi_scrambling) 4719 return 0; 4720 4721 /* 4722 * HDMI 2.0 says that one should not send scrambled data 4723 * prior to configuring the sink scrambling, and that 4724 * TMDS clock/data transmission should be suspended when 4725 * changing the TMDS clock rate in the sink. So let's 4726 * just do a full modeset here, even though some sinks 4727 * would be perfectly happy if were to just reconfigure 4728 * the SCDC settings on the fly. 4729 */ 4730 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4731 } 4732 4733 static void intel_ddi_link_check(struct intel_encoder *encoder) 4734 { 4735 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4736 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4737 4738 /* TODO: Move checking the HDMI link state here as well. */ 4739 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4740 4741 intel_dp_link_check(encoder); 4742 } 4743 4744 static enum intel_hotplug_state 4745 intel_ddi_hotplug(struct intel_encoder *encoder, 4746 struct intel_connector *connector) 4747 { 4748 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4749 struct intel_dp *intel_dp = &dig_port->dp; 4750 bool is_tc = intel_encoder_is_tc(encoder); 4751 struct drm_modeset_acquire_ctx ctx; 4752 enum intel_hotplug_state state; 4753 int ret; 4754 4755 if (intel_dp_test_phy(intel_dp)) 4756 return INTEL_HOTPLUG_UNCHANGED; 4757 4758 state = intel_encoder_hotplug(encoder, connector); 4759 4760 if (!intel_tc_port_link_reset(dig_port)) { 4761 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4762 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4763 ret = intel_hdmi_reset_link(encoder, &ctx); 4764 drm_WARN_ON(encoder->base.dev, ret); 4765 } else { 4766 intel_dp_check_link_state(intel_dp); 4767 } 4768 } 4769 4770 /* 4771 * Unpowered type-c dongles can take some time to boot and be 4772 * responsible, so here giving some time to those dongles to power up 4773 * and then retrying the probe. 4774 * 4775 * On many platforms the HDMI live state signal is known to be 4776 * unreliable, so we can't use it to detect if a sink is connected or 4777 * not. Instead we detect if it's connected based on whether we can 4778 * read the EDID or not. That in turn has a problem during disconnect, 4779 * since the HPD interrupt may be raised before the DDC lines get 4780 * disconnected (due to how the required length of DDC vs. HPD 4781 * connector pins are specified) and so we'll still be able to get a 4782 * valid EDID. To solve this schedule another detection cycle if this 4783 * time around we didn't detect any change in the sink's connection 4784 * status. 4785 * 4786 * Type-c connectors which get their HPD signal deasserted then 4787 * reasserted, without unplugging/replugging the sink from the 4788 * connector, introduce a delay until the AUX channel communication 4789 * becomes functional. Retry the detection for 5 seconds on type-c 4790 * connectors to account for this delay. 4791 */ 4792 if (state == INTEL_HOTPLUG_UNCHANGED && 4793 connector->hotplug_retries < (is_tc ? 5 : 1) && 4794 !dig_port->dp.is_mst) 4795 state = INTEL_HOTPLUG_RETRY; 4796 4797 return state; 4798 } 4799 4800 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4801 { 4802 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4803 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4804 4805 return intel_de_read(dev_priv, SDEISR) & bit; 4806 } 4807 4808 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4809 { 4810 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4811 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4812 4813 return intel_de_read(dev_priv, DEISR) & bit; 4814 } 4815 4816 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4817 { 4818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4819 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4820 4821 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4822 } 4823 4824 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4825 { 4826 struct intel_connector *connector; 4827 enum port port = dig_port->base.port; 4828 4829 connector = intel_connector_alloc(); 4830 if (!connector) 4831 return -ENOMEM; 4832 4833 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4834 4835 if (!intel_hdmi_init_connector(dig_port, connector)) { 4836 /* 4837 * HDMI connector init failures may just mean conflicting DDC 4838 * pins or not having enough lanes. Handle them gracefully, but 4839 * don't fail the entire DDI init. 4840 */ 4841 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4842 kfree(connector); 4843 } 4844 4845 return 0; 4846 } 4847 4848 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4849 { 4850 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4851 4852 if (dig_port->base.port != PORT_A) 4853 return false; 4854 4855 if (dig_port->ddi_a_4_lanes) 4856 return false; 4857 4858 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4859 * supported configuration 4860 */ 4861 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4862 return true; 4863 4864 return false; 4865 } 4866 4867 static int 4868 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4869 { 4870 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4871 enum port port = dig_port->base.port; 4872 int max_lanes = 4; 4873 4874 if (DISPLAY_VER(dev_priv) >= 11) 4875 return max_lanes; 4876 4877 if (port == PORT_A || port == PORT_E) { 4878 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4879 max_lanes = port == PORT_A ? 4 : 0; 4880 else 4881 /* Both A and E share 2 lanes */ 4882 max_lanes = 2; 4883 } 4884 4885 /* 4886 * Some BIOS might fail to set this bit on port A if eDP 4887 * wasn't lit up at boot. Force this bit set when needed 4888 * so we use the proper lane count for our calculations. 4889 */ 4890 if (intel_ddi_a_force_4_lanes(dig_port)) { 4891 drm_dbg_kms(&dev_priv->drm, 4892 "Forcing DDI_A_4_LANES for port A\n"); 4893 dig_port->ddi_a_4_lanes = true; 4894 max_lanes = 4; 4895 } 4896 4897 return max_lanes; 4898 } 4899 4900 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4901 enum port port) 4902 { 4903 if (port >= PORT_D_XELPD) 4904 return HPD_PORT_D + port - PORT_D_XELPD; 4905 else if (port >= PORT_TC1) 4906 return HPD_PORT_TC1 + port - PORT_TC1; 4907 else 4908 return HPD_PORT_A + port - PORT_A; 4909 } 4910 4911 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4912 enum port port) 4913 { 4914 if (port >= PORT_TC1) 4915 return HPD_PORT_C + port - PORT_TC1; 4916 else 4917 return HPD_PORT_A + port - PORT_A; 4918 } 4919 4920 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4921 enum port port) 4922 { 4923 if (port >= PORT_TC1) 4924 return HPD_PORT_TC1 + port - PORT_TC1; 4925 else 4926 return HPD_PORT_A + port - PORT_A; 4927 } 4928 4929 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4930 enum port port) 4931 { 4932 if (HAS_PCH_TGP(dev_priv)) 4933 return tgl_hpd_pin(dev_priv, port); 4934 4935 if (port >= PORT_TC1) 4936 return HPD_PORT_C + port - PORT_TC1; 4937 else 4938 return HPD_PORT_A + port - PORT_A; 4939 } 4940 4941 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4942 enum port port) 4943 { 4944 if (port >= PORT_C) 4945 return HPD_PORT_TC1 + port - PORT_C; 4946 else 4947 return HPD_PORT_A + port - PORT_A; 4948 } 4949 4950 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4951 enum port port) 4952 { 4953 if (port == PORT_D) 4954 return HPD_PORT_A; 4955 4956 if (HAS_PCH_TGP(dev_priv)) 4957 return icl_hpd_pin(dev_priv, port); 4958 4959 return HPD_PORT_A + port - PORT_A; 4960 } 4961 4962 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4963 { 4964 if (HAS_PCH_TGP(dev_priv)) 4965 return icl_hpd_pin(dev_priv, port); 4966 4967 return HPD_PORT_A + port - PORT_A; 4968 } 4969 4970 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4971 { 4972 if (DISPLAY_VER(i915) >= 12) 4973 return port >= PORT_TC1; 4974 else if (DISPLAY_VER(i915) >= 11) 4975 return port >= PORT_C; 4976 else 4977 return false; 4978 } 4979 4980 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4981 { 4982 intel_dp_encoder_suspend(encoder); 4983 } 4984 4985 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4986 { 4987 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4988 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4989 4990 /* 4991 * TODO: Move this to intel_dp_encoder_suspend(), 4992 * once modeset locking around that is removed. 4993 */ 4994 intel_encoder_link_check_flush_work(encoder); 4995 intel_tc_port_suspend(dig_port); 4996 } 4997 4998 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4999 { 5000 if (intel_encoder_is_dp(encoder)) 5001 intel_dp_encoder_shutdown(encoder); 5002 if (intel_encoder_is_hdmi(encoder)) 5003 intel_hdmi_encoder_shutdown(encoder); 5004 } 5005 5006 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5007 { 5008 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5009 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5010 5011 intel_tc_port_cleanup(dig_port); 5012 } 5013 5014 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5015 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5016 5017 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 5018 { 5019 /* straps not used on skl+ */ 5020 if (DISPLAY_VER(i915) >= 9) 5021 return true; 5022 5023 switch (port) { 5024 case PORT_A: 5025 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5026 case PORT_B: 5027 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5028 case PORT_C: 5029 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5030 case PORT_D: 5031 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5032 case PORT_E: 5033 return true; /* no strap for DDI-E */ 5034 default: 5035 MISSING_CASE(port); 5036 return false; 5037 } 5038 } 5039 5040 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5041 { 5042 return init_dp || intel_encoder_is_tc(encoder); 5043 } 5044 5045 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 5046 { 5047 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 5048 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 5049 "Platform does not support DSI\n"); 5050 } 5051 5052 static bool port_in_use(struct drm_i915_private *i915, enum port port) 5053 { 5054 struct intel_encoder *encoder; 5055 5056 for_each_intel_encoder(&i915->drm, encoder) { 5057 /* FIXME what about second port for dual link DSI? */ 5058 if (encoder->port == port) 5059 return true; 5060 } 5061 5062 return false; 5063 } 5064 5065 void intel_ddi_init(struct intel_display *display, 5066 const struct intel_bios_encoder_data *devdata) 5067 { 5068 struct drm_i915_private *dev_priv = to_i915(display->drm); 5069 struct intel_digital_port *dig_port; 5070 struct intel_encoder *encoder; 5071 bool init_hdmi, init_dp; 5072 enum port port; 5073 enum phy phy; 5074 u32 ddi_buf_ctl; 5075 5076 port = intel_bios_encoder_port(devdata); 5077 if (port == PORT_NONE) 5078 return; 5079 5080 if (!port_strap_detected(dev_priv, port)) { 5081 drm_dbg_kms(&dev_priv->drm, 5082 "Port %c strap not detected\n", port_name(port)); 5083 return; 5084 } 5085 5086 if (!assert_port_valid(display, port)) 5087 return; 5088 5089 if (port_in_use(dev_priv, port)) { 5090 drm_dbg_kms(&dev_priv->drm, 5091 "Port %c already claimed\n", port_name(port)); 5092 return; 5093 } 5094 5095 if (intel_bios_encoder_supports_dsi(devdata)) { 5096 /* BXT/GLK handled elsewhere, for now at least */ 5097 if (!assert_has_icl_dsi(dev_priv)) 5098 return; 5099 5100 icl_dsi_init(display, devdata); 5101 return; 5102 } 5103 5104 phy = intel_port_to_phy(dev_priv, port); 5105 5106 /* 5107 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5108 * have taken over some of the PHYs and made them unavailable to the 5109 * driver. In that case we should skip initializing the corresponding 5110 * outputs. 5111 */ 5112 if (intel_hti_uses_phy(display, phy)) { 5113 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5114 port_name(port), phy_name(phy)); 5115 return; 5116 } 5117 5118 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5119 intel_bios_encoder_supports_hdmi(devdata); 5120 init_dp = intel_bios_encoder_supports_dp(devdata); 5121 5122 if (intel_bios_encoder_is_lspcon(devdata)) { 5123 /* 5124 * Lspcon device needs to be driven with DP connector 5125 * with special detection sequence. So make sure DP 5126 * is initialized before lspcon. 5127 */ 5128 init_dp = true; 5129 init_hdmi = false; 5130 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5131 port_name(port)); 5132 } 5133 5134 if (!init_dp && !init_hdmi) { 5135 drm_dbg_kms(&dev_priv->drm, 5136 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5137 port_name(port)); 5138 return; 5139 } 5140 5141 if (intel_phy_is_snps(dev_priv, phy) && 5142 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 5143 drm_dbg_kms(&dev_priv->drm, 5144 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5145 phy_name(phy)); 5146 } 5147 5148 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5149 if (!dig_port) 5150 return; 5151 5152 dig_port->aux_ch = AUX_CH_NONE; 5153 5154 encoder = &dig_port->base; 5155 encoder->devdata = devdata; 5156 5157 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 5158 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5159 DRM_MODE_ENCODER_TMDS, 5160 "DDI %c/PHY %c", 5161 port_name(port - PORT_D_XELPD + PORT_D), 5162 phy_name(phy)); 5163 } else if (DISPLAY_VER(dev_priv) >= 12) { 5164 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5165 5166 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5167 DRM_MODE_ENCODER_TMDS, 5168 "DDI %s%c/PHY %s%c", 5169 port >= PORT_TC1 ? "TC" : "", 5170 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5171 tc_port != TC_PORT_NONE ? "TC" : "", 5172 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5173 } else if (DISPLAY_VER(dev_priv) >= 11) { 5174 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 5175 5176 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5177 DRM_MODE_ENCODER_TMDS, 5178 "DDI %c%s/PHY %s%c", 5179 port_name(port), 5180 port >= PORT_C ? " (TC)" : "", 5181 tc_port != TC_PORT_NONE ? "TC" : "", 5182 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5183 } else { 5184 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5185 DRM_MODE_ENCODER_TMDS, 5186 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5187 } 5188 5189 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5190 5191 mutex_init(&dig_port->hdcp_mutex); 5192 dig_port->num_hdcp_streams = 0; 5193 5194 encoder->hotplug = intel_ddi_hotplug; 5195 encoder->compute_output_type = intel_ddi_compute_output_type; 5196 encoder->compute_config = intel_ddi_compute_config; 5197 encoder->compute_config_late = intel_ddi_compute_config_late; 5198 encoder->enable = intel_ddi_enable; 5199 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5200 encoder->pre_enable = intel_ddi_pre_enable; 5201 encoder->disable = intel_ddi_disable; 5202 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5203 encoder->post_disable = intel_ddi_post_disable; 5204 encoder->update_pipe = intel_ddi_update_pipe; 5205 encoder->audio_enable = intel_audio_codec_enable; 5206 encoder->audio_disable = intel_audio_codec_disable; 5207 encoder->get_hw_state = intel_ddi_get_hw_state; 5208 encoder->sync_state = intel_ddi_sync_state; 5209 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5210 encoder->suspend = intel_ddi_encoder_suspend; 5211 encoder->shutdown = intel_ddi_encoder_shutdown; 5212 encoder->get_power_domains = intel_ddi_get_power_domains; 5213 5214 encoder->type = INTEL_OUTPUT_DDI; 5215 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5216 encoder->port = port; 5217 encoder->cloneable = 0; 5218 encoder->pipe_mask = ~0; 5219 5220 if (DISPLAY_VER(dev_priv) >= 14) { 5221 encoder->enable_clock = intel_mtl_pll_enable; 5222 encoder->disable_clock = intel_mtl_pll_disable; 5223 encoder->port_pll_type = intel_mtl_port_pll_type; 5224 encoder->get_config = mtl_ddi_get_config; 5225 } else if (IS_DG2(dev_priv)) { 5226 encoder->enable_clock = intel_mpllb_enable; 5227 encoder->disable_clock = intel_mpllb_disable; 5228 encoder->get_config = dg2_ddi_get_config; 5229 } else if (IS_ALDERLAKE_S(dev_priv)) { 5230 encoder->enable_clock = adls_ddi_enable_clock; 5231 encoder->disable_clock = adls_ddi_disable_clock; 5232 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5233 encoder->get_config = adls_ddi_get_config; 5234 } else if (IS_ROCKETLAKE(dev_priv)) { 5235 encoder->enable_clock = rkl_ddi_enable_clock; 5236 encoder->disable_clock = rkl_ddi_disable_clock; 5237 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5238 encoder->get_config = rkl_ddi_get_config; 5239 } else if (IS_DG1(dev_priv)) { 5240 encoder->enable_clock = dg1_ddi_enable_clock; 5241 encoder->disable_clock = dg1_ddi_disable_clock; 5242 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5243 encoder->get_config = dg1_ddi_get_config; 5244 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5245 if (intel_ddi_is_tc(dev_priv, port)) { 5246 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5247 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5248 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5249 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5250 encoder->get_config = icl_ddi_combo_get_config; 5251 } else { 5252 encoder->enable_clock = icl_ddi_combo_enable_clock; 5253 encoder->disable_clock = icl_ddi_combo_disable_clock; 5254 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5255 encoder->get_config = icl_ddi_combo_get_config; 5256 } 5257 } else if (DISPLAY_VER(dev_priv) >= 11) { 5258 if (intel_ddi_is_tc(dev_priv, port)) { 5259 encoder->enable_clock = icl_ddi_tc_enable_clock; 5260 encoder->disable_clock = icl_ddi_tc_disable_clock; 5261 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5262 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5263 encoder->get_config = icl_ddi_tc_get_config; 5264 } else { 5265 encoder->enable_clock = icl_ddi_combo_enable_clock; 5266 encoder->disable_clock = icl_ddi_combo_disable_clock; 5267 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5268 encoder->get_config = icl_ddi_combo_get_config; 5269 } 5270 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5271 /* BXT/GLK have fixed PLL->port mapping */ 5272 encoder->get_config = bxt_ddi_get_config; 5273 } else if (DISPLAY_VER(dev_priv) == 9) { 5274 encoder->enable_clock = skl_ddi_enable_clock; 5275 encoder->disable_clock = skl_ddi_disable_clock; 5276 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5277 encoder->get_config = skl_ddi_get_config; 5278 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5279 encoder->enable_clock = hsw_ddi_enable_clock; 5280 encoder->disable_clock = hsw_ddi_disable_clock; 5281 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5282 encoder->get_config = hsw_ddi_get_config; 5283 } 5284 5285 if (DISPLAY_VER(dev_priv) >= 14) { 5286 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5287 } else if (IS_DG2(dev_priv)) { 5288 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5289 } else if (DISPLAY_VER(dev_priv) >= 12) { 5290 if (intel_encoder_is_combo(encoder)) 5291 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5292 else 5293 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5294 } else if (DISPLAY_VER(dev_priv) >= 11) { 5295 if (intel_encoder_is_combo(encoder)) 5296 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5297 else 5298 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5299 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5300 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5301 } else { 5302 encoder->set_signal_levels = hsw_set_signal_levels; 5303 } 5304 5305 intel_ddi_buf_trans_init(encoder); 5306 5307 if (DISPLAY_VER(dev_priv) >= 13) 5308 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5309 else if (IS_DG1(dev_priv)) 5310 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5311 else if (IS_ROCKETLAKE(dev_priv)) 5312 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5313 else if (DISPLAY_VER(dev_priv) >= 12) 5314 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5315 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5316 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5317 else if (DISPLAY_VER(dev_priv) == 11) 5318 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5319 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5320 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5321 else 5322 encoder->hpd_pin = intel_hpd_pin_default(port); 5323 5324 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 5325 5326 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5327 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5328 5329 dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5330 5331 dig_port->dp.output_reg = INVALID_MMIO_REG; 5332 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5333 5334 if (need_aux_ch(encoder, init_dp)) { 5335 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5336 if (dig_port->aux_ch == AUX_CH_NONE) 5337 goto err; 5338 } 5339 5340 if (intel_encoder_is_tc(encoder)) { 5341 bool is_legacy = 5342 !intel_bios_encoder_supports_typec_usb(devdata) && 5343 !intel_bios_encoder_supports_tbt(devdata); 5344 5345 if (!is_legacy && init_hdmi) { 5346 is_legacy = !init_dp; 5347 5348 drm_dbg_kms(&dev_priv->drm, 5349 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5350 port_name(port), 5351 str_yes_no(init_dp), 5352 is_legacy ? "legacy" : "non-legacy"); 5353 } 5354 5355 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5356 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5357 5358 dig_port->lock = intel_tc_port_lock; 5359 dig_port->unlock = intel_tc_port_unlock; 5360 5361 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5362 goto err; 5363 } 5364 5365 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5366 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5367 5368 if (DISPLAY_VER(dev_priv) >= 11) { 5369 if (intel_encoder_is_tc(encoder)) 5370 dig_port->connected = intel_tc_port_connected; 5371 else 5372 dig_port->connected = lpt_digital_port_connected; 5373 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5374 dig_port->connected = bdw_digital_port_connected; 5375 } else if (DISPLAY_VER(dev_priv) == 9) { 5376 dig_port->connected = lpt_digital_port_connected; 5377 } else if (IS_BROADWELL(dev_priv)) { 5378 if (port == PORT_A) 5379 dig_port->connected = bdw_digital_port_connected; 5380 else 5381 dig_port->connected = lpt_digital_port_connected; 5382 } else if (IS_HASWELL(dev_priv)) { 5383 if (port == PORT_A) 5384 dig_port->connected = hsw_digital_port_connected; 5385 else 5386 dig_port->connected = lpt_digital_port_connected; 5387 } 5388 5389 intel_infoframe_init(dig_port); 5390 5391 if (init_dp) { 5392 if (intel_ddi_init_dp_connector(dig_port)) 5393 goto err; 5394 5395 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5396 5397 if (dig_port->dp.mso_link_count) 5398 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5399 } 5400 5401 /* 5402 * In theory we don't need the encoder->type check, 5403 * but leave it just in case we have some really bad VBTs... 5404 */ 5405 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5406 if (intel_ddi_init_hdmi_connector(dig_port)) 5407 goto err; 5408 } 5409 5410 return; 5411 5412 err: 5413 drm_encoder_cleanup(&encoder->base); 5414 kfree(dig_port); 5415 } 5416