1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/drm_fixed.h> 30 #include <drm/intel/i915_component.h> 31 32 #include "i915_drv.h" 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_audio_regs.h" 36 #include "intel_cdclk.h" 37 #include "intel_crtc.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_lpe_audio.h" 41 42 /** 43 * DOC: High Definition Audio over HDMI and Display Port 44 * 45 * The graphics and audio drivers together support High Definition Audio over 46 * HDMI and Display Port. The audio programming sequences are divided into audio 47 * codec and controller enable and disable sequences. The graphics driver 48 * handles the audio codec sequences, while the audio driver handles the audio 49 * controller sequences. 50 * 51 * The disable sequences must be performed before disabling the transcoder or 52 * port. The enable sequences may only be performed after enabling the 53 * transcoder and port, and after completed link training. Therefore the audio 54 * enable/disable sequences are part of the modeset sequence. 55 * 56 * The codec and controller sequences could be done either parallel or serial, 57 * but generally the ELDV/PD change in the codec sequence indicates to the audio 58 * driver that the controller sequence should start. Indeed, most of the 59 * co-operation between the graphics and audio drivers is handled via audio 60 * related registers. (The notable exception is the power management, not 61 * covered here.) 62 * 63 * The struct &i915_audio_component is used to interact between the graphics 64 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 65 * defined in graphics driver and called in audio driver. The 66 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 67 */ 68 69 struct intel_audio_funcs { 70 void (*audio_codec_enable)(struct intel_encoder *encoder, 71 const struct intel_crtc_state *crtc_state, 72 const struct drm_connector_state *conn_state); 73 void (*audio_codec_disable)(struct intel_encoder *encoder, 74 const struct intel_crtc_state *old_crtc_state, 75 const struct drm_connector_state *old_conn_state); 76 void (*audio_codec_get_config)(struct intel_encoder *encoder, 77 struct intel_crtc_state *crtc_state); 78 }; 79 80 struct hdmi_aud_ncts { 81 int sample_rate; 82 int clock; 83 int n; 84 int cts; 85 }; 86 87 static const struct { 88 int clock; 89 u32 config; 90 } hdmi_audio_clock[] = { 91 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 92 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 93 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 94 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 95 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 96 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 97 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 98 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 99 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 100 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 101 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 102 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 103 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 104 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 105 }; 106 107 /* HDMI N/CTS table */ 108 #define TMDS_297M 297000 109 #define TMDS_296M 296703 110 #define TMDS_594M 594000 111 #define TMDS_593M 593407 112 113 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 114 { 32000, TMDS_296M, 5824, 421875 }, 115 { 32000, TMDS_297M, 3072, 222750 }, 116 { 32000, TMDS_593M, 5824, 843750 }, 117 { 32000, TMDS_594M, 3072, 445500 }, 118 { 44100, TMDS_296M, 4459, 234375 }, 119 { 44100, TMDS_297M, 4704, 247500 }, 120 { 44100, TMDS_593M, 8918, 937500 }, 121 { 44100, TMDS_594M, 9408, 990000 }, 122 { 88200, TMDS_296M, 8918, 234375 }, 123 { 88200, TMDS_297M, 9408, 247500 }, 124 { 88200, TMDS_593M, 17836, 937500 }, 125 { 88200, TMDS_594M, 18816, 990000 }, 126 { 176400, TMDS_296M, 17836, 234375 }, 127 { 176400, TMDS_297M, 18816, 247500 }, 128 { 176400, TMDS_593M, 35672, 937500 }, 129 { 176400, TMDS_594M, 37632, 990000 }, 130 { 48000, TMDS_296M, 5824, 281250 }, 131 { 48000, TMDS_297M, 5120, 247500 }, 132 { 48000, TMDS_593M, 5824, 562500 }, 133 { 48000, TMDS_594M, 6144, 594000 }, 134 { 96000, TMDS_296M, 11648, 281250 }, 135 { 96000, TMDS_297M, 10240, 247500 }, 136 { 96000, TMDS_593M, 11648, 562500 }, 137 { 96000, TMDS_594M, 12288, 594000 }, 138 { 192000, TMDS_296M, 23296, 281250 }, 139 { 192000, TMDS_297M, 20480, 247500 }, 140 { 192000, TMDS_593M, 23296, 562500 }, 141 { 192000, TMDS_594M, 24576, 594000 }, 142 }; 143 144 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 145 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 146 #define TMDS_371M 371250 147 #define TMDS_370M 370878 148 149 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 150 { 32000, TMDS_370M, 5824, 527344 }, 151 { 32000, TMDS_371M, 6144, 556875 }, 152 { 44100, TMDS_370M, 8918, 585938 }, 153 { 44100, TMDS_371M, 4704, 309375 }, 154 { 88200, TMDS_370M, 17836, 585938 }, 155 { 88200, TMDS_371M, 9408, 309375 }, 156 { 176400, TMDS_370M, 35672, 585938 }, 157 { 176400, TMDS_371M, 18816, 309375 }, 158 { 48000, TMDS_370M, 11648, 703125 }, 159 { 48000, TMDS_371M, 5120, 309375 }, 160 { 96000, TMDS_370M, 23296, 703125 }, 161 { 96000, TMDS_371M, 10240, 309375 }, 162 { 192000, TMDS_370M, 46592, 703125 }, 163 { 192000, TMDS_371M, 20480, 309375 }, 164 }; 165 166 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 167 #define TMDS_445_5M 445500 168 #define TMDS_445M 445054 169 170 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 171 { 32000, TMDS_445M, 5824, 632813 }, 172 { 32000, TMDS_445_5M, 4096, 445500 }, 173 { 44100, TMDS_445M, 8918, 703125 }, 174 { 44100, TMDS_445_5M, 4704, 371250 }, 175 { 88200, TMDS_445M, 17836, 703125 }, 176 { 88200, TMDS_445_5M, 9408, 371250 }, 177 { 176400, TMDS_445M, 35672, 703125 }, 178 { 176400, TMDS_445_5M, 18816, 371250 }, 179 { 48000, TMDS_445M, 5824, 421875 }, 180 { 48000, TMDS_445_5M, 5120, 371250 }, 181 { 96000, TMDS_445M, 11648, 421875 }, 182 { 96000, TMDS_445_5M, 10240, 371250 }, 183 { 192000, TMDS_445M, 23296, 421875 }, 184 { 192000, TMDS_445_5M, 20480, 371250 }, 185 }; 186 187 /* 188 * WA_14020863754: Implement Audio Workaround 189 * Corner case with Min Hblank Fix can cause audio hang 190 */ 191 static bool needs_wa_14020863754(struct intel_display *display) 192 { 193 return DISPLAY_VER(display) == 20 || display->platform.battlemage; 194 } 195 196 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 197 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 198 { 199 struct intel_display *display = to_intel_display(crtc_state); 200 const struct drm_display_mode *adjusted_mode = 201 &crtc_state->hw.adjusted_mode; 202 int i; 203 204 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 205 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 206 break; 207 } 208 209 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) 210 i = ARRAY_SIZE(hdmi_audio_clock); 211 212 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 213 drm_dbg_kms(display->drm, 214 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 215 adjusted_mode->crtc_clock); 216 i = 1; 217 } 218 219 drm_dbg_kms(display->drm, 220 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 221 hdmi_audio_clock[i].clock, 222 hdmi_audio_clock[i].config); 223 224 return hdmi_audio_clock[i].config; 225 } 226 227 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 228 int rate) 229 { 230 const struct hdmi_aud_ncts *hdmi_ncts_table; 231 int i, size; 232 233 if (crtc_state->pipe_bpp == 36) { 234 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 235 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 236 } else if (crtc_state->pipe_bpp == 30) { 237 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 238 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 239 } else { 240 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 241 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 242 } 243 244 for (i = 0; i < size; i++) { 245 if (rate == hdmi_ncts_table[i].sample_rate && 246 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 247 return hdmi_ncts_table[i].n; 248 } 249 } 250 return 0; 251 } 252 253 /* ELD buffer size in dwords */ 254 static int g4x_eld_buffer_size(struct intel_display *display) 255 { 256 u32 tmp; 257 258 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 259 260 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 261 } 262 263 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 264 struct intel_crtc_state *crtc_state) 265 { 266 struct intel_display *display = to_intel_display(encoder); 267 u32 *eld = (u32 *)crtc_state->eld; 268 int eld_buffer_size, len, i; 269 u32 tmp; 270 271 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 272 if ((tmp & G4X_ELD_VALID) == 0) 273 return; 274 275 intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 276 277 eld_buffer_size = g4x_eld_buffer_size(display); 278 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 279 280 for (i = 0; i < len; i++) 281 eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID); 282 } 283 284 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 285 const struct intel_crtc_state *old_crtc_state, 286 const struct drm_connector_state *old_conn_state) 287 { 288 struct intel_display *display = to_intel_display(encoder); 289 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 290 291 /* Invalidate ELD */ 292 intel_de_rmw(display, G4X_AUD_CNTL_ST, 293 G4X_ELD_VALID, 0); 294 295 intel_crtc_wait_for_next_vblank(crtc); 296 intel_crtc_wait_for_next_vblank(crtc); 297 } 298 299 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 300 const struct intel_crtc_state *crtc_state, 301 const struct drm_connector_state *conn_state) 302 { 303 struct intel_display *display = to_intel_display(encoder); 304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 305 const u32 *eld = (const u32 *)crtc_state->eld; 306 int eld_buffer_size, len, i; 307 308 intel_crtc_wait_for_next_vblank(crtc); 309 310 intel_de_rmw(display, G4X_AUD_CNTL_ST, 311 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 312 313 eld_buffer_size = g4x_eld_buffer_size(display); 314 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 315 316 for (i = 0; i < len; i++) 317 intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]); 318 for (; i < eld_buffer_size; i++) 319 intel_de_write(display, G4X_HDMIW_HDMIEDID, 0); 320 321 drm_WARN_ON(display->drm, 322 (intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 323 324 intel_de_rmw(display, G4X_AUD_CNTL_ST, 325 0, G4X_ELD_VALID); 326 } 327 328 static void 329 hsw_dp_audio_config_update(struct intel_encoder *encoder, 330 const struct intel_crtc_state *crtc_state) 331 { 332 struct intel_display *display = to_intel_display(encoder); 333 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 334 335 /* Enable time stamps. Let HW calculate Maud/Naud values */ 336 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 337 AUD_CONFIG_N_VALUE_INDEX | 338 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 339 AUD_CONFIG_UPPER_N_MASK | 340 AUD_CONFIG_LOWER_N_MASK | 341 AUD_CONFIG_N_PROG_ENABLE, 342 AUD_CONFIG_N_VALUE_INDEX); 343 344 } 345 346 static void 347 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state) 349 { 350 struct intel_display *display = to_intel_display(encoder); 351 struct i915_audio_component *acomp = display->audio.component; 352 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 353 enum port port = encoder->port; 354 int n, rate; 355 u32 tmp; 356 357 rate = acomp ? acomp->aud_sample_rate[port] : 0; 358 359 tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder)); 360 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 361 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 362 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 363 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 364 365 n = audio_config_hdmi_get_n(crtc_state, rate); 366 if (n != 0) { 367 drm_dbg_kms(display->drm, "using N %d\n", n); 368 369 tmp &= ~AUD_CONFIG_N_MASK; 370 tmp |= AUD_CONFIG_N(n); 371 tmp |= AUD_CONFIG_N_PROG_ENABLE; 372 } else { 373 drm_dbg_kms(display->drm, "using automatic N\n"); 374 } 375 376 intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp); 377 378 /* 379 * Let's disable "Enable CTS or M Prog bit" 380 * and let HW calculate the value 381 */ 382 tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 383 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 384 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 385 intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 386 } 387 388 static void 389 hsw_audio_config_update(struct intel_encoder *encoder, 390 const struct intel_crtc_state *crtc_state) 391 { 392 if (intel_crtc_has_dp_encoder(crtc_state)) 393 hsw_dp_audio_config_update(encoder, crtc_state); 394 else 395 hsw_hdmi_audio_config_update(encoder, crtc_state); 396 } 397 398 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 399 const struct intel_crtc_state *old_crtc_state, 400 const struct drm_connector_state *old_conn_state) 401 { 402 struct intel_display *display = to_intel_display(encoder); 403 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 404 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 405 406 mutex_lock(&display->audio.mutex); 407 408 /* Disable timestamps */ 409 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 410 AUD_CONFIG_N_VALUE_INDEX | 411 AUD_CONFIG_UPPER_N_MASK | 412 AUD_CONFIG_LOWER_N_MASK, 413 AUD_CONFIG_N_PROG_ENABLE | 414 (intel_crtc_has_dp_encoder(old_crtc_state) ? 415 AUD_CONFIG_N_VALUE_INDEX : 0)); 416 417 /* Invalidate ELD */ 418 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 419 AUDIO_ELD_VALID(cpu_transcoder), 0); 420 421 intel_crtc_wait_for_next_vblank(crtc); 422 intel_crtc_wait_for_next_vblank(crtc); 423 424 /* Disable audio presence detect */ 425 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 426 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 427 428 if (needs_wa_14020863754(display)) 429 intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); 430 431 mutex_unlock(&display->audio.mutex); 432 } 433 434 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 435 const struct intel_crtc_state *crtc_state) 436 { 437 struct intel_display *display = to_intel_display(encoder); 438 unsigned int link_clks_available, link_clks_required; 439 unsigned int tu_data, tu_line, link_clks_active; 440 unsigned int h_active, h_total, hblank_delta, pixel_clk; 441 unsigned int fec_coeff, cdclk, vdsc_bppx16; 442 unsigned int link_clk, lanes; 443 unsigned int hblank_rise; 444 445 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 446 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 447 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 448 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 449 cdclk = display->cdclk.hw.cdclk; 450 /* fec= 0.972261, using rounding multiplier of 1000000 */ 451 fec_coeff = 972261; 452 link_clk = crtc_state->port_clock; 453 lanes = crtc_state->lane_count; 454 455 drm_dbg_kms(display->drm, 456 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", 457 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); 458 459 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 460 return 0; 461 462 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 463 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 464 465 if (link_clks_available > link_clks_required) 466 hblank_delta = 32; 467 else 468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 469 mul_u32_u32(link_clk, cdclk)); 470 471 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 472 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 473 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 474 mul_u32_u32(64 * pixel_clk, 1000000)); 475 link_clks_active = (tu_line - 1) * 64 + tu_data; 476 477 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 478 479 return h_active - hblank_rise + hblank_delta; 480 } 481 482 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 483 { 484 unsigned int h_active, h_total, pixel_clk; 485 unsigned int link_clk, lanes; 486 487 h_active = crtc_state->hw.adjusted_mode.hdisplay; 488 h_total = crtc_state->hw.adjusted_mode.htotal; 489 pixel_clk = crtc_state->hw.adjusted_mode.clock; 490 link_clk = crtc_state->port_clock; 491 lanes = crtc_state->lane_count; 492 493 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 494 (pixel_clk * (48 / lanes + 2)); 495 } 496 497 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 498 const struct intel_crtc_state *crtc_state) 499 { 500 struct intel_display *display = to_intel_display(encoder); 501 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 502 unsigned int hblank_early_prog, samples_room; 503 unsigned int val; 504 505 if (DISPLAY_VER(display) < 11) 506 return; 507 508 val = intel_de_read(display, AUD_CONFIG_BE); 509 510 if (DISPLAY_VER(display) == 11) 511 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 512 else if (DISPLAY_VER(display) >= 12) 513 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 514 515 if (crtc_state->dsc.compression_enable && 516 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 517 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 518 /* Get hblank early enable value required */ 519 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 520 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 521 if (hblank_early_prog < 32) 522 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 523 else if (hblank_early_prog < 64) 524 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 525 else if (hblank_early_prog < 96) 526 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 527 else 528 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 529 530 /* Get samples room value required */ 531 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 532 samples_room = calc_samples_room(crtc_state); 533 if (samples_room < 3) 534 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 535 else /* Program 0 i.e "All Samples available in buffer" */ 536 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 537 } 538 539 intel_de_write(display, AUD_CONFIG_BE, val); 540 } 541 542 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 543 const struct intel_crtc_state *crtc_state, 544 const struct drm_connector_state *conn_state) 545 { 546 struct intel_display *display = to_intel_display(encoder); 547 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 548 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 549 550 mutex_lock(&display->audio.mutex); 551 552 /* Enable Audio WA for 4k DSC usecases */ 553 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 554 enable_audio_dsc_wa(encoder, crtc_state); 555 556 if (needs_wa_14020863754(display)) 557 intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); 558 559 /* Enable audio presence detect */ 560 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 561 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 562 563 intel_crtc_wait_for_next_vblank(crtc); 564 565 /* Invalidate ELD */ 566 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 567 AUDIO_ELD_VALID(cpu_transcoder), 0); 568 569 /* 570 * The audio component is used to convey the ELD 571 * instead using of the hardware ELD buffer. 572 */ 573 574 /* Enable timestamps */ 575 hsw_audio_config_update(encoder, crtc_state); 576 577 mutex_unlock(&display->audio.mutex); 578 } 579 580 struct ibx_audio_regs { 581 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 582 }; 583 584 static void ibx_audio_regs_init(struct intel_display *display, 585 enum pipe pipe, 586 struct ibx_audio_regs *regs) 587 { 588 struct drm_i915_private *i915 = to_i915(display->drm); 589 590 if (display->platform.valleyview || display->platform.cherryview) { 591 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 592 regs->aud_config = VLV_AUD_CFG(pipe); 593 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 594 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 595 } else if (HAS_PCH_CPT(i915)) { 596 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 597 regs->aud_config = CPT_AUD_CFG(pipe); 598 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 599 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 600 } else if (HAS_PCH_IBX(i915)) { 601 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 602 regs->aud_config = IBX_AUD_CFG(pipe); 603 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 604 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 605 } 606 } 607 608 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 609 const struct intel_crtc_state *old_crtc_state, 610 const struct drm_connector_state *old_conn_state) 611 { 612 struct intel_display *display = to_intel_display(encoder); 613 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 614 enum port port = encoder->port; 615 enum pipe pipe = crtc->pipe; 616 struct ibx_audio_regs regs; 617 618 if (drm_WARN_ON(display->drm, port == PORT_A)) 619 return; 620 621 ibx_audio_regs_init(display, pipe, ®s); 622 623 mutex_lock(&display->audio.mutex); 624 625 /* Disable timestamps */ 626 intel_de_rmw(display, regs.aud_config, 627 AUD_CONFIG_N_VALUE_INDEX | 628 AUD_CONFIG_UPPER_N_MASK | 629 AUD_CONFIG_LOWER_N_MASK, 630 AUD_CONFIG_N_PROG_ENABLE | 631 (intel_crtc_has_dp_encoder(old_crtc_state) ? 632 AUD_CONFIG_N_VALUE_INDEX : 0)); 633 634 /* Invalidate ELD */ 635 intel_de_rmw(display, regs.aud_cntrl_st2, 636 IBX_ELD_VALID(port), 0); 637 638 mutex_unlock(&display->audio.mutex); 639 640 intel_crtc_wait_for_next_vblank(crtc); 641 intel_crtc_wait_for_next_vblank(crtc); 642 } 643 644 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 645 const struct intel_crtc_state *crtc_state, 646 const struct drm_connector_state *conn_state) 647 { 648 struct intel_display *display = to_intel_display(encoder); 649 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 650 enum port port = encoder->port; 651 enum pipe pipe = crtc->pipe; 652 struct ibx_audio_regs regs; 653 654 if (drm_WARN_ON(display->drm, port == PORT_A)) 655 return; 656 657 intel_crtc_wait_for_next_vblank(crtc); 658 659 ibx_audio_regs_init(display, pipe, ®s); 660 661 mutex_lock(&display->audio.mutex); 662 663 /* Invalidate ELD */ 664 intel_de_rmw(display, regs.aud_cntrl_st2, 665 IBX_ELD_VALID(port), 0); 666 667 /* 668 * The audio component is used to convey the ELD 669 * instead using of the hardware ELD buffer. 670 */ 671 672 /* Enable timestamps */ 673 intel_de_rmw(display, regs.aud_config, 674 AUD_CONFIG_N_VALUE_INDEX | 675 AUD_CONFIG_N_PROG_ENABLE | 676 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 677 (intel_crtc_has_dp_encoder(crtc_state) ? 678 AUD_CONFIG_N_VALUE_INDEX : 679 audio_config_hdmi_pixel_clock(crtc_state))); 680 681 mutex_unlock(&display->audio.mutex); 682 } 683 684 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) 685 { 686 struct intel_display *display = to_intel_display(crtc_state); 687 enum transcoder trans = crtc_state->cpu_transcoder; 688 689 if (HAS_DP20(display)) 690 intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 691 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 692 } 693 694 bool intel_audio_compute_config(struct intel_encoder *encoder, 695 struct intel_crtc_state *crtc_state, 696 struct drm_connector_state *conn_state) 697 { 698 struct intel_display *display = to_intel_display(encoder); 699 struct drm_connector *connector = conn_state->connector; 700 const struct drm_display_mode *adjusted_mode = 701 &crtc_state->hw.adjusted_mode; 702 703 mutex_lock(&connector->eld_mutex); 704 if (!connector->eld[0]) { 705 drm_dbg_kms(display->drm, 706 "Bogus ELD on [CONNECTOR:%d:%s]\n", 707 connector->base.id, connector->name); 708 mutex_unlock(&connector->eld_mutex); 709 return false; 710 } 711 712 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 713 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 714 715 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 716 mutex_unlock(&connector->eld_mutex); 717 718 return true; 719 } 720 721 /** 722 * intel_audio_codec_enable - Enable the audio codec for HD audio 723 * @encoder: encoder on which to enable audio 724 * @crtc_state: pointer to the current crtc state. 725 * @conn_state: pointer to the current connector state. 726 * 727 * The enable sequences may only be performed after enabling the transcoder and 728 * port, and after completed link training. 729 */ 730 void intel_audio_codec_enable(struct intel_encoder *encoder, 731 const struct intel_crtc_state *crtc_state, 732 const struct drm_connector_state *conn_state) 733 { 734 struct intel_display *display = to_intel_display(encoder); 735 struct i915_audio_component *acomp = display->audio.component; 736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 737 struct intel_connector *connector = to_intel_connector(conn_state->connector); 738 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 739 struct intel_audio_state *audio_state; 740 enum port port = encoder->port; 741 742 if (!crtc_state->has_audio) 743 return; 744 745 drm_dbg_kms(display->drm, 746 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 747 connector->base.base.id, connector->base.name, 748 encoder->base.base.id, encoder->base.name, 749 crtc->base.base.id, crtc->base.name, 750 drm_eld_size(crtc_state->eld)); 751 752 if (display->funcs.audio) 753 display->funcs.audio->audio_codec_enable(encoder, 754 crtc_state, 755 conn_state); 756 757 mutex_lock(&display->audio.mutex); 758 759 audio_state = &display->audio.state[cpu_transcoder]; 760 761 audio_state->encoder = encoder; 762 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 763 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 764 765 mutex_unlock(&display->audio.mutex); 766 767 if (acomp && acomp->base.audio_ops && 768 acomp->base.audio_ops->pin_eld_notify) { 769 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 770 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 771 cpu_transcoder = -1; 772 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 773 (int)port, (int)cpu_transcoder); 774 } 775 776 intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld, 777 crtc_state->port_clock, 778 intel_crtc_has_dp_encoder(crtc_state)); 779 } 780 781 /** 782 * intel_audio_codec_disable - Disable the audio codec for HD audio 783 * @encoder: encoder on which to disable audio 784 * @old_crtc_state: pointer to the old crtc state. 785 * @old_conn_state: pointer to the old connector state. 786 * 787 * The disable sequences must be performed before disabling the transcoder or 788 * port. 789 */ 790 void intel_audio_codec_disable(struct intel_encoder *encoder, 791 const struct intel_crtc_state *old_crtc_state, 792 const struct drm_connector_state *old_conn_state) 793 { 794 struct intel_display *display = to_intel_display(encoder); 795 struct i915_audio_component *acomp = display->audio.component; 796 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 797 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 798 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 799 struct intel_audio_state *audio_state; 800 enum port port = encoder->port; 801 802 if (!old_crtc_state->has_audio) 803 return; 804 805 drm_dbg_kms(display->drm, 806 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 807 connector->base.base.id, connector->base.name, 808 encoder->base.base.id, encoder->base.name, 809 crtc->base.base.id, crtc->base.name); 810 811 if (display->funcs.audio) 812 display->funcs.audio->audio_codec_disable(encoder, 813 old_crtc_state, 814 old_conn_state); 815 816 mutex_lock(&display->audio.mutex); 817 818 audio_state = &display->audio.state[cpu_transcoder]; 819 820 audio_state->encoder = NULL; 821 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 822 823 mutex_unlock(&display->audio.mutex); 824 825 if (acomp && acomp->base.audio_ops && 826 acomp->base.audio_ops->pin_eld_notify) { 827 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 828 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 829 cpu_transcoder = -1; 830 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 831 (int)port, (int)cpu_transcoder); 832 } 833 834 intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false); 835 } 836 837 static void intel_acomp_get_config(struct intel_encoder *encoder, 838 struct intel_crtc_state *crtc_state) 839 { 840 struct intel_display *display = to_intel_display(encoder); 841 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 842 struct intel_audio_state *audio_state; 843 844 mutex_lock(&display->audio.mutex); 845 846 audio_state = &display->audio.state[cpu_transcoder]; 847 848 if (audio_state->encoder) 849 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 850 851 mutex_unlock(&display->audio.mutex); 852 } 853 854 void intel_audio_codec_get_config(struct intel_encoder *encoder, 855 struct intel_crtc_state *crtc_state) 856 { 857 struct intel_display *display = to_intel_display(encoder); 858 859 if (!crtc_state->has_audio) 860 return; 861 862 if (display->funcs.audio) 863 display->funcs.audio->audio_codec_get_config(encoder, crtc_state); 864 } 865 866 static const struct intel_audio_funcs g4x_audio_funcs = { 867 .audio_codec_enable = g4x_audio_codec_enable, 868 .audio_codec_disable = g4x_audio_codec_disable, 869 .audio_codec_get_config = g4x_audio_codec_get_config, 870 }; 871 872 static const struct intel_audio_funcs ibx_audio_funcs = { 873 .audio_codec_enable = ibx_audio_codec_enable, 874 .audio_codec_disable = ibx_audio_codec_disable, 875 .audio_codec_get_config = intel_acomp_get_config, 876 }; 877 878 static const struct intel_audio_funcs hsw_audio_funcs = { 879 .audio_codec_enable = hsw_audio_codec_enable, 880 .audio_codec_disable = hsw_audio_codec_disable, 881 .audio_codec_get_config = intel_acomp_get_config, 882 }; 883 884 /** 885 * intel_audio_hooks_init - Set up chip specific audio hooks 886 * @display: display device 887 */ 888 void intel_audio_hooks_init(struct intel_display *display) 889 { 890 struct drm_i915_private *i915 = to_i915(display->drm); 891 892 if (display->platform.g4x) 893 display->funcs.audio = &g4x_audio_funcs; 894 else if (display->platform.valleyview || display->platform.cherryview || 895 HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915)) 896 display->funcs.audio = &ibx_audio_funcs; 897 else if (display->platform.haswell || DISPLAY_VER(display) >= 8) 898 display->funcs.audio = &hsw_audio_funcs; 899 } 900 901 struct aud_ts_cdclk_m_n { 902 u8 m; 903 u16 n; 904 }; 905 906 void intel_audio_cdclk_change_pre(struct intel_display *display) 907 { 908 if (DISPLAY_VER(display) >= 13) 909 intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 910 } 911 912 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 913 { 914 aud_ts->m = 60; 915 aud_ts->n = cdclk * aud_ts->m / 24000; 916 } 917 918 void intel_audio_cdclk_change_post(struct intel_display *display) 919 { 920 struct aud_ts_cdclk_m_n aud_ts; 921 922 if (DISPLAY_VER(display) >= 13) { 923 get_aud_ts_cdclk_m_n(display->cdclk.hw.ref, 924 display->cdclk.hw.cdclk, &aud_ts); 925 926 intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n); 927 intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 928 drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n", 929 aud_ts.m, aud_ts.n); 930 } 931 } 932 933 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 934 struct intel_crtc *crtc, 935 bool enable) 936 { 937 struct intel_cdclk_state *cdclk_state; 938 int ret; 939 940 /* need to hold at least one crtc lock for the global state */ 941 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 942 if (ret) 943 return ret; 944 945 cdclk_state = intel_atomic_get_cdclk_state(state); 946 if (IS_ERR(cdclk_state)) 947 return PTR_ERR(cdclk_state); 948 949 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 950 951 return drm_atomic_commit(&state->base); 952 } 953 954 static void glk_force_audio_cdclk(struct intel_display *display, 955 bool enable) 956 { 957 struct drm_modeset_acquire_ctx ctx; 958 struct drm_atomic_state *state; 959 struct intel_crtc *crtc; 960 int ret; 961 962 crtc = intel_first_crtc(display); 963 if (!crtc) 964 return; 965 966 drm_modeset_acquire_init(&ctx, 0); 967 state = drm_atomic_state_alloc(display->drm); 968 if (drm_WARN_ON(display->drm, !state)) 969 return; 970 971 state->acquire_ctx = &ctx; 972 to_intel_atomic_state(state)->internal = true; 973 974 retry: 975 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 976 enable); 977 if (ret == -EDEADLK) { 978 drm_atomic_state_clear(state); 979 drm_modeset_backoff(&ctx); 980 goto retry; 981 } 982 983 drm_WARN_ON(display->drm, ret); 984 985 drm_atomic_state_put(state); 986 987 drm_modeset_drop_locks(&ctx); 988 drm_modeset_acquire_fini(&ctx); 989 } 990 991 int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) 992 { 993 struct intel_display *display = to_intel_display(crtc_state); 994 int min_cdclk = 0; 995 996 if (!crtc_state->has_audio) 997 return 0; 998 999 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 1000 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 1001 * there may be audio corruption or screen corruption." This cdclk 1002 * restriction for GLK is 316.8 MHz. 1003 */ 1004 if (intel_crtc_has_dp_encoder(crtc_state) && 1005 crtc_state->port_clock >= 540000 && 1006 crtc_state->lane_count == 4) { 1007 if (DISPLAY_VER(display) == 10) { 1008 /* Display WA #1145: glk */ 1009 min_cdclk = max(min_cdclk, 316800); 1010 } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { 1011 /* Display WA #1144: skl,bxt */ 1012 min_cdclk = max(min_cdclk, 432000); 1013 } 1014 } 1015 1016 /* 1017 * According to BSpec, "The CD clock frequency must be at least twice 1018 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1019 */ 1020 if (DISPLAY_VER(display) >= 9) 1021 min_cdclk = max(min_cdclk, 2 * 96000); 1022 1023 /* 1024 * "For DP audio configuration, cdclk frequency shall be set to 1025 * meet the following requirements: 1026 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 1027 * 270 | 320 or higher 1028 * 162 | 200 or higher" 1029 */ 1030 if ((display->platform.valleyview || display->platform.cherryview) && 1031 intel_crtc_has_dp_encoder(crtc_state)) 1032 min_cdclk = max(min_cdclk, crtc_state->port_clock); 1033 1034 return min_cdclk; 1035 } 1036 1037 static unsigned long intel_audio_component_get_power(struct device *kdev) 1038 { 1039 struct intel_display *display = to_intel_display(kdev); 1040 intel_wakeref_t wakeref; 1041 1042 /* Catch potential impedance mismatches before they occur! */ 1043 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1044 1045 wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); 1046 1047 if (display->audio.power_refcount++ == 0) { 1048 if (DISPLAY_VER(display) >= 9) { 1049 intel_de_write(display, AUD_FREQ_CNTRL, 1050 display->audio.freq_cntrl); 1051 drm_dbg_kms(display->drm, 1052 "restored AUD_FREQ_CNTRL to 0x%x\n", 1053 display->audio.freq_cntrl); 1054 } 1055 1056 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1057 if (display->platform.geminilake) 1058 glk_force_audio_cdclk(display, true); 1059 1060 if (DISPLAY_VER(display) >= 10) 1061 intel_de_rmw(display, AUD_PIN_BUF_CTL, 1062 0, AUD_PIN_BUF_ENABLE); 1063 } 1064 1065 return (unsigned long)wakeref; 1066 } 1067 1068 static void intel_audio_component_put_power(struct device *kdev, 1069 unsigned long cookie) 1070 { 1071 struct intel_display *display = to_intel_display(kdev); 1072 intel_wakeref_t wakeref = (intel_wakeref_t)cookie; 1073 1074 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1075 if (--display->audio.power_refcount == 0) 1076 if (display->platform.geminilake) 1077 glk_force_audio_cdclk(display, false); 1078 1079 intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); 1080 } 1081 1082 static void intel_audio_component_codec_wake_override(struct device *kdev, 1083 bool enable) 1084 { 1085 struct intel_display *display = to_intel_display(kdev); 1086 unsigned long cookie; 1087 1088 if (DISPLAY_VER(display) < 9) 1089 return; 1090 1091 cookie = intel_audio_component_get_power(kdev); 1092 1093 /* 1094 * Enable/disable generating the codec wake signal, overriding the 1095 * internal logic to generate the codec wake to controller. 1096 */ 1097 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1098 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1099 usleep_range(1000, 1500); 1100 1101 if (enable) { 1102 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1103 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1104 usleep_range(1000, 1500); 1105 } 1106 1107 intel_audio_component_put_power(kdev, cookie); 1108 } 1109 1110 /* Get CDCLK in kHz */ 1111 static int intel_audio_component_get_cdclk_freq(struct device *kdev) 1112 { 1113 struct intel_display *display = to_intel_display(kdev); 1114 1115 if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) 1116 return -ENODEV; 1117 1118 return display->cdclk.hw.cdclk; 1119 } 1120 1121 /* 1122 * get the intel audio state according to the parameter port and cpu_transcoder 1123 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1124 * when port is matched 1125 * MST & (cpu_transcoder < 0): this is invalid 1126 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1127 * will get the right intel_encoder with port matched 1128 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1129 */ 1130 static struct intel_audio_state *find_audio_state(struct intel_display *display, 1131 int port, int cpu_transcoder) 1132 { 1133 /* MST */ 1134 if (cpu_transcoder >= 0) { 1135 struct intel_audio_state *audio_state; 1136 struct intel_encoder *encoder; 1137 1138 if (drm_WARN_ON(display->drm, 1139 cpu_transcoder >= ARRAY_SIZE(display->audio.state))) 1140 return NULL; 1141 1142 audio_state = &display->audio.state[cpu_transcoder]; 1143 encoder = audio_state->encoder; 1144 1145 if (encoder && encoder->port == port && 1146 encoder->type == INTEL_OUTPUT_DP_MST) 1147 return audio_state; 1148 } 1149 1150 /* Non-MST */ 1151 if (cpu_transcoder > 0) 1152 return NULL; 1153 1154 for_each_cpu_transcoder(display, cpu_transcoder) { 1155 struct intel_audio_state *audio_state; 1156 struct intel_encoder *encoder; 1157 1158 audio_state = &display->audio.state[cpu_transcoder]; 1159 encoder = audio_state->encoder; 1160 1161 if (encoder && encoder->port == port && 1162 encoder->type != INTEL_OUTPUT_DP_MST) 1163 return audio_state; 1164 } 1165 1166 return NULL; 1167 } 1168 1169 static int intel_audio_component_sync_audio_rate(struct device *kdev, int port, 1170 int cpu_transcoder, int rate) 1171 { 1172 struct intel_display *display = to_intel_display(kdev); 1173 struct i915_audio_component *acomp = display->audio.component; 1174 const struct intel_audio_state *audio_state; 1175 struct intel_encoder *encoder; 1176 struct intel_crtc *crtc; 1177 unsigned long cookie; 1178 int err = 0; 1179 1180 if (!HAS_DDI(display)) 1181 return 0; 1182 1183 cookie = intel_audio_component_get_power(kdev); 1184 mutex_lock(&display->audio.mutex); 1185 1186 audio_state = find_audio_state(display, port, cpu_transcoder); 1187 if (!audio_state) { 1188 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1189 port_name(port)); 1190 err = -ENODEV; 1191 goto unlock; 1192 } 1193 1194 encoder = audio_state->encoder; 1195 1196 /* FIXME stop using the legacy crtc pointer */ 1197 crtc = to_intel_crtc(encoder->base.crtc); 1198 1199 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1200 acomp->aud_sample_rate[port] = rate; 1201 1202 /* FIXME get rid of the crtc->config stuff */ 1203 hsw_audio_config_update(encoder, crtc->config); 1204 1205 unlock: 1206 mutex_unlock(&display->audio.mutex); 1207 intel_audio_component_put_power(kdev, cookie); 1208 return err; 1209 } 1210 1211 static int intel_audio_component_get_eld(struct device *kdev, int port, 1212 int cpu_transcoder, bool *enabled, 1213 unsigned char *buf, int max_bytes) 1214 { 1215 struct intel_display *display = to_intel_display(kdev); 1216 const struct intel_audio_state *audio_state; 1217 int ret = 0; 1218 1219 mutex_lock(&display->audio.mutex); 1220 1221 audio_state = find_audio_state(display, port, cpu_transcoder); 1222 if (!audio_state) { 1223 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1224 port_name(port)); 1225 mutex_unlock(&display->audio.mutex); 1226 return -EINVAL; 1227 } 1228 1229 *enabled = audio_state->encoder != NULL; 1230 if (*enabled) { 1231 const u8 *eld = audio_state->eld; 1232 1233 ret = drm_eld_size(eld); 1234 memcpy(buf, eld, min(max_bytes, ret)); 1235 } 1236 1237 mutex_unlock(&display->audio.mutex); 1238 return ret; 1239 } 1240 1241 static const struct drm_audio_component_ops intel_audio_component_ops = { 1242 .owner = THIS_MODULE, 1243 .get_power = intel_audio_component_get_power, 1244 .put_power = intel_audio_component_put_power, 1245 .codec_wake_override = intel_audio_component_codec_wake_override, 1246 .get_cdclk_freq = intel_audio_component_get_cdclk_freq, 1247 .sync_audio_rate = intel_audio_component_sync_audio_rate, 1248 .get_eld = intel_audio_component_get_eld, 1249 }; 1250 1251 static int intel_audio_component_bind(struct device *drv_kdev, 1252 struct device *hda_kdev, void *data) 1253 { 1254 struct intel_display *display = to_intel_display(drv_kdev); 1255 struct i915_audio_component *acomp = data; 1256 int i; 1257 1258 if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev)) 1259 return -EEXIST; 1260 1261 if (drm_WARN_ON(display->drm, 1262 !device_link_add(hda_kdev, drv_kdev, 1263 DL_FLAG_STATELESS))) 1264 return -ENOMEM; 1265 1266 drm_modeset_lock_all(display->drm); 1267 acomp->base.ops = &intel_audio_component_ops; 1268 acomp->base.dev = drv_kdev; 1269 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1270 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1271 acomp->aud_sample_rate[i] = 0; 1272 display->audio.component = acomp; 1273 drm_modeset_unlock_all(display->drm); 1274 1275 return 0; 1276 } 1277 1278 static void intel_audio_component_unbind(struct device *drv_kdev, 1279 struct device *hda_kdev, void *data) 1280 { 1281 struct intel_display *display = to_intel_display(drv_kdev); 1282 struct i915_audio_component *acomp = data; 1283 1284 drm_modeset_lock_all(display->drm); 1285 acomp->base.ops = NULL; 1286 acomp->base.dev = NULL; 1287 display->audio.component = NULL; 1288 drm_modeset_unlock_all(display->drm); 1289 1290 device_link_remove(hda_kdev, drv_kdev); 1291 1292 if (display->audio.power_refcount) 1293 drm_err(display->drm, 1294 "audio power refcount %d after unbind\n", 1295 display->audio.power_refcount); 1296 } 1297 1298 static const struct component_ops intel_audio_component_bind_ops = { 1299 .bind = intel_audio_component_bind, 1300 .unbind = intel_audio_component_unbind, 1301 }; 1302 1303 #define AUD_FREQ_TMODE_SHIFT 14 1304 #define AUD_FREQ_4T 0 1305 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1306 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1307 #define AUD_FREQ_BCLK_96M BIT(4) 1308 1309 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1310 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1311 1312 /** 1313 * intel_audio_component_init - initialize and register the audio component 1314 * @display: display device 1315 * 1316 * This will register with the component framework a child component which 1317 * will bind dynamically to the snd_hda_intel driver's corresponding master 1318 * component when the latter is registered. During binding the child 1319 * initializes an instance of struct i915_audio_component which it receives 1320 * from the master. The master can then start to use the interface defined by 1321 * this struct. Each side can break the binding at any point by deregistering 1322 * its own component after which each side's component unbind callback is 1323 * called. 1324 * 1325 * We ignore any error during registration and continue with reduced 1326 * functionality (i.e. without HDMI audio). 1327 */ 1328 static void intel_audio_component_init(struct intel_display *display) 1329 { 1330 u32 aud_freq, aud_freq_init; 1331 1332 if (DISPLAY_VER(display) >= 9) { 1333 aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL); 1334 1335 if (DISPLAY_VER(display) >= 12) 1336 aud_freq = AUD_FREQ_GEN12; 1337 else 1338 aud_freq = aud_freq_init; 1339 1340 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1341 if ((display->platform.tigerlake || display->platform.rocketlake) && 1342 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1343 aud_freq = aud_freq_init; 1344 1345 drm_dbg_kms(display->drm, 1346 "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1347 aud_freq, aud_freq_init); 1348 1349 display->audio.freq_cntrl = aud_freq; 1350 } 1351 1352 /* init with current cdclk */ 1353 intel_audio_cdclk_change_post(display); 1354 } 1355 1356 static void intel_audio_component_register(struct intel_display *display) 1357 { 1358 int ret; 1359 1360 ret = component_add_typed(display->drm->dev, 1361 &intel_audio_component_bind_ops, 1362 I915_COMPONENT_AUDIO); 1363 if (ret < 0) { 1364 drm_err(display->drm, 1365 "failed to add audio component (%d)\n", ret); 1366 /* continue with reduced functionality */ 1367 return; 1368 } 1369 1370 display->audio.component_registered = true; 1371 } 1372 1373 /** 1374 * intel_audio_component_cleanup - deregister the audio component 1375 * @display: display device 1376 * 1377 * Deregisters the audio component, breaking any existing binding to the 1378 * corresponding snd_hda_intel driver's master component. 1379 */ 1380 static void intel_audio_component_cleanup(struct intel_display *display) 1381 { 1382 if (!display->audio.component_registered) 1383 return; 1384 1385 component_del(display->drm->dev, &intel_audio_component_bind_ops); 1386 display->audio.component_registered = false; 1387 } 1388 1389 /** 1390 * intel_audio_init() - Initialize the audio driver either using 1391 * component framework or using lpe audio bridge 1392 * @display: display device 1393 * 1394 */ 1395 void intel_audio_init(struct intel_display *display) 1396 { 1397 if (intel_lpe_audio_init(display) < 0) 1398 intel_audio_component_init(display); 1399 } 1400 1401 void intel_audio_register(struct intel_display *display) 1402 { 1403 if (!display->audio.lpe.platdev) 1404 intel_audio_component_register(display); 1405 } 1406 1407 /** 1408 * intel_audio_deinit() - deinitialize the audio driver 1409 * @display: display device 1410 */ 1411 void intel_audio_deinit(struct intel_display *display) 1412 { 1413 if (display->audio.lpe.platdev) 1414 intel_lpe_audio_teardown(display); 1415 else 1416 intel_audio_component_cleanup(display); 1417 } 1418