1 /************************************************************************** 2 * 3 * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 /* 28 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> 29 */ 30 31 #include <linux/export.h> 32 #include <drm/drmP.h> 33 34 #if defined(CONFIG_X86) 35 #include <asm/smp.h> 36 37 /* 38 * clflushopt is an unordered instruction which needs fencing with mfence or 39 * sfence to avoid ordering issues. For drm_clflush_page this fencing happens 40 * in the caller. 41 */ 42 static void 43 drm_clflush_page(struct page *page) 44 { 45 uint8_t *page_virtual; 46 unsigned int i; 47 const int size = boot_cpu_data.x86_clflush_size; 48 49 if (unlikely(page == NULL)) 50 return; 51 52 page_virtual = kmap_atomic(page); 53 for (i = 0; i < PAGE_SIZE; i += size) 54 clflushopt(page_virtual + i); 55 kunmap_atomic(page_virtual); 56 } 57 58 static void drm_cache_flush_clflush(struct page *pages[], 59 unsigned long num_pages) 60 { 61 unsigned long i; 62 63 mb(); 64 for (i = 0; i < num_pages; i++) 65 drm_clflush_page(*pages++); 66 mb(); 67 } 68 #endif 69 70 /** 71 * drm_clflush_pages - Flush dcache lines of a set of pages. 72 * @pages: List of pages to be flushed. 73 * @num_pages: Number of pages in the array. 74 * 75 * Flush every data cache line entry that points to an address belonging 76 * to a page in the array. 77 */ 78 void 79 drm_clflush_pages(struct page *pages[], unsigned long num_pages) 80 { 81 82 #if defined(CONFIG_X86) 83 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 84 drm_cache_flush_clflush(pages, num_pages); 85 return; 86 } 87 88 if (wbinvd_on_all_cpus()) 89 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 90 91 #elif defined(__powerpc__) 92 unsigned long i; 93 for (i = 0; i < num_pages; i++) { 94 struct page *page = pages[i]; 95 void *page_virtual; 96 97 if (unlikely(page == NULL)) 98 continue; 99 100 page_virtual = kmap_atomic(page); 101 flush_dcache_range((unsigned long)page_virtual, 102 (unsigned long)page_virtual + PAGE_SIZE); 103 kunmap_atomic(page_virtual); 104 } 105 #else 106 printk(KERN_ERR "Architecture has no drm_cache.c support\n"); 107 WARN_ON_ONCE(1); 108 #endif 109 } 110 EXPORT_SYMBOL(drm_clflush_pages); 111 112 /** 113 * drm_clflush_sg - Flush dcache lines pointing to a scather-gather. 114 * @st: struct sg_table. 115 * 116 * Flush every data cache line entry that points to an address in the 117 * sg. 118 */ 119 void 120 drm_clflush_sg(struct sg_table *st) 121 { 122 #if defined(CONFIG_X86) 123 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 124 struct sg_page_iter sg_iter; 125 126 mb(); 127 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) 128 drm_clflush_page(sg_page_iter_page(&sg_iter)); 129 mb(); 130 131 return; 132 } 133 134 if (wbinvd_on_all_cpus()) 135 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 136 #else 137 printk(KERN_ERR "Architecture has no drm_cache.c support\n"); 138 WARN_ON_ONCE(1); 139 #endif 140 } 141 EXPORT_SYMBOL(drm_clflush_sg); 142 143 /** 144 * drm_clflush_virt_range - Flush dcache lines of a region 145 * @addr: Initial kernel memory address. 146 * @length: Region size. 147 * 148 * Flush every data cache line entry that points to an address in the 149 * region requested. 150 */ 151 void 152 drm_clflush_virt_range(void *addr, unsigned long length) 153 { 154 #if defined(CONFIG_X86) 155 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 156 const int size = boot_cpu_data.x86_clflush_size; 157 void *end = addr + length; 158 addr = (void *)(((unsigned long)addr) & -size); 159 mb(); 160 for (; addr < end; addr += size) 161 clflushopt(addr); 162 clflushopt(end - 1); /* force serialisation */ 163 mb(); 164 return; 165 } 166 167 if (wbinvd_on_all_cpus()) 168 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 169 #else 170 printk(KERN_ERR "Architecture has no drm_cache.c support\n"); 171 WARN_ON_ONCE(1); 172 #endif 173 } 174 EXPORT_SYMBOL(drm_clflush_virt_range); 175